{"task_id": "gbaHD", "path": "gbaHD/hdl/borderGen.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Border Generator\n-- Author: zwenergy\n-----------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\nentity borderGen is \n", "right_context": " yMin : integer;\n yMax : integer\n );\n port (\n x : in integer range xMin to xMax;\n y : in integer range yMin to yMax; \n r : out std_logic_vector( 7 downto 0 );\n g : out std_logic_vector( 7 downto 0 );\n b : out std_logic_vector( 7 downto 0 )\n );\nend borderGen;\narchitecture rtl of borderGen is\nbegin\n\n r <= ( others => '0' );\n g <= ( others => '0' );\n b <= ( others => '0' );\n \nend rtl;\n", "groundtruth": " generic(\n xMin : integer;\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/captureGBA.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: GBA Display Capture\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nentity captureGBA is\n generic(\n clkPeriodNS : real := 13.0 -- Clock period in ns.\n );\n port(\n clk : in std_logic;\n rst : in std_logic;\n redPxl : in std_logic_vector( 4 downto 0 );\n greenPxl : in std_logic_vector( 4 downto 0 );\n bluePxl : in std_logic_vector( 4 downto 0 );\n vsync : in std_logic;\n dclk : in std_logic;\n \n colorMode : in std_logic;\n \n redPxlOut : out std_logic_vector( 7 downto 0 );\n greenPxlOut : out std_logic_vector( 7 downto 0 );\n bluePxlOut : out std_logic_vector( 7 downto 0 );\n validPxlOut : out std_logic;\n pxlCnt : out std_logic_vector( 7 downto 0 );\n \n validLine : out std_logic;\n newFrame : out std_logic\n );\nend captureGBA;\n\narchitecture rtl of captureGBA is\nsignal cntX : integer range -1 to 245;\nsignal cntY : integer range 0 to 165;\nsignal prevCntX : integer range -1 to 245;\nsignal prevCntY : integer range 0 to 165;\nsignal validLine_int : std_logic;\nsignal curRedPxl : std_logic_vector( 4 downto 0 );\nsignal curGreenPxl : std_logic_vector( 4 downto 0 );\nsignal curBluePxl : std_logic_vector( 4 downto 0 );\nsignal dclk_int : std_logic;\nsignal dclk_prev : std_logic;\nsignal dclkRise : std_logic;\nsignal newPxl : std_logic;\nsignal vsyncFall : std_logic;\nsignal vsyncRise : std_logic;\nsignal vsync_int : std_logic;\nsignal vsync_del : std_logic;\nsignal syncCnt : integer range 0 to integer(ceil(325000.0/clkPeriodNS));\nconstant minSyncCnt : integer := integer(ceil(136500.0/clkPeriodNS));\n\n-- GBA Color Correction\nsignal redGBACol, greenGBACol, blueGBACol, redExt, greenExt, blueExt : std_logic_vector( 7 downto 0 );\nbegin\n\n -- Thanks to ManCloud for improving my stupid color extension :)\n \n redExtProc : process( curRedPxl ) is\n variable pxl_tmp, curPxl : unsigned( 7 downto 0 );\n begin\n curPxl := unsigned( curRedPxl ) & \"000\";\n pxl_tmp := \"00000\" & unsigned( curRedPxl( 4 downto 2 ) );\n pxl_tmp := pxl_tmp + curPxl;\n \n redExt <= std_logic_vector( pxl_tmp ) ;\n \n -- Keep limited range.\n-- if ( unsigned( pxl_tmp ) < 16 ) then\n-- pxl_tmp := std_logic_vector( to_unsigned( 16, pxl_tmp'length ) );\n-- elsif ( unsigned( pxl_tmp ) > 235 ) then\n-- pxl_tmp := std_logic_vector( to_unsigned( 235, pxl_tmp'length ) );\n-- end if;\n end process;\n \n blueExtProc : process( curBluePxl ) is\n variable pxl_tmp, curPxl : unsigned( 7 downto 0 );\n begin\n curPxl := unsigned( curBluePxl ) & \"000\";\n pxl_tmp := \"00000\" & unsigned( curBluePxl( 4 downto 2 ) );\n pxl_tmp := pxl_tmp + curPxl;\n \n blueExt <= std_logic_vector( pxl_tmp ) ;\n end process;\n \n greenExtProc : process( curGreenPxl ) is\n variable pxl_tmp, curPxl : unsigned( 7 downto 0 );\n begin\n curPxl := unsigned( curGreenPxl ) & \"000\";\n pxl_tmp := \"00000\" & unsigned( curGreenPxl( 4 downto 2 ) );\n pxl_tmp := pxl_tmp + curPxl;\n \n greenExt <= std_logic_vector( pxl_tmp ) ;\n end process;\n \n -- GBA color correction.\n colorCorrection : entity work.gbaColorCorrNew( rtl )\n port map(\n gbaRed => curRedPxl,\n gbaGreen => curGreenPxl,\n gbaBlue => curBluePxl,\n rGBACol => redGBACol,\n gGBACol => greenGBACol,\n bGBACol => blueGBACol\n );\n \n -- Choose color mode.\n", "right_context": " redPxlOut <= redExt;\n greenPxlOut <= greenExt;\n bluePxlOut <= blueExt;\n \n end if;\n \n pxlCnt <= std_logic_vector( to_unsigned( prevCntX, pxlCnt'length ) );\n \n -- Since the very first bit is a start bit, we have to count until 239\n if ( ( newPxl = '1' ) and ( prevCntX = 239 ) ) then\n validLine <= '1';\n else\n validLine <= '0';\n end if;\n \n if ( prevCntY = 0 ) then\n newFrame <= '1';\n else\n newFrame <= '0';\n end if;\n\n validPxlOut <= newPxl;\n \n end if;\n end process;\n \n \n dclkRise <= '1' when ( dclk_int = '1' and dclk_prev = '0' ) else '0';\n \n \n vsyncRise <= '1' when ( vsync_int = '1' and vsync_del = '0' ) else '0';\n vsyncFall <= '1' when ( vsync_int = '0' and vsync_del = '1' ) else '0';\n\n process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( rst = '1' ) then\n syncCnt <= 0;\n vsync_int <= '1';\n vsync_del <= '1';\n cntY <= 0;\n cntX <= -1;\n dclk_prev <= '1';\n curRedPxl <= ( others => '0' );\n curGreenPxl <= ( others => '0' );\n curBluePxl <= ( others => '0' );\n newPxl <= '0';\n prevCntY <= 0;\n prevCntX <= 0;\n dclk_int <= '1';\n \n else\n -- Shift prev. dclk\n dclk_int <= dclk;\n dclk_prev <= dclk_int;\n \n vsync_int <= vsync;\n vsync_del <= vsync_int;\n \n -- Shift newPxl.\n -- The very first pixel seems to be not a valid one (...start bit?)\n if ( cntX = -1 ) then\n newPxl <= '0';\n else\n newPxl <= dclkRise;\n end if;\n \n prevCntX <= cntX;\n prevCntY <= cntY;\n \n -- Capture new pxl.\n if ( dclkRise = '1' ) then\n curRedPxl <= redPxl;\n curGreenPxl <= greenPxl;\n curBluePxl <= bluePxl;\n end if;\n \n if ( vsyncFall = '1' ) then\n syncCnt <= 0;\n elsif ( vsync_int = '0' ) then\n syncCnt <= syncCnt + 1;\n end if;\n \n if ( vsyncRise = '1' and syncCnt >= minSyncCnt ) then\n cntY <= 0;\n cntX <= -1;\n elsif ( dclkRise = '1' ) then\n if ( cntX = 239 ) then\n cntX <= -1;\n cntY <= cntY + 1;\n else\n cntX <= cntX + 1;\n end if;\n end if;\n end if;\n end if;\n end process;\n \n \n\nend rtl;", "groundtruth": " process( clk ) is\n begin\n if rising_edge( clk ) then\n if ( colorMode = '1' ) then\n redPxlOut <= redGBACol;\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/commTransceiver.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Controller Transceiver\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\nuse IEEE.math_real.ALL;\nuse IEEE.std_logic_misc.ALL;\n\nentity commTransceiver is\n generic( \n packetBits : integer := 16;\n clkFreq0 : real; -- kHz\n clkFreq1 : real; -- kHz\n clkFreqMax : real; -- kHz\n usBit : real\n );\n port(\n serDatIn : in std_logic;\n clk : in std_logic;\n rst : in std_logic;\n \n -- Corresponding to the generics.\n clkFreq : in std_logic;\n \n --serDatOut : out std_logic;\n --txActive : out std_logic;\n controllerOut : out std_logic_vector( 9 downto 0 );\n controllerOSDActive : out std_logic;\n \n osdActive : out std_logic;\n osdState : out std_logic_vector( 7 downto 0 );\n osdStateValid : out std_logic;\n \n -- Settings\n osdSmooth2x : out std_logic;\n osdSmooth4x : out std_logic;\n osdGridActive : out std_logic;\n osdGridBright : out std_logic;\n osdGridMult : out std_logic;\n osdColorCorrection : out std_logic;\n osdRate : out std_logic;\n osdSettingsValid : out std_logic;\n \n rxValid : out std_logic\n );\n \nend commTransceiver;\n\narchitecture rtl of commTransceiver is\n constant cyclesBitMax : integer := integer( ceil( ( usBit / 1000000.0 ) / ( 1.0 / ( clkFreqMax * 1000.0 ) ) ) );\n constant cyclesTimeout : integer := 2 * cyclesBitMax;\n \n constant cyclesBit0 : integer := integer( ceil( ( usBit / 1000000.0 ) / ( 1.0 / ( clkFreq0 * 1000.0 ) ) ) );\n constant cyclesBit1 : integer := integer( ceil( ( usBit / 1000000.0 ) / ( 1.0 / ( clkFreq1 * 1000.0 ) ) ) );\n constant cyclesHalfBit0 : integer := cyclesBit0 / 2;\n constant cyclesHalfBit1 : integer := cyclesBit1 / 2;\n \n constant prefixLen : integer := 4;\n constant controllerOSD_prefix : std_logic_vector( prefixLen - 1 downto 0 ) := \"1000\";\n constant config_prefix : std_logic_vector( prefixLen - 1 downto 0 ) := \"0100\";\n constant osdState_prefix : std_logic_vector( prefixLen - 1 downto 0 ) := \"0010\";\n \n -- Timeout counter.\n signal timeoutCnt : integer range 0 to cyclesTimeout;\n -- Bit counter.\n signal bitCnt : integer range 0 to packetBits;\n -- Packet.\n signal curPacket : std_logic_vector( packetBits - 1 downto 0 );\n -- Flag for a new packet.\n signal newPacket : std_logic;\n\n signal serDatInPrev, serDatIn_filtered : std_logic;\n signal serDatFilter : std_logic_vector( 7 downto 0 );\n \n -- A few status bits.\n signal rxPacket : std_logic;\n \nbegin\n \n \n -- Synch. part.\n process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( rst = '1' ) then\n timeoutCnt <= 0;\n bitCnt <= 0;\n curPacket <= ( others => '0' );\n newPacket <= '0';\n serDatInPrev <= '0';\n rxPacket <= '0';\n controllerOut <= ( others => '0' );\n rxValid <= '0';\n serDatFilter <= ( others => '1' );\n \n controllerOut <= ( others => '0' );\n controllerOSDActive <= '0';\n osdActive <= '0';\n osdState <= ( others => '0' );\n osdStateValid <= '0';\n osdSmooth2x <= '0';\n osdSmooth4x <= '0';\n osdGridActive <= '0';\n osdGridBright <= '0';\n osdGridMult <= '0';\n osdColorCorrection <= '0';\n osdRate <= '0';\n osdSettingsValid <= '0';\n \n serDatIn_filtered <= '1';\n --serDatOut <= '1';\n --txActive <= '0';\n else\n \n -- Serial Input related stuff.\n serDatFilter( 7 ) <= serDatIn;\n serDatFilter( 6 downto 0 ) <= serDatFilter( 7 downto 1 );\n \n if ( and_reduce( serDatFilter ) = '1' ) then\n serDatIn_filtered <= '1';\n elsif ( or_reduce( serDatFilter ) = '0' ) then\n serDatIn_filtered <= '0';\n end if; \n \n serDatInPrev <= serDatIn_filtered;\n \n -- Per default, there is no new packet.\n newPacket <= '0';\n \n -- Falling edge, a new bit is arriving.\n if ( serDatInPrev = '1' and serDatIn_filtered = '0' ) then\n -- Reset counter.\n timeoutCnt <= 0;\n rxPacket <= '1';\n elsif ( rxPacket = '1' ) then\n timeoutCnt <= timeoutCnt + 1;\n \n -- Sample?\n if ( ( clkFreq = '0' and timeoutCnt = cyclesHalfBit0 ) or\n ( clkFreq = '1' and timeoutCnt = cyclesHalfBit1 ) ) then\n curPacket( packetBits - 1 ) <= serDatIn_filtered;\n curPacket( packetBits - 2 downto 0 ) <= curPacket( packetBits - 1 downto 1 );\n bitCnt <= bitCnt + 1;\n \n -- Timeout?\n elsif ( timeoutCnt = cyclesTimeout ) then\n rxPacket <= '0';\n bitCnt <= 0;\n if ( bitCnt = packetBits ) then\n newPacket <= '1';\n end if;\n end if;\n end if;\n \n \n -- Controller output related stuff.\n if ( newPacket = '1' ) then\n \n -- On screen buttons?\n if ( curPacket( packetBits - 1 downto packetBits - prefixLen ) = controllerOSD_prefix ) then\n controllerOut <= curPacket( 9 downto 0 );\n \n -- Settings packet?\n elsif ( curPacket( packetBits - 1 downto packetBits - prefixLen ) = config_prefix ) then\n osdSmooth2x <= curPacket( 0 );\n osdSmooth4x <= curPacket( 1 );\n osdGridActive <= curPacket( 2 );\n osdGridBright <= curPacket( 3 );\n osdGridMult <= curPacket( 4 );\n osdColorCorrection <= curPacket( 5 );\n osdRate <= curPacket( 6 );\n controllerOSDActive <= curPacket( 7 );\n osdSettingsValid <= '1';\n \n -- OSD state?\n", "right_context": " \n end if;\n \n rxValid <= '1';\n else \n rxValid <= '0';\n osdSettingsValid <= '0';\n osdStateValid <= '0';\n \n end if;\n\n end if;\n end if;\n end process;\nend rtl;\n", "groundtruth": " elsif ( curPacket( packetBits - 1 downto packetBits - prefixLen ) = osdState_prefix ) then\n osdActive <= curPacket( 0 );\n osdState( 6 downto 0 ) <= curPacket( 7 downto 1 );\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/drp.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: DRP\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.numeric_std.all;\n\nentity drp is\n port (\n -- 000: 60 Hz, 720p\n -- 001: 59.x Hz, 720p\n -- 010: 60 Hz, 1080p\n -- 011: 59.x Hz, 1080p\n -- 100: 60 Hz, 480p\n -- 101: 59.x Hz, 480p\n stateSel : in std_logic_vector( 2 downto 0 );\n doSwitch : in std_logic;\n \n doSig : in std_logic_vector( 15 downto 0 );\n drdy : in std_logic;\n locked : in std_logic;\n \n clk : in std_logic;\n rst : in std_logic;\n \n busy : out std_logic;\n \n dwe : out std_logic;\n den : out std_logic;\n daddr : out std_logic_vector( 6 downto 0 );\n diSig : out std_logic_vector( 15 downto 0 );\n dclk : out std_logic;\n rstMMCM : out std_logic\n );\nend drp;\n\narchitecture rtl of drp is\ntype reconfEntry_t is record\n addr : std_logic_vector( 6 downto 0 );\n data : std_logic_vector( 15 downto 0 );\n mask : std_logic_vector( 15 downto 0 );\nend record reconfEntry_t;\ntype reconfSetting_t is array( 0 to 13 ) of reconfEntry_t;\ntype reconfROM_t is array( 0 to 5 ) of reconfSetting_t;\n\n-- The actual ROM.\nconstant reconfROM : reconfROM_t :=\n-- 60 Hz, 720p\n( 0 =>\n -- General settings\n ( 0 =>\n (\n addr => std_logic_vector( to_unsigned( 16#14#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1491#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n \n 1 =>\n (\n addr => std_logic_vector( to_unsigned( 16#15#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1800#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 2 =>\n (\n addr => std_logic_vector( to_unsigned( 16#13#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#2400#, 16 ) ),\n mask => \"1100001100000000\"\n ),\n 3 =>\n (\n addr => std_logic_vector( to_unsigned( 16#16#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0083#, 16 ) ),\n mask => \"1100000000000000\"\n ),\n 4 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4F#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1000#, 16 ) ),\n mask => \"0110011001101111\"\n ),\n 5 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4E#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0900#, 16 ) ),\n mask => \"0110011011111111\"\n ),\n 6 =>\n (\n addr => std_logic_vector( to_unsigned( 16#28#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#FFFF#, 16 ) ),\n mask => \"0000000000000000\"\n ),\n 7 =>\n (\n addr => std_logic_vector( to_unsigned( 16#18#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#00fa#, 16 ) ),\n mask => \"1111110000000000\"\n ),\n 8 =>\n (\n addr => std_logic_vector( to_unsigned( 16#19#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7c01#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 9 =>\n (\n addr => std_logic_vector( to_unsigned( 16#1A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7de9#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout0\n 10 =>\n (\n addr => std_logic_vector( to_unsigned( 16#08#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1041#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n 11 =>\n (\n addr => std_logic_vector( to_unsigned( 16#09#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0000#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout1\n 12 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1145#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 13 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0B#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0000#, 16 ) ),\n mask => \"1111110000000000\"\n )\n ),\n \n -- 59.7 Hz, 720 p\n 1 =>\n -- General settings\n ( 0 =>\n (\n addr => std_logic_vector( to_unsigned( 16#14#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1410#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n \n 1 =>\n (\n addr => std_logic_vector( to_unsigned( 16#15#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#2800#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 2 =>\n (\n addr => std_logic_vector( to_unsigned( 16#13#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#2800#, 16 ) ),\n mask => \"1100001100000000\"\n ),\n 3 =>\n (\n addr => std_logic_vector( to_unsigned( 16#16#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0042#, 16 ) ),\n mask => \"1100000000000000\"\n ),\n 4 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4F#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1000#, 16 ) ),\n mask => \"0110011001101111\"\n ),\n 5 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4E#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0900#, 16 ) ),\n mask => \"0110011011111111\"\n ),\n 6 =>\n (\n addr => std_logic_vector( to_unsigned( 16#28#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#FFFF#, 16 ) ),\n mask => \"0000000000000000\"\n ),\n 7 =>\n (\n addr => std_logic_vector( to_unsigned( 16#18#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#002c#, 16 ) ),\n mask => \"1111110000000000\"\n ),\n 8 =>\n (\n addr => std_logic_vector( to_unsigned( 16#19#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7c01#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 9 =>\n (\n addr => std_logic_vector( to_unsigned( 16#1A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7de9#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout0\n 10 =>\n (\n addr => std_logic_vector( to_unsigned( 16#08#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1042#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n 11 =>\n (\n addr => std_logic_vector( to_unsigned( 16#09#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout1\n 12 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#11c8#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 13 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0B#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1111110000000000\"\n )\n ),\n \n -- 60 Hz, 1080p\n 2 =>\n -- General settings\n ( 0 =>\n (\n addr => std_logic_vector( to_unsigned( 16#14#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1491#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n \n 1 =>\n (\n addr => std_logic_vector( to_unsigned( 16#15#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1800#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 2 =>\n (\n addr => std_logic_vector( to_unsigned( 16#13#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#2400#, 16 ) ),\n mask => \"1100001100000000\"\n ),\n 3 =>\n (\n addr => std_logic_vector( to_unsigned( 16#16#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0083#, 16 ) ),\n mask => \"1100000000000000\"\n ),\n 4 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4F#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1000#, 16 ) ),\n mask => \"0110011001101111\"\n ),\n 5 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4E#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0900#, 16 ) ),\n mask => \"0110011011111111\"\n ),\n 6 =>\n (\n addr => std_logic_vector( to_unsigned( 16#28#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#FFFF#, 16 ) ),\n mask => \"0000000000000000\"\n ),\n 7 =>\n (\n addr => std_logic_vector( to_unsigned( 16#18#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#00fa#, 16 ) ),\n mask => \"1111110000000000\"\n ),\n 8 =>\n (\n addr => std_logic_vector( to_unsigned( 16#19#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7c01#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 9 =>\n (\n addr => std_logic_vector( to_unsigned( 16#1A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7de9#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout0\n 10 =>\n (\n addr => std_logic_vector( to_unsigned( 16#08#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1041#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n 11 =>\n (\n addr => std_logic_vector( to_unsigned( 16#09#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#00c0#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout1\n 12 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1083#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 13 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0B#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1111110000000000\"\n )\n ),\n \n -- 59.x Hz, 1080p\n 3 =>\n -- General settings\n ( 0 =>\n (\n addr => std_logic_vector( to_unsigned( 16#14#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#175c#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n \n 1 =>\n (\n addr => std_logic_vector( to_unsigned( 16#15#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1800#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 2 =>\n (\n addr => std_logic_vector( to_unsigned( 16#13#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#2400#, 16 ) ),\n mask => \"1100001100000000\"\n ),\n 3 =>\n (\n addr => std_logic_vector( to_unsigned( 16#16#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0104#, 16 ) ),\n mask => \"1100000000000000\"\n ),\n 4 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4F#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1000#, 16 ) ),\n mask => \"0110011001101111\"\n ),\n 5 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4E#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0800#, 16 ) ),\n mask => \"0110011011111111\"\n ),\n 6 =>\n (\n addr => std_logic_vector( to_unsigned( 16#28#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#FFFF#, 16 ) ),\n mask => \"0000000000000000\"\n ),\n 7 =>\n (\n addr => std_logic_vector( to_unsigned( 16#18#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#00fa#, 16 ) ),\n mask => \"1111110000000000\"\n ),\n 8 =>\n (\n addr => std_logic_vector( to_unsigned( 16#19#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7c01#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 9 =>\n (\n addr => std_logic_vector( to_unsigned( 16#1A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7de9#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout0\n 10 =>\n (\n addr => std_logic_vector( to_unsigned( 16#08#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1041#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n 11 =>\n (\n addr => std_logic_vector( to_unsigned( 16#09#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#00c0#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout1\n 12 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1083#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 13 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0B#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1111110000000000\"\n )\n ),\n \n -- 60 Hz, 480p\n 4 =>\n -- General settings\n ( 0 =>\n (\n addr => std_logic_vector( to_unsigned( 16#14#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#15d7#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n \n 1 =>\n (\n addr => std_logic_vector( to_unsigned( 16#15#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#2800#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 2 =>\n (\n addr => std_logic_vector( to_unsigned( 16#13#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#2800#, 16 ) ),\n mask => \"1100001100000000\"\n ),\n 3 =>\n (\n addr => std_logic_vector( to_unsigned( 16#16#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0083#, 16 ) ),\n mask => \"1100000000000000\"\n ),\n 4 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4F#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0100#, 16 ) ),\n mask => \"0110011001101111\"\n ),\n 5 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4E#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1900#, 16 ) ),\n mask => \"0110011011111111\"\n ),\n 6 =>\n (\n addr => std_logic_vector( to_unsigned( 16#28#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#FFFF#, 16 ) ),\n mask => \"0000000000000000\"\n ),\n 7 =>\n (\n addr => std_logic_vector( to_unsigned( 16#18#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#00fa#, 16 ) ),\n mask => \"1111110000000000\"\n ),\n 8 =>\n (\n addr => std_logic_vector( to_unsigned( 16#19#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7c01#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 9 =>\n (\n addr => std_logic_vector( to_unsigned( 16#1A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7de9#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout0\n 10 =>\n (\n addr => std_logic_vector( to_unsigned( 16#08#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#10c4#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n 11 =>\n (\n addr => std_logic_vector( to_unsigned( 16#09#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout1\n 12 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1452#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 13 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0B#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1111110000000000\"\n )\n ),\n \n-- -- 59.x Hz, 480p\n 5 =>\n -- General settings\n ( 0 =>\n (\n addr => std_logic_vector( to_unsigned( 16#14#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#175d#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n \n 1 =>\n (\n addr => std_logic_vector( to_unsigned( 16#15#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#4c00#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 2 =>\n (\n addr => std_logic_vector( to_unsigned( 16#13#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1400#, 16 ) ),\n mask => \"1100001100000000\"\n ),\n 3 =>\n (\n addr => std_logic_vector( to_unsigned( 16#16#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0105#, 16 ) ),\n mask => \"1100000000000000\"\n ),\n 4 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4F#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1000#, 16 ) ),\n mask => \"0110011001101111\"\n ),\n 5 =>\n (\n addr => std_logic_vector( to_unsigned( 16#4E#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0800#, 16 ) ),\n mask => \"0110011011111111\"\n ),\n 6 =>\n (\n addr => std_logic_vector( to_unsigned( 16#28#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#FFFF#, 16 ) ),\n mask => \"0000000000000000\"\n ),\n 7 =>\n (\n addr => std_logic_vector( to_unsigned( 16#18#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#00fa#, 16 ) ),\n mask => \"1111110000000000\"\n ),\n 8 =>\n (\n addr => std_logic_vector( to_unsigned( 16#19#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7c01#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 9 =>\n (\n addr => std_logic_vector( to_unsigned( 16#1A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#7de9#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout0\n 10 =>\n (\n addr => std_logic_vector( to_unsigned( 16#08#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#1083#, 16 ) ),\n mask => \"0001000000000000\"\n ),\n 11 =>\n (\n addr => std_logic_vector( to_unsigned( 16#09#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n -- Clkout1\n 12 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0A#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#130d#, 16 ) ),\n mask => \"1000000000000000\"\n ),\n 13 =>\n (\n addr => std_logic_vector( to_unsigned( 16#0B#, 7 ) ),\n data => std_logic_vector( to_unsigned( 16#0080#, 16 ) ),\n mask => \"1111110000000000\"\n )\n )\n);\n\ntype fsmSingleValStates is ( idle, setDADDR, waitDRDY0, \n applyMask, doWrite, waitDRDY1 );\ntype fsmTopStates is ( idle, setVal, waitVal, incInd, waitLock );\nsignal fsmTopCur, fsmTopNext : fsmTopStates := idle;\nsignal fsmSingleValCur, fsmSingleValNext : fsmSingleValStates := idle;\nsignal nextAddr : std_logic_vector( 6 downto 0 );\nsignal nextVal : std_logic_vector( 15 downto 0 );\nsignal nextMask : std_logic_vector( 15 downto 0 );\nsignal setNewVal : std_logic;\n\nsignal itemInd : integer range 0 to 13;\n\nsignal maskedVal : std_logic_vector( 15 downto 0 );\n\nsignal stateSel_int : std_logic_vector( 2 downto 0 );\nbegin\n\n dclk <= clk;\n \n -- Do masking.\n", "right_context": " -- Simple seq.\n process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( fsmTopCur = idle ) then\n stateSel_int <= stateSel;\n end if;\n end if;\n end process;\n \n -- Do index increasing.\n process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( rst = '1' ) then\n itemInd <= 0; \n else\n if ( fsmTopCur = idle ) then\n itemInd <= 0;\n elsif ( fsmTopCur = incInd ) then\n itemInd <= itemInd + 1;\n end if; \n end if;\n end if;\n end process;\n \n -- Top FSM.\n process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( rst = '1' ) then\n fsmTopCur <= idle;\n else\n fsmTopCur <= fsmTopNext;\n end if;\n end if;\n end process;\n \n process( fsmTopCur, doSwitch, fsmSingleValCur, locked, itemInd ) is\n begin\n case fsmTopCur is\n when idle =>\n if ( doSwitch = '1' ) then\n fsmTopNext <= setVal;\n else\n fsmTopNext <= idle;\n end if;\n \n when setVal =>\n fsmTopNext <= waitVal;\n \n when waitVal =>\n if ( fsmSingleValCur = idle ) then\n if ( itemInd = 13 ) then\n fsmTopNext <= waitLock;\n else\n fsmTopNext <= incInd;\n end if;\n else\n fsmTopNext <= waitVal;\n end if;\n \n when incInd =>\n fsmTopNext <= setVal;\n \n when waitLock =>\n if ( locked = '1' ) then\n fsmTopNext <= idle;\n else\n fsmTopNext <= waitLock;\n end if;\n\n end case;\n end process; \n \n process( fsmTopCur, stateSel_int, itemInd ) is\n begin\n case fsmTopCur is\n when idle =>\n nextMask <= ( others => '-' );\n nextVal <= ( others => '-' );\n nextAddr <= ( others => '-' );\n setNewVal <= '0';\n rstMMCM <= '0'; \n \n when setVal =>\n nextMask <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).mask;\n nextVal <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).data;\n nextAddr <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).addr;\n rstMMCM <= '1';\n setNewVal <= '1';\n \n when waitVal =>\n nextMask <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).mask;\n nextVal <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).data;\n nextAddr <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).addr;\n rstMMCM <= '1';\n setNewVal <= '0';\n \n when incInd =>\n nextMask <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).mask;\n nextVal <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).data;\n nextAddr <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).addr;\n rstMMCM <= '1';\n setNewVal <= '0';\n \n when waitLock =>\n nextMask <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).mask;\n nextVal <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).data;\n nextAddr <= reconfROM( to_integer( unsigned( stateSel_int ) ) )( itemInd ).addr;\n rstMMCM <= '0';\n setNewVal <= '0';\n \n end case;\n end process;\n\n -- FSM for changing a single value.\n process( clk ) is\n begin\n \n if ( rising_edge( clk ) ) then\n if ( rst = '1' ) then\n fsmSingleValCur <= idle;\n else\n fsmSingleValCur <= fsmSingleValNext;\n end if;\n end if;\n end process;\n \n process( fsmSingleValCur, setNewVal, drdy ) is\n begin\n case fsmSingleValCur is\n when idle =>\n if ( setNewVal = '1' ) then\n fsmSingleValNext <= setDADDR;\n else\n fsmSingleValNext <= idle;\n end if;\n \n when setDADDR =>\n fsmSingleValNext <= waitDRDY0;\n \n when waitDRDY0 =>\n if ( drdy = '1' ) then\n fsmSingleValNext <= applyMask;\n else\n fsmSingleValNext <= waitDRDY0;\n end if;\n \n when applyMask =>\n fsmSingleValNext <= doWrite;\n \n when doWrite =>\n fsmSingleValNext <= waitDRDY1;\n \n when waitDRDY1 =>\n if ( drdy = '1' ) then\n fsmSingleValNext <= idle;\n else\n fsmSingleValNext <= waitDRDY1;\n end if;\n \n when others =>\n fsmSingleValNext <= idle;\n end case;\n end process;\n \n process( fsmSingleValCur, nextAddr, maskedVal ) is\n begin\n case fsmSingleValCur is\n when idle =>\n diSig <= ( others => '-' );\n dwe <= '0';\n den <= '0';\n daddr <= ( others => '-' ); \n \n when setDADDR =>\n diSig <= ( others => '-' );\n dwe <= '0';\n den <= '1';\n daddr <= nextAddr;\n \n when waitDRDY0 =>\n diSig <= ( others => '-' );\n dwe <= '0';\n den <= '0';\n daddr <= nextAddr;\n \n when applyMask =>\n diSig <= ( others => '-' );\n dwe <= '0';\n den <= '0';\n daddr <= nextAddr;\n \n when doWrite =>\n diSig <= maskedVal;\n dwe <= '1';\n den <= '1';\n daddr <= nextAddr;\n \n when waitDRDY1 =>\n diSig <= ( others => '-' );\n dwe <= '0';\n den <= '0';\n daddr <= nextAddr; \n end case;\n \n end process;\n\nend rtl;\n", "groundtruth": " process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( fsmSingleValCur = applyMask ) then\n maskedVal <= ( nextMask and doSig ) or ( nextVal and not( nextMask ) ) ;\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/font5x7.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Font 5x7\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nentity font5x7 is\n port(\n char : in integer range 0 to 43;\n x : in integer range 0 to 4;\n y : in integer range 0 to 6;\n \n clk : in std_logic;\n rst : in std_logic;\n \n charPxl : out std_logic\n );\nend entity;\n\narchitecture rtl of font5x7 is\ntype tFontRAM is array( 0 to 43 ) of std_logic_vector( 0 to 34 );\nconstant font : tFontRAM := \n( \"00000000000000000000000000000000000\", -- 0, Space\n \"01110100011000111111100011000110001\", -- 1, A\n \"11110100011000111110100011000111110\", -- 2, B\n \"11111100001000010000100001000011111\", -- 3, C\n \"11110100011000110001100011000111110\", -- 4, D\n \"11111100001000011110100001000011111\", -- 5, E\n \"11111100001000011110100001000010000\", -- 6, F\n \"01111100001000010011100011000101110\", -- 7, G\n \"10001100011000111111100011000110001\", -- 8, H\n \"01110001000010000100001000010001110\", -- 9, I\n \"11111000010000100001000011000101110\", -- 10, J\n \"10001100011001011100100101000110001\", -- 11, K\n \"10000100001000010000100001000011111\", -- 12, L\n \"10001110111010110001100011000110001\", -- 13, M\n \"10001110011100110101100111001110001\", -- 14, N\n \"01110100011000110001100011000101110\", -- 15, O\n \"11110100011000111110100001000010000\", -- 16, P\n \"01110100011000101111000010000100001\", -- 17, Q\n \"11110100011000111110100011000110001\", -- 18, R\n \"01111100001000001110000010000111110\", -- 19, S\n \"11111001000010000100001000010000100\", -- 20, T\n \"10001100011000110001100011000101110\", -- 21, U\n \"10001100011000101010010100010000100\", -- 22, V\n \"10001100011000110001100011010101010\", -- 23, W\n \"10001100010101000100010101000110001\", -- 24, X\n \"10001100010101000100001000010000100\", -- 25, Y\n \"11111000010001000100010001000011111\", -- 26, Z\n \"00100011000010000100001000010001110\", -- 27, 1\n \"01110100010000100010001000100011111\", -- 28, 2\n \"01110100010000100110000011000101110\", -- 29, 3\n \"10000100001010011111001000010000100\", -- 30, 4\n \"11111100001000001110000010000111110\", -- 31, 5\n \"01111110001000010110110011000101110\", -- 32, 6\n \"11111000010001000100010001000010000\", -- 33, 7\n \"01110100011000101110100011000101110\", -- 34, 8\n \"01110100011000101111000010000100001\", -- 35, 9\n \"00000000000000000000000000000000100\", -- 36, .\n \"00000010000010000010001000100000000\", -- 37, > \n \"00000000100010001000001000001000000\", -- 38, < \n \"00001000100001000100010000100010000\", -- 39, / \n \"10000010000100000100000100001000001\", -- 40, \\\n \"00100001000010000100001000010000100\", -- 41, |\n \"00000001000010000000001000010000000\", -- 42, :\n \"00000000000000011111000000000000000\" -- 43, -\n );\nbegin\n\n process( clk ) is\n variable offset : integer range 0 to 30;\n variable ind : integer range 0 to 34;\n begin\n if ( rising_edge( clk ) ) then\n if ( rst = '1' ) then\n charPxl <= '0';\n else\n offset := 0;\n case y is\n when 0 => offset := 0;\n when 1 => offset := 5;\n when 2 => offset := 10;\n when 3 => offset := 15;\n when 4 => offset := 20;\n when 5 => offset := 25;\n when 6 => offset := 30;\n end case;\n \n", "right_context": "", "groundtruth": " ind := offset + x;\n \n charPxl <= font( char )( ind );\n end if;\n end if;\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/fracDiv.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Fractional Divier\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.numeric_std.all;\n\nentity fracDiv is\n generic (\n mul : integer;\n div : integer;\n maxInt : integer\n );\n port (\n clk : in std_logic;\n rst : in std_logic;\n clkOut : out std_logic\n );\nend fracDiv;\n\narchitecture rtl of fracDiv is\nsignal cnt : integer range 0 to maxInt;\nbegin\n\n \n process( clk ) is \n variable tmpCnt : integer range 0 to maxInt;\n begin\n if ( rising_edge( clk ) ) then \n if ( rst = '1' ) then\n cnt <= 0;\n else\n tmpCnt := cnt + mul;\n if ( tmpCnt >= div ) then\n tmpCnt := tmpCnt - div;\n", "right_context": " clkOut <= '0' when ( cnt <= div / 2 ) else '1';\n \nend rtl;\n", "groundtruth": " end if;\n \n cnt <= tmpCnt;\n end if;\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/gbaShaderApprox.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: GBA color correction\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.numeric_std.all;\n\nentity gbaColorCorr is\n port(\n gbaRed : in std_logic_vector( 4 downto 0 );\n gbaGreen : in std_logic_vector( 4 downto 0 );\n gbaBlue : in std_logic_vector( 4 downto 0 );\n \n rGBACol : out std_logic_vector( 7 downto 0 );\n gGBACol : out std_logic_vector( 7 downto 0 );\n bGBACol : out std_logic_vector( 7 downto 0 )\n );\nend gbaColorCorr;\n\narchitecture rtl of gbaColorCorr is\nsignal baseRed, baseGreen, baseBlue : std_logic_vector( 7 downto 0 );\nbegin\n\n process( baseRed, baseGreen, baseBlue, gbaRed, gbaGreen, gbaBlue ) is\n variable tmpRed, tmpGreen, tmpBlue : signed( 9 downto 0 );\n begin\n tmpRed := signed( \"00\" & baseRed ) + signed( \"00000000\" & gbaRed( 1 downto 0 ) ) + signed( \"0000\" & gbaGreen( 4 downto 0 ) & '0' ) - signed( \"00000\" & gbaBlue );\n if ( tmpRed < 0 ) then\n tmpRed := to_signed( 0, tmpRed'length );\n elsif ( tmpRed > 255 ) then\n tmpRed := to_signed( 255, tmpRed'length ); \n end if;\n \n tmpGreen := signed( \"00\" & baseGreen ) + signed( \"0000\" & gbaRed( 4 downto 0 ) & '0' ) - signed( \"00000\" & gbaGreen( 4 downto 0 ) ) + signed( \"000000\" & gbaBlue( 3 downto 0 ) );\n if ( tmpGreen < 0 ) then\n tmpGreen := to_signed( 0, tmpGreen'length );\n elsif ( tmpGreen > 255 ) then\n tmpGreen := to_signed( 255, tmpGreen'length ); \n end if;\n \n tmpBlue := signed( \"00\" & baseBlue ) + signed( \"00000000\" & gbaRed( 1 downto 0 ) ) + signed( \"0000\" & gbaGreen( 4 downto 0 ) & '0' ) - signed( \"00000\" & gbaBlue( 4 downto 0 ) );\n if ( tmpBlue < 0 ) then\n tmpBlue := to_signed( 0, tmpBlue'length );\n elsif ( tmpBlue > 255 ) then\n tmpBlue := to_signed( 255, tmpBlue'length ); \n end if;\n \n rGBACol <= std_logic_vector( tmpRed( 7 downto 0 ) );\n gGBACol <= std_logic_vector( tmpGreen( 7 downto 0 ) );\n bGBACol <= std_logic_vector( tmpBlue( 7 downto 0 ) );\n end process;\n \nprocess( gbaRed ) is begin\n", "right_context": " when \"01000\" => baseRed <= \"00100011\";\n when \"01001\" => baseRed <= \"00101001\";\n when \"01010\" => baseRed <= \"00110000\";\n when \"01011\" => baseRed <= \"00110111\";\n when \"01100\" => baseRed <= \"00111110\";\n when \"01101\" => baseRed <= \"01000101\";\n when \"01110\" => baseRed <= \"01001101\";\n when \"01111\" => baseRed <= \"01010100\";\n when \"10000\" => baseRed <= \"01011100\";\n when \"10001\" => baseRed <= \"01100101\";\n when \"10010\" => baseRed <= \"01101101\";\n when \"10011\" => baseRed <= \"01110110\";\n when \"10100\" => baseRed <= \"01111110\";\n when \"10101\" => baseRed <= \"10000111\";\n when \"10110\" => baseRed <= \"10010000\";\n when \"10111\" => baseRed <= \"10011010\";\n when \"11000\" => baseRed <= \"10100011\";\n when \"11001\" => baseRed <= \"10101101\";\n when \"11010\" => baseRed <= \"10110110\";\n when \"11011\" => baseRed <= \"11000000\";\n when \"11100\" => baseRed <= \"11001010\";\n when \"11101\" => baseRed <= \"11010100\";\n when \"11110\" => baseRed <= \"11011111\";\n when \"11111\" => baseRed <= \"11101001\";\n end case;\nend process;\nprocess( gbaGreen ) is begin\n case gbaGreen is \n when \"00000\" => baseGreen <= \"00000000\";\n when \"00001\" => baseGreen <= \"00000001\";\n when \"00010\" => baseGreen <= \"00000100\";\n when \"00011\" => baseGreen <= \"00001000\";\n when \"00100\" => baseGreen <= \"00001011\";\n when \"00101\" => baseGreen <= \"00010000\";\n when \"00110\" => baseGreen <= \"00010101\";\n when \"00111\" => baseGreen <= \"00011010\";\n when \"01000\" => baseGreen <= \"00011111\";\n when \"01001\" => baseGreen <= \"00100101\";\n when \"01010\" => baseGreen <= \"00101011\";\n when \"01011\" => baseGreen <= \"00110001\";\n when \"01100\" => baseGreen <= \"00110111\";\n when \"01101\" => baseGreen <= \"00111110\";\n when \"01110\" => baseGreen <= \"01000100\";\n when \"01111\" => baseGreen <= \"01001011\";\n when \"10000\" => baseGreen <= \"01010010\";\n when \"10001\" => baseGreen <= \"01011010\";\n when \"10010\" => baseGreen <= \"01100001\";\n when \"10011\" => baseGreen <= \"01101001\";\n when \"10100\" => baseGreen <= \"01110001\";\n when \"10101\" => baseGreen <= \"01111001\";\n when \"10110\" => baseGreen <= \"10000001\";\n when \"10111\" => baseGreen <= \"10001001\";\n when \"11000\" => baseGreen <= \"10010010\";\n when \"11001\" => baseGreen <= \"10011010\";\n when \"11010\" => baseGreen <= \"10100011\";\n when \"11011\" => baseGreen <= \"10101100\";\n when \"11100\" => baseGreen <= \"10110101\";\n when \"11101\" => baseGreen <= \"10111110\";\n when \"11110\" => baseGreen <= \"11000111\";\n when \"11111\" => baseGreen <= \"11010000\";\n end case;\nend process;\nprocess( gbaBlue ) is begin\n case gbaBlue is \n when \"00000\" => baseBlue <= \"00000000\";\n when \"00001\" => baseBlue <= \"00000001\";\n when \"00010\" => baseBlue <= \"00000100\";\n when \"00011\" => baseBlue <= \"00001000\";\n when \"00100\" => baseBlue <= \"00001100\";\n when \"00101\" => baseBlue <= \"00010001\";\n when \"00110\" => baseBlue <= \"00010110\";\n when \"00111\" => baseBlue <= \"00011011\";\n when \"01000\" => baseBlue <= \"00100001\";\n when \"01001\" => baseBlue <= \"00100111\";\n when \"01010\" => baseBlue <= \"00101101\";\n when \"01011\" => baseBlue <= \"00110011\";\n when \"01100\" => baseBlue <= \"00111010\";\n when \"01101\" => baseBlue <= \"01000001\";\n when \"01110\" => baseBlue <= \"01001000\";\n when \"01111\" => baseBlue <= \"01010000\";\n when \"10000\" => baseBlue <= \"01010111\";\n when \"10001\" => baseBlue <= \"01011111\";\n when \"10010\" => baseBlue <= \"01100111\";\n when \"10011\" => baseBlue <= \"01101111\";\n when \"10100\" => baseBlue <= \"01110111\";\n when \"10101\" => baseBlue <= \"10000000\";\n when \"10110\" => baseBlue <= \"10001000\";\n when \"10111\" => baseBlue <= \"10010001\";\n when \"11000\" => baseBlue <= \"10011010\";\n when \"11001\" => baseBlue <= \"10100011\";\n when \"11010\" => baseBlue <= \"10101100\";\n when \"11011\" => baseBlue <= \"10110101\";\n when \"11100\" => baseBlue <= \"10111111\";\n when \"11101\" => baseBlue <= \"11001000\";\n when \"11110\" => baseBlue <= \"11010010\";\n when \"11111\" => baseBlue <= \"11011100\";\n end case;\nend process;\n\nend rtl;\n", "groundtruth": " case gbaRed is \n when \"00000\" => baseRed <= \"00000000\";\n when \"00001\" => baseRed <= \"00000001\";\n when \"00010\" => baseRed <= \"00000101\";\n when \"00011\" => baseRed <= \"00001000\";\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/gbaShader_new.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: GBA color correction (updated)\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.numeric_std.all;\n\n", "right_context": " gGBACol : out std_logic_vector( 7 downto 0 );\n bGBACol : out std_logic_vector( 7 downto 0 )\n );\nend gbaColorCorrNew;\n\narchitecture rtl of gbaColorCorrNew is\nsignal redT, greenT, blueT : std_logic_vector( 7 downto 0 );\nbegin\n\n rGBACol <= redT;\n gGBACol <= greenT;\n bGBACol <= blueT;\n\n process( gbaRed ) is begin\n case gbaRed is\n when \"00000\" => redT <= \"00000000\";\n when \"00001\" => redT <= \"00001000\";\n when \"00010\" => redT <= \"00001111\";\n when \"00011\" => redT <= \"00010111\";\n when \"00100\" => redT <= \"00011110\";\n when \"00101\" => redT <= \"00100110\";\n when \"00110\" => redT <= \"00101101\";\n when \"00111\" => redT <= \"00110101\";\n when \"01000\" => redT <= \"00111101\";\n when \"01001\" => redT <= \"01000100\";\n when \"01010\" => redT <= \"01001100\";\n when \"01011\" => redT <= \"01010011\";\n when \"01100\" => redT <= \"01011011\";\n when \"01101\" => redT <= \"01100011\";\n when \"01110\" => redT <= \"01101010\";\n when \"01111\" => redT <= \"01110010\";\n when \"10000\" => redT <= \"01111001\";\n when \"10001\" => redT <= \"10000001\";\n when \"10010\" => redT <= \"10001000\";\n when \"10011\" => redT <= \"10010000\";\n when \"10100\" => redT <= \"10011000\";\n when \"10101\" => redT <= \"10011111\";\n when \"10110\" => redT <= \"10100111\";\n when \"10111\" => redT <= \"10101110\";\n when \"11000\" => redT <= \"10110110\";\n when \"11001\" => redT <= \"10111110\";\n when \"11010\" => redT <= \"11000101\";\n when \"11011\" => redT <= \"11001101\";\n when \"11100\" => redT <= \"11010100\";\n when \"11101\" => redT <= \"11011100\";\n when \"11110\" => redT <= \"11100011\";\n when \"11111\" => redT <= \"11101011\";\n end case;\n end process;\n\n process( gbaGreen ) is begin\n case gbaGreen is\n when \"00000\" => greenT <= \"00000000\";\n when \"00001\" => greenT <= \"00000111\";\n when \"00010\" => greenT <= \"00001110\";\n when \"00011\" => greenT <= \"00010101\";\n when \"00100\" => greenT <= \"00011100\";\n when \"00101\" => greenT <= \"00100100\";\n when \"00110\" => greenT <= \"00101011\";\n when \"00111\" => greenT <= \"00110010\";\n when \"01000\" => greenT <= \"00111001\";\n when \"01001\" => greenT <= \"01000000\";\n when \"01010\" => greenT <= \"01000111\";\n when \"01011\" => greenT <= \"01001110\";\n when \"01100\" => greenT <= \"01010101\";\n when \"01101\" => greenT <= \"01011100\";\n when \"01110\" => greenT <= \"01100011\";\n when \"01111\" => greenT <= \"01101011\";\n when \"10000\" => greenT <= \"01110010\";\n when \"10001\" => greenT <= \"01111001\";\n when \"10010\" => greenT <= \"10000000\";\n when \"10011\" => greenT <= \"10000111\";\n when \"10100\" => greenT <= \"10001110\";\n when \"10101\" => greenT <= \"10010101\";\n when \"10110\" => greenT <= \"10011100\";\n when \"10111\" => greenT <= \"10100011\";\n when \"11000\" => greenT <= \"10101010\";\n when \"11001\" => greenT <= \"10110010\";\n when \"11010\" => greenT <= \"10111001\";\n when \"11011\" => greenT <= \"11000000\";\n when \"11100\" => greenT <= \"11000111\";\n when \"11101\" => greenT <= \"11001110\";\n when \"11110\" => greenT <= \"11010101\";\n when \"11111\" => greenT <= \"11011100\";\n end case;\n end process;\n\n process( gbaBlue ) is begin\n case gbaBlue is\n when \"00000\" => blueT <= \"00000000\";\n when \"00001\" => blueT <= \"00000111\";\n when \"00010\" => blueT <= \"00001111\";\n when \"00011\" => blueT <= \"00010110\";\n when \"00100\" => blueT <= \"00011101\";\n when \"00101\" => blueT <= \"00100101\";\n when \"00110\" => blueT <= \"00101100\";\n when \"00111\" => blueT <= \"00110011\";\n when \"01000\" => blueT <= \"00111011\";\n when \"01001\" => blueT <= \"01000010\";\n when \"01010\" => blueT <= \"01001001\";\n when \"01011\" => blueT <= \"01010000\";\n when \"01100\" => blueT <= \"01011000\";\n when \"01101\" => blueT <= \"01011111\";\n when \"01110\" => blueT <= \"01100110\";\n when \"01111\" => blueT <= \"01101110\";\n when \"10000\" => blueT <= \"01110101\";\n when \"10001\" => blueT <= \"01111100\";\n when \"10010\" => blueT <= \"10000100\";\n when \"10011\" => blueT <= \"10001011\";\n when \"10100\" => blueT <= \"10010010\";\n when \"10101\" => blueT <= \"10011010\";\n when \"10110\" => blueT <= \"10100001\";\n when \"10111\" => blueT <= \"10101000\";\n when \"11000\" => blueT <= \"10110000\";\n when \"11001\" => blueT <= \"10110111\";\n when \"11010\" => blueT <= \"10111110\";\n when \"11011\" => blueT <= \"11000101\";\n when \"11100\" => blueT <= \"11001101\";\n when \"11101\" => blueT <= \"11010100\";\n when \"11110\" => blueT <= \"11011011\";\n when \"11111\" => blueT <= \"11100011\";\n end case;\n end process;\n\nend rtl;\n", "groundtruth": "entity gbaColorCorrNew is\n port(\n gbaRed : in std_logic_vector( 4 downto 0 );\n gbaGreen : in std_logic_vector( 4 downto 0 );\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/lineBuffer.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Line buffer\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse ieee.numeric_std.all;\n\nentity lineBuffer is\n generic(\n nrStgs : integer range 1 to 20 := 4\n );\n port(\n clkW : in std_logic;\n clkR : in std_logic;\n rst : in std_logic;\n redIn : in std_logic_vector( 7 downto 0 );\n greenIn : in std_logic_vector( 7 downto 0 );\n blueIn : in std_logic_vector( 7 downto 0 );\n wEn : in std_logic;\n pxlCntWrite : in std_logic_vector( 7 downto 0 );\n pushLine : in std_logic;\n newFrameIn : in std_logic;\n \n redOutPrev : out std_logic_vector( 7 downto 0 );\n greenOutPrev : out std_logic_vector( 7 downto 0 );\n blueOutPrev : out std_logic_vector( 7 downto 0 );\n redOutCur : out std_logic_vector( 7 downto 0 );\n greenOutCur : out std_logic_vector( 7 downto 0 );\n blueOutCur : out std_logic_vector( 7 downto 0 );\n redOutNext : out std_logic_vector( 7 downto 0 );\n greenOutNext : out std_logic_vector( 7 downto 0 );\n blueOutNext : out std_logic_vector( 7 downto 0 );\n \n pxlCntRead : in std_logic_vector( 7 downto 0 );\n pullLine : in std_logic;\n \n sameLine : out std_logic;\n newFrameOut : out std_logic\n );\nend lineBuffer;\n\narchitecture rtl of lineBuffer is\nsignal inCnt : integer range 0 to nrStgs-1;\nsignal outCntCur, outCntPrev, outCntNext : integer range 0 to nrStgs-1;\nsignal inCntSel, outCntCurSel, outCntPrevSel, outCntNextSel : std_logic;\nsignal newFrames_sel0, newFrames_sel1 : std_logic_vector( nrStgs - 1 downto 0 );\nsignal wEnMult : std_logic_vector( nrStgs - 1 downto 0 );\n\ntype readDataMult is array (0 to nrStgs - 1) of std_logic_vector( 7 downto 0 );\nsignal redOut_int : readDataMult;\nsignal greenOut_int : readDataMult;\nsignal blueOut_int : readDataMult;\n\nsignal readAddr, writeAddr : std_logic_vector( 8 downto 0 );\nsignal readSel : std_logic_vector( 0 to nrStgs - 1 );\n\nbegin\n\n process( wEn, inCnt ) is\n begin\n \n for i in 0 to nrStgs - 1 loop\n if ( inCnt = i ) then\n wEnMult( i ) <= wEn;\n else\n wEnMult( i ) <= '0';\n end if;\n end loop;\n \n end process;\n \n redOutPrev <= redOut_int( outCntPrev );\n greenOutPrev <= greenOut_int( outCntPrev );\n blueOutPrev <= blueOut_int( outCntPrev );\n \n redOutCur <= redOut_int( outCntCur );\n greenOutCur <= greenOut_int( outCntCur );\n blueOutCur <= blueOut_int( outCntCur );\n \n redOutNext <= redOut_int( outCntNext );\n greenOutNext <= greenOut_int( outCntNext );\n blueOutNext <= blueOut_int( outCntNext );\n \n process( outCntCurSel, outCntPrevSel, outCntNextSel,\n outCntCur, outCntPrev, outCntNext ) is\n begin\n for i in 0 to nrStgs - 1 loop\n if ( ( outCntCur = i and outCntCurSel = '1' ) or\n ( outCntPrev = i and outCntPrevSel = '1' ) or\n ( outCntNext = i and outCntNextSel = '1' ) ) then\n readSel( i ) <= '1';\n else\n", "right_context": " if ( rising_edge( clkW ) ) then\n if ( rst = '1' ) then\n inCnt <= 0;\n inCntSel <= '0';\n newFrames_Sel0 <= ( others => '0' );\n newFrames_Sel1 <= ( others => '0' );\n else\n if ( pushLine = '1' ) then\n if ( inCntSel = '1' ) then\n newFrames_Sel1( inCnt ) <= newFrameIn;\n else\n newFrames_Sel0( inCnt ) <= newFrameIn;\n end if;\n \n if ( inCnt = nrStgs - 1 ) then\n inCnt <= 0;\n inCntSel <= not inCntSel;\n else\n inCnt <= inCnt + 1;\n end if;\n end if;\n end if;\n end if;\n end process;\n \n process( clkR ) is\n begin\n if ( rising_edge( clkR ) ) then\n if ( rst = '1' ) then\n outCntPrev <= nrStgs - 1;\n outCntCur <= 0;\n outCntNext <= 1;\n outCntPrevSel <= '1';\n outCntCurSel <= '0';\n outCntNextSel <= '0';\n else\n if ( pullLine = '1' ) then\n if ( outCntCur = nrStgs - 1 ) then\n outCntCur <= 0;\n outCntCurSel <= not outCntCurSel;\n else\n outCntCur <= outCntCur + 1;\n end if;\n \n if ( outCntPrev = nrStgs - 1 ) then\n outCntPrev <= 0;\n outCntPrevSel <= not outCntPrevSel;\n else\n outCntPrev <= outCntPrev + 1;\n end if;\n \n if ( outCntNext = nrStgs - 1 ) then\n outCntNext <= 0;\n outCntNextSel <= not outCntNextSel;\n else\n outCntNext <= outCntNext + 1;\n end if;\n end if;\n end if;\n end if;\n end process;\n \n sameLine <= '1' when ( inCnt = outCntCur and inCntSel = outCntCurSel ) else '0';\n newFrameOut <= newFrames_Sel0( outCntCur ) when outCntCurSel = '0' else newFrames_Sel1( outCntCur );\n writeAddr <= inCntSel & pxlCntWrite;\n \n -- Instantiate buffers.\n gen_buffers : for i in 0 to nrStgs - 1 generate\n curBuff : entity work.singeLineBuffer( rtl )\n port map(\n clkW => clkW,\n clkR => clkR, \n rst => rst,\n wAddr => writeAddr,\n wEn => wEnMult( i ),\n rAddr( 8 ) => readSel( i ),\n rAddr( 7 downto 0 ) => pxlCntRead,\n redDataIn => redIn,\n greenDataIn => greenIn,\n blueDataIn => blueIn,\n redDataOut => redOut_int( i ),\n greenDataOut => greenOut_int( i ),\n blueDataOut => blueOut_int( i ) \n );\n end generate gen_buffers;\n\nend rtl;", "groundtruth": " readSel( i ) <= '0';\n end if;\n end loop;\n end process;\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/lineCache.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Line Cache\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse ieee.numeric_std.all;\nuse IEEE.std_logic_misc.all;\n\nentity lineCache is \n port(\n clk : in std_logic;\n", "right_context": " curPxlCnt : in std_logic_vector( 7 downto 0 );\n lineChange : in std_logic;\n \n curLineCurPxlRedIn : in std_logic_vector( 7 downto 0 );\n curLineCurPxlGreenIn : in std_logic_vector( 7 downto 0 );\n curLineCurPxlBlueIn : in std_logic_vector( 7 downto 0 );\n \n prevLineCurPxlRedIn : in std_logic_vector( 7 downto 0 );\n prevLineCurPxlGreenIn : in std_logic_vector( 7 downto 0 );\n prevLineCurPxlBlueIn : in std_logic_vector( 7 downto 0 );\n \n nextLineCurPxlRedIn : in std_logic_vector( 7 downto 0 );\n nextLineCurPxlGreenIn : in std_logic_vector( 7 downto 0 );\n nextLineCurPxlBlueIn : in std_logic_vector( 7 downto 0 );\n \n prevLinePrevPxlRedOut : out std_logic_vector( 7 downto 0 );\n prevLinePrevPxlGreenOut : out std_logic_vector( 7 downto 0 );\n prevLinePrevPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n prevLineCurPxlRedOut : out std_logic_vector( 7 downto 0 );\n prevLineCurPxlGreenOut : out std_logic_vector( 7 downto 0 );\n prevLineCurPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n prevLineNextPxlRedOut : out std_logic_vector( 7 downto 0 );\n prevLineNextPxlGreenOut : out std_logic_vector( 7 downto 0 );\n prevLineNextPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n curLinePrevPxlRedOut : out std_logic_vector( 7 downto 0 );\n curLinePrevPxlGreenOut : out std_logic_vector( 7 downto 0 );\n curLinePrevPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n curLineCurPxlRedOut : out std_logic_vector( 7 downto 0 );\n curLineCurPxlGreenOut : out std_logic_vector( 7 downto 0 );\n curLineCurPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n curLineNextPxlRedOut : out std_logic_vector( 7 downto 0 );\n curLineNextPxlGreenOut : out std_logic_vector( 7 downto 0 );\n curLineNextPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n nextLinePrevPxlRedOut : out std_logic_vector( 7 downto 0 );\n nextLinePrevPxlGreenOut : out std_logic_vector( 7 downto 0 );\n nextLinePrevPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n nextLineCurPxlRedOut : out std_logic_vector( 7 downto 0 );\n nextLineCurPxlGreenOut : out std_logic_vector( 7 downto 0 );\n nextLineCurPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n nextLineNextPxlRedOut : out std_logic_vector( 7 downto 0 );\n nextLineNextPxlGreenOut : out std_logic_vector( 7 downto 0 );\n nextLineNextPxlBlueOut : out std_logic_vector( 7 downto 0 );\n \n pxlCntRead : out std_logic_vector( 7 downto 0 )\n );\nend lineCache;\n\narchitecture rtl of lineCache is\ntype pixel is array( 0 to 2 ) of std_logic_vector( 7 downto 0 );\nsignal curLinePrevPxl, curLineCurPxl, curLineNextPxl, \n prevLinePrevPxl, prevLineCurPxl, prevLineNextPxl,\n nextLinePrevPxl, nextLineCurPxl, nextLineNextPxl : pixel;\n \nsignal pxlCntRead_int, pxlCntRead_del, pxlCntRead_del2 : std_logic_vector( 7 downto 0 );\nsignal incAddr, firstPxlHandled, shiftRegs, lineChange_del : std_logic;\nbegin\n \n process( clk ) is\n begin\n if rising_edge( clk ) then\n if ( rst = '1' ) then\n pxlCntRead_del <= ( others => '0' );\n pxlCntRead_del2 <= ( others => '0' );\n firstPxlHandled <= '0';\n lineChange_del <= '0';\n else\n pxlCntRead_del <= pxlCntRead_int;\n pxlCntRead_del2 <= pxlCntRead_del;\n lineChange_del <= lineChange;\n \n if ( curPxlCnt = \"00000000\" ) then\n firstPxlHandled <= '1';\n else\n firstPxlHandled <= '0';\n end if;\n \n if ( lineChange_del = '1' ) then\n firstPxlHandled <= '0';\n end if;\n \n curLineNextPxl( 0 ) <= curLineCurPxlRedIn;\n curLineNextPxl( 1 ) <= curLineCurPxlGreenIn;\n curLineNextPxl( 2 ) <= curLineCurPxlBlueIn;\n \n prevLineNextPxl( 0 ) <= prevLineCurPxlRedIn;\n prevLineNextPxl( 1 ) <= prevLineCurPxlGreenIn;\n prevLineNextPxl( 2 ) <= prevLineCurPxlBlueIn;\n \n nextLineNextPxl( 0 ) <= nextLineCurPxlRedIn;\n nextLineNextPxl( 1 ) <= nextLineCurPxlGreenIn;\n nextLineNextPxl( 2 ) <= nextLineCurPxlBlueIn;\n \n \n if ( shiftRegs = '1' ) then\n curLineCurPxl <= curLineNextPxl;\n curLinePrevPxl <= curLineCurPxl;\n \n prevLineCurPxl <= prevLineNextPxl;\n prevLinePrevPxl <= prevLineCurPxl;\n \n nextLineCurPxl <= nextLineNextPxl;\n nextLinePrevPxl <= nextLineCurPxl;\n end if;\n \n end if;\n end if;\n end process;\n \n incAddr <= '0' when curPxlCnt = \"00000000\" and firstPxlHandled = '0' else '1';\n pxlCntRead_int <= std_logic_vector( unsigned( curPxlCnt ) + 1 ) when incAddr = '1' else\n curPxlCnt;\n\n pxlCntRead <= pxlCntRead_int;\n \n shiftRegs <= '1' when pxlCntRead_del /= pxlCntRead_del2 else '0';\n \n prevLinePrevPxlRedOut <= prevLinePrevPxl( 0 );\n prevLinePrevPxlGreenOut <= prevLinePrevPxl( 1 );\n prevLinePrevPxlBlueOut <= prevLinePrevPxl( 2 );\n \n prevLineCurPxlRedOut <= prevLineCurPxl( 0 );\n prevLineCurPxlGreenOut <= prevLineCurPxl( 1 );\n prevLineCurPxlBlueOut <= prevLineCurPxl( 2 );\n \n prevLineNextPxlRedOut <= prevLineNextPxl( 0 );\n prevLineNextPxlGreenOut <= prevLineNextPxl( 1 );\n prevLineNextPxlBlueOut <= prevLineNextPxl( 2 );\n \n curLinePrevPxlRedOut <= curLinePrevPxl( 0 );\n curLinePrevPxlGreenOut <= curLinePrevPxl( 1 );\n curLinePrevPxlBlueOut <= curLinePrevPxl( 2 );\n \n curLineCurPxlRedOut <= curLineCurPxl( 0 );\n curLineCurPxlGreenOut <= curLineCurPxl( 1 );\n curLineCurPxlBlueOut <= curLineCurPxl( 2 );\n \n curLineNextPxlRedOut <= curLineNextPxl( 0 );\n curLineNextPxlGreenOut <= curLineNextPxl( 1 );\n curLineNextPxlBlueOut <= curLineNextPxl( 2 );\n \n nextLinePrevPxlRedOut <= nextLinePrevPxl( 0 );\n nextLinePrevPxlGreenOut <= nextLinePrevPxl( 1 );\n nextLinePrevPxlBlueOut <= nextLinePrevPxl( 2 );\n \n nextLineCurPxlRedOut <= nextLineCurPxl( 0 );\n nextLineCurPxlGreenOut <= nextLineCurPxl( 1 );\n nextLineCurPxlBlueOut <= nextLineCurPxl( 2 );\n \n nextLineNextPxlRedOut <= nextLineNextPxl( 0 );\n nextLineNextPxlGreenOut <= nextLineNextPxl( 1 );\n nextLineNextPxlBlueOut <= nextLineNextPxl( 2 );\n \nend rtl;\n", "groundtruth": " rst : in std_logic;\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/osd.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: OSD\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.numeric_std.ALL;\n\nentity osd is\n generic(\n scale : integer;\n frameWidth : integer;\n frameHeight : integer\n );\n port(\n pxlX : in integer range 0 to 1665;\n pxlY : in integer range -25 to 1000;\n osdEnableIn : in std_logic;\n clk : in std_logic;\n rst : in std_logic;\n \n osdRed : out std_logic_vector( 7 downto 0 );\n osdGreen : out std_logic_vector( 7 downto 0 );\n osdBlue : out std_logic_vector( 7 downto 0 );\n \n smooth2xIn : in std_logic;\n smooth4xIn : in std_logic;\n pixelGridIn : in std_logic;\n bgridIn : in std_logic;\n gridMultIn : in std_logic;\n colorModeIn : in std_logic;\n rateIn : in std_logic;\n controllerOSDActive : in std_logic;\n \n osdEnableOut : out std_logic;\n smooth2xOut : out std_logic;\n smooth4xOut : out std_logic;\n pixelGridOut : out std_logic;\n bgridOut : out std_logic;\n gridMultOut : out std_logic;\n colorModeOut : out std_logic;\n rateOut : out std_logic;\n \n osdState : in std_logic_vector( 7 downto 0 );\n \n configValid : in std_logic;\n stateValid : in std_logic;\n rxValid : in std_logic\n );\nend entity;\n\narchitecture rtl of osd is\n-- Assuming the resolution is 1280x720\nconstant MENU_WIDTHFIELDS : integer := 27;\nconstant MENU_HEIGHTFIELDS : integer := 12;\nconstant CHARWIDTH : integer := 5;\nconstant CHARHEIGHT : integer := 7;\nconstant CHARSPACE : integer := 1;\nconstant FIELDHEIGHT : integer := CHARHEIGHT + CHARSPACE;\nconstant FIELDWIDTH : integer := CHARWIDTH + CHARSPACE;\nconstant MENUSTARTX : integer := (frameWidth/2) - ( ( ( FIELDWIDTH * MENU_WIDTHFIELDS ) / 2 ) * scale );\nconstant MENUSTARTY : integer := (frameHeight/2) - ( ( ( FIELDHEIGHT * MENU_HEIGHTFIELDS ) / 2) * scale );\nconstant MENUENDX : integer := MENUSTARTX + ( FIELDWIDTH * MENU_WIDTHFIELDS * scale );\nconstant MENUENDY : integer := MENUSTARTY + ( FIELDHEIGHT * MENU_HEIGHTFIELDS * scale );\nconstant PXLGRIDFIELDX : integer := 15;\nconstant PXLGRIDFIELDY : integer := 3;\nconstant GRIDMULTFIELDX : integer := 15;\nconstant GRIDMULTFIELDY : integer := PXLGRIDFIELDY + 1;\nconstant SMOOTHFIELDX : integer := 15;\nconstant SMOOTHFIELDY : integer := GRIDMULTFIELDY + 1;\nconstant COLORFIELDX : integer := 15;\nconstant COLORFIELDY : integer := SMOOTHFIELDY + 1;\nconstant FRAMEFIELDX : integer := 15;\nconstant FRAMEFIELDY : integer := COLORFIELDY + 1;\nconstant PADDISPFIELDX : integer := 15;\nconstant PADDISPFIELDY : integer := FRAMEFIELDY + 1;\n\ntype tLine is array( 0 to MENU_WIDTHFIELDS - 1 ) of integer range 0 to 43;\ntype tMenuFrame is array( 0 to MENU_HEIGHTFIELDS - 1 ) of tLine;\n\nattribute ram_style : string;\nsignal mainMenu : tMenuFrame := (\n-- One empty line\n( 39, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 40 ),\n-- GBAHD v1.4B\n( 41, 00, 00, 00, 00, 00, 00, 00, 07, 02, 01, 08, 04, 00, 27, 36, 30, 02, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- One empty line\n( 37, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 38 ),\n-- PXL GRID\n( 41, 00, 16, 24, 12, 00, 07, 18, 09, 04, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- Method\n( 41, 00, 13, 05, 20, 08, 15, 04, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- Smoothing\n( 41, 00, 19, 13, 15, 15, 20, 08, 09, 14, 07, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- Color\n( 41, 00, 03, 15, 12, 15, 18, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- Framerate\n( 41, 00, 06, 18, 01, 13, 05, 18, 01, 20, 05, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- Pad display\n( 41, 00, 16, 01, 04, 00, 04, 09, 19, 16, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- One empty line\n( 41, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 41 ),\n-- START: SAVE | B: REVERT\n( 41, 00, 19, 20, 01, 18, 20, 42, 00, 19, 01, 22, 05, 00, 41, 00, 02, 42, 00, 01, 02, 15, 18, 20, 00, 00, 41 ),\n-- Bottom Line\n( 40, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 43, 39 )\n);\n\n-- Have to add this attribute to NOT use RAM (since all is used for the line buffer)\nattribute ram_style of mainMenu : signal is \"registers\";\n\n\nsignal fieldYCnt : integer range 0 to MENU_HEIGHTFIELDS - 1;\nsignal fieldXCnt : integer range 0 to MENU_WIDTHFIELDS - 1;\nsignal pxlXCnt : integer range 0 to FIELDWIDTH - 1;\nsignal pxlYCnt : integer range 0 to FIELDHEIGHT - 1;\n\nsignal menuArea : std_logic;\nsignal curSpace : std_logic;\nsignal nextOSDShow : std_logic;\n\nsignal char, char_reg : integer range 0 to 37;\n-- Have to add this attribute to NOT use RAM (since all is used for the line buffer)\nattribute ram_style of char_reg : signal is \"registers\";\n\nsignal charX : integer range 0 to 4;\nsignal charY: integer range 0 to 6;\nsignal charPxl : std_logic;\n\nsignal scaleCntX, scaleCntY : integer range 0 to SCALE - 1;\n\n-- 0: Normal, 1: GBA mode\nsignal colorMode_int : std_logic;\n\n-- 0: 60hz, 1: 59....\nsignal framerate : std_logic;\n\nsignal smooth2x_int, smooth4x_int, pixelGrid_int, bgrid_int, gridMult_int : std_logic;\n\nsignal lineSelected : integer range 0 to MENU_HEIGHTFIELDS - 1;\nsignal lineActive, osdEnable_int : std_logic;\n\nbegin\n\n smooth2xOut <= smooth2x_int;\n smooth4xOut <= smooth4x_int;\n pixelGridOut <= pixelGrid_int;\n bgridOut <= bgrid_int;\n gridMultOut <= gridMult_int;\n colorModeOut <= colorMode_int;\n rateOut <= framerate;\n \n -- Update menu.\n process( smooth2x_int, smooth4x_int, pixelGrid_int, bgrid_int, gridMult_int, colorMode_int, framerate, controllerOSDActive ) is\n begin\n if ( smooth2x_int = '1' ) then\n -- 2X\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX ) <= 28;\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 1 ) <= 24;\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 2 ) <= 0;\n elsif ( smooth4x_int = '1' ) then\n -- 4X\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX ) <= 30;\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 1 ) <= 24;\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 2 ) <= 0;\n else\n -- OFF\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX ) <= 15;\n mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 1 ) <= 6;\n", "right_context": " mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 3 ) <= 7;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 4 ) <= 8;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 5 ) <= 20;\n else\n -- Dark\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX ) <= 4;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 1 ) <= 1;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 2 ) <= 18;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 3 ) <= 11;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 4 ) <= 0;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 5 ) <= 0;\n \n end if;\n else\n -- OFF\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX ) <= 15;\n mainMenu( PXLGRIDFIELDY )( SMOOTHFIELDX + 1 ) <= 6;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 2 ) <= 6;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 3 ) <= 0;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 4 ) <= 0;\n mainMenu( PXLGRIDFIELDY )( PXLGRIDFIELDX + 5 ) <= 0;\n end if;\n\n if ( gridMult_int = '1' ) then\n -- MULT\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX ) <= 13;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 1 ) <= 21;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 2 ) <= 12;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 3 ) <= 20;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 4 ) <= 0;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 5 ) <= 0;\n else\n -- ADD\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX ) <= 1;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 1 ) <= 4;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 2 ) <= 4;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 3 ) <= 0;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 4 ) <= 0;\n mainMenu( GRIDMULTFIELDY )( GRIDMULTFIELDX + 5 ) <= 0;\n end if;\n \n if ( colorMode_int = '0' ) then\n -- Normal\n mainMenu( COLORFIELDY )( COLORFIELDX ) <= 14;\n mainMenu( COLORFIELDY )( COLORFIELDX + 1 ) <= 15;\n mainMenu( COLORFIELDY )( COLORFIELDX + 2 ) <= 18;\n mainMenu( COLORFIELDY )( COLORFIELDX + 3 ) <= 13;\n mainMenu( COLORFIELDY )( COLORFIELDX + 4 ) <= 1;\n mainMenu( COLORFIELDY )( COLORFIELDX + 5 ) <= 12;\n else\n --GBA\n mainMenu( COLORFIELDY )( COLORFIELDX ) <= 7;\n mainMenu( COLORFIELDY )( COLORFIELDX + 1 ) <= 2;\n mainMenu( COLORFIELDY )( COLORFIELDX + 2 ) <= 1;\n mainMenu( COLORFIELDY )( COLORFIELDX + 3 ) <= 0;\n mainMenu( COLORFIELDY )( COLORFIELDX + 4 ) <= 0;\n mainMenu( COLORFIELDY )( COLORFIELDX + 5 ) <= 0;\n end if;\n \n --60hz\n if ( framerate = '0' ) then\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX ) <= 32;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 1 ) <= 15;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 2 ) <= 8;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 3 ) <= 26;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 4 ) <= 0;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 5 ) <= 0;\n else\n --59.7Hz\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX ) <= 31;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 1 ) <= 35;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 2 ) <= 36;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 3 ) <= 33;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 4 ) <= 8;\n mainMenu( FRAMEFIELDY )( FRAMEFIELDX + 5 ) <= 26;\n end if;\n \n -- Input display\n if ( controllerOSDActive = '0' ) then\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX ) <= 15;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 1 ) <= 6;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 2 ) <= 6;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 3 ) <= 0;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 4 ) <= 0;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 5 ) <= 0;\n else\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX ) <= 15;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 1 ) <= 14;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 2 ) <= 0;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 3 ) <= 0;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 4 ) <= 0;\n mainMenu( PADDISPFIELDY )( PADDISPFIELDX + 5 ) <= 0;\n end if;\n end process;\n \n menuArea <= '1' when ( pxlX >= MENUSTARTX and pxlX < MENUENDX and\n pxlY >= MENUSTARTY and pxlY < MENUENDY ) else '0';\n \n lineActive <= '1' when ( lineSelected = fieldYCnt ) else '0';\n \n curSpace <= '1' when ( pxlXCnt = FIELDWIDTH - 1 or pxlYCnt = FIELDHEIGHT - 1 ) else '0';\n \n char <= mainMenu( fieldYCnt )( fieldXCnt ) when ( curSpace = '0' ) else 0;\n charX <= pxlXCnt when ( menuArea = '1' and curSpace = '0' ) else 0;\n charY <= pxlYCnt when ( menuArea = '1' and curSpace = '0' ) else 0;\n \n \n font_inst : entity work.font5x7( rtl )\n port map(\n char => char,\n x => charX,\n y => charY,\n clk => clk,\n rst => rst,\n charPxl => charPxl\n );\n\n process( clk ) is\n begin\n if ( rising_edge( clk ) ) then\n if ( rst = '1' ) then\n osdEnable_int <= '0';\n fieldYCnt <= 0;\n fieldXCnt <= 0;\n pxlYCnt <= 0;\n pxlXCnt <= 0;\n nextOSDShow <= '0';\n scaleCntX <= 0;\n scaleCntY <= 0;\n \n smooth2x_int <= '0';\n smooth4x_int <= '0';\n pixelGrid_int <= '0';\n gridMult_int <= '0';\n bgrid_int <= '0';\n colorMode_int <= '0';\n framerate <= '0';\n lineSelected <= 3;\n \n char_reg <= 0;\n\n else\n \n nextOSDShow <= menuArea and osdEnable_int;\n char_reg <= char;\n \n if ( rxValid = '1' ) then\n if ( stateValid = '1' ) then\n osdEnable_int <= osdEnableIn;\n lineSelected <= to_integer( unsigned( osdState ) );\n \n elsif ( configValid = '1' ) then\n smooth2x_int <= smooth2xIn;\n smooth4x_int <= smooth4xIn;\n pixelGrid_int <= pixelGridIn;\n bgrid_int <= bgridIn;\n gridMult_int <= gridMultIn;\n colorMode_int <= colorModeIn;\n framerate <= rateIn;\n \n end if;\n \n end if;\n \n -- Zero everything.\n if ( pxlX = 0 and pxlY = 0 ) then\n fieldYCnt <= 0;\n fieldXCnt <= 0;\n pxlYCnt <= 0;\n pxlXCnt <= 0;\n scaleCntX <= 0;\n scaleCntY <= 0;\n end if;\n \n if ( osdEnable_int = '1' and menuArea = '1' ) then\n -- Increase counters.\n if ( scaleCntX = SCALE - 1 ) then\n scaleCntX <= 0;\n else\n scaleCntX <= scaleCntX + 1;\n end if;\n \n if ( scaleCntX = SCALE - 1 ) then\n -- Reached end of a field (X)\n if ( pxlXCnt = FIELDWIDTH - 1 ) then\n pxlXCnt <= 0;\n \n -- Reached end of the menu (X)\n if ( fieldXCnt = MENU_WIDTHFIELDS - 1 ) then\n fieldXCnt <= 0;\n \n if ( scaleCntY = SCALE - 1 ) then\n scaleCntY <= 0;\n else\n scaleCntY <= scaleCntY + 1;\n end if;\n \n if ( scaleCntY = SCALE - 1 ) then\n -- Reached end of a field (Y)\n if ( pxlYCnt = FIELDHEIGHT - 1 ) then\n pxlYCnt <= 0;\n if ( fieldYCnt = MENU_HEIGHTFIELDS - 1 ) then\n fieldYCnt <= 0;\n else\n fieldYCnt <= fieldYCnt + 1;\n end if;\n else\n pxlYCnt <= pxlYCnt + 1;\n end if;\n end if;\n \n else\n fieldXCnt <= fieldXCnt + 1;\n end if;\n else\n \n pxlXCnt <= pxlXCnt + 1;\n end if;\n end if;\n end if;\n \n -- Pipeline outgoing signals.\n osdEnableOut <= nextOSDShow;\n \n if ( lineActive = '1' ) then\n osdRed <= ( others => ( not charPxl ) );\n osdGreen <= ( others => ( not charPxl ) );\n osdBlue <= ( others => ( not charPxl ) );\n else\n osdRed <= ( others => ( charPxl ) );\n osdGreen <= ( others => ( charPxl ) );\n osdBlue <= ( others => ( charPxl ) );\n end if;\n \n end if;\n end if;\n end process;\n\nend rtl;\n", "groundtruth": " mainMenu( SMOOTHFIELDY )( SMOOTHFIELDX + 2 ) <= 6;\n end if;\n \n if ( pixelGrid_int = '1' ) then\n if ( bgrid_int = '1' ) then\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/padOverlay.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Pad overlay generator\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.numeric_std.ALL;\n\nentity padOverlay is\n generic(\n -- PosX is multiplied with scale.\n posX : integer;\n -- PosY is multiplied with scale.\n posY : integer;\n scale : integer;\n frameWidth : integer;\n frameHeight : integer\n );\n \n port(\n pxlX : in integer range 0 to 2300;\n pxlY : in integer range -25 to 1300;\n buttons : in std_logic_vector( 9 downto 0 );\n \n clk : in std_logic;\n rst : in std_logic;\n\n overlayInact : out std_logic;\n overlayAct : out std_logic\n );\nend entity;\n\narchitecture behaviour of padOverlay is\ntype tROMline is array( 0 to 21 ) of integer range 0 to 10;\n-- 0: UP\n-- 1: DOWN\n-- 2: LEFT\n-- 3: RIGHT\n-- 4: A\n-- 5: B\n-- 6: L\n-- 7: R\n-- 8: START\n-- 9: SELECT\n-- 10: NONE\ntype tPadOverlayROM is array( 0 to 11 ) of tROMline;\n-- Changing this overlay also needs a change in the logic.\nconstant overlayROM : tPadOverlayROM := (\n( 10, 10, 06, 06, 06, 06, 06, 06, 10, 10, 10, 10, 10, 10, 07, 07, 07, 07, 07, 07, 10, 10 ),\n( 06, 06, 06, 06, 06, 06, 06, 06, 10, 10, 10, 10, 10, 10, 07, 07, 07, 07, 07, 07, 07, 07 ),\n( 06, 06, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 07, 07 ),\n( 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 ),\n( 10, 10, 10, 10, 00, 00, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 ),\n( 10, 10, 10, 10, 00, 00, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 ),\n( 10, 10, 02, 02, 10, 10, 03, 03, 10, 10, 10, 10, 10, 10, 05, 05, 10, 10, 04, 04, 10, 10 ),\n( 10, 10, 02, 02, 10, 10, 03, 03, 10, 10, 10, 10, 10, 10, 05, 05, 10, 10, 04, 04, 10, 10 ),\n( 10, 10, 10, 10, 01, 01, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 ),\n( 10, 10, 10, 10, 01, 01, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 ),\n( 10, 10, 10, 10, 10, 10, 10, 10, 09, 09, 10, 10, 08, 08, 10, 10, 10, 10, 10, 10, 10, 10 ),\n( 10, 10, 10, 10, 10, 10, 10, 10, 09, 09, 10, 10, 08, 08, 10, 10, 10, 10, 10, 10, 10, 10 )\n);\n \nsignal scaleCntX, scaleCntY : integer range 0 to scale - 1;\n\nsignal pxlXCnt : integer range 0 to frameWidth - 1;\nsignal pxlYCnt : integer range 0 to frameHeight - 1;\n\nsignal pxlXCnt_sub : integer range -frameWidth to frameWidth - 1;\nsignal pxlYCnt_sub : integer range -frameHeight to frameHeight - 1;\n", "right_context": " process( clk ) is\n begin\n if rising_edge( clk ) then\n if ( rst = '1' ) then\n pxlXCnt <= 0;\n pxlYCnt <= 0;\n pxlXCnt_sub <= 0;\n pxlYCnt_sub <= 0;\n scaleCntX <= 0;\n scaleCntY <= 0;\n \n butUp <= '0';\n butDown <= '0';\n butLeft <= '0';\n butRight <= '0';\n butA <= '0';\n butB <= '0';\n butL <= '0';\n butR <= '0';\n butStart <= '0';\n butSelect <= '0';\n \n overlayInact <= '0';\n overlayAct <= '0';\n \n else\n -- Zero everything.\n if ( pxlX = 0 ) then\n pxlXCnt <= 0;\n scaleCntX <= 0;\n \n if ( pxlY = 0 ) then\n scaleCntY <= 0;\n pxlYCnt <= 0;\n end if;\n end if;\n \n \n if ( scaleCntX = scale - 1 ) then\n scaleCntX <= 0;\n pxlXCnt <= pxlXCnt + 1;\n else\n scaleCntX <= scaleCntX + 1;\n end if;\n \n if ( pxlX = frameWidth -1 ) then\n scaleCntX <= 0;\n pxlXCnt <= 0;\n \n if ( scaleCntY = scale - 1 ) then\n scaleCntY <= 0;\n pxlYCnt <= pxlYCnt + 1;\n else\n scaleCntY <= scaleCntY + 1;\n end if;\n end if;\n \n butUp <= buttons( 0 );\n butDown <= buttons( 1 );\n butLeft <= buttons( 2 );\n butRight <= buttons( 3 );\n butA <= buttons( 4 );\n butB <= buttons( 5 );\n butL <= buttons( 6 );\n butR <= buttons( 7 );\n butStart <= buttons( 8 );\n butSelect <= buttons( 9 );\n \n -- Shift pxlCnt\n pxlXCnt_sub <= pxlXCnt - posX;\n pxlYCnt_sub <= pxlYCnt - posY;\n --pxlXCnt_sub <= pxlX;\n --pxlYCnt_sub <= pxlY;\n \n -- Output logic.\n if ( pxlXCnt_sub >= 0 and pxlXCnt_sub <= 21 and\n pxlYCnt_sub >= 0 and pxlYCnt_sub <= 11 ) then\n -- Overlay window.\n case overlayROM( pxlYCnt_sub )( pxlXCnt_sub ) is\n when 00 =>\n overlayInact <= '1';\n overlayAct <= butUp;\n \n when 01 =>\n overlayInact <= '1';\n overlayAct <= butDown;\n \n when 02 =>\n overlayInact <= '1';\n overlayAct <= butLeft;\n \n when 03 =>\n overlayInact <= '1';\n overlayAct <= butRight;\n \n when 04 =>\n overlayInact <= '1';\n overlayAct <= butA;\n \n when 05 =>\n overlayInact <= '1';\n overlayAct <= butB;\n \n when 06=>\n overlayInact <= '1';\n overlayAct <= butL;\n \n when 07 =>\n overlayInact <= '1';\n overlayAct <= butR;\n \n when 08 =>\n overlayInact <= '1';\n overlayAct <= butStart;\n \n when 09 =>\n overlayInact <= '1';\n overlayAct <= butSelect;\n \n when others =>\n overlayInact <= '0';\n overlayAct <= '0';\n end case;\n \n else\n overlayInact <= '0';\n overlayAct <= '0';\n end if;\n \n \n end if;\n \n end if;\n end process;\n\nend behaviour;\n", "groundtruth": "\nsignal butUp, butDown, butLeft, butRight, butA, butB, butL, butR,\n butStart, butSelect : std_logic;\n\n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/singeLineBuffer.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: Single Line buffer\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse ieee.numeric_std.all;\nlibrary UNIMACRO;\nuse unimacro.Vcomponents.all;\n\nentity singeLineBuffer is\n port(\n clkW : in std_logic;\n clkR : in std_logic;\n rst : in std_logic;\n wAddr : in std_logic_vector( 8 downto 0 );\n wEn : in std_logic;\n rAddr : in std_logic_vector( 8 downto 0 );\n", "right_context": " );\nend singeLineBuffer;\n\narchitecture rtl of singeLineBuffer is\nsignal readData : std_logic_vector( 31 downto 0 );\nsignal wea_int : std_logic_vector( 3 downto 0 );\nsignal addra_int : std_logic_vector( 8 downto 0 );\nsignal dina_int : std_logic_vector( 31 downto 0 );\nsignal addrb_int : std_logic_vector( 8 downto 0 );\n\nbegin\n\n wea_int <= ( others => wEn );\n addra_int <= wAddr;\n dina_int <= \"00000000\" & redDataIn & greenDataIn & blueDataIn;\n addrb_int <= rAddr;\n \n bram_inst : BRAM_SDP_MACRO\n generic map(\n BRAM_SIZE => \"18Kb\",\n DEVICE => \"7SERIES\",\n WRITE_WIDTH => 32,\n READ_WIDTH => 32,\n DO_REG => 0,\n INIT_FILE => \"NONE\",\n SIM_COLLISION_CHECK => \"WARNING_ONLY\",\n SRVAL => X\"000000000000000000\",\n WRITE_MODE => \"WRITE_FIRST\"\n )\n port map(\n DO => readData,\n DI => dina_int,\n RDADDR => addrb_int,\n RDCLK => clkR,\n RDEN => '1',\n REGCE => '1',\n RST => rst,\n WE => wea_int,\n WRADDR => addra_int,\n WRCLK => clkW,\n WREN => wEn\n );\n \n redDataOut <= readData( 23 downto 16 );\n greenDataOut <= readData( 15 downto 8 );\n blueDataOut <= readData( 7 downto 0 );\n\nend rtl;", "groundtruth": " redDataIn : in std_logic_vector( 7 downto 0 );\n blueDataIn : in std_logic_vector( 7 downto 0 );\n greenDataIn : in std_logic_vector( 7 downto 0 );\n \n", "crossfile_context": ""} {"task_id": "gbaHD", "path": "gbaHD/hdl/smooth.vhd", "left_context": "-----------------------------------------------------------------------\n-- Title: 4x Smoother\n-- Author: zwenergy\n-----------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nentity smooth4x is\n generic(\n colorDepth : integer := 8\n );\n port (\n -- Source pixels\n rTL : in std_logic_vector( colorDepth - 1 downto 0 );\n gTL : in std_logic_vector( colorDepth - 1 downto 0 );\n bTL : in std_logic_vector( colorDepth - 1 downto 0 );\n rTM : in std_logic_vector( colorDepth - 1 downto 0 );\n gTM : in std_logic_vector( colorDepth - 1 downto 0 );\n bTM : in std_logic_vector( colorDepth - 1 downto 0 );\n rTR : in std_logic_vector( colorDepth - 1 downto 0 );\n gTR : in std_logic_vector( colorDepth - 1 downto 0 );\n bTR : in std_logic_vector( colorDepth - 1 downto 0 );\n \n rCL : in std_logic_vector( colorDepth - 1 downto 0 );\n gCL : in std_logic_vector( colorDepth - 1 downto 0 );\n bCL : in std_logic_vector( colorDepth - 1 downto 0 );\n rCM : in std_logic_vector( colorDepth - 1 downto 0 );\n gCM : in std_logic_vector( colorDepth - 1 downto 0 );\n bCM : in std_logic_vector( colorDepth - 1 downto 0 );\n rCR : in std_logic_vector( colorDepth - 1 downto 0 );\n gCR : in std_logic_vector( colorDepth - 1 downto 0 );\n bCR : in std_logic_vector( colorDepth - 1 downto 0 );\n \n rBL : in std_logic_vector( colorDepth - 1 downto 0 );\n gBL : in std_logic_vector( colorDepth - 1 downto 0 );\n bBL : in std_logic_vector( colorDepth - 1 downto 0 );\n rBM : in std_logic_vector( colorDepth - 1 downto 0 );\n gBM : in std_logic_vector( colorDepth - 1 downto 0 );\n bBM : in std_logic_vector( colorDepth - 1 downto 0 );\n rBR : in std_logic_vector( colorDepth - 1 downto 0 );\n gBR : in std_logic_vector( colorDepth - 1 downto 0 );\n bBR : in std_logic_vector( colorDepth - 1 downto 0 );\n \n xSel : in std_logic_vector( 1 downto 0 );\n ySel : in std_logic_vector( 1 downto 0 );\n \n do4x : in std_logic;\n \n -- Out pixel\n rOut : out std_logic_vector( colorDepth - 1 downto 0 );\n gOut : out std_logic_vector( colorDepth - 1 downto 0 );\n bOut : out std_logic_vector( colorDepth - 1 downto 0 ) \n );\nend smooth4x;\n\narchitecture rtl of smooth4x is\ntype pixel is array( 0 to 2 ) of std_logic_vector( colorDepth - 1 downto 0 );\ntype pixel4 is array( 0 to 3 ) of pixel;\ntype pixel16 is array( 0 to 3 ) of pixel4; \n\nfunction smooth2x( \n signal pxTM: in pixel;\n signal pxCL: in pixel;\n signal pxCM: in pixel;\n signal pxCR: in pixel;\n signal pxBM: in pixel ) return pixel4 is \n variable sm : pixel4;\n variable tmpTL, tmpTR, tmpBL, tmpBR : pixel;\nbegin\n if ( pxTM /= pxBM and pxCL /= pxCR ) then\n if ( pxCL = pxTM ) then\n tmpTL := pxCL;\n else\n tmpTL := pxCM;\n end if;\n \n if ( pxTM = pxCR ) then\n tmpTR := pxCR;\n else\n tmpTR := pxCM;\n end if;\n \n if ( pxCL = pxBM ) then\n tmpBL := pxCL;\n else\n tmpBL := pxCM;\n end if;\n \n if ( pxBM = pxCR ) then\n tmpBR := pxCR;\n else\n tmpBR := pxCM;\n end if;\n \n else\n tmpTL := pxCM;\n tmpTR := pxCM;\n tmpBL := pxCM;\n tmpBR := pxCM;\n end if;\n \n sm( 0 ) := tmpTL;\n sm( 1 ) := tmpTR;\n sm( 2 ) := tmpBL;\n sm( 3 ) := tmpBR;\n \n return sm;\nend smooth2x;\n\nfunction smooth2xMod( \n signal pxTM: in pixel;\n signal pxCL: in pixel;\n signal pxCM: in pixel;\n signal pxCR: in pixel;\n signal pxBM: in pixel;\n signal ignoreTopBottom: in std_logic;\n signal ignoreLeftRight: in std_logic ) return pixel4 is \n variable sm : pixel4;\n variable tmpTL, tmpTR, tmpBL, tmpBR : pixel;\nbegin\n if ( ( ignoreTopBottom = '1' and pxCL /= pxCR ) or\n ( ignoreLeftRight = '1' and pxTM /= pxBM ) or\n ( pxTM /= pxBM and pxCL /= pxCR and \n ignoreTopBottom = '0' and ignoreLeftRight = '0' ) ) then\n if ( pxCL = pxTM ) then\n tmpTL := pxCL;\n else\n tmpTL := pxCM;\n end if;\n \n if ( pxTM = pxCR ) then\n tmpTR := pxCR;\n else\n tmpTR := pxCM;\n end if;\n \n if ( pxCL = pxBM ) then\n tmpBL := pxCL;\n else\n tmpBL := pxCM;\n end if;\n \n if ( pxBM = pxCR ) then\n tmpBR := pxCR;\n else\n tmpBR := pxCM;\n end if;\n \n else\n tmpTL := pxCM;\n tmpTR := pxCM;\n tmpBL := pxCM;\n tmpBR := pxCM;\n end if;\n \n sm( 0 ) := tmpTL;\n sm( 1 ) := tmpTR;\n sm( 2 ) := tmpBL;\n sm( 3 ) := tmpBR;\n \n return sm;\nend smooth2xMod; \n\nsignal pxTL, pxTM, pxTR, pxCL, pxCM, pxCR, pxBL, pxBM, pxBR : pixel;\nsignal smoothOut : pixel16;\nsignal tm2x, cl2x, cm2x, cr2x, bm2x : pixel4;\nsignal ignoreSig : std_logic := '1';\nsignal notIgnoreSig : std_logic := '0';\nbegin\n\n pxTL( 0 ) <= rTL;\n pxTL( 1 ) <= gTL;\n pxTL( 2 ) <= bTL;\n \n pxTM( 0 ) <= rTM;\n pxTM( 1 ) <= gTM;\n pxTM( 2 ) <= bTM;\n \n pxTR( 0 ) <= rTR;\n pxTR( 1 ) <= gTR;\n pxTR( 2 ) <= bTR;\n \n pxCL( 0 ) <= rCL;\n pxCL( 1 ) <= gCL;\n pxCL( 2 ) <= bCL;\n \n pxCM( 0 ) <= rCM;\n pxCM( 1 ) <= gCM;\n pxCM( 2 ) <= bCM;\n \n pxCR( 0 ) <= rCR;\n pxCR( 1 ) <= gCR;\n pxCR( 2 ) <= bCR;\n \n pxBL( 0 ) <= rBL;\n pxBL( 1 ) <= gBL;\n pxBL( 2 ) <= bBL;\n \n pxBM( 0 ) <= rBM;\n pxBM( 1 ) <= gBM;\n pxBM( 2 ) <= bBM;\n \n pxBR( 0 ) <= rBR;\n pxBR( 1 ) <= gBR;\n pxBR( 2 ) <= bBR;\n \n process( pxTL, pxTM, pxTR, pxCL, pxCM, pxCR, pxBL, pxBM, pxBR, ignoreSig, notIgnoreSig ) is\n begin\n \n -- Smooth 2x\n tm2x <= smooth2xMod( pxCM, pxTL, pxTM, pxTR, pxCM, ignoreSig, notIgnoreSig );\n cl2x <= smooth2xMod( pxTL, pxCM, pxCL, pxCM, pxBL, notIgnoreSig, ignoreSig );\n cm2x <= smooth2x( pxTM, pxCL, pxCM, pxCR, pxBM );\n cr2x <= smooth2xMod( pxTR, pxCM, pxCR, pxCM, pxBR, notIgnoreSig, ignoreSig );\n bm2x <= smooth2xMod( pxCM, pxBL, pxBM, pxBR, pxCM, ignoreSig, notIgnoreSig );\n end process;\n \n process( tm2x, cl2x, cm2x, cr2x, bm2x ) is\n begin\n -- And 4x.\n smoothOut( 0 ) <= smooth2x( tm2x( 2 ), cl2x( 1 ), cm2x( 0 ),\n cm2x( 1 ), cm2x( 2 ) );\n \n smoothOut( 1 ) <= smooth2x( tm2x( 3 ), cm2x( 0 ), cm2x( 1 ), cr2x( 0 ),\n cm2x( 3 ) );\n \n smoothOut( 2 ) <= smooth2x( cm2x( 0 ), cl2x( 3 ), cm2x( 2 ),\n cm2x( 3 ), bm2x( 0 ) );\n \n smoothOut( 3 ) <= smooth2x( cm2x( 1 ), cm2x( 2 ), cm2x( 3 ),\n cr2x( 2 ), bm2x( 1 ) );\n end process;\n \n -- Output.\n process( tm2x, cl2x, cm2x, cr2x, bm2x, xSel, ySel, smoothOut, do4x ) is\n begin\n if ( do4x = '0' ) then\n case xSel is\n when \"00\"|\"01\" =>\n case ySel is\n when \"00\"|\"01\" =>\n rOut <= cm2x( 0 )( 0 );\n gOut <= cm2x( 0 )( 1 );\n bOut <= cm2x( 0 )( 2 );\n when \"10\"|\"11\" =>\n rOut <= cm2x( 2 )( 0 );\n gOut <= cm2x( 2 )( 1 );\n bOut <= cm2x( 2 )( 2 );\n when others =>\n rOut <= cm2x( 0 )( 0 );\n gOut <= cm2x( 0 )( 1 );\n bOut <= cm2x( 0 )( 2 );\n end case;\n \n when \"10\"|\"11\" =>\n case ySel is\n when \"00\"|\"01\" =>\n rOut <= cm2x( 1 )( 0 );\n gOut <= cm2x( 1 )( 1 );\n bOut <= cm2x( 1 )( 2 );\n when \"10\"|\"11\" =>\n rOut <= cm2x( 3 )( 0 );\n gOut <= cm2x( 3 )( 1 );\n bOut <= cm2x( 3 )( 2 );\n when others =>\n rOut <= cm2x( 0 )( 0 );\n gOut <= cm2x( 0 )( 1 );\n bOut <= cm2x( 0 )( 2 );\n end case;\n \n when others =>\n rOut <= cm2x( 0 )( 0 );\n gOut <= cm2x( 0 )( 1 );\n bOut <= cm2x( 0 )( 2 );\n end case;\n \n else \n case xSel is\n when \"00\" =>\n case ySel is\n when \"00\" =>\n rOut <= smoothOut( 0 )( 0 )( 0 );\n gOut <= smoothOut( 0 )( 0 )( 1 );\n bOut <= smoothOut( 0 )( 0 )( 2 );\n \n when \"01\" =>\n rOut <= smoothOut( 0 )( 2 )( 0 );\n gOut <= smoothOut( 0 )( 2 )( 1 );\n bOut <= smoothOut( 0 )( 2 )( 2 );\n \n when \"10\" =>\n rOut <= smoothOut( 2 )( 0 )( 0 );\n gOut <= smoothOut( 2 )( 0 )( 1 );\n bOut <= smoothOut( 2 )( 0 )( 2 );\n \n when \"11\" =>\n rOut <= smoothOut( 2 )( 2 )( 0 );\n gOut <= smoothOut( 2 )( 2 )( 1 );\n bOut <= smoothOut( 2 )( 2 )( 2 );\n \n when others =>\n rOut <= smoothOut( 0 )( 0 )( 0 );\n gOut <= smoothOut( 0 )( 0 )( 0 );\n bOut <= smoothOut( 0 )( 0 )( 0 );\n end case;\n \n when \"01\" =>\n case ySel is\n when \"00\" =>\n rOut <= smoothOut( 0 )( 1 )( 0 );\n gOut <= smoothOut( 0 )( 1 )( 1 );\n bOut <= smoothOut( 0 )( 1 )( 2 );\n \n when \"01\" =>\n", "right_context": " \n when \"10\" =>\n rOut <= smoothOut( 2 )( 1 )( 0 );\n gOut <= smoothOut( 2 )( 1 )( 1 );\n bOut <= smoothOut( 2 )( 1 )( 2 );\n \n when \"11\" =>\n rOut <= smoothOut( 2 )( 3 )( 0 );\n gOut <= smoothOut( 2 )( 3 )( 1 );\n bOut <= smoothOut( 2 )( 3 )( 2 );\n \n when others =>\n rOut <= smoothOut( 0 )( 0 )( 0 );\n gOut <= smoothOut( 0 )( 0 )( 0 );\n bOut <= smoothOut( 0 )( 0 )( 0 );\n end case;\n \n when \"10\" =>\n case ySel is\n when \"00\" =>\n rOut <= smoothOut( 1 )( 0 )( 0 );\n gOut <= smoothOut( 1 )( 0 )( 1 );\n bOut <= smoothOut( 1 )( 0 )( 2 );\n \n when \"01\" =>\n rOut <= smoothOut( 1 )( 2 )( 0 );\n gOut <= smoothOut( 1 )( 2 )( 1 );\n bOut <= smoothOut( 1 )( 2 )( 2 );\n \n when \"10\" =>\n rOut <= smoothOut( 3 )( 0 )( 0 );\n gOut <= smoothOut( 3 )( 0 )( 1 );\n bOut <= smoothOut( 3 )( 0 )( 2 );\n \n when \"11\" =>\n rOut <= smoothOut( 3 )( 2 )( 0 );\n gOut <= smoothOut( 3 )( 2 )( 1 );\n bOut <= smoothOut( 3 )( 2 )( 2 );\n \n when others =>\n rOut <= smoothOut( 0 )( 0 )( 0 );\n gOut <= smoothOut( 0 )( 0 )( 0 );\n bOut <= smoothOut( 0 )( 0 )( 0 );\n end case;\n \n when \"11\" =>\n case ySel is\n when \"00\" =>\n rOut <= smoothOut( 1 )( 1 )( 0 );\n gOut <= smoothOut( 1 )( 1 )( 1 );\n bOut <= smoothOut( 1 )( 1 )( 2 );\n \n when \"01\" =>\n rOut <= smoothOut( 1 )( 3 )( 0 );\n gOut <= smoothOut( 1 )( 3 )( 1 );\n bOut <= smoothOut( 1 )( 3 )( 2 );\n \n when \"10\" =>\n rOut <= smoothOut( 3 )( 1 )( 0 );\n gOut <= smoothOut( 3 )( 1 )( 1 );\n bOut <= smoothOut( 3 )( 1 )( 2 );\n \n when \"11\" =>\n rOut <= smoothOut( 3 )( 3 )( 0 );\n gOut <= smoothOut( 3 )( 3 )( 1 );\n bOut <= smoothOut( 3 )( 3 )( 2 );\n \n when others =>\n rOut <= smoothOut( 0 )( 0 )( 0 );\n gOut <= smoothOut( 0 )( 0 )( 0 );\n bOut <= smoothOut( 0 )( 0 )( 0 );\n end case;\n \n when others =>\n rOut <= smoothOut( 0 )( 0 )( 0 );\n gOut <= smoothOut( 0 )( 0 )( 0 );\n bOut <= smoothOut( 0 )( 0 )( 0 );\n end case;\n end if;\n end process;\n\nend rtl;\n", "groundtruth": " rOut <= smoothOut( 0 )( 3 )( 0 );\n gOut <= smoothOut( 0 )( 3 )( 1 );\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/bad_line_detect.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity bad_line_detect is\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\treg : in t_regs;\n\taec : in std_wire;\n\tstrb : in t_strb;\n\tcycl : in t_ppos;\n\typos : in t_ppos;\n\tbdln : out std_wire;\n\tccax : out std_wire\n);\nend entity;\n\n\narchitecture rtl of bad_line_detect is\n\n\tsignal rst_1r : std_wire := '1';\n\tsignal den : std_wire;\n\tsignal enable : std_wire;\n\tsignal yscroll : unsigned(2 downto 0);\n\nbegin\n\n\tyscroll <= unsigned(reg(17)(2 downto 0));\n\tden <= reg(17)(4);\n", "right_context": "\n\t\t\tv_enable := enable;\n\n\t\t\tif strb = 1 then\n\t\t\t\tif ((den = '1') and (ypos = 48)) then\n\t\t\t\t\tv_enable := '1';\n\t\t\t\tend if;\n\n\t\t\t\tif ypos >= 48 and ypos <= 247 then\n\t\t\t\t\tif (v_enable = '1') and (yscroll = ypos(2 downto 0)) then\n\t\t\t\t\t\tbdln <= '1';\n\t\t\t\t\telse\n\t\t\t\t\t\tbdln <= '0';\n\t\t\t\t\tend if;\n\t\t\t\telse\n\t\t\t\t\tbdln <= '0';\n\t\t\t\t\tv_enable := '0';\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\tif (strb = 9) then\n\t\t\t\tif (cycl = c_cycl_ref - 1) then\n\t\t\t\t\tccax <= '0';\n\t\t\t\telse\n\t\t\t\t\tccax <= '0';\n\t\t\t\t\tif (ypos >= 48) and (ypos <= 247) and\n\t\t\t\t\t (cycl >= c_cycl_ref) and (cycl < c_cycl_ref + 40)\n\t\t\t\t\tthen\n\t\t\t\t\t\tccax <= not aec;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\tenable <= v_enable;\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\t\t\t\tbdln <= '0';\n\t\t\t\tccax <= '0';\n\t\t\t\tenable <= '0';\n\t\t\tend if;\n\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "\n\tp_detect : process(clk) is\n\t\tvariable v_enable : std_wire;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/border.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity border is\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\tstrb : in t_strb;\n\tspecs : in t_vic_specs;\n\tcycl : in t_ppos;\n\txpos : in t_ppos;\n", "right_context": "\tenable : in std_word(1 downto 0);\n\n\tmark_bord : out std_wire;\n\tmark_colr : out t_colr\n);\nend entity;\n\n\narchitecture rtl of border is\n\n\tsignal rst_1r : std_wire := '1';\n\n\tsignal ff_main : std_wire;\n\tsignal ff_vert : std_wire;\n\n\tsignal edge_ll : t_ppos;\n\tsignal edge_rr : t_ppos;\n\tsignal edge_hi : t_ppos;\n\tsignal edge_lo : t_ppos;\n\n\tsignal reg_rsel : std_wire;\n\tsignal reg_csel : std_wire;\n\n\tsignal reg_rsel_1r : std_wire;\n\tsignal reg_csel_1r : std_wire;\n\n\talias reg_ec : std_word is reg(32)(3 downto 0);\n\talias reg_den : std_wire is reg(17)(4);\n\nbegin\n\n\t----------------------------------------------------------------------------\n\t-- DIAGNOSTICS --\n\t----------------------------------------------------------------------------\n\n\tprocess(all) is\n\tbegin\n\t\treg_rsel <= reg(17)(3);\n\t\treg_csel <= reg(22)(3);\n\n\t\tif enable = \"01\" then\n\t\t\t-- force wide border\n\t\t\treg_rsel <= '1';\n\t\t\treg_csel <= '1';\n\t\telsif enable = \"10\" then\n\t\t\t-- force narrow border\n\t\t\treg_rsel <= '0';\n\t\t\treg_csel <= '0';\n\t\tend if;\n\tend process;\n\n\t----------------------------------------------------------------------------\n\n\tedge_ll <= specs.xfvc + 7 when (reg_csel = '0') else specs.xfvc;\n\tedge_rr <= specs.xlvc - 8 when (reg_csel = '0') else specs.xlvc + 1;\n\tedge_hi <= specs.yfvc + 4 when (reg_rsel = '0') else specs.yfvc;\n\tedge_lo <= specs.ylvc - 3 when (reg_rsel = '0') else specs.ylvc + 1;\n\n\tP_border : process(clk) is\n\t\tvariable v_ff_main : std_wire;\n\t\tvariable v_ff_vert : std_wire;\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\tv_ff_main := ff_main;\n\t\t\tv_ff_vert := ff_vert;\n\n\t\t\tif strb(0) = '1' then\n\n\t\t\t\t-- vertical ff control\n\t\t\t\tif (ypos = edge_lo) then\n\t\t\t\t\tv_ff_vert := '1';\n\t\t\t\tend if;\n\n\t\t\t\tif (xpos = edge_ll) then\n\t\t\t\t\to_vbrd <= v_ff_vert;\n\t\t\t\tend if;\n\n\t\t\t\tif (ypos = edge_hi) and (reg_den = '1') then\n\t\t\t\t\tv_ff_vert := '0';\n\t\t\t\t\to_vbrd <= v_ff_vert;\n\t\t\t\tend if;\n\n\t\t\t\t-- main ff control\n\t\t\t\tif (xpos = edge_rr) then\n\t\t\t\t\tv_ff_main := '1';\n\t\t\t\tend if;\n\t\t\t\tif (xpos = edge_ll) and (v_ff_vert = '0') then\n\t\t\t\t\tv_ff_main := '0';\n\t\t\t\tend if;\n\n\t\t\t\t-- this is copied from kawarii\n\t\t\t\tif (cycl = 0)then\n\t\t\t\t\to_vbrd <= v_ff_vert;\n\t\t\t\tend if;\n\n\t\t\t\to_bord <= v_ff_main;\n\t\t\t\to_colr <= t_colr(reg_ec);\n\n\t\t\t\tff_vert <= v_ff_vert;\n\t\t\t\tff_main <= v_ff_main;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- DIAGNOSTICS --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\t-- turning off border\n\t\t\t\tif enable = \"00\" then\n\t\t\t\t\to_bord <= '0';\n\t\t\t\tend if;\n\n\t\t\t\t-- marking csel and rsel changes (opening border)\n\t\t\t\treg_csel_1r <= reg_csel;\n\t\t\t\treg_rsel_1r <= reg_rsel;\n\n\t\t\t\tmark_bord <= '0';\n\t\t\t\tif reg_csel_1r /= reg_csel then\n\t\t\t\t\tmark_bord <= '1';\n\t\t\t\t\tmark_colr <= x\"d\"; -- LIGHT GREEN\n\t\t\t\tend if;\n\n\t\t\t\tif reg_rsel_1r /= reg_rsel then\n\t\t\t\t\tmark_bord <= '1';\n\t\t\t\t\tmark_colr <= x\"4\"; -- PURPLE\n\t\t\t\tend if;\n\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\tend if;\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\t\t\t\tff_main <= '0';\n\t\t\t\tff_vert <= '0';\n\t\t\tend if;\n\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "\typos : in t_ppos;\n\treg : in t_regs;\n\n\to_vbrd : out std_wire;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/bus_latch.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.gp3r_pkg.all;\nuse work.vic_pkg.all;\n\nentity bus_latch is\ngeneric\n(\n\tg_enable : boolean := True\n);\nport\n", "right_context": "\ti_a : in t_addr;\n\ti_rw : in std_wire;\n\ti_cs : in std_wire;\n\ti_aec : in std_wire;\n\n\to_ph0 : out std_wire;\n\to_db : out std_word(11 downto 0);\n\to_a : out t_addr;\n\to_rw : out std_wire;\n\to_cs : out std_wire;\n\to_aec : out std_wire\n);\nend entity;\n\n\narchitecture rtl of bus_latch is\n\n\tsignal vector_in : std_word(21 downto 0);\n\tsignal vector_out : std_word(21 downto 0);\n\nbegin\n\n\tprocess(all) is\n\tbegin\n\t\tvector_in <= i_ph0 & i_db & std_word(i_a) & i_rw & i_cs & i_aec;\n\t\to_ph0 <= vector_out(21);\n\t\to_db <= vector_out(20 downto 9);\n\t\to_a <= unsigned(vector_out(8 downto 3));\n\t\to_rw <= vector_out(2);\n\t\to_cs <= vector_out(1);\n\t\to_aec <= vector_out(0);\n\tend process;\n\n\n\ti_multi_flop : entity work.multi_flop\n\tgeneric map\n\t(\n\t\tg_num_stages => switch(g_enable, 2, 0),\n\t\tg_input_reg => false\n\t)\n\tport map\n\t(\n\t\ti_clk => clk,\n\t\ti_rst => rst,\n\t\ti_data => vector_in,\n\n\t\to_clk => clk,\n\t\to_rst => rst,\n\t\to_data => vector_out\n\t);\n\nend architecture;\n", "groundtruth": "(\n\tclk : in std_wire; -- must be twice the video clock (16 times ph0)\n\trst : in std_wire;\n\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/bus_logger.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.gp3r_pkg.all;\nuse work.vic_pkg.all;\n\nentity bus_logger is\ngeneric\n(\n\tg_enable : boolean\n);\nport\n(\n\tclk : in std_wire; -- must be twice the video clock (16 times ph0)\n\trst : in std_wire;\n\n\t-- gp3r master\n\treq : in t_gp3r_req;\n\trsp : out t_gp3r_rsp;\n\n\txpos : in t_ppos;\n\typos : in t_ppos;\n\n\t-- VIC signals\n\tstrb : in t_strb;\n\tph0 : in std_wire;\n\tdb : in std_word(11 downto 0);\n\ta : in t_addr;\n\trw : in std_wire;\n\tcs : in std_wire;\n\taec : in std_wire\n);\nend entity;\n\n\narchitecture rtl of bus_logger is\n\n\tconstant c_bit_width : positive := 32;\n\tconstant c_fifo_depth : positive := 2048;\n\n\tsignal rst_1r : std_wire := '1';\n\n\tsignal req_fifo : req'subtype;\n\tsignal rsp_fifo : rsp'subtype;\n\n\tsignal count : natural range 0 to c_fifo_depth;\n\tsignal dumping : std_wire;\n\tsignal pixl_num : unsigned(bits_for_value(c_fifo_depth) - 1 downto 0);\n\tsignal line_num : unsigned(31 downto 0);\n\tsignal line_num_push : std_wire;\n\n", "right_context": "\tsignal data_out : std_word(c_bit_width - 1 downto 0);\n\tsignal read_out : std_wire;\n\tsignal push_out : std_wire;\n\nbegin\n\n\tr_enable : if g_enable generate\n\t\ti_memmap : entity work.memmap_bus_logger\n\t\tgeneric map\n\t\t(\n\t\t\tg_decouple => true\n\t\t)\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treq => req,\n\t\t\trsp => rsp,\n\t\t\tline_num => line_num,\n\t\t\tpixl_num => lresize(pixl_num, 32),\n\t\t\tline_num_push => line_num_push,\n\t\t\treq_line_read => req_fifo,\n\t\t\trsp_line_read => rsp_fifo\n\t\t);\n\n\n\t\tp_input : process(clk) is\n\t\tbegin\n\t\t\tif rising_edge(clk) then\n\n\t\t\t\tpush_in <= '0';\n\n\t\t\t\tif ((ypos = line_num) and (xpos = 0) and (count = 0)) or\n\t\t\t\t ((dumping = '1') and (xpos = count) )\n\t\t\t\tthen\n\t\t\t\t\tdumping <= '1';\n\t\t\t\t\tpush_in <= '1';\n\t\t\t\t\tdata_in <= \"000000\" &\n\t\t\t\t\t std_word(strb) & -- 25 downto 22\n\t\t\t\t\t ph0 & -- 21\n\t\t\t\t\t db & -- 20 downto 9\n\t\t\t\t\t std_word(a) & -- 8 downto 3\n\t\t\t\t\t rw & -- 2\n\t\t\t\t\t cs & -- 1\n\t\t\t\t\t aec; -- 0\n\n\t\t\t\t\tif strb(0) = '1' then\n\t\t\t\t\t\tcount <= count + 1;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\tif line_num_push then\n\t\t\t\t\tcount <= 0;\n\t\t\t\t\tdumping <= '0';\n\t\t\t\tend if;\n\n\t\t\t\trst_1r <= rst;\n\t\t\t\tif rst_1r then\n\t\t\t\t\tcount <= c_fifo_depth;\n\t\t\t\t\tdumping <= '0';\n\t\t\t\t\tpush_in <= '0';\n\t\t\t\tend if;\n\n\t\t\tend if;\n\t\tend process;\n\n\n\t\ti_fifo : entity work.fifo\n\t\tgeneric map\n\t\t(\n\t\t\tg_depth => c_fifo_depth,\n\t\t\tg_width => c_bit_width\n\t\t)\n\t\tport map\n\t\t(\n\t\t\ti_clk => clk,\n\t\t\ti_rst => rst,\n\t\t\ti_push => push_in,\n\t\t\ti_read => open,\n\t\t\ti_data => data_in,\n\n\t\t\to_clk => clk,\n\t\t\to_rst => rst,\n\t\t\to_flush => '0',\n\t\t\to_push => push_out,\n\t\t\to_read => read_out,\n\t\t\to_data => data_out,\n\t\t\to_nfull => pixl_num\n\t\t);\n\n\n\t\ti_stream_to_gp3r : entity work.gp3r_istream\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treq => req_fifo,\n\t\t\trsp => rsp_fifo,\n\t\t\tdata => data_out,\n\t\t\tread => read_out,\n\t\t\tpush => push_out\n\t\t);\n\n\telse generate\n\n\t\ti_nack : entity work.gp3r_dummy\n\t\tgeneric map\n\t\t(\n\t\t\tg_nack => c_gp3r_nack_addr\n\t\t)\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treq => req,\n\t\t\trsp => rsp\n\t\t);\n\n\tend generate;\n\nend architecture;\n", "groundtruth": "\tsignal data_in : std_word(c_bit_width - 1 downto 0);\n\tsignal push_in : std_wire;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/dot_clock.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity dot_clock is\ngeneric\n(\n\tg_clk_frq : real\n);\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\ti_phi : in std_wire;\n\to_dot : out std_wire;\n\to_phi : out std_wire;\n\to_clk : out std_wire\n);\nend entity;\n\n\narchitecture rtl of dot_clock is\n\n\tfunction calc_toggle_times(i_phi_frq : real; sys_frq : real; mult : positive)\n\treturn integer_vector is\n\t\tvariable ret : integer_vector(0 to mult * 2 - 1);\n\tbegin\n\t\tfor i in 0 to ret'length - 2 loop\n\t\t\tret(i) := integer(round(((sys_frq / i_phi_frq) / real(ret'length)) * real(i + 1)));\n\t\tend loop;\n\t\tret(ret'length - 1) := 0;\n\t\treturn ret;\n\tend function;\n\n\tconstant c_mult : positive := 16;\n\tconstant c_i_phi_frq_pal : real := 0.985e6;\n\tconstant c_i_phi_frq_ntsc : real := 1.023e6;\n\n\tconstant c_max_prd_pal : integer := integer(ceil(g_clk_frq / c_i_phi_frq_pal));\n\tconstant c_max_prd_ntsc : integer := integer(ceil(g_clk_frq / c_i_phi_frq_ntsc));\n\tconstant c_prd_thr : integer := (c_max_prd_pal + c_max_prd_ntsc) / 2;\n\tconstant c_max_prd : integer := c_max_prd_pal;\n\tconstant c_toggle_pal : integer_vector := calc_toggle_times(c_i_phi_frq_pal , g_clk_frq, c_mult);\n\tconstant c_toggle_ntsc : integer_vector := calc_toggle_times(c_i_phi_frq_ntsc, g_clk_frq, c_mult);\n\n\tsignal rst_1r : std_wire := '1';\n\tsignal i_phi_mf : std_wire;\n\tsignal i_phi_1r : std_wire;\n\tsignal prd : natural range 0 to c_max_prd;\n\tsignal toggle : c_toggle_pal'subtype;\n\tsignal toggle_val : integer range 0 to c_max_prd;\n\tsignal count : natural range 0 to toggle'length;\n\nbegin\n\n\ti_i_phi_mf : entity work.multi_flop\n\tgeneric map\n\t(\n\t\tg_num_stages => 5\n\t)\n\tport map\n\t(\n\t\ti_data(0) => i_phi,\n\t\to_clk => clk,\n\t\to_rst => rst,\n\t\to_data(0) => i_phi_mf\n\t);\n\n\to_phi <= i_phi_mf;\n\n\tp_dot_clock : process(clk) is\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\tif prd = toggle_val then\n\t\t\t\to_clk <= not o_clk;\n\t\t\t\tcount <= count + 1; -- cannot wrap because the last element of the toggle array is zero\n\t\t\t\ttoggle_val <= toggle(count);\n\n\t\t\t\t-- the \"dot\"\n\t\t\t\tif o_clk = '1' then\n\t\t\t\t\to_dot <= not o_dot;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\t-- calculating the period\n\t\t\tif prd /= c_max_prd then\n\t\t\t\tprd <= prd + 1;\n\t\t\tend if;\n\n\t\t\ti_phi_1r <= i_phi_mf;\n\t\t\tif (i_phi_1r = '1') and (i_phi_mf = '0') then\n\t\t\t\tprd <= 1;\n\t\t\t\to_clk <= '1';\n\t\t\t\to_dot <= '0';\n\t\t\t\tcount <= 1;\n\n\t\t\t\tif prd > c_prd_thr then\n\t\t\t\t\ttoggle <= c_toggle_pal;\n\t\t\t\t\ttoggle_val <= c_toggle_pal(0);\n\t\t\t\telse\n\t\t\t\t\ttoggle <= c_toggle_ntsc;\n\t\t\t\t\ttoggle_val <= c_toggle_ntsc(0);\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\t\t\t\tprd <= 0;\n\t\t\t\ti_phi_1r <= '0';\n\t\t\t\to_dot <= '0';\n", "right_context": "end architecture;\n", "groundtruth": "\t\t\t\to_clk <= '0';\n\t\t\tend if;\n\t\tend if;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/graphics_gen.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity graphics_gen is\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\treg : in t_regs;\n\tstrb : in t_strb;\n\n\ti_actv : in std_wire;\n\ti_vbrd : in std_wire;\n\ti_grfx : in std_word( 7 downto 0);\n\ti_data : in std_word(11 downto 0);\n\to_bgnd : out std_wire;\n\to_colr : out t_colr;\n\n\t-- diagnostics & debug\n\tmark_mode : in std_wire\n);\nend entity;\n\n\narchitecture rtl of graphics_gen is\n\n\tconstant c_shreg_len : natural := 8;\n\n\tsignal rst_1r : std_wire := '1';\n\n\tsignal shreg : unsigned(c_shreg_len - 1 downto 0);\n\tsignal xscroll : natural range 0 to 7;\n\n\tsignal actv_1r : std_wire;\n\tsignal actv_2r : std_wire;\n\n\tsignal vbrd_1r : std_wire;\n\n\tsignal grfx_1r : i_grfx'subtype;\n\tsignal grfx_2r : i_grfx'subtype;\n\n\tsignal data_1r : i_data'subtype;\n\tsignal data_2r : i_data'subtype;\n\tsignal data_3r : i_data'subtype;\n\tsignal mc_phy : std_wire;\n\tsignal bg_colr_1r : t_colr_vector(0 to 3);\n\tsignal bg_colr_2r : t_colr_vector(0 to 3);\n\n\tsignal ecm_1r : std_wire;\n\tsignal ecm_2r : std_wire;\n\tsignal ecm_3r : std_wire;\n\n\tsignal mcm_1r : std_wire;\n\tsignal mcm_2r : std_wire;\n\tsignal mcm_3r : std_wire;\n\n\tsignal bmm_1r : std_wire;\n\tsignal bmm_2r : std_wire;\n\tsignal bmm_3r : std_wire;\n\n\tsignal ecm : std_wire;\n\tsignal mcm : std_wire;\n\tsignal bmm : std_wire;\n\tsignal mcm_old : std_wire;\n\n\tsignal gfx_val : unsigned(1 downto 0);\n\tsignal bg_sel : unsigned(1 downto 0);\n\tsignal gfx_bgnd : std_wire;\n\n\n\tfunction get_mode(ecm : std_wire; bmm : std_wire; mcm : std_wire) return t_vic_mode is\n\t\tvariable mode : std_word(2 downto 0) := ecm & bmm & mcm;\n\tbegin\n\t\tcase mode is\n\t\t\twhen \"000\" =>\n\t\t\t\treturn MODE_STD_TEXT;\n\t\t\twhen \"001\" =>\n\t\t\t\treturn MODE_MCL_TEXT;\n\t\t\twhen \"010\" =>\n\t\t\t\treturn MODE_STD_BMAP;\n\t\t\twhen \"011\" =>\n\t\t\t\treturn MODE_MCL_BMAP;\n\t\t\twhen \"100\" =>\n\t\t\t\treturn MODE_ECM_TEXT;\n\t\t\twhen others =>\n\t\t\t\treturn MODE_INVALID;\n\t\tend case;\n\tend function;\n\nbegin\n\n\tp_serialize : process(clk) is\n\t\tvariable v_mode : t_vic_mode;\n\t\tvariable v_mc_flag : std_wire;\n\t\tvariable v_data_colr : i_data'subtype;\n\t\tvariable v_gfx_colr : t_colr_vector(0 to 3);\n\t\tvariable v_gfx_val : unsigned(1 downto 0);\n\t\tvariable v_gfx_bgnd : std_wire;\n\t\tvariable v_bg_sel : unsigned(1 downto 0);\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\tif strb(0) = '1' then\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- LATCHING NEW CHARACTER --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tif strb = 15 then\n\t\t\t\t\tactv_2r <= actv_1r;\n\t\t\t\t\tgrfx_2r <= grfx_1r;\n\t\t\t\t\tdata_2r <= data_1r;\n\n\t\t\t\t\tif i_actv then\n\t\t\t\t\t\txscroll <= to_integer(unsigned(reg(22)(2 downto 0)));\n\t\t\t\t\tend if;\n\n\t\t\t\t\tif i_actv then\n\t\t\t\t\t\tgrfx_1r <= i_grfx;\n\t\t\t\t\t\tdata_1r <= i_data;\n\t\t\t\t\t\tactv_1r <= i_actv;\n\t\t\t\t\telse\n\t\t\t\t\t\tdata_1r <= (others => '0');\n\t\t\t\t\t\tactv_1r <= '0';\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- LATCHING MODE FLAGS --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tmc_phy <= not mc_phy;\n\n\t\t\t\tecm_1r <= reg(17)(6);\n\t\t\t\tecm_2r <= ecm_1r;\n\t\t\t\tecm_3r <= ecm_2r;\n\n\t\t\t\tbmm_1r <= reg(17)(5);\n\t\t\t\tbmm_2r <= bmm_1r;\n\t\t\t\tbmm_3r <= bmm_2r;\n\n\t\t\t\tmcm_1r <= reg(22)(4);\n\t\t\t\tmcm_2r <= mcm_1r;\n\t\t\t\tmcm_3r <= mcm_2r;\n\n\t\t\t\tvbrd_1r <= i_vbrd;\n\n\t\t\t\tif strb = 1 then\n\t\t\t\t\tecm <= ecm or ecm_3r;\n\t\t\t\t\tbmm <= bmm or bmm_3r;\n\t\t\t\tend if;\n\n\t\t\t\tif strb = 3 then\n\t\t\t\t\tecm <= ecm and ecm_3r;\n\t\t\t\t\tbmm <= bmm and bmm_3r;\n\t\t\t\tend if;\n\n\t\t\t\tif strb = 9 then\n\t\t\t\t\tmcm <= mcm_3r;\n\t\t\t\tend if;\n\n\t\t\t\tif strb = 15 then\n\t\t\t\t\tmcm_old <= mcm;\n\t\t\t\t\tif mcm_old /= mcm then\n\t\t\t\t\t\tmc_phy <= '1';\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- LOADING SHIFT REGISTER --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tshreg <= lshift(shreg, 1);\n\n\t\t\t\tif rshift(strb, 1) = xscroll then\n\t\t\t\t\tif (actv_2r = '1') or (strb < 7) then\n\t\t\t\t\t\tmc_phy <= '0';\n\t\t\t\t\tend if;\n\n\t\t\t\t\tif actv_2r then\n\t\t\t\t\t\tdata_3r <= data_2r;\n\t\t\t\t\t\tshreg(7 downto 0) <= unsigned(grfx_2r);\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- COLOR LATCHING --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tbg_colr_1r(0) <= unsigned(reg(33)(3 downto 0));\n\t\t\t\tbg_colr_1r(1) <= unsigned(reg(34)(3 downto 0));\n\t\t\t\tbg_colr_1r(2) <= unsigned(reg(35)(3 downto 0));\n\t\t\t\tbg_colr_1r(3) <= unsigned(reg(36)(3 downto 0));\n\t\t\t\tbg_colr_2r <= bg_colr_1r;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- COLOR SELECTION --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tv_mc_flag := data_3r(11);\n\n\t\t\t\tif mcm_old then\n\t\t\t\t\tif bmm or v_mc_flag then\n\t\t\t\t\t\tif mc_phy = '0' then\n\t\t\t\t\t\t\tv_gfx_val := rresize(shreg, 2);\n\t\t\t\t\t\t\tv_gfx_bgnd := not shreg(shreg'high);\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tv_gfx_val := gfx_val;\n\t\t\t\t\t\t\tv_gfx_bgnd := gfx_bgnd;\n\t\t\t\t\t\tend if;\n\t\t\t\t\telse\n\t\t\t\t\t\tv_gfx_val := (others => shreg(shreg'high));\n\t\t\t\t\t\tv_gfx_bgnd := not shreg(shreg'high);\n\t\t\t\t\tend if;\n\t\t\t\telse\n\t\t\t\t\tif bmm or v_mc_flag then\n\t\t\t\t\t\tv_gfx_val := shreg(shreg'high) & '0';\n\t\t\t\t\t\tv_gfx_bgnd := not shreg(shreg'high);\n\t\t\t\t\telse\n\t\t\t\t\t\tv_gfx_val := (others => shreg(shreg'high));\n\t\t\t\t\t\tv_gfx_bgnd := not shreg(shreg'high);\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t-- color selection is based on current mode flags\n\t\t\t\tv_mode := get_mode(ecm, bmm, mcm);\n\n\t\t\t\tv_gfx_colr(0) := (others => '0');\n\t\t\t\tv_gfx_colr(1) := (others => '0');\n\t\t\t\tv_gfx_colr(2) := (others => '0');\n\t\t\t\tv_gfx_colr(3) := (others => '0');\n\n\t\t\t\tv_data_colr := data_3r;\n\n\t\t\t\t-- only useful for ECM\n\t\t\t\tv_bg_sel := unsigned(v_data_colr(7 downto 6));\n\n\t\t\t\t-- vertical border disables graphics, not clear if the delay is correct here\n\t\t\t\tif vbrd_1r = '1' then\n\t\t\t\t\tv_bg_sel := bg_sel; -- this is a super dirty hack to fix ECM\n\t\t\t\t\tv_gfx_val := \"00\";\n\t\t\t\t\tv_gfx_bgnd := '1';\n\t\t\t\tend if;\n\n\t\t\t\tcase v_mode is\n\t\t\t\t\twhen MODE_STD_TEXT =>\n\t\t\t\t\t\tv_gfx_colr(0) := bg_colr_2r(0);\n\t\t\t\t\t\tv_gfx_colr(1) := bg_colr_2r(0);\n\t\t\t\t\t\tv_gfx_colr(2) := unsigned(v_data_colr(11 downto 8));\n\t\t\t\t\t\tv_gfx_colr(3) := unsigned(v_data_colr(11 downto 8));\n\n\t\t\t\t\twhen MODE_MCL_TEXT =>\n\t\t\t\t\t\tif v_mc_flag then\n\t\t\t\t\t\t\tv_gfx_colr(0) := bg_colr_2r(0);\n\t\t\t\t\t\t\tv_gfx_colr(1) := bg_colr_2r(1);\n\t\t\t\t\t\t\tv_gfx_colr(2) := bg_colr_2r(2);\n\t\t\t\t\t\t\tv_gfx_colr(3) := '0' & unsigned(v_data_colr(10 downto 8));\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tv_gfx_colr(0) := bg_colr_2r(0);\n\t\t\t\t\t\t\tv_gfx_colr(1) := bg_colr_2r(0);\n\t\t\t\t\t\t\tv_gfx_colr(2) := '0' & unsigned(v_data_colr(10 downto 8));\n\t\t\t\t\t\t\tv_gfx_colr(3) := '0' & unsigned(v_data_colr(10 downto 8));\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\twhen MODE_STD_BMAP =>\n\t\t\t\t\t\tv_gfx_colr(0) := unsigned(v_data_colr(3 downto 0));\n\t\t\t\t\t\tv_gfx_colr(1) := unsigned(v_data_colr(3 downto 0));\n\t\t\t\t\t\tv_gfx_colr(2) := unsigned(v_data_colr(7 downto 4));\n\t\t\t\t\t\tv_gfx_colr(3) := unsigned(v_data_colr(7 downto 4));\n\n\t\t\t\t\twhen MODE_MCL_BMAP =>\n\t\t\t\t\t\tv_gfx_colr(0) := bg_colr_2r(0);\n\t\t\t\t\t\tv_gfx_colr(1) := unsigned(v_data_colr( 7 downto 4));\n\t\t\t\t\t\tv_gfx_colr(2) := unsigned(v_data_colr( 3 downto 0));\n\t\t\t\t\t\tv_gfx_colr(3) := unsigned(v_data_colr(11 downto 8));\n\n\t\t\t\t\twhen MODE_ECM_TEXT =>\n\t\t\t\t\t\tv_gfx_colr(0) := bg_colr_2r(to_integer(v_bg_sel));\n\t\t\t\t\t\tv_gfx_colr(1) := bg_colr_2r(to_integer(v_bg_sel));\n\t\t\t\t\t\tv_gfx_colr(2) := unsigned(v_data_colr(11 downto 8));\n\t\t\t\t\t\tv_gfx_colr(3) := unsigned(v_data_colr(11 downto 8));\n\n\t\t\t\t\twhen others =>\n\t\t\t\t\t\t-- NOP\n\t\t\t\tend case;\n\n\t\t\t\t-- saving former pixel values\n\t\t\t\tgfx_val <= v_gfx_val;\n\t\t\t\tgfx_bgnd <= v_gfx_bgnd;\n\t\t\t\tbg_sel <= v_bg_sel;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- OUTPUT --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\to_colr <= v_gfx_colr(to_integer(v_gfx_val));\n\t\t\t\to_bgnd <= v_gfx_bgnd;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- DIAGNOSTICS --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tif mark_mode then\n\t\t\t\t\to_bgnd <= '0';\n\n\t\t\t\t\tcase v_mode is\n", "right_context": "\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\to_colr <= x\"2\"; -- RED\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\twhen MODE_STD_BMAP =>\n\t\t\t\t\t\t\to_colr <= x\"3\"; -- CYAN\n\t\t\t\t\t\twhen MODE_MCL_BMAP =>\n\t\t\t\t\t\t\to_colr <= x\"4\"; -- PURPLE\n\t\t\t\t\t\twhen MODE_ECM_TEXT =>\n\t\t\t\t\t\t\to_colr <= x\"5\"; -- GREEN\n\t\t\t\t\t\twhen others =>\n\t\t\t\t\t\t\to_colr <= x\"6\"; -- BLUE\n\t\t\t\t\tend case;\n\t\t\t\tend if;\n\n\t\t\tend if;\n\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "\t\t\t\t\t\twhen MODE_STD_TEXT =>\n\t\t\t\t\t\t\to_colr <= x\"0\"; -- BLACK\n\t\t\t\t\t\twhen MODE_MCL_TEXT =>\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/graphics_mux.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity graphics_mux is\ngeneric\n(\n\tg_mark_lines : boolean := false\n);\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\tspecs : in t_vic_specs;\n\tstrb : in t_strb;\n\ti_xpos : in t_ppos;\n\ti_ypos : in t_ppos;\n\ti_bdln : in std_wire;\n\n\ti_mark_actv : in std_wire;\n\ti_mark_colr : in t_colr;\n\n\ti_bord_actv : in std_wire;\n\ti_bord_colr : in t_colr;\n\n\ti_grfx_colr : in t_colr;\n\ti_grfx_bgnd : in std_wire;\n\n\ti_sprt_actv : in std_wire;\n", "right_context": "\to_push : out std_wire;\n\to_lstr : out std_wire;\n\to_lend : out std_wire;\n\to_fstr : out std_wire;\n\to_colr : out t_colr;\n\n\tmark_bdln : in std_wire\n);\nend entity;\n\n\narchitecture rtl of graphics_mux is\n\n\tsignal rst_1r : std_wire := '1';\n\tsignal xval : std_wire;\n\tsignal yval : std_wire;\n\n\tsignal bord_actv_1r : std_wire;\n\tsignal bord_actv_2r : std_wire;\n\tsignal bord_actv_3r : std_wire;\n\tsignal bord_actv_4r : std_wire;\n\tsignal bord_actv_5r : std_wire;\n\tsignal bord_actv_6r : std_wire;\n\tsignal bord_actv_7r : std_wire;\n\tsignal bord_actv_8r : std_wire;\n\tsignal bord_actv_9r : std_wire;\n\n\tsignal bord_colr_1r : t_colr;\n\tsignal bord_colr_2r : t_colr;\n\n\tsignal sprt_actv_1r : std_wire;\n\tsignal sprt_actv_2r : std_wire;\n\n\tsignal sprt_prio_1r : std_wire;\n\tsignal sprt_prio_2r : std_wire;\n\n\tsignal sprt_colr_1r : t_colr;\n\tsignal sprt_colr_2r : t_colr;\n\nbegin\n\n\to_push <= xval and yval and strb(0);\n\n\tp_mux : process(clk) is\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\tif strb(0) = '0' then\n\n\t\t\t\tbord_actv_1r <= i_bord_actv;\n\t\t\t\tbord_actv_2r <= bord_actv_1r;\n\t\t\t\tbord_actv_3r <= bord_actv_2r;\n\t\t\t\tbord_actv_4r <= bord_actv_3r;\n\t\t\t\tbord_actv_5r <= bord_actv_4r;\n\t\t\t\tbord_actv_6r <= bord_actv_5r;\n\t\t\t\tbord_actv_7r <= bord_actv_6r;\n\t\t\t\tbord_actv_8r <= bord_actv_7r;\n\t\t\t\tbord_actv_9r <= bord_actv_8r;\n\n\t\t\t\tbord_colr_1r <= i_bord_colr;\n\t\t\t\tbord_colr_2r <= bord_colr_1r;\n\n\t\t\t\tsprt_actv_1r <= i_sprt_actv;\n\t\t\t\tsprt_actv_2r <= sprt_actv_1r;\n\n\t\t\t\tsprt_prio_1r <= i_sprt_prio;\n\t\t\t\tsprt_prio_2r <= sprt_prio_1r;\n\n\t\t\t\tsprt_colr_1r <= i_sprt_colr;\n\t\t\t\tsprt_colr_2r <= sprt_colr_1r;\n\n\n\t\t\t\to_lstr <= '0';\n\t\t\t\to_lend <= '0';\n\n\t\t\t\tif bord_actv_9r then\n\t\t\t\t\to_colr <= bord_colr_2r;\n\t\t\t\telse\n\t\t\t\t\tif (sprt_actv_2r = '0') or ((sprt_prio_2r = '0') and (i_grfx_bgnd = '0')) then\n\t\t\t\t\t\to_colr <= i_grfx_colr;\n\t\t\t\t\telse\n\t\t\t\t\t\to_colr <= sprt_colr_2r;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\tif i_mark_actv then\n\t\t\t\t\to_colr <= i_mark_colr;\n\t\t\t\tend if;\n\n\t\t\t\tif g_mark_lines then\n\t\t\t\t\tif (i_xpos >= specs.xnul) and (i_xpos <= specs.xnul + 16) and\n\t\t\t\t\t (i_ypos >= specs.ynul) and (i_ypos <= specs.yend )\n\t\t\t\t\tthen\n\t\t\t\t\t\to_colr <= lresize(i_ypos, 4);\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t-- marking badlines cyan\n\t\t\t\tif mark_bdln and i_bdln then\n\t\t\t\t\to_colr <= x\"3\";\n\t\t\t\tend if;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- FRAME ALIGNMENT SIGNALS --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tif (i_xpos = specs.xnul) then\n\t\t\t\t\to_lstr <= '1';\n\t\t\t\t\txval <= '1';\n\t\t\t\t\tif (i_ypos = specs.ynul) then\n\t\t\t\t\t\tyval <= '1';\n\t\t\t\t\t\to_fstr <= '1';\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\tif (i_xpos = specs.xend) then\n\t\t\t\t\to_lend <= '1';\n\t\t\t\tend if;\n\n\t\t\t\tif (i_xpos = specs.xend + 1) then\n\t\t\t\t\txval <= '0';\n\t\t\t\t\to_fstr <= '0';\n\t\t\t\t\tif (i_ypos = specs.yend) then\n\t\t\t\t\t\tyval <= '0';\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\t\t\tend if;\n\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "\ti_sprt_prio : in std_wire;\n\ti_sprt_colr : in t_colr;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/registers.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.gp3r_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity registers is\ngeneric\n(\n\tg_ext_code_tail : std_word_vector(open)(7 downto 0)\n);\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\t-- gp3r master\n\to_req : out t_gp3r_req;\n\to_rsp : in t_gp3r_rsp;\n\n\tstrb : in t_strb;\n\tdb : in std_word(11 downto 0);\n\ta : in unsigned(5 downto 0);\n\trw : in std_wire;\n\tcs : in std_wire;\n\n\treg : out t_regs;\n\twrt : out std_word(t_regs'range);\n\tgdot_en : in std_wire\n);\nend entity;\n\n\narchitecture rtl of registers is\n\n\tconstant c_code_len : positive := c_ext_code'length + g_ext_code_tail'length;\n\tconstant c_code : std_word_vector(0 to c_code_len - 1) := c_ext_code & g_ext_code_tail;\n\n\tsignal rst_1r : std_wire := '1';\n\tsignal enable : boolean;\n\tsignal cs_1r : std_wire;\n\n\tsignal wen : boolean;\n\tsignal a_tmp : a'subtype;\n\tsignal d_tmp : std_word(7 downto 0);\n\n\tsignal reg_addr : std_word(31 downto 0);\n\tsignal reg_data : std_word(31 downto 0);\n\n\tsignal ext_enable : boolean;\n\tsignal count_code : natural range 0 to c_code'length - 1;\n\n\tsignal reg_i : t_regs;\n\nbegin\n\n\treg_addr <= swap_endianness(merge(reg(c_reg_adr0_idx to c_reg_adr3_idx)));\n\treg_data <= swap_endianness(merge(reg(c_reg_dat0_idx to c_reg_dat3_idx)));\n\n\tp_regs : process(clk) is\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\tcs_1r <= cs;\n\n\t\t\tif (cs and cs_1r) then\n\t\t\t\tenable <= true;\n\t\t\tend if;\n\n\t\t\t-- handshake for the output master bus\n\t\t\tif (o_rsp.read = '1') then\n\t\t\t\to_req.push <= '0';\n\t\t\tend if;\n\n\t\t\to_req.read <= o_rsp.push;\n\t\t\to_req.r_nw <= '0';\n\n\t\t\t-- latching register value and operating master bus\n\t\t\tif (strb = 10) then\n\t\t\t\ta_tmp <= a;\n\t\t\t\twrt <= (others => '0');\n\n\t\t\t\tif (cs = '0') and (rw = '0') and enable then\n\t\t\t\t\twen <= true;\n\t\t\t\t\twrt(to_integer(a)) <= '1';\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\tif strb = 14 then\n\t\t\t\td_tmp <= db(7 downto 0);\n\t\t\tend if;\n\n\n\t\t\tif (strb = 15) then\n\t\t\t\tif wen then\n\t\t\t\t\twen <= false;\n\t\t\t\t\treg (to_integer(a_tmp)) <= d_tmp;\n\t\t\t\t\treg_i(to_integer(a_tmp)) <= d_tmp;\n\n\t\t\t\t\t-- the VIC contains 47 valid 8-bit registers [0:46] the rest\n\t\t\t\t\t-- are used by the CPU to establish a write-only connection to\n\t\t\t\t\t-- the HD-64 register bus. The connection does not support\n\t\t\t\t\t-- backpressure\n\n\t\t\t\t\t-- first of all, we run a simple state machine that verifies\n\t\t\t\t\t-- the special code necessary to enable the extended registes\n\n\t\t\t\t\tif (a_tmp = c_reg_code_idx) then\n\t\t\t\t\t\tif (d_tmp = c_code(count_code)) then\n\t\t\t\t\t\t\tif (count_code = c_code_len - 1) then\n\t\t\t\t\t\t\t\text_enable <= true;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tcount_code <= count_code + 1;\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount_code <= 0;\n\t\t\t\t\t\tend if;\n\t\t\t\t\tend if;\n\n\t\t\t\t\t-- then we run a simple gp3r_master that writes to the bus\n\t\t\t\t\t-- whenever a write is performed to the trigger register\n\n\t\t\t\t\tif (a_tmp = c_reg_trig_idx) and ext_enable then\n\t\t\t\t\t\tif (o_req.push = '0') or (o_rsp.read = '1') then\n\t\t\t\t\t\t\to_req.push <= '1';\n\t\t\t\t\t\t\to_req.addr <= vlresize(to_gp3r_addr(unsigned(reg_addr)), o_req.addr'length);\n\t\t\t\t\t\t\to_req.data <= vlresize(to_gp3r_data(reg_data), o_req.data'length);\n\t\t\t\t\t\tend if;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\t----------------------------------------------------------------\n\t\t\t-- GREY DOT BUG --\n\t\t\t----------------------------------------------------------------\n\n\t\t\tif strb(0) then\n\t\t\t\t-- aligned to strb=14 because it operates on all clock cycles\n\t\t\t\tif (gdot_en = '1') then\n\t\t\t\t\tfor i in 32 to 46 loop\n\t\t\t\t\t\tif (wrt(i) = '1') then\n\t\t\t\t\t\t\tif (strb = 13) then\n\t\t\t\t\t\t\t\t-- overriding with grey, will get re-overwritten\n\t\t\t\t\t\t\t\t-- on the next odd cycle\n\t\t\t\t\t\t\t\treg(i)(3 downto 0) <= x\"f\";\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\t\t\t\t\tend loop;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\t\t\t\tenable <= false;\n\t\t\t\twen <= false;\n\t\t\t\twrt <= (others => '0');\n\t\t\t\tcs_1r <= '1';\n\t\t\t\text_enable <= false;\n\t\t\t\tcount_code <= 0;\n", "right_context": "", "groundtruth": "\t\t\tend if;\n\t\tend if;\n\tend process;\n\nend architecture;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/sprites.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity sprites is\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\tspecs : in t_vic_specs;\n\twrt : in std_word(t_regs'range);\n\n\treg : in t_regs;\n\tstrb : in t_strb;\n\tcycl : in t_ppos;\n\txpos : in t_ppos;\n\typos : in t_ppos;\n\n\tenable : in std_word(7 downto 0);\n\tmark : in std_word(7 downto 0);\n\tenforce : in std_word(7 downto 0);\n", "right_context": "architecture rtl of sprites is\n\n\tsubtype t_xcount is natural range 0 to 24; -- generic counter\n\ttype t_xcount_vector is array(natural range <>) of t_xcount;\n\n\tsubtype t_ycount is unsigned(5 downto 0);\n\ttype t_ycount_vector is array(natural range <>) of t_ycount;\n\n\tsignal acquire : std_wire;\n\tsignal spen : std_word(7 downto 0);\n\tsignal prio : std_word(7 downto 0);\n\tsignal mxmc : std_word(7 downto 0);\n\tsignal xexp_1r : std_word(7 downto 0);\n\tsignal xexp_2r : std_word(7 downto 0);\n\tsignal xexp_3r : std_word(7 downto 0);\n\tsignal xexp_4r : std_word(7 downto 0);\n\tsignal yexp : std_word(7 downto 0);\n\tsignal yexp_1r : std_word(7 downto 0);\n\tsignal colr : t_colr_vector(0 to 7);\n\tsignal mclr : t_colr_vector(0 to 1);\n\tsignal sp_xpos : unsigned_vector(0 to 8)(8 downto 0);\n\tsignal sp_ypos : unsigned_vector(0 to 8)(7 downto 0);\n\n\tsignal xpos_1r : t_ppos;\n\tsignal xpos_2r : t_ppos;\n\tsignal xpos_3r : t_ppos;\n\tsignal xpos_4r : t_ppos;\n\tsignal xpos_5r : t_ppos;\n\tsignal xpos_6r : t_ppos;\n\n\tsignal ydisp : unsigned(7 downto 0);\n\tsignal ypend : unsigned(7 downto 0);\n\tsignal xdisp : unsigned(7 downto 0);\n\tsignal yincr : unsigned(7 downto 0);\n\tsignal xincr : unsigned(7 downto 0);\n\tsignal spdma : unsigned(7 downto 0);\n\n\tsignal count_sprt : integer range 0 to 7;\n\tsignal count_data : integer range 0 to 3;\n\tsignal count_mc : t_ycount_vector(0 to 7);\n\tsignal count_mb : t_ycount_vector(0 to 7);\n\tsignal count_xlen : t_xcount_vector(0 to 7);\n\tsignal shreg : unsigned_vector(0 to 7)(23 downto 0);\n\tsignal sprt_val : unsigned_vector(0 to 7)( 1 downto 0);\n\tsignal mc_phy : unsigned(7 downto 0);\n\n\tsignal rst_1r : std_wire := '1';\n\nbegin\n\n\tp_sprites : process(clk) is\n\t\tvariable v_sprt_val : sprt_val'element'subtype;\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\t--------------------------------------------------------------------\n\t\t\t-- these behave as sequential assignments as they operate on odd\n\t\t\t-- cycles too\n\n\t\t\tspen <= reg(21);\n\t\t\tprio <= not reg(27);\n\t\t\tmxmc <= reg(28);\n\t\t\tyexp <= reg(23);\n\n\t\t\tfor i in 0 to 7 loop\n\t\t\t\tcolr (i) <= unsigned(reg(39 + i)(3 downto 0));\n\t\t\t\tsp_ypos(i) <= unsigned(reg(i*2 + 1));\n\t\t\t\tsp_xpos(i) <= unsigned(reg(16)(i) & reg(i*2));\n\t\t\tend loop;\n\n\t\t\tmclr(0) <= unsigned(reg(37)(3 downto 0));\n\t\t\tmclr(1) <= unsigned(reg(38)(3 downto 0));\n\n\t\t\t--------------------------------------------------------------------\n\t\t\t-- rising edges of DOT clock\n\n\t\t\tif strb(0) then\n\n\t\t\t\txpos_1r <= xpos;\n\t\t\t\txpos_2r <= xpos_1r;\n\t\t\t\txpos_3r <= xpos_2r;\n\t\t\t\txpos_4r <= xpos_3r;\n\t\t\t\txpos_5r <= xpos_4r;\n\t\t\t\txpos_6r <= xpos_5r;\n\n\t\t\t\txexp_1r <= reg(29);\n\t\t\t\txexp_2r <= xexp_1r;\n\t\t\t\txexp_3r <= xexp_2r;\n\t\t\t\txexp_4r <= xexp_3r;\n\n\n\t\t\t\to_actv <= '0';\n\t\t\t\to_prio <= '0';\n\n\t\t\t\t-- looping over the sprites\n\t\t\t\tfor i in 7 downto 0 loop\n\n\t\t\t\t\t------------------------------------------------------------\n\t\t\t\t\t-- SPRITE PLAYBACK --\n\t\t\t\t\t------------------------------------------------------------\n\n\t\t\t\t\t-- horizontal trigger\n\t\t\t\t\tif ydisp(i) then\n\t\t\t\t\t\tif (xpos_6r = sp_xpos(i))\n\t\t\t\t\t\tthen\n\t\t\t\t\t\t\tcount_xlen(i) <= 0;\n\t\t\t\t\t\t\txdisp (i) <= '1';\n\t\t\t\t\t\t\txincr (i) <= not xexp_4r(i);\n\t\t\t\t\t\t\tmc_phy(i) <= '0';\n\t\t\t\t\t\tend if;\n\t\t\t\t\tend if;\n\n\t\t\t\t\t-- execution\n\t\t\t\t\tif xdisp(i) then\n\t\t\t\t\t\t-- handle multi-color here\n\t\t\t\t\t\tif mxmc(i) then\n\t\t\t\t\t\t\tif mc_phy(i) = '0' then\n\t\t\t\t\t\t\t\tv_sprt_val := shreg(i)(23 downto 22);\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tv_sprt_val := sprt_val(i);\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tv_sprt_val := shreg(i)(23) & '0';\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\tsprt_val(i) <= v_sprt_val;\n\n\t\t\t\t\t\t-- selecting color and transparency\n\t\t\t\t\t\tif (v_sprt_val /= \"00\") and (enable(i) = '1') then\n\t\t\t\t\t\t\to_actv <= '1';\n\t\t\t\t\t\t\to_prio <= prio(i);\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t-- bringing sprites forward when marking\n\t\t\t\t\t\tif mark(i) then\n\t\t\t\t\t\t\to_prio <= '1';\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\tif v_sprt_val = \"01\" then\n\t\t\t\t\t\t\to_colr <= mclr(0);\n\t\t\t\t\t\telsif v_sprt_val = \"10\" then\n\t\t\t\t\t\t\to_colr <= colr(i);\n\t\t\t\t\t\telsif v_sprt_val = \"11\" then\n\t\t\t\t\t\t\to_colr <= mclr(1);\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\tif (count_xlen(i) = 23) and (xincr(i) = '1') then\n\t\t\t\t\t\t\t-- horizontal end of a sprite\n\t\t\t\t\t\t\txdisp(i) <= '0';\n\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tif (xincr(i) = '1') then\n\t\t\t\t\t\t\t\tcount_xlen(i) <= count_xlen(i) + 1;\n\t\t\t\t\t\t\t\tshreg(i) <= lshift(shreg(i), 1);\n\t\t\t\t\t\t\t\tshreg(i)(0) <= '0';\n\t\t\t\t\t\t\t\tmc_phy(i) <= not mc_phy(i);\n\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t\tif xexp_4r(i) then\n\t\t\t\t\t\t\t\txincr(i) <= not xincr(i);\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\txincr(i) <= '1';\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\tif mark(i) then\n\t\t\t\t\t\t\tif (count_xlen(i) = 0 ) or\n\t\t\t\t\t\t\t (count_xlen(i) = 23 ) or\n\t\t\t\t\t\t\t (((count_mc(i) = 3 ) or (count_mc(i) = 63 )) and\n\t\t\t\t\t\t\t ((count_xlen(i) < 4) or (count_xlen(i) > 19)))\n\t\t\t\t\t\t\tthen\n\t\t\t\t\t\t\t\to_actv <= '1';\n\t\t\t\t\t\t\t\to_prio <= '1';\n\t\t\t\t\t\t\t\to_colr <= to_unsigned(i, 4);\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\tend if;\n\n\t\t\t\t\t------------------------------------------------------------\n\t\t\t\t\t-- VERTICAL TRIGGER --\n\t\t\t\t\t------------------------------------------------------------\n\n\t\t\t\t\tif strb = 3 then\n\n\t\t\t\t\t\tyexp_1r(i) <= yexp(i);\n\n\t\t\t\t\t\t-- delaying display by one character cycle\n\t\t\t\t\t\tydisp(i) <= ypend(i) or enforce(i);\n\n\t\t\t\t\t\tif (yexp(i) = '0') and (yincr(i) = '0') then\n\t\t\t\t\t\t\tyincr(i) <= '1';\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\tif ((cycl = specs.sprt_dma1_cycl)) then\n\t\t\t\t\t\t\tif (spdma(i) = '0') and (spen(i) = '1') and\n\t\t\t\t\t\t\t (sp_ypos(i) = ypos(7 downto 0))\n\t\t\t\t\t\t\tthen\n\t\t\t\t\t\t\t\tspdma(i) <= '1';\n\t\t\t\t\t\t\t\tyincr(i) <= '1';\n\t\t\t\t\t\t\t\tcount_mb(i) <= (others => '0');\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\tif ((cycl = specs.sprt_dma2_cycl)) then\n\t\t\t\t\t\t\tif (spdma(i) = '0') and (spen(i) = '1') and\n\t\t\t\t\t\t\t (sp_ypos(i) = ypos(7 downto 0))\n\t\t\t\t\t\t\tthen\n\t\t\t\t\t\t\t\tspdma(i) <= '1';\n\t\t\t\t\t\t\t\tyincr(i) <= '1';\n\t\t\t\t\t\t\t\tcount_mb(i) <= (others => '0');\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\tif (cycl = specs.sprt_yexp_cycl) then\n\t\t\t\t\t\t\tif (spdma(i) and yexp(i)) then\n\t\t\t\t\t\t\t\tyincr(i) <= not yincr(i);\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t-- turning on the display\n\t\t\t\t\t\tif (cycl = specs.sprt_disp_cycl) then\n\t\t\t\t\t\t\tcount_mc(i) <= count_mb(i);\n\n\t\t\t\t\t\t\tif (spdma(i) = '1') then\n\t\t\t\t\t\t\t\tif (sp_ypos(i) = ypos(7 downto 0)) and (spen(i) = '1') then\n\t\t\t\t\t\t\t\t\typend(i) <= '1';\n\t\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\typend(i) <= '0';\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t-- updating MC\n\t\t\t\t\t\tif (cycl = 14) then\n\t\t\t\t\t\t\t-- doesn't really matter when we update the counter as long as it is\n\t\t\t\t\t\t\t-- after (if) the DMA has been turned on and before it is turned off\n\t\t\t\t\t\t\tcount_mc(i) <= count_mc(i) + 3;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t-- upddating MCBASE\n\t\t\t\t\t\tif (cycl = 15) then\n\t\t\t\t\t\t\tif yincr(i) = '1' then\n\t\t\t\t\t\t\t\tcount_mb(i) <= count_mc(i);\n\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t\t-- handle sprite crunch\n\t\t\t\t\t\t\tif yincr(i) = '0' then\n\t\t\t\t\t\t\t\tif (spdma(i) = '1') and (yexp(i) = '0') and (yexp_1r(i) = '1') and (wrt(23) = '1') then\n\t\t\t\t\t\t\t\t\tcount_mb(i) <= (\"101010\" and (count_mb(i) and count_mc(i))) or\n\t\t\t\t\t\t\t\t\t (\"010101\" and (count_mb(i) or count_mc(i)));\n\t\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t-- we could turn off the DMA anywhere between the update of mb and the\n\t\t\t\t\t\t-- check for start\n\t\t\t\t\t\tif (cycl = specs.sprt_dma1_cycl - 1) then\n\t\t\t\t\t\t\tif count_mb(i) = 63 then\n\t\t\t\t\t\t\t\tspdma(i) <= '0';\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\tend if;\n\t\t\t\t\tend if;\n\t\t\t\tend loop;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- SPRITE ACQUISITION --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tif (strb = 1) and (cycl = specs.sprt_strt_cycl) then\n\t\t\t\t\t-- initiate sprite data acquisition on all lines\n\t\t\t\t\tcount_sprt <= 0;\n\t\t\t\t\tcount_data <= 3;\n\t\t\t\t\tacquire <= '1';\n\t\t\t\tend if;\n\n\t\t\t\t-- sprite data acquisition\n\t\t\t\tif acquire then\n\t\t\t\t\tif count_data /= 3 then\n\t\t\t\t\t\t-- holding the shift register while it's being filled\n\t\t\t\t\t\tshreg(count_sprt) <= shreg(count_sprt);\n\t\t\t\t\tend if;\n\n\t\t\t\t\tif (strb = 7) or (strb = 15) then\n\t\t\t\t\t\tif (count_data /= 3) then\n\t\t\t\t\t\t\tif count_data = 0 then\n\t\t\t\t\t\t\t\tshreg(count_sprt)(23 downto 16) <= unsigned(i_data(7 downto 0));\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\t\tif count_data = 1 then\n\t\t\t\t\t\t\t\tshreg(count_sprt)(15 downto 8) <= unsigned(i_data(7 downto 0));\n\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\t\tif count_data = 2 then\n\t\t\t\t\t\t\t\tshreg(count_sprt)(7 downto 0) <= unsigned(i_data(7 downto 0));\n\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t\tif (count_data = 2) then\n\t\t\t\t\t\t\t\tif (count_sprt = 7) then\n\t\t\t\t\t\t\t\t\tacquire <= '0';\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tcount_sprt <= count_sprt + 1;\n\t\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t\tcount_data <= count_data + 1;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tcount_data <= 0;\n\t\t\t\t\t\tend if;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t----------------------------------------------------------------\n\t\t\t\t-- OTHER --\n\t\t\t\t----------------------------------------------------------------\n\n\t\t\t\tif false then\n\t\t\t\t\t-- just marking a specific column\n\t\t\t\t\tif (strb = 1) and (cycl = specs.sprt_disp_cycl) then\n\t\t\t\t\t\to_actv <= '1';\n\t\t\t\t\t\to_prio <= '1';\n\t\t\t\t\t\to_colr <= to_unsigned(1, 4);\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\tend if;\n\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\t\t\t\tacquire <= '0';\n\t\t\t\txdisp <= (others => '0');\n\t\t\t\tydisp <= (others => '0');\n\t\t\t\tspdma <= (others => '0');\n\t\t\tend if;\n\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "\n\ti_data : in std_word(7 downto 0);\n\to_prio : out std_wire;\n\to_actv : out std_wire;\n\to_colr : out t_colr\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/strobe.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n-- --\n-- Crucially, the ph0 signal LEADS slightly compared to the VIC clock, so --\n-- strobe-0 corresponds to the first half-cycle of the VIC clock where ph0 --\n-- is zero for the entire time --\n-- ______________ _______________ _____ --\n-- ph0 |_______________| |_______________| --\n-- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ --\n-- vic _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ --\n-- --\n-- clk _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| --\n-- str 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 --\n-- --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity strobe is\n", "right_context": "\tph0 : in std_wire;\n\tstrb : out t_strb\n);\nend entity;\n\n\narchitecture rtl of strobe is\n\n\tsignal rst_1r : std_wire := '1';\n\tsignal ph0_1r : std_wire;\n\nbegin\n\n\ti_strobe_gen : process(clk) is\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\t-- we make sure that additional edges don't cause wraparounds\n\t\t\tif strb /= 0 then\n\t\t\t\tstrb <= strb + 1;\n\t\t\tend if;\n\n\t\t\t-- we intentionally skip rising edges of the dot-clock to sample\n\t\t\t-- phi0 because phi0 edges are too close to dot-clock rising edges\n\t\t\tif (dot = '1') then\n\t\t\t\tph0_1r <= ph0;\n\t\t\t\tif (ph0_1r = '1') and (ph0 = '0') then\n\t\t\t\t\tstrb <= to_unsigned(1, strb'length);\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n\t\t\t\tph0_1r <= '0';\n\t\t\t\tstrb <= (others => '0');\n\t\t\tend if;\n\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "port\n(\n\tclk : in std_wire;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/sync_flex.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity sync_flex is\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\ta : in t_addr;\n\tstrb : in t_strb;\n\n\tenable : in std_wire;\n\n\tspecs : out t_vic_specs;\n\tlock : out std_wire;\n\tcycl : out t_ppos;\n\txpos : out t_ppos;\n\typos : out t_ppos;\n\n\tdgn_out : out std_word(3 downto 0) := (others => '0')\n);\nend entity;\n\n\narchitecture rtl of sync_flex is\n\n\tsignal h63_lock : std_wire;\n\tsignal h63_cycl : t_ppos;\n\tsignal h63_xpos : t_ppos;\n\tsignal h63_ypos : t_ppos;\n\n\tsignal h64_lock : std_wire;\n\tsignal h64_cycl : t_ppos;\n\tsignal h64_xpos : t_ppos;\n\tsignal h64_ypos : t_ppos;\n\n\tsignal h65_lock : std_wire;\n\tsignal h65_cycl : t_ppos;\n\tsignal h65_xpos : t_ppos;\n\tsignal h65_ypos : t_ppos;\n\nbegin\n\n\ti_h63_sync : entity work.xy_sync\n\tport map\n\t(\n\t\tclk => clk,\n\t\trst => rst,\n\t\ta => a,\n\t\tstrb => strb,\n\t\tenable => enable,\n\t\tspecs => c_vic_h63_specs,\n\t\tlock => h63_lock,\n\t\tcycl => h63_cycl,\n\t\txpos => h63_xpos,\n\t\typos => h63_ypos,\n\t\tdgn_out => open --dgn_out\n\t);\n\n\n\ti_h64_sync : entity work.xy_sync\n\tport map\n\t(\n\t\tclk => clk,\n\t\trst => rst,\n\t\ta => a,\n\t\tstrb => strb,\n\t\tenable => enable,\n\t\tspecs => c_vic_h64_specs,\n\t\tlock => h64_lock,\n\t\tcycl => h64_cycl,\n\t\txpos => h64_xpos,\n\t\typos => h64_ypos,\n\t\tdgn_out => open --dgn_out\n\t);\n\n\n\ti_h65_sync : entity work.xy_sync\n\tport map\n\t(\n\t\tclk => clk,\n\t\trst => rst,\n\t\ta => a,\n\t\tstrb => strb,\n\t\tenable => enable,\n\t\tspecs => c_vic_h65_specs,\n\t\tlock => h65_lock,\n\t\tcycl => h65_cycl,\n\t\txpos => h65_xpos,\n\t\typos => h65_ypos,\n\t\tdgn_out => open --dgn_out\n\t);\n\n\n\tp_mux : process(all) is\n\tbegin\n\t\tif (h63_lock = '1') then\n\t\t\tlock <= h63_lock;\n\t\t\tcycl <= h63_cycl;\n\t\t\txpos <= h63_xpos;\n\t\t\typos <= h63_ypos;\n\t\t\tspecs <= c_vic_h63_specs;\n\n\t\telsif h64_lock then\n\t\t\tlock <= h64_lock;\n\t\t\tcycl <= h64_cycl;\n\t\t\txpos <= h64_xpos;\n\t\t\typos <= h64_ypos;\n\t\t\tspecs <= c_vic_h64_specs;\n\n\t\telsif h65_lock then\n\t\t\tlock <= h65_lock;\n\t\t\tcycl <= h65_cycl;\n\t\t\txpos <= h65_xpos;\n", "right_context": "\t\t\tcycl <= (others => '0');\n\t\t\txpos <= (others => '0');\n\t\t\typos <= (others => '0');\n\t\t\tspecs <= c_vic_h63_specs;\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "\t\t\typos <= h65_ypos;\n\t\t\tspecs <= c_vic_h65_specs;\n\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/vic_passive.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.gp3r_pkg.all;\nuse work.vic_pkg.all;\nuse work.memmap_vicii_pkg.all;\n\n\nentity vic_passive is\ngeneric\n(\n\tg_ext_code_tail : std_word_vector(open)(7 downto 0);\n\tg_log_only : boolean := false\n);\nport\n(\n\t-- VIC signals\n\tclk : in std_wire; -- must be twice the video clock (16 times ph0)\n\trst : in std_wire;\n\tdot : in std_wire;\n\n\t-- gp3r master\n\to_req : out t_gp3r_req;\n\to_rsp : in t_gp3r_rsp;\n\n\t-- gp3r_slave\n\ti_req : in t_gp3r_req;\n\ti_rsp : out t_gp3r_rsp;\n\n", "right_context": "\t-- memory bus\n\tph0 : in std_wire;\n\tdb : in std_word(11 downto 0);\n\ta : in t_addr;\n\trw : in std_wire;\n\tcs : in std_wire;\n\taec : in std_wire;\n\n\to_push : out std_wire;\n\to_lstr : out std_wire;\n\to_fstr : out std_wire;\n\to_lend : out std_wire;\n\to_colr : out t_colr;\n\n\t-- feature switches\n\tgdot_en : in std_wire;\n\n\t-- diagnostics\n\tsprt_en : in std_word(7 downto 0) := (others => '1');\n\tbord_en : in std_word(1 downto 0) := (others => '1');\n\tidle_en : in std_wire := '1';\n\tmark_mode : in std_wire := '0';\n\tmark_bdln : in std_wire := '0';\n\tmark_sprt : in std_word(7 downto 0) := (others => '0');\n\tforce_sprt : in std_word(7 downto 0) := (others => '0');\n\tlock : out std_wire\n);\nend entity;\n\n\narchitecture rtl of vic_passive is\n\n\tsignal req_bus_logger : t_gp3r_req_tpl := c_gp3r_req_tpl;\n\tsignal rsp_bus_logger : t_gp3r_rsp_tpl := c_gp3r_rsp_tpl;\n\n\tsignal mf_ph0 : ph0'subtype;\n\tsignal mf_db : db 'subtype;\n\tsignal mf_a : a 'subtype;\n\tsignal mf_rw : rw 'subtype;\n\tsignal mf_cs : cs 'subtype;\n\tsignal mf_aec : aec'subtype;\n\n\tsignal reg : t_regs;\n\tsignal wrt : std_word(t_regs'range);\n\tsignal strb : t_strb;\n\tsignal specs : t_vic_specs;\n\tsignal cycl : t_ppos;\n\tsignal bdln : std_wire;\n\tsignal ccax : std_wire;\n\tsignal xpos : t_ppos;\n\tsignal ypos : t_ppos;\n\n\tsignal cc_vm : db'subtype;\n\tsignal gg_vm : std_word(7 downto 0);\n\tsignal grfx_actv : std_wire;\n\tsignal vbrd_actv : std_wire;\n\tsignal bord_actv : std_wire;\n\tsignal bord_colr : t_colr;\n\n\tsignal mark_actv : std_wire := '0';\n\tsignal mark_colr : t_colr := x\"0\";\n\n\tsignal grfx_colr : t_colr;\n\tsignal grfx_bgnd : std_wire;\n\n\tsignal sprt_actv : std_wire;\n\tsignal sprt_prio : std_wire;\n\tsignal sprt_colr : t_colr;\n\nbegin\n\n\tvic_type <= specs.tvic;\n\n\ti_bus_latch : entity work.bus_latch\n\tgeneric map\n\t(\n\t\tg_enable => false\n\t)\n\tport map\n\t(\n\t\tclk => clk,\n\t\trst => rst,\n\n\t\ti_ph0 => ph0,\n\t\ti_db => db ,\n\t\ti_a => a ,\n\t\ti_rw => rw ,\n\t\ti_cs => cs ,\n\t\ti_aec => aec,\n\n\t\to_ph0 => mf_ph0,\n\t\to_db => mf_db ,\n\t\to_a => mf_a ,\n\t\to_rw => mf_rw ,\n\t\to_cs => mf_cs ,\n\t\to_aec => mf_aec\n\t);\n\n\n\ti_strobe : entity work.strobe\n\tport map\n\t(\n\t\tclk => clk,\n\t\trst => rst,\n\t\tdot => dot,\n\t\tph0 => mf_ph0,\n\t\tstrb => strb\n\t);\n\n\n\ti_registers : entity work.registers\n\tgeneric map\n\t(\n\t\tg_ext_code_tail => g_ext_code_tail\n\t)\n\tport map\n\t(\n\t\t-- VIC signals\n\t\tclk => clk,\n\t\trst => rst,\n\n\t\to_req => o_req,\n\t\to_rsp => o_rsp,\n\n\t\tstrb => strb,\n\t\tdb => mf_db ,\n\t\ta => mf_a ,\n\t\trw => mf_rw ,\n\t\tcs => mf_cs ,\n\t\treg => reg,\n\t\twrt => wrt,\n\t\tgdot_en => gdot_en\n\t);\n\n\n\ti_frame_sync : entity work.sync_flex\n\tport map\n\t(\n\t\tclk => clk,\n\t\trst => rst,\n\t\ta => mf_a,\n\t\tstrb => strb,\n\t\tenable => '1',\n\t\tspecs => specs,\n\t\tlock => lock,\n\t\tcycl => cycl,\n\t\txpos => xpos,\n\t\typos => ypos,\n\t\tdgn_out => open --dgn_out\n\t);\n\n\n\tr_graphics : if not g_log_only generate\n\n\t\t------------------------------------------------------------------------\n\t\t-- BADLINE DETECTION --\n\t\t------------------------------------------------------------------------\n\n\t\ti_bdln_detect : entity work.bad_line_detect\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treg => reg,\n\t\t\taec => mf_aec,\n\t\t\tstrb => strb,\n\t\t\tcycl => cycl,\n\t\t\typos => ypos,\n\t\t\tbdln => bdln,\n\t\t\tccax => ccax\n\t\t);\n\n\t\t------------------------------------------------------------------------\n\t\t-- VIDEO MATRIX --\n\t\t------------------------------------------------------------------------\n\n\t\ti_video_matrix : entity work.video_matrix\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\tstrb => strb,\n\t\t\tcycl => cycl,\n\t\t\tbdln => bdln,\n\t\t\tccax => ccax,\n\t\t\typos => ypos,\n\t\t\tspecs => specs,\n\t\t\ti_db => mf_db,\n\t\t\to_cc => cc_vm,\n\t\t\to_gg => gg_vm,\n\t\t\to_en => grfx_actv,\n\t\t\tidle_en => idle_en\n\t\t);\n\n\t\t------------------------------------------------------------------------\n\t\t-- GRAPHICS GENERATOR --\n\t\t------------------------------------------------------------------------\n\n\t\ti_graphics_gen : entity work.graphics_gen\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treg => reg,\n\t\t\tstrb => strb,\n\t\t\ti_actv => grfx_actv,\n\t\t\ti_vbrd => vbrd_actv,\n\t\t\ti_grfx => gg_vm,\n\t\t\ti_data => cc_vm,\n\t\t\to_bgnd => grfx_bgnd,\n\t\t\to_colr => grfx_colr,\n\n\t\t\tmark_mode => mark_mode\n\t\t);\n\n\t\t------------------------------------------------------------------------\n\t\t-- BORDER GENERATOR --\n\t\t------------------------------------------------------------------------\n\n\t\ti_border : entity work.border\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\tstrb => strb,\n\t\t\tspecs => specs,\n\t\t\tcycl => cycl,\n\t\t\txpos => xpos,\n\t\t\typos => ypos,\n\t\t\treg => reg,\n\t\t\to_vbrd => vbrd_actv,\n\t\t\to_bord => bord_actv,\n\t\t\to_colr => bord_colr,\n\t\t\tenable => bord_en\n\n--\t\t\t-- marking border events\n--\t\t\tmark_bord => mark_actv,\n--\t\t\tmark_colr => mark_colr\n\t\t);\n\n\t\t------------------------------------------------------------------------\n\t\t-- SPRITE GENERATOR --\n\t\t------------------------------------------------------------------------\n\n\t\ti_sprites : entity work.sprites\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\tspecs => specs,\n\t\t\treg => reg,\n\t\t\twrt => wrt,\n\t\t\tstrb => strb,\n\t\t\tcycl => cycl,\n\t\t\txpos => xpos,\n\t\t\typos => ypos,\n\t\t\tenable => sprt_en,\n\t\t\tmark => mark_sprt,\n\t\t\tenforce => force_sprt,\n\n\t\t\ti_data => mf_db(7 downto 0),\n\t\t\to_prio => sprt_prio,\n\t\t\to_actv => sprt_actv,\n\t\t\to_colr => sprt_colr\n\t\t);\n\n\t\t------------------------------------------------------------------------\n\t\t-- GRAPHICS MULTIPLEXER --\n\t\t------------------------------------------------------------------------\n\n\t\ti_graphics_mux : entity work.graphics_mux\n\t\tgeneric map\n\t\t(\n\t\t\tg_mark_lines => false\n\t\t)\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\tspecs => specs,\n\t\t\tstrb => strb,\n\t\t\ti_bdln => bdln,\n\t\t\ti_xpos => xpos,\n\t\t\ti_ypos => ypos,\n\n\t\t\ti_mark_actv => mark_actv,\n\t\t\ti_mark_colr => mark_colr,\n\n\t\t\ti_bord_actv => bord_actv,\n\t\t\ti_bord_colr => bord_colr,\n\n\t\t\ti_sprt_actv => sprt_actv,\n\t\t\ti_sprt_prio => sprt_prio,\n\t\t\ti_sprt_colr => sprt_colr,\n\n\t\t\ti_grfx_colr => grfx_colr,\n\t\t\ti_grfx_bgnd => grfx_bgnd,\n\n\t\t\to_push => o_push,\n\t\t\to_lstr => o_lstr,\n\t\t\to_lend => o_lend,\n\t\t\to_fstr => o_fstr,\n\t\t\to_colr => o_colr,\n\n\t\t\tmark_bdln => mark_bdln\n\t\t);\n\n\n\t\t-- dummy to terminate the logger bus\n\t\ti_nack : entity work.gp3r_dummy\n\t\tgeneric map\n\t\t(\n\t\t\tg_nack => c_gp3r_nack_addr\n\t\t)\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treq => i_req,\n\t\t\trsp => i_rsp\n\t\t);\n\n\telse generate\n\n\t\ti_bus_logger : entity work.bus_logger\n\t\tgeneric map\n\t\t(\n\t\t\tg_enable => false\n\t\t)\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treq => req_bus_logger,\n\t\t\trsp => rsp_bus_logger,\n\t\t\txpos => xpos,\n\t\t\typos => ypos,\n\t\t\tstrb => strb,\n\t\t\tph0 => mf_ph0,\n\t\t\tdb => mf_db,\n\t\t\ta => mf_a,\n\t\t\trw => mf_rw,\n\t\t\tcs => mf_cs,\n\t\t\taec => mf_aec\n\t\t);\n\n\n\t\ti_memmap_vicii : entity work.memmap_vicii\n\t\tport map\n\t\t(\n\t\t\tclk => clk,\n\t\t\trst => rst,\n\t\t\treq => i_req,\n\t\t\trsp => i_rsp,\n\t\t\treq_bus_logger => req_bus_logger,\n\t\t\trsp_bus_logger => rsp_bus_logger,\n\t\t\treg_0 => reg(0 ),\n\t\t\treg_1 => reg(1 ),\n\t\t\treg_2 => reg(2 ),\n\t\t\treg_3 => reg(3 ),\n\t\t\treg_4 => reg(4 ),\n\t\t\treg_5 => reg(5 ),\n\t\t\treg_6 => reg(6 ),\n\t\t\treg_7 => reg(7 ),\n\t\t\treg_8 => reg(8 ),\n\t\t\treg_9 => reg(9 ),\n\t\t\treg_10 => reg(10),\n\t\t\treg_11 => reg(11),\n\t\t\treg_12 => reg(12),\n\t\t\treg_13 => reg(13),\n\t\t\treg_14 => reg(14),\n\t\t\treg_15 => reg(15),\n\t\t\treg_16 => reg(16),\n\t\t\treg_17 => reg(17),\n\t\t\treg_18 => reg(18),\n\t\t\treg_19 => reg(19),\n\t\t\treg_20 => reg(20),\n\t\t\treg_21 => reg(21),\n\t\t\treg_22 => reg(22),\n\t\t\treg_23 => reg(23),\n\t\t\treg_24 => reg(24),\n\t\t\treg_25 => reg(25),\n\t\t\treg_26 => reg(26),\n\t\t\treg_27 => reg(27),\n\t\t\treg_28 => reg(28),\n\t\t\treg_29 => reg(29),\n\t\t\treg_30 => reg(30),\n\t\t\treg_31 => reg(31),\n\t\t\treg_32 => reg(32),\n\t\t\treg_33 => reg(33),\n\t\t\treg_34 => reg(34),\n\t\t\treg_35 => reg(35),\n\t\t\treg_36 => reg(36),\n\t\t\treg_37 => reg(37),\n\t\t\treg_38 => reg(38),\n\t\t\treg_39 => reg(39),\n\t\t\treg_40 => reg(40),\n\t\t\treg_41 => reg(41),\n\t\t\treg_42 => reg(42),\n\t\t\treg_43 => reg(43),\n\t\t\treg_44 => reg(44),\n\t\t\treg_45 => reg(45),\n\t\t\treg_46 => reg(46)\n\t\t);\n\n\tend generate;\n\nend architecture;\n", "groundtruth": "\t-- vic detection\n\tvic_type : out t_vic_type;\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/vic_pkg.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\n\n\npackage vic_pkg is\n\n\tconstant c_xres_h63 : positive := 403;\n\tconstant c_yres_h63 : positive := 284;\n\n\tconstant c_num_regs : positive := 64;\n\tconstant c_max_xlen : positive := 65 * 8;\n\tconstant c_max_ylen : positive := 312;\n\n", "right_context": "\tconstant c_ypos_bits : positive := bits_for_range(c_max_ylen);\n\tconstant c_ppos_bits : positive := maximum(c_xpos_bits, c_ypos_bits);\n\n\tsubtype t_colr is unsigned(3 downto 0);\n\tsubtype t_ppos is unsigned(c_ppos_bits - 1 downto 0);\n\tsubtype t_addr is unsigned(5 downto 0);\n\tsubtype t_strb is unsigned(3 downto 0);\n\tsubtype t_regs is std_word_vector(0 to c_num_regs - 1) (7 downto 0);\n\n\tsubtype t_colr_vector is unsigned_vector(open)(3 downto 0);\n\n\tfunction to_ppos(x : natural; m : natural := 0) return t_ppos;\n\n\ttype t_vic_type is\n\t(\n\t\tvic_h63,\n\t\tvic_h64,\n\t\tvic_h65\n\t);\n\n\n\ttype t_vic_mode is\n\t(\n\t\tmode_std_text,\n\t\tmode_mcl_text,\n\t\tmode_std_bmap,\n\t\tmode_mcl_bmap,\n\t\tmode_ecm_text,\n\t\tmode_invalid\n\t);\n\n\n\t-- this implementation\n\n\ttype t_vic_specs is record\n\t\ttvic : t_vic_type;\n\n\t\tcycl : t_ppos; -- Number of characters (visible & invisible) in a line\n\t\txref : t_ppos; -- x position for the synchronization cycle (end of RAM refresh for each line)\n\t\txnul : t_ppos; -- x position of the first visible pixel (line start)\n\t\txend : t_ppos; -- x position of the last visible pixel (line end)\n\t\txlen : t_ppos; -- total pixels in a line (cycl * 8)\n\t\txres : t_ppos; -- total visible pixels in a line\n\t\txfvc : t_ppos; -- first pixel of active area\n\t\txlvc : t_ppos; -- last pixel of active area\n\n\t\tyref : t_ppos; -- y position for the synchronization line (RAM refresh)\n\t\tynul : t_ppos; -- y position of the first visible pixel\n\t\tyend : t_ppos; -- y position of the last visible pixel\n\t\tylen : t_ppos; -- total lines in a frame\n\t\tyres : t_ppos; -- total visible lines in a frame\n\t\tyfvc : t_ppos; -- first line of active area\n\t\tylvc : t_ppos; -- last line of active area\n\n\t\tsprt_dma1_cycl : t_ppos;\n\t\tsprt_dma2_cycl : t_ppos;\n\t\tsprt_yexp_cycl : t_ppos;\n\t\tsprt_disp_cycl : t_ppos;\n\t\tsprt_strt_cycl : t_ppos;\n\tend record;\n\n\t-- PAL with 63 lines\n\tconstant c_vic_h63_specs : t_vic_specs :=\n\t(\n\t\ttvic => vic_h63,\n\n\t\tcycl => to_ppos(63), -- number of character cycles in a line\n\t\txref => to_ppos(16), -- value of xpos on the 1st clock cycle of the 1st character access after the refresh pattern\n\t\txlen => to_ppos(504), -- number of pixels in a line\n\t\txres => to_ppos(402), -- visible pixels in a line\n\t\txnul => to_ppos(498), -- solely needed to center the picture\n\t\txend => to_ppos(498 + 402 - 1, 504), -- ((xnul + xres - 1) % xlen)\n\t\txfvc => to_ppos(24), -- first video coordinate (after border)\n\t\txlvc => to_ppos(24 + 319), -- last video coordinate (before border)\n\n\t\tyref => to_ppos(0),\n\t\tylen => to_ppos(312),\n\t\tyres => to_ppos(284),\n\t\tynul => to_ppos(8),\n\t\tyend => to_ppos(8 + 280 - 1),\n\t\tyfvc => to_ppos(51),\n\t\tylvc => to_ppos(51 + 199),\n\n\t\tsprt_dma1_cycl => to_ppos(54),\n\t\tsprt_dma2_cycl => to_ppos(55),\n\t\tsprt_yexp_cycl => to_ppos(55),\n\t\tsprt_disp_cycl => to_ppos(57),\n\t\tsprt_strt_cycl => to_ppos(57)\n\t);\n\n\t-- NTSC with 64 lines\n\tconstant c_vic_h64_specs : t_vic_specs :=\n\t(\n\t\ttvic => vic_h64,\n\n\t\tcycl => to_ppos(64),\n\t\txref => to_ppos(16),\n\t\txlen => to_ppos(512),\n\t\txres => to_ppos(420),\n\t\txnul => to_ppos(495),\n\t\txend => to_ppos(495 + 420 - 1, 512),\n\t\txfvc => to_ppos(24),\n\t\txlvc => to_ppos(24 + 319),\n\n\t\tyref => to_ppos(0),\n\t\tylen => to_ppos(262),\n\t\tyres => to_ppos(252),\n\t\tynul => to_ppos(26),\n\t\tyend => to_ppos(26 + 252 - 1, 262),\n\t\tyfvc => to_ppos(51),\n\t\tylvc => to_ppos(51 + 199),\n\n\t\tsprt_dma1_cycl => to_ppos(55),\n\t\tsprt_dma2_cycl => to_ppos(56),\n\t\tsprt_yexp_cycl => to_ppos(56),\n\t\tsprt_disp_cycl => to_ppos(57),\n\t\tsprt_strt_cycl => to_ppos(58)\n\t);\n\n\t-- NTSC with 65 lines\n\tconstant c_vic_h65_specs : t_vic_specs :=\n\t(\n\t\ttvic => vic_h65,\n\n\t\tcycl => to_ppos(65),\n\t\txref => to_ppos(16),\n\t\txlen => to_ppos(520),\n\t\txres => to_ppos(420),\n\t\txnul => to_ppos(504),\n\t\txend => to_ppos(504 + 420 - 1, 520),\n\t\txfvc => to_ppos(24),\n\t\txlvc => to_ppos(24 + 319),\n\n\t\tyref => to_ppos(0),\n\t\tylen => to_ppos(263),\n\t\tyres => to_ppos(252),\n\t\tynul => to_ppos(25),\n\t\tyend => to_ppos(25 + 252 - 1, 263),\n\t\tyfvc => to_ppos(51),\n\t\tylvc => to_ppos(51 + 199),\n\n\t\tsprt_dma1_cycl => to_ppos(55),\n\t\tsprt_dma2_cycl => to_ppos(56),\n\t\tsprt_yexp_cycl => to_ppos(56),\n\t\tsprt_disp_cycl => to_ppos(58),\n\t\tsprt_strt_cycl => to_ppos(58)\n\t);\n\n\tconstant c_csmp_strb : t_strb := to_unsigned(6, 4);\n\tconstant c_cycl_ref : t_ppos := to_ppos(14); -- -1 from the docs because they start from 1... :(\n\tconstant c_cycl_vend : t_ppos := to_ppos(54); -- like above :(\n\tconstant c_cycle_yff : t_ppos := to_ppos(62); -- same same :(\n\n\t-- these are constants for accessing the system's register bus from the C64\n\t-- CPU and shall be replicated manually in the C64 code\n\n\tconstant c_reg_code_idx : natural := 47;\n\tconstant c_reg_trig_idx : natural := 48;\n\n\tconstant c_reg_adr0_idx : natural := 49;\n\tconstant c_reg_adr1_idx : natural := 50;\n\tconstant c_reg_adr2_idx : natural := 51;\n\tconstant c_reg_adr3_idx : natural := 52;\n\n\tconstant c_reg_dat0_idx : natural := 53;\n\tconstant c_reg_dat1_idx : natural := 54;\n\tconstant c_reg_dat2_idx : natural := 55;\n\tconstant c_reg_dat3_idx : natural := 56;\n\n\tconstant c_ext_code : std_word_vector(0 to 5)(7 downto 0) :=\n\t(\n\t\tx\"fe\",\n\t\tx\"ed\",\n\t\tx\"60\",\n\t\tx\"0d\",\n\t\tx\"f0\",\n\t\tx\"0d\"\n\t);\n\nend package;\n\n\npackage body vic_pkg is\n\n\tfunction to_ppos(x : natural; m : natural := 0) return t_ppos is\n\t\tvariable ret : integer := x;\n\tbegin\n\t\tif m /= 0 then\n\t\t\tret := x mod m;\n\t\tend if;\n\t\treturn ltrim(unsigned(to_signed(ret, t_ppos'length + 1)), 1);\n\tend function;\n\nend package body;\n", "groundtruth": "\tconstant c_xpos_bits : positive := bits_for_range(c_max_xlen);\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/video_matrix.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity video_matrix is\ngeneric\n(\n\tg_mark_bdln : boolean := false\n);\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\n\tstrb : in t_strb;\n\tcycl : in t_ppos;\n\tbdln : in std_wire;\n\tccax : in std_wire;\n\typos : in t_ppos;\n\tspecs : in t_vic_specs;\n\n\ti_db : in std_word(11 downto 0);\n\to_cc : out std_word(11 downto 0); -- color info\n\to_gg : out std_word( 7 downto 0); -- graphics info\n\to_en : out std_wire;\n\n\tidle_en : in std_wire := '1'\n);\nend entity;\n\n\narchitecture rtl of video_matrix is\n\n\tconstant c_ram_len : positive := 40;\n\tconstant c_ram_width : positive := i_db'length;\n\tconstant c_addr_bits : positive := bits_for_range(c_ram_len);\n\n\tsignal rst_1r : std_wire := '1';\n\tsignal ram_wadd : unsigned(c_addr_bits - 1 downto 0);\n\tsignal ram_wdat : std_word(c_ram_width - 1 downto 0);\n\tsignal ram_wen : std_wire;\n\tsignal ram_radd : unsigned(c_addr_bits - 1 downto 0);\n\tsignal ram_rdat : std_word(c_ram_width - 1 downto 0);\n\n\tsignal count_line : natural range 0 to 8;\n\tsignal count_cycl : natural range 0 to c_ram_len;\n\n\tsignal bdln_1r : std_wire;\n\tsignal idle : std_wire;\n\nbegin\n\n\ti_ram : entity work.true_dual_port_ram\n\tgeneric map\n\t(\n\t\tg_bit_width => c_ram_width,\n\t\tg_size => 40\n\t)\n\tport map\n\t(\n\t\tclk1 => clk,\n\t\taddr1 => ram_wadd,\n\t\tdin1 => ram_wdat,\n\t\tdout1 => open,\n\t\twen1 => ram_wen,\n\n\t\tclk2 => clk,\n\t\taddr2 => ram_radd,\n\t\tdin2 => (others => '0'),\n\t\tdout2 => ram_rdat,\n\t\twen2 => '0'\n\t);\n\n\n\tp_control : process(clk) is\n\tbegin\n\t\tif rising_edge(clk) then\n\n\t\t\tram_wen <= '0';\n\n\t\t\t-- c-accesses are most stable on strobe 13-14\n\t\t\tif (strb = 13) then\n\n\t\t\t\t-- checking this here ensures the effects are properly delayed\n\t\t\t\t-- to the next (output) cycle\n\t\t\t\tif (bdln = '1') then\n\t\t\t\t\tidle <= '0';\n\t\t\t\t\tbdln_1r <= '1';\n\t\t\t\tend if;\n\n\t\t\t\tif (cycl = 13) then\n\t\t\t\t\tif (bdln = '1') then\n\t\t\t\t\t\tcount_line <= 0;\n\t\t\t\t\telse\n\t\t\t\t\t\tbdln_1r <= '0';\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\tif (cycl = c_cycl_ref) then\n\t\t\t\t\tram_wadd <= (others => '0');\n\t\t\t\telsif (ram_wadd < c_ram_len - 1) then\n\t\t\t\t\tram_wadd <= ram_wadd + 1;\n\t\t\t\tend if;\n\n\t\t\t\tif (bdln or bdln_1r or ccax) then\n\t\t\t\t\tif (cycl = c_cycl_ref) or (ram_wadd < c_ram_len - 1) then\n\t\t\t\t\t\tram_wen <= '1';\n\t\t\t\t\t\tif (ccax = '1') then\n\t\t\t\t\t\t\tram_wdat <= i_db;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tram_wdat <= i_db or x\"0ff\";\n\t\t\t\t\t\tend if;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\n\t\t\t\tif (cycl = 57) then\n\t\t\t\t\tif (count_line /= 7) then\n\t\t\t\t\t\tcount_line <= count_line + 1;\n\t\t\t\t\telsif bdln = '0' then\n\t\t\t\t\t\tidle <= '1';\n\t\t\t\t\telse\n\t\t\t\t\t\t-- line doubling trick\n\t\t\t\t\t\tcount_line <= 0;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\tend if;\n\n\t\t\t-- start video matrix read soon enough for the data to be available\n\t\t\t-- when it needs to be produced on the output\n\t\t\tif (strb = 2) then\n\t\t\t\tif count_cycl < c_ram_len then\n\t\t\t\t\tcount_cycl <= count_cycl + 1;\n\t\t\t\tend if;\n\n\t\t\t\tif (cycl = c_cycl_ref + 1) then\n\t\t\t\t\tram_radd <= (others => '0');\n\t\t\t\t\tcount_cycl <= 0;\n\n\t\t\t\telsif (ram_radd < c_ram_len - 1) then\n\t\t\t\t\tram_radd <= ram_radd + 1;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\tif (strb = 7) then\n\t\t\t\tif (count_cycl /= c_ram_len) then\n\t\t\t\t\to_en <= '1';\n\t\t\t\t\to_gg <= i_db(7 downto 0);\n\t\t\t\t\to_cc <= ram_rdat;\n\t\t\t\telse\n\t\t\t\t\to_en <= '0';\n\t\t\t\tend if;\n\n\t\t\t\tif idle and idle_en then\n\t\t\t\t\to_gg <= i_db(7 downto 0);\n\t\t\t\t\to_cc <= (others => '0');\n\t\t\t\tend if;\n\t\t\tend if;\n", "right_context": "\t\t\t\tidle <= '1';\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\nend architecture;\n", "groundtruth": "\n\t\t\trst_1r <= rst;\n\t\t\tif rst_1r then\n", "crossfile_context": ""} {"task_id": "HD-64", "path": "HD-64/development/firmware/vicii/xy_sync.vhdl", "left_context": "--------------------------------------------------------------------------------\n-- .XXXXXXXXXXXXXXXX. .XXXXXXXXXXXXXXXX. .XX. --\n-- XXXXXXXXXXXXXXXXX' XXXXXXXXXXXXXXXXXX XXXX --\n-- XXXX XXXX XXXX XXXX --\n-- XXXXXXXXXXXXXXXXX. XXXXXXXXXXXXXXXXXX XXXX --\n-- 'XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX' XXXX --\n-- XXXX XXXX XXXX --\n-- .XXXXXXXXXXXXXXXXX XXXX XXXXXXXXXXXXXXXXX. --\n-- 'XXXXXXXXXXXXXXXX' 'XX' 'XXXXXXXXXXXXXXXX' --\n--------------------------------------------------------------------------------\n-- Copyright 2023 Vittorio Pascucci (SideProjectsLab) --\n-- --\n-- Licensed under the GNU General Public License, Version 3 (the \"License\"); --\n-- you may not use this file except in compliance with the License. --\n-- You may obtain a copy of the License at --\n-- --\n-- https://www.gnu.org/licenses/gpl-3.0.en.html#license-text --\n-- --\n-- Unless required by applicable law or agreed to in writing, software --\n-- distributed under the License is distributed on an \"AS IS\" BASIS, --\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --\n-- See the License for the specific language governing permissions and --\n-- limitations under the License. --\n--------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nlibrary work;\nuse work.qol_pkg.all;\nuse work.vic_pkg.all;\n\n\nentity xy_sync is\nport\n(\n\tclk : in std_wire;\n\trst : in std_wire;\n\ta : in t_addr;\n\tstrb : in t_strb;\n\n\tenable : in std_wire;\n\tspecs : in t_vic_specs;\n\n\tlock : out std_wire;\n\tcycl : out t_ppos;\n\txpos : out t_ppos;\n\typos : out t_ppos;\n\n\tdgn_out : out std_word(3 downto 0) := (others => '0')\n);\nend entity;\n\n\narchitecture rtl of xy_sync is\n\n\tconstant c_unlock_cycles : natural := 3;\n\n\ttype t_state is\n\t(\n\t\tst_unlocked,\n\t\tst_llocking,\n\t\tst_llocked,\n\t\tst_locked\n\t);\n\n\tsignal rst_1r : std_wire := '1';\n\tsignal state : t_state;\n\tsignal shreg : unsigned(9 downto 0);\n\tsignal shreg_old : shreg'subtype;\n\tsignal refpat : shreg'subtype;\n\tsignal count_unlock : natural range 0 to c_unlock_cycles;\n\tsignal cycl_i : t_ppos;\n\n\tsignal ypos_i : t_ppos;\n\n\tfunction is_refresh(shreg : unsigned) return boolean is\n\tbegin\n\t\treturn (shreg = \"1110010011\") or\n\t\t\t (shreg = \"1001001110\") or\n\t\t\t (shreg = \"0100111001\") or\n\t\t\t (shreg = \"0011100100\");\n\tend function;\n\nbegin\n\n\tshreg <= ltrim(shreg_old, 2) & lresize(a, 2);\n\tlock <= '1' when state = st_locked else '0';\n\n\tp_xy_pos : process(clk) is\n\tbegin\n\t\tif rising_edge(clk) then\n\t\t\tif (strb = 1) and (enable = '1') then\n\n\t\t\t\tshreg_old <= shreg;\n\n\t\t\t\tif (cycl_i < specs.cycl - 1) then\n\t\t\t\t\tcycl_i <= cycl_i + 1;\n\t\t\t\telse\n\t\t\t\t\tcycl_i <= (others => '0');\n\n\t\t\t\t\tif (ypos_i < specs.ylen - 1) then\n\t\t\t\t\t\typos_i <= ypos_i + 1;\n\t\t\t\t\telse\n\t\t\t\t\t\typos_i <= (others => '0');\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\n\t\t\t\tif (cycl_i = c_cycl_ref) then\n\n\t\t\t\t\t-- always checking for cycl_i allows us to scan the line one\n\t\t\t\t\t-- character-cycle at a time, thus guaranteeing a finite\n\t\t\t\t\t-- lock time\n\n\t\t\t\t\tcase state is\n\t\t\t\t\t\twhen st_unlocked =>\n\t\t\t\t\t\t\tif is_refresh(shreg) then\n\t\t\t\t\t\t\t\tstate <= st_llocking;\n\t\t\t\t\t\t\t\trefpat <= ltrim(shreg, 2) & shreg(7 downto 6);\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t-- skip a cycle and try again\n\t\t\t\t\t\t\t\tcycl_i <= c_cycl_ref + 2;\n\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\twhen st_llocking =>\n\t\t\t\t\t\t\tif (shreg = refpat) then\n\t\t\t\t\t\t\t--if is_refresh(shreg) then\n\t\t\t\t\t\t\t\tstate <= st_llocked;\n\t\t\t\t\t\t\t\tcount_unlock <= c_unlock_cycles;\n\t\t\t\t\t\t\t\trefpat <= ltrim(shreg, 2) & shreg(7 downto 6);\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t-- skip a cycle and start over\n\t\t\t\t\t\t\t\tstate <= st_unlocked;\n\t\t\t\t\t\t\t\tcycl_i <= c_cycl_ref + 2;\n\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\twhen st_llocked =>\n\t\t\t\t\t\t\tif (shreg = \"1111111111\") then\n\t\t\t\t\t\t\t\tstate <= st_locked;\n\t\t\t\t\t\t\t\typos_i <= specs.ylen - 1;\n\t\t\t\t\t\t\t\trefpat <= \"1110010011\";\n\t\t\t\t\t\t\t\tcount_unlock <= c_unlock_cycles;\n\n\t\t\t\t\t\t\telsif (shreg = refpat) then\n\t\t\t\t\t\t\t--elsif is_refresh(shreg) then\n\t\t\t\t\t\t\t\trefpat <= ltrim(refpat, 2) & refpat(7 downto 6);\n\t\t\t\t\t\t\t\tcount_unlock <= c_unlock_cycles;\n\n\t\t\t\t\t\t\telsif count_unlock /= 0 then\n\t\t\t\t\t\t\t\trefpat <= ltrim(refpat, 2) & refpat(7 downto 6);\n\t\t\t\t\t\t\t\tcount_unlock <= count_unlock - 1;\n\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t-- skip a cycle and start over\n\t\t\t\t\t\t\t\tstate <= st_unlocked;\n\t\t\t\t\t\t\t\tcycl_i <= c_cycl_ref + 2;\n", "right_context": "\n\t\t\t\t\t\twhen st_locked =>\n\t\t\t\t\t\t\tif (ypos_i = specs.ylen - 1) then\n\t\t\t\t\t\t\t\tif (shreg = \"1111111111\") then\n\t\t\t\t\t\t\t\t\trefpat <= \"1110010011\";\n\t\t\t\t\t\t\t\t\tcount_unlock <= c_unlock_cycles;\n\n\t\t\t\t\t\t\t\telsif count_unlock /= 0 then\n\t\t\t\t\t\t\t\t\trefpat <= \"1110010011\";\n\t\t\t\t\t\t\t\t\tcount_unlock <= count_unlock - 1;\n\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t-- skip a cycle and start over\n\t\t\t\t\t\t\t\t\tstate <= st_unlocked;\n\t\t\t\t\t\t\t\t\tcycl_i <= c_cycl_ref + 2;\n\t\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tif (shreg = refpat) then\n\t\t\t\t\t\t\t\t--if is_refresh(shreg) then\n\t\t\t\t\t\t\t\t\trefpat <= ltrim(refpat, 2) & refpat(7 downto 6);\n\t\t\t\t\t\t\t\t\tcount_unlock <= c_unlock_cycles;\n\n\t\t\t\t\t\t\t\telsif count_unlock /= 0 then\n\t\t\t\t\t\t\t\t\tcount_unlock <= count_unlock - 1;\n\t\t\t\t\t\t\t\t\trefpat <= ltrim(refpat, 2) & refpat(7 downto 6);\n\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t-- skip a cycle and start over\n\t\t\t\t\t\t\t\t\tstate <= st_unlocked;\n\t\t\t\t\t\t\t\t\tcycl_i <= c_cycl_ref + 2;\n\t\t\t\t\t\t\t\tend if;\n\t\t\t\t\t\t\tend if;\n\n\t\t\t\t\t\twhen others =>\n\t\t\t\t\tend case;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\n\t\t\t-- advancing the pixel counter on odd strobe cycles\n\t\t\tif (strb(0) = '1') then\n\t\t\t\tif (xpos < specs.xlen - 1) then\n\t\t\t\t\txpos <= xpos + 1;\n\t\t\t\telse\n\t\t\t\t\txpos <= to_ppos(0);\n\t\t\t\tend if;\n\t\t\tend if;\n\n\t\t\t-- position outputs are latched on the last strobe of a character\n\t\t\t-- cycle, so that they are constant and correct during the whole\n\t\t\t-- cycle\n\t\t\tif (strb = 15) then\n\t\t\t\t-- cycl_i already contains the next cycle index\n\t\t\t\tcycl <= cycl_i;\n\n\t\t\t\t-- y coordinate cycles automatically\n\t\t\t\tif (cycl_i = 0) then\n\t\t\t\t\tif (ypos < specs.ylen - 1) then\n\t\t\t\t\t\typos <= ypos + 1;\n\t\t\t\t\telse\n\t\t\t\t\t\typos <= to_ppos(0);\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\n\t\t\t\t-- on the reference cycle we re-synchronize all counters with\n\t\t\t\t-- appropriate offsets\n\t\t\t\tif (cycl_i = c_cycl_ref + 1) then\n\t\t\t\t\txpos <= specs.xref;\n\n\t\t\t\t\tif (ypos_i = 0) then\n\t\t\t\t\t\typos <= specs.yref;\n\t\t\t\t\tend if;\n\t\t\t\tend if;\n\t\t\tend if;\n\n\n\t\t\trst_1r <= rst;\n\t\t\tif (rst_1r = '1') then\n\t\t\t\tstate <= st_unlocked;\n\t\t\t\tshreg_old <= (others => '0');\n\t\t\t\tcycl_i <= (others => '0');\n\t\t\t\typos_i <= (others => '0');\n\t\t\tend if;\n\n\t\tend if;\n\n\tend process;\n\nend architecture;\n", "groundtruth": "\t\t\t\t\t\t\tend if;\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/tests/rpu_core_tb.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Company: \n-- Engineer: \n-- \n-- Create Date: 12.11.2018 22:51:11\n-- Design Name: \n-- Module Name: rpu_core_tb - Behavioral\n-- Project Name: \n-- Target Devices: \n-- Tool Versions: \n-- Description: \n-- \n-- Dependencies: \n-- \n-- Revision:\n-- Revision 0.01 - File Created\n-- Additional Comments:\n-- \n----------------------------------------------------------------------------------\n\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\n-- Uncomment the following library declaration if using\n-- arithmetic functions with Signed or Unsigned values\nuse IEEE.NUMERIC_STD.ALL;\n\n-- Uncomment the following library declaration if instantiating\n-- any Xilinx leaf cells in this code.\n--library UNISIM;\n--use UNISIM.VComponents.all;\n\nlibrary work;\nuse work.constants.all;\n\nentity rpu_core_tb is\n-- Port ( );\nend rpu_core_tb;\n\narchitecture Behavioral of rpu_core_tb is\n\n\n -- The RPU core definition\n COMPONENT core\n PORT(\n I_clk : IN std_logic;\n I_reset : IN std_logic;\n I_halt : IN std_logic;\n -- External Interrupt interface\n I_int_data: in STD_LOGIC_VECTOR(31 downto 0);\n I_int: in STD_LOGIC;\n O_int_ack: out STD_LOGIC;\n \n MEM_O_cmd : OUT std_logic;\n MEM_O_we : OUT std_logic;\n \n MEM_O_byteEnable : OUT std_logic_vector(1 downto 0);\n MEM_O_addr : OUT std_logic_vector(31 downto 0);\n MEM_O_data : OUT std_logic_vector(31 downto 0);\n MEM_I_data : IN std_logic_vector(31 downto 0);\n \n MEM_I_ready : IN std_logic;\n MEM_I_dataReady : IN std_logic\n \n ;\n O_DBG:out std_logic_vector(63 downto 0)\n );\n END COMPONENT;\n \n \n signal CLK12MHZ : STD_LOGIC := '0';\n signal CLKTIME : STD_LOGIC := '0';\n constant I_CLKTIME_period : time := 8 ns;\n \n signal cEng_core : std_logic := '0';\n signal I_reset : std_logic := '1';\n signal I_halt : std_logic := '0';\n signal I_int : std_logic := '0';\n signal MEM_I_ready : std_logic := '1';\n signal MEM_I_data : std_logic_vector(31 downto 0) := (others => '0');\n signal MEM_I_dataReady : std_logic := '0';\n\n signal MEM_O_data_swizzed : std_logic_vector(31 downto 0) := (others => '0');\n \n signal O_int_ack : std_logic:= '0';\n signal O_int_ack_stable_12mhz : std_logic:= '0';\n signal O_int_ack_stable_12mhz_core : std_logic:= '0';\n \n signal MEM_O_cmd : std_logic := '0';\n signal MEM_O_we : std_logic := '0';\n signal MEM_O_byteEnable : std_logic_vector(1 downto 0) := (others => '0');\n signal MEM_O_addr : std_logic_vector(31 downto 0) := (others => '0');\n signal MEM_O_data : std_logic_vector(31 downto 0) := (others => '0');\n \n signal I_int_data: STD_LOGIC_VECTOR(31 downto 0);\n signal MEM_I_data_raw : std_logic_vector(31 downto 0) := (others => '0');\n \n -- Clock period definitions\n constant I_clk_period : time := 5 ns;\n \n \n signal MEM_readyState: integer := 0;\n \n \n -- SOC_CtrState definitions - running off SOC clock domain\n constant SOC_CtlState_Ready : integer := 0;\n \n -- IMM SOC control states are immediate 1-cycle latency\n -- i.e. BRAM or explicit IO\n constant SOC_CtlState_IMM_WriteCmdComplete : integer := 9;\n constant SOC_CtlState_IMM_ReadCmdComplete : integer := 6;\n \n signal IO_LEDS: STD_LOGIC_VECTOR(7 downto 0):= (others => '0');\n signal INT_DATA: std_logic_vector(BWIDTHM1 downto 0):= (others => '0');\n signal IO_DATA: std_logic_vector(BWIDTHM1 downto 0):= (others => '0');\n signal DDR3_DATA: std_logic_vector(BWIDTHM1 downto 0):= (others => '0');\n \n -- Block ram management\n signal MEM_64KB_ADDR : std_logic_vector(31 downto 0):= (others => '0');\n signal MEM_BANK_ID : std_logic_vector(15 downto 0):= (others => '0');\n signal MEM_ANY_CS : std_logic := '0';\n signal MEM_WE : std_logic := '0';\n \n signal MEM_CS_BRAM_1 : std_logic := '0';\n signal MEM_CS_BRAM_2 : std_logic := '0';\n signal MEM_CS_BRAM_3 : std_logic := '0';\n \n signal mI_wea : STD_LOGIC_VECTOR ( 3 downto 0 ):= (others => '0');\n \n signal MEM_CS_DDR3 : std_logic := '0';\n \n signal MEM_CS_SYSTEM : std_logic := '0';\n \n signal MEM_DATA_OUT_BRAM_1: std_logic_vector(BWIDTHM1 downto 0):= (others => '0');\n signal MEM_DATA_OUT_BRAM_2: std_logic_vector(BWIDTHM1 downto 0):= (others => '0');\n signal MEM_DATA_OUT_BRAM_3: std_logic_vector(BWIDTHM1 downto 0):= (others => '0');\n \n \n signal O_DBG: std_logic_vector(63 downto 0);\n \n constant mmio_addr_mtime_lo: STD_LOGIC_VECTOR( 31 downto 0) := X\"4400bff8\";\n constant mmio_addr_mtime_hi: STD_LOGIC_VECTOR( 31 downto 0) := X\"4400bffc\";\n signal gcsr_mtime_lo: STD_LOGIC_VECTOR( 31 downto 0) := (others => '0');\n signal gcsr_mtime_hi: STD_LOGIC_VECTOR( 31 downto 0) := (others => '0');\n \n signal memcontroller_reset_count: integer := 100000;\n \n signal count12MHz: std_logic_vector(63 downto 0) := X\"0000000000000000\"; \n \n constant mmio_addr_mtimecmp0_lo: STD_LOGIC_VECTOR( 31 downto 0) := X\"44004000\";\n constant mmio_addr_mtimecmp0_hi: STD_LOGIC_VECTOR( 31 downto 0) := X\"44004004\";\n -- constant mmio_addr_mtimecmp0_lo: STD_LOGIC_VECTOR( 31 downto 0) := X\"00000004\";\n -- constant mmio_addr_mtimecmp0_hi: STD_LOGIC_VECTOR( 31 downto 0) := X\"00000008\";\n signal gcsr_timer_initialized : STD_LOGIC:='0';\n signal gcsr_mtimecmp0_lo: STD_LOGIC_VECTOR( 31 downto 0) := X\"0000000c\";--X\"07270E00\";--20s 0E4E1C00\"; --?10 seconds of 12mhz counter?\"; --(others => '0');\n signal gcsr_mtimecmp0_hi: STD_LOGIC_VECTOR( 31 downto 0) := (others => '0');\n signal gcsr_mtimecmp0_stable: STD_LOGIC_VECTOR( 63 downto 0) := (others => '0');\n \n signal gcsr_mtimecmp0_lo_written: STD_LOGIC := '0';\n signal gcsr_mtimecmp0_hi_written: STD_LOGIC := '0';\n signal gcsr_mtimecmp_irq_reset: STD_LOGIC := '0';\n signal gcsr_mtimecmp_irq_reset_stable: STD_LOGIC := '0';\n signal gcsr_mtimecmp_irq_en: STD_LOGIC := '0'; ----\n signal gcsr_mtimecmp_irq_en_stable: STD_LOGIC := '0'; ------\n signal gcsr_mtimecmp_irq: STD_LOGIC := '0';\n \n signal gcsr_mtimecmp_irq_served: std_logic := '0';\n signal plic_int : std_logic := '0';\n \n type rom_type is array (0 to 16384)\n of std_logic_vector(31 downto 0);\n signal ROM2: rom_type :=(others => X\"00000000\"); \n signal ROM3: rom_type :=(others => X\"00000000\"); \n signal ROM: rom_type:=( \n X\"00000097\", --auipc\tra,0x0\n X\"14408093\", --addi ra,ra,324 # 10000230 <_trap_handler>\n X\"30509ff3\", --csrrw t6,mtvec,ra\n X\"00002197\", --auipc gp,0x2\n X\"f0818193\", --addi gp,gp,-248 # 10002000 \n X\"00002117\", --auipc sp,0x2\n X\"f1010113\", --addi sp,sp,-240 # 10002010 \n X\"00002097\", --auipc ra,0x2\n X\"f1808093\", --addi ra,ra,-232 # 10002020 \n X\"00500293\", --li t0,5\n X\"00600313\", --li t1,6\n X\"0001a203\", --lw tp,0(gp)\n X\"00412023\", --sw tp,0(sp)\n X\"0011a203\", --lw tp,1(gp)\n X\"00412223\", --sw tp,4(sp)\n X\"0021a203\", --lw tp,2(gp)\n X\"00412423\", --sw tp,8(sp)\n X\"0031a203\", --lw tp,3(gp)\n X\"00412623\", --sw tp,12(sp)\n X\"00002197\", --auipc gp,0x2\n X\"ecc18193\", --addi gp,gp,-308 # 10002004 \n X\"00002117\", --auipc sp,0x2\n X\"ef810113\", --addi sp,sp,-264 # 10002038 \n X\"00002097\", --auipc ra,0x2\n X\"f1008093\", --addi ra,ra,-240 # 10002058 \n X\"00500293\", --li t0,5\n X\"00600313\", --li t1,6\n X\"00019203\", --lh tp,0(gp)\n X\"00412023\", --sw tp,0(sp)\n X\"00119203\", --lh tp,1(gp)\n X\"00412223\", --sw tp,4(sp)\n X\"00219203\", --lh tp,2(gp)\n X\"00412423\", --sw tp,8(sp)\n X\"00319203\", --lh tp,3(gp)\n X\"00412623\", --sw tp,12(sp)\n X\"0001d203\", --lhu tp,0(gp)\n X\"00412823\", --sw tp,16(sp)\n X\"0011d203\", --lhu tp,1(gp)\n X\"00412a23\", --sw tp,20(sp)\n X\"0021d203\", --lhu tp,2(gp)\n X\"00412c23\", --sw tp,24(sp)\n X\"0031d203\", --lhu tp,3(gp)\n X\"00412e23\", --sw tp,28(sp)\n X\"00002117\", --auipc sp,0x2\n X\"ee010113\", --addi sp,sp,-288 # 10002078 \n X\"00002097\", --auipc ra,0x2\n X\"ee808093\", --addi ra,ra,-280 # 10002088 \n X\"00000313\", --li t1,0\n X\"9999a2b7\", --lui t0,0x9999a\n X\"99928293\", --addi t0,t0,-1639 # 99999999 <_end+0x89997795>\n X\"00512023\", --sw t0,0(sp)\n X\"00512223\", --sw t0,4(sp)\n X\"00512423\", --sw t0,8(sp)\n X\"00512623\", --sw t0,12(sp)\n X\"00612023\", --sw t1,0(sp)\n X\"00410113\", --addi sp,sp,4\n X\"006120a3\", --sw t1,1(sp)\n X\"00410113\", --addi sp,sp,4\n X\"00612123\", --sw t1,2(sp)\n X\"00410113\", --addi sp,sp,4\n X\"006121a3\", --sw t1,3(sp)\n X\"00002117\", --auipc sp,0x2\n X\"ec010113\", --addi sp,sp,-320 # 100020a0 \n X\"00002097\", --auipc ra,0x2\n X\"ec808093\", --addi ra,ra,-312 # 100020b0 \n X\"00000313\", --li t1,0\n X\"9999a2b7\", --lui t0,0x9999a\n X\"99928293\", --addi t0,t0,-1639 # 99999999 <_end+0x89997795>\n X\"00512023\", --sw t0,0(sp)\n X\"00512223\", --sw t0,4(sp)\n X\"00512423\", --sw t0,8(sp)\n X\"00512623\", --sw t0,12(sp)\n X\"00611023\", --sh t1,0(sp)\n X\"00410113\", --addi sp,sp,4\n X\"006110a3\", --sh t1,1(sp)\n X\"00410113\", --addi sp,sp,4\n X\"00611123\", --sh t1,2(sp)\n X\"00410113\", --addi sp,sp,4\n X\"006111a3\", --sh t1,3(sp)\n X\"305f9073\", --csrw mtvec,t6\n X\"02c0006f\", --j 10000258 \n \n \n X\"34102f73\", --csrr t5,mepc\n X\"004f0f13\", --addi t5,t5,4\n X\"341f1073\", --csrw mepc,t5\n X\"34302f73\", --csrr t5,mtval\n X\"003f7f13\", --andi t5,t5,3\n X\"01e0a023\", --sw t5,0(ra)\n X\"34202f73\", --csrr t5,mcause\n X\"01e0a223\", --sw t5,4(ra)\n X\"00808093\", --addi ra,ra,8\n X\"30200073\", --mret\n \n \n X\"00100193\", --li gp,1\n X\"00002f17\", --auipc t5,0x2\n X\"e64f0f13\", --addi t5,t5,-412 # 100020c0 \n X\"000f2103\", --lw sp,0(t5)\n X\"00412083\", --lw ra,4(sp)\n X\"00812283\", --lw t0,8(sp)\n X\"00c12303\", --lw t1,12(sp)\n X\"01012383\", --lw t2,16(sp)\n X\"01412403\", --lw s0,20(sp)\n X\"01812483\", --lw s1,24(sp)\n X\"01c12503\", --lw a0,28(sp)\n X\"02012583\", --lw a1,32(sp)\n X\"02412603\", --lw a2,36(sp)\n X\"02812683\", --lw a3,40(sp)\n X\"02c12703\", --lw a4,44(sp)\n X\"03012783\", --lw a5,48(sp)\n X\"03412803\", --lw a6,52(sp)\n X\"03812883\", --lw a7,56(sp)\n X\"03c12903\", --lw s2,60(sp)\n X\"04012983\", --lw s3,64(sp)\n X\"04412a03\", --lw s4,68(sp)\n X\"04812a83\", --lw s5,72(sp)\n X\"04c12b03\", --lw s6,76(sp)\n X\"05012b83\", --lw s7,80(sp)\n X\"05412c03\", --lw s8,84(sp)\n X\"05812c83\", --lw s9,88(sp)\n X\"05c12d03\", --lw s10,92(sp)\n X\"06012d83\", --lw s11,96(sp)\n X\"06412e03\", --lw t3,100(sp)\n X\"06812e83\", --lw t4,104(sp)\n X\"06c12f03\", --lw t5,108(sp)\n X\"07012f83\", --lw t6,112(sp)\n X\"08010113\", --addi sp,sp,128\n X\"0000006f\", -- j 00 \n-- X\"00008067\", --ret\n \n \n X\"00002f17\", --auipc t5,0x2\n X\"de0f0f13\", --addi t5,t5,-544 # 100020c0 \n X\"000f2103\", --lw sp,0(t5)\n X\"00412083\", --lw ra,4(sp)\n X\"00812283\", --lw t0,8(sp)\n X\"00c12303\", --lw t1,12(sp)\n X\"01012383\", --lw t2,16(sp)\n X\"01412403\", --lw s0,20(sp)\n X\"01812483\", --lw s1,24(sp)\n X\"01c12503\", --lw a0,28(sp)\n X\"02012583\", --lw a1,32(sp)\n X\"02412603\", --lw a2,36(sp)\n X\"02812683\", --lw a3,40(sp)\n X\"02c12703\", --lw a4,44(sp)\n X\"03012783\", --lw a5,48(sp)\n X\"03412803\", --lw a6,52(sp)\n X\"03812883\", --lw a7,56(sp)\n X\"03c12903\", --lw s2,60(sp)\n X\"04012983\", --lw s3,64(sp)\n X\"04412a03\", --lw s4,68(sp)\n X\"04812a83\", --lw s5,72(sp)\n X\"04c12b03\", --lw s6,76(sp)\n X\"05012b83\", --lw s7,80(sp)\n X\"05412c03\", --lw s8,84(sp)\n X\"05812c83\", --lw s9,88(sp)\n X\"05c12d03\", --lw s10,92(sp)\n X\"06012d83\", --lw s11,96(sp)\n X\"06412e03\", --lw t3,100(sp)\n X\"06812e83\", --lw t4,104(sp)\n X\"06c12f03\", --lw t5,108(sp)\n X\"07012f83\", --lw t6,112(sp)\n X\"08010113\", --addi sp,sp,128\n X\"0000006f\", -- j 00 \n\n -- X\"00008067\", --ret\n -- X\"c0001073\", --unimp\n-- \n-- X\"00000097\", --auipc ra,0x0\n-- X\"20808093\", --addi ra,ra,520 # 100002f4 <_trap_handler>\n-- X\"30509ff3\", --csrrw t6,mtvec,ra\n-- X\"30127073\", --csrci misa,4\n-- X\"00002097\", --auipc ra,0x2\n-- X\"f0408093\", --addi ra,ra,-252 # 10002000 \n-- X\"11111137\", --lui sp,0x11111\n-- X\"11110113\", --addi sp,sp,273 # 11111111 <_end+0x110ef0d>\n-- X\"00a0006f\", --j 10000116 \n-- X\"00000113\", --li sp,0\n-- X\"00002097\", --auipc ra,0x2\n-- X\"ef808093\", --addi ra,ra,-264 # 1000200c \n-- X\"22222137\", --lui sp,0x22222\n-- X\"22210113\", --addi sp,sp,546 # 22222222 <_end+0x1222001e>\n-- X\"00000217\", --auipc tp,0x0\n-- X\"01120213\", --addi tp,tp,17 # 10000135 \n-- X\"00020067\", --jr tp # 0 <_start-0x10000000>\n-- X\"00000113\", --li sp,0\n-- X\"0020a023\", --sw sp,0(ra)\n-- X\"00408093\", --addi ra,ra,4\n-- X\"33333137\", --lui sp,0x33333\n-- X\"33310113\", --addi sp,sp,819 # 33333333 <_end+0x2333112f>\n-- X\"00000217\", --auipc tp,0x0\n-- X\"01020213\", --addi tp,tp,16 # 10000154 \n-- X\"00120067\", --jr 1(tp) # 0 <_start-0x10000000>\n-- X\"00000113\", --li sp,0\n-- X\"0020a023\", --sw sp,0(ra)\n-- X\"00408093\", --addi ra,ra,4\n-- X\"44444137\", --lui sp,0x44444\n-- X\"44410113\", --addi sp,sp,1092 # 44444444 <_end+0x34442240>\n-- X\"00000217\", --auipc tp,0x0\n-- X\"01420213\", --addi tp,tp,20 # 10000178 \n-- X\"ffd20067\", --jr -3(tp) # 0 <_start-0x10000000>\n-- X\"00000113\", --li sp,0\n-- X\"0020a023\", --sw sp,0(ra)\n-- X\"00408093\", --addi ra,ra,4\n-- X\"00002097\", --auipc ra,0x2\n-- X\"e9c08093\", --addi ra,ra,-356 # 10002018 \n-- X\"55555137\", --lui sp,0x55555\n-- X\"55510113\", --addi sp,sp,1365 # 55555555 <_end+0x45553351>\n-- X\"00000217\", --auipc tp,0x0\n-- X\"01220213\", --addi tp,tp,18 # 1000019e \n-- X\"00020067\", --jr tp # 0 <_start-0x10000000>\n-- X\"00000113\", --li sp,0\n-- X\"66666137\", --lui sp,0x66666\n-- X\"66610113\", --addi sp,sp,1638 # 66666666 <_end+0x56664462>\n-- X\"00000217\", --auipc tp,0x0\n-- X\"01320213\", --addi tp,tp,19 # 100001b7 \n-- X\"00020067\", --jr tp # 0 <_start-0x10000000>\n-- X\"00000113\", --li sp,0\n-- X\"77777137\", --lui sp,0x77777\n-- X\"77710113\", --addi sp,sp,1911 # 77777777 <_end+0x67775573>\n-- X\"00000217\", --auipc tp,0x0\n-- X\"01020213\", --addi tp,tp,16 # 100001cc \n-- X\"00220067\", --jr 2(tp) # 0 <_start-0x10000000>\n-- X\"00000113\", --li sp,0\n-- X\"88889137\", --lui sp,0x88889\n-- X\"88810113\", --addi sp,sp,-1912 # 88888888 <_end+0x78886684>\n-- X\"00000217\", --auipc tp,0x0\n-- X\"01020213\", --addi tp,tp,16 # 100001e4 \n-- X\"00320067\", --jr 3(tp) # 0 <_start-0x10000000>\n-- X\"00000113\", --li sp,0\n-- X\"00002097\", --auipc ra,0x2\n-- X\"e6408093\", --addi ra,ra,-412 # 10002048 \n-- X\"00500293\", --li t0,5\n-- X\"00600313\", --li t1,6\n-- X\"00628763\", --beq t0,t1,10000202 \n-- X\"9999a137\", --lui sp,0x9999a\n-- X\"99910113\", --addi sp,sp,-1639 # 99999999 <_end+0x89997795>\n-- X\"00000013\", --nop\n-- X\"00000013\", --nop\n-- X\"00528563\", --beq t0,t0,10000212 \n-- X\"00000113\", --li sp,0\n-- X\"00002097\", --auipc ra,0x2\n-- X\"e4408093\", --addi ra,ra,-444 # 10002054 \n-- X\"00500293\", --li t0,5\n-- X\"00600313\", --li t1,6\n-- X\"00529763\", --bne t0,t0,1000022e \n-- X\"aaaab137\", --lui sp,0xaaaab\n-- X\"aaa10113\", --addi sp,sp,-1366 # aaaaaaaa <_end+0x9aaa88a6>\n-- X\"00000013\", --nop\n-- X\"00000013\", --nop\n-- X\"00629563\", --bne t0,t1,1000023e \n-- X\"00000113\", --li sp,0\n-- X\"00002097\", --auipc ra,0x2\n-- X\"e2408093\", --addi ra,ra,-476 # 10002060 \n-- X\"00500293\", --li t0,5\n-- X\"00600313\", --li t1,6\n-- X\"00534763\", --blt t1,t0,1000025a \n-- X\"bbbbc137\", --lui sp,0xbbbbc\n-- X\"bbb10113\", --addi sp,sp,-1093 # bbbbbbbb <_end+0xabbb99b7>\n-- X\"00000013\", --nop\n-- X\"00000013\", --nop\n-- X\"0062c563\", --blt t0,t1,1000026a \n-- X\"00000113\", --li sp,0\n-- X\"00002097\", --auipc ra,0x2\n-- X\"e0408093\", --addi ra,ra,-508 # 1000206c \n-- X\"00500293\", --li t0,5\n-- X\"00600313\", --li t1,6\n-- X\"00536763\", --bltu t1,t0,10000286 \n-- X\"ccccd137\", --lui sp,0xccccd\n-- X\"ccc10113\", --addi sp,sp,-820 # cccccccc <_end+0xbcccaac8>\n-- X\"00000013\", --nop\n-- X\"00000013\", --nop\n-- X\"0062e563\", --bltu t0,t1,10000296 \n-- X\"00000113\", --li sp,0\n-- X\"00002097\", --auipc ra,0x2\n-- X\"de408093\", --addi ra,ra,-540 # 10002078 \n-- X\"00500293\", --li t0,5\n-- X\"00600313\", --li t1,6\n-- X\"0062d763\", --bge t0,t1,100002b2 \n-- X\"dddde137\", --lui sp,0xdddde\n-- X\"ddd10113\", --addi sp,sp,-547 # dddddddd <_end+0xcdddbbd9>\n-- X\"00000013\", --nop\n-- X\"00000013\", --nop\n-- X\"00535563\", --bge t1,t0,100002c2 \n-- X\"00000113\", --li sp,0\n-- X\"00002097\", --auipc ra,0x2\n-- X\"dc408093\", --addi ra,ra,-572 # 10002084 \n-- X\"00500293\", --li t0,5\n-- X\"00600313\", --li t1,6\n-- X\"0062f763\", --bgeu t0,t1,100002de \n-- X\"eeeef137\", --lui sp,0xeeeef\n-- X\"eee10113\", --addi sp,sp,-274 # eeeeeeee <_end+0xdeeeccea>\n-- X\"00000013\", --nop\n-- X\"00000013\", --nop\n-- X\"00537563\", --bgeu t1,t0,100002ee \n-- X\"00000113\", --li sp,0\n-- X\"305f9073\", --csrw mtvec,t6\n-- X\"0300006f\", --j 10000320 \n-- \n-- --<_trap_handler>:\n-- X\"34302f73\", --csrr t5,mtval\n-- X\"ffef0f13\", --addi t5,t5,-2\n-- X\"341f1073\", --csrw mepc,t5\n-- X\"34302f73\", --csrr t5,mtval\n-- X\"003f7f13\", --andi t5,t5,3\n-- X\"01e0a023\", --sw t5,0(ra)\n-- X\"34202f73\", --csrr t5,mcause\n-- X\"01e0a223\", --sw t5,4(ra)\n-- X\"0020a423\", --sw sp,8(ra)\n-- X\"00c08093\", --addi ra,ra,12\n-- X\"30200073\", --mret\n-- \n-- -- :\n-- X\"00100193\", --li gp,1\n-- X\"00100f13\", -- \tli\tt5,1\n-- X\"00100e93\", -- li t4,1\n-- X\"03df0eb3\", -- mul t4,t5,t4\n-- \n \n X\"0000006f\", -- j 00 \n \n X\"06300513\", -- 0 \tli\ta0,99 0\n X\"00a00693\", -- 4 li a3,10\n X\"02d57733\", -- 8 remu a4,a0,a3\n X\"00f605b3\", -- c add a1,a2,a5\n X\"00178793\", -- 10 addi a5,a5,1\n X\"02d55533\", -- 14 divu a0,a0,a3\n X\"03070713\", -- 18 addi a4,a4,48\n\n \n \n --X\"00812423\", -- \tsw\ts0,8(sp)\n -- X\"00112623\", -- sw ra,12(sp)\n --X\"00048413\", -- mv s0,s1\n --X\"00048793\", -- mv a5,s1\n --X\"40960633\", -- sub a2,a2,s1\n X\"00a00693\", -- li a3,10\n X\"02d57733\", -- remu a4,a0,a3\n X\"00f605b3\", -- add a1,a2,a5\n X\"00178793\", -- addi a5,a5,1\n X\"02d55533\", -- divu a0,a0,a3\n X\"03070713\", -- addi a4,a4,48\n X\"fee78fa3\", -- sb a4,-1(a5)\n X\"fe0514e3\", -- bnez a0,20bbc \n -- 00000000 :\n X\"0000006f\", -- j 00 \n\n others => X\"00000000\");\n \n signal I_hart0_int0_coreclk_stable : STD_LOGIC := '0';\n signal O_hart0_int_ack0_coreclk_stable : STD_LOGIC := '0';\n signal hart0_int_ack0_external : STD_LOGIC := '0';\n signal int_was_inactive: STD_LOGIC := '0';\n \n signal count12MHz_stable: STD_LOGIC_VECTOR(63 downto 0) := (others => '0');\nBEGIN\n\n I_int <= gcsr_mtimecmp_irq;\n \nprocess(CLK12MHZ)\nbegin\n if rising_edge(CLK12MHZ) then\n count12MHz <= std_logic_vector(unsigned(count12MHz) + 1);\n end if;\nend process;\n\nprocess (cEng_core)\n", "right_context": " if rising_edge(cEng_core) then\n if gcsr_mtimecmp_irq_en = '1' then\n if count12MHz_stable >= (gcsr_mtimecmp0_hi & gcsr_mtimecmp0_lo) then\n gcsr_mtimecmp_irq <= '1';\n gcsr_mtimecmp_irq_en <= '0';\n end if;\n else\n if gcsr_mtimecmp_irq_reset = '1' then\n gcsr_mtimecmp_irq_en <= '1';\n end if;\n if gcsr_mtimecmp_irq = '1' and O_int_ack = '1' then\n gcsr_mtimecmp_irq <= '0';\n end if;\n end if;\n end if;\nend process;\n\n I_int_data <= EXCEPTION_INT_MACHINE_TIMER;\n\n \t-- The O_we signal can sustain too long. Clamp it to only when O_cmd is active.\n MEM_WE <= MEM_O_cmd and MEM_O_we;\n \n -- \"Local\" BRAM banks are 64KB. To address inside we need lower 16b\n MEM_64KB_ADDR <= X\"0000\" & MEM_O_addr(15 downto 0);\n MEM_BANK_ID <= MEM_O_addr(31 downto 16);\n\n MEM_CS_BRAM_1 <= '1' when (MEM_BANK_ID = X\"0000\") else '0'; -- 0x0000ffff bank 64KB\n MEM_CS_BRAM_2 <= '1' when (MEM_BANK_ID = X\"0001\") else '0'; -- 0x0001ffff bank 64KB\n MEM_CS_BRAM_3 <= '1' when (MEM_BANK_ID = X\"0002\") else '0'; -- 0x0002ffff bank 64KB\n \n MEM_CS_DDR3 <= '1' when (MEM_BANK_ID(15 downto 12) = X\"1\") else '0'; -- 0x1******* ddr3 bank 256MB\n \n -- if any CS line is active, this is 1\n MEM_ANY_CS <= MEM_CS_BRAM_1 or MEM_CS_BRAM_2 or MEM_CS_BRAM_3;\n \n -- select the correct data to send to cpu\n MEM_I_data_raw <= \n MEM_DATA_OUT_BRAM_1 when MEM_CS_BRAM_1 = '1' \n else MEM_DATA_OUT_BRAM_2 when MEM_CS_BRAM_2 = '1' \n else MEM_DATA_OUT_BRAM_3 when MEM_CS_BRAM_3 = '1' \n else X\"91a1b1c1\";--IO_DATA;\n \n MEM_DATA_OUT_BRAM_1 <= ROM(to_integer(unsigned( MEM_64KB_ADDR(15 downto 2)and \"01\" & X\"fff\" )));--and \"00\"&X\"03F\" )));\n MEM_DATA_OUT_BRAM_2 <= ROM2(to_integer(unsigned( MEM_64KB_ADDR(15 downto 2)and \"01\" & X\"fff\" )));--and \"00\"&X\"03F\" )));\n MEM_DATA_OUT_BRAM_3 <= ROM3(to_integer(unsigned( MEM_64KB_ADDR(15 downto 2)and \"01\" & X\"fff\" )));--and \"00\"&X\"03F\" )));\n\n MEM_I_data <= MEM_I_data_raw; \n\n \n \n cEng_core_clk: process\n begin\n cEng_core <= '0';\n wait for I_clk_period/2;\n cEng_core <= '1';\n wait for I_clk_period/2;\n end process;\n \nCLKTIME_clk: process\nbegin\n CLKTIME <= '0';\n wait for I_CLKTIME_period/2;\n CLKTIME <= '1';\n wait for I_CLKTIME_period/2;\nend process;\n \n CLK12MHZ <= CLKTIME;\n\n core0: core PORT MAP (\n I_clk => cEng_core,\n I_reset => I_reset,\n I_halt => I_halt,\n I_int => I_int,\n O_int_ack => O_int_ack,\n I_int_data => I_int_data,\n MEM_I_ready => MEM_I_ready,\n MEM_O_cmd => MEM_O_cmd,\n MEM_O_we => MEM_O_we,\n MEM_O_byteEnable => MEM_O_byteEnable,\n MEM_O_addr => MEM_O_addr,\n MEM_O_data => MEM_O_data,\n MEM_I_data => MEM_I_data,\n MEM_I_dataReady => MEM_I_dataReady\n\t\t ,\n\t\t O_DBG=>O_DBG\n );\n \n \n\n\n -- Huge process which handles memory request arbitration at the Soc/Core clock \n MEM_proc: process(cEng_core)\n begin\n if rising_edge(cEng_core) then\n if gcsr_mtimecmp_irq_en = '1' and gcsr_mtimecmp_irq_reset = '1' then\n gcsr_mtimecmp_irq_reset <= '0';\n end if;\n \n if MEM_readyState = SOC_CtlState_Ready then\n if MEM_O_cmd = '1' then\n \n -- system memory maps\n if MEM_O_addr = X\"f0009000\" and MEM_O_we = '1' then\n -- onboard leds\n IO_LEDS <= \"0000\" & MEM_O_data( 3 downto 0);\n end if;\n if MEM_O_addr = X\"f0009000\" and MEM_O_we = '0' then\n -- onboard leds\n IO_DATA <= X\"000000\" & IO_LEDS;\n end if;\n\n if MEM_O_addr = mmio_addr_mtime_lo and MEM_O_we = '0' then\n IO_DATA <= count12MHz_stable(31 downto 0);\n end if; \n \n if MEM_O_addr = mmio_addr_mtime_hi and MEM_O_we = '0' then\n IO_DATA <= count12MHz_stable(63 downto 32);\n end if;\n \n \n if MEM_O_addr = mmio_addr_mtimecmp0_lo and MEM_O_we = '1' then---1\n gcsr_mtimecmp0_lo <= MEM_O_data;\n gcsr_mtimecmp0_lo_written <= '1';\n end if; \n \n if MEM_O_addr = mmio_addr_mtimecmp0_hi and MEM_O_we = '1' then---1\n gcsr_mtimecmp0_hi <= MEM_O_data;\n if gcsr_mtimecmp0_lo_written = '1' then\n --gcsr_mtimecmp0_hi_written <= '1';\n gcsr_mtimecmp_irq_reset <= '1';\n gcsr_mtimecmp0_lo_written <= '0';\n --gcsr_mtimecmp0_hi_written <= '0';\n end if;\n end if;\n \n \n if MEM_O_addr = mmio_addr_mtimecmp0_lo and MEM_O_we = '0' then\n IO_DATA <= (gcsr_mtimecmp0_lo);\n end if; \n \n if MEM_O_addr = mmio_addr_mtimecmp0_hi and MEM_O_we = '0' then\n IO_DATA <= (gcsr_mtimecmp0_hi);\n end if;\n \n \n MEM_I_ready <= '0';\n MEM_I_dataReady <= '0';\n if MEM_O_we = '1' then\n -- DDR3 request, or immediate command?\n \n MEM_readyState <= SOC_CtlState_IMM_WriteCmdComplete;\n if (MEM_CS_BRAM_1 = '1') then\n ROM(to_integer(unsigned( MEM_64KB_ADDR(15 downto 2)))) <= MEM_O_data;\n end if;\n if (MEM_CS_BRAM_2 = '1') then\n ROM2(to_integer(unsigned( MEM_64KB_ADDR(15 downto 2)))) <= MEM_O_data;\n end if;\n if (MEM_CS_BRAM_3 = '1') then\n ROM3(to_integer(unsigned( MEM_64KB_ADDR(15 downto 2)))) <= MEM_O_data;\n end if;\n else\n -- DDR3 request, or immediate command?\n \n MEM_readyState <= SOC_CtlState_IMM_ReadCmdComplete; \n end if;\n \n end if;\n elsif MEM_readyState >= 1 then\n\n -- Immediate commands do not cross clock domains and complete immediately\n if MEM_readyState = SOC_CtlState_IMM_ReadCmdComplete then\n MEM_I_ready <= '1';\n MEM_I_dataReady <= '1'; \n MEM_readyState <= SOC_CtlState_Ready; \n \n elsif MEM_readyState = SOC_CtlState_IMM_WriteCmdComplete then\n MEM_I_ready <= '1';\n MEM_I_dataReady <= '0'; \n MEM_readyState <= SOC_CtlState_Ready;\n \n end if;\n \n \n end if;\n end if;\n end process;\n \n \n -- Stimulus process\n stim_proc: process\n begin \n -- hold reset state for 100 ns.\n wait for 20 ns; \n memcontroller_reset_count <= 0;\n \n I_reset <= '0';\n\n wait;\n-- \n end process;\n\n\nend Behavioral;\n", "groundtruth": "begin\nif rising_edge(cEng_core) then\n count12MHz_stable <= count12MHz;\nend if;\nend process;\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/tests/tb_alu_int32_div.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Company: \n-- Engineer: \n-- \n-- Create Date: 12.11.2018 22:51:11\n-- Design Name: \n-- Module Name: rpu_core_tb - Behavioral\n-- Project Name: \n-- Target Devices: \n-- Tool Versions: \n-- Description: \n-- \n-- Dependencies: \n-- \n-- Revision:\n-- Revision 0.01 - File Created\n-- Additional Comments:\n-- \n----------------------------------------------------------------------------------\n\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\n-- Uncomment the following library declaration if using\n-- arithmetic functions with Signed or Unsigned values\nuse IEEE.NUMERIC_STD.ALL;\n\n-- Uncomment the following library declaration if instantiating\n-- any Xilinx leaf cells in this code.\n--library UNISIM;\n--use UNISIM.VComponents.all;\n\nlibrary work;\nuse work.constants.all;\n\n", "right_context": "\n\n -- The RPU core definition\n component alu_int32_div is\n Port ( \n I_clk : in STD_LOGIC;\n I_exec : in STD_LOGIC;\n I_dividend : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_divisor : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_op : in STD_LOGIC_VECTOR (1 downto 0);\n O_dataResult : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n O_done : out STD_LOGIC;\n O_int : out std_logic\n );\n end component;\n \n signal I_clk : std_logic := '0';\n signal I_exec : std_logic := '0';\n signal I_dividend : std_logic_vector(31 downto 0) := (others => '0');\n signal I_divisor : std_logic_vector(31 downto 0) := (others => '0');\n signal I_op : std_logic_vector(1 downto 0) := (others => '0');\n signal O_dataResult : std_logic_vector(31 downto 0) := (others => '0');\n signal O_done : std_logic := '0';\n signal O_int : std_logic := '0';\n\n\n -- Clock period definitions\n constant I_clk_period : time := 10 ns;\nBEGIN\n\n\t-- Instantiate the Unit Under Test (UUT)\n uut: alu_int32_div PORT MAP (\n I_clk => I_clk,\n I_exec => I_exec,\n I_dividend => I_dividend,\n I_divisor => I_divisor, \n I_op => I_op,\n O_dataResult => O_dataResult,\n O_done => O_done,\n O_int => O_int\n );\n\n -- Clock process definitions\n I_clk_process :process\n begin\n\t\tI_clk <= '0';\n\t\twait for I_clk_period/2;\n\t\tI_clk <= '1';\n\t\twait for I_clk_period/2;\n end process;\n \n\n -- Stimulus process\n stim_proc: process\n begin\t\t\n -- hold reset state for 100 ns.\n wait for 100 ns;\t\n\n wait for I_clk_period*10;\n -- insert stimulus here \n\n I_dividend <= X\"ffffffff\";\n\t\tI_divisor <= X\"00000000\";\n\t\tI_op <= ALU_INT32_DIV_OP_DIVU;\n\t\tI_exec <= '1';\n wait for I_clk_period;\n\t\tI_exec <= '0';\n\t\t\n wait for I_clk_period*500;\n\n \n I_dividend <= X\"0000000a\";\n I_divisor <= X\"0000000a\";\n I_op <= ALU_INT32_DIV_OP_REMU;\n I_exec <= '1';\n wait for I_clk_period;\n I_exec <= '0';\n \n wait for I_clk_period*500;\n\t\t\n I_dividend <= X\"00001001\";\n I_divisor <= X\"00000111\";\n I_op <= ALU_INT32_DIV_OP_REM;\n I_exec <= '1';\n wait for I_clk_period;\n I_exec <= '0';\n \n wait for I_clk_period*500;\n \n I_dividend <= X\"ffff0001\";\n I_divisor <= X\"00000111\";\n I_op <= ALU_INT32_DIV_OP_DIV;\n I_exec <= '1';\n wait for I_clk_period;\n I_exec <= '0';\n \n wait for I_clk_period*500;\n \n \n-- I_dividend <= X\"ffff0001\";\n-- I_divisor <= X\"00000111\";\n-- I_op <= ALU_INT32_DIV_OP_DIVU;\n-- I_exec <= '1';\n-- wait for I_clk_period;\n-- I_exec <= '0'; \n-- wait for I_clk_period*500;\n \n I_dividend <= X\"00011101\";\n I_divisor <= X\"00000001\";\n I_op <= ALU_INT32_DIV_OP_DIV;\n I_exec <= '1';\n wait for I_clk_period;\n I_exec <= '0';\n \n wait for I_clk_period*500;\n \n I_dividend <= X\"00010001\";\n I_divisor <= X\"00000111\";\n I_op <= ALU_INT32_DIV_OP_DIV;\n I_exec <= '1';\n wait for I_clk_period;\n I_exec <= '0';\n wait;\n end process;\n\n\nend Behavioral;\n", "groundtruth": "entity alu_int32_div_tb is\n-- Port ( );\nend alu_int32_div_tb;\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/tests/tb_unit_alu_RV32I_01.vhd", "left_context": "--------------------------------------------------------------------------------\n-- Company: \n-- Engineer:\n--\n-- Create Date: 16:43:32 12/10/2016\n-- Design Name: \n-- Module Name: C:/Users/colin/Desktop/riscy/ise/tb_unit_alu_RV32I_01.vhd\n-- Project Name: riscv32_v1\n-- Target Device: \n-- Tool versions: \n-- Description: \n-- \n-- VHDL Test Bench Created by ISE for module: alu_RV32I\n-- \n-- Dependencies:\n-- \n-- Revision:\n-- Revision 0.01 - File Created\n-- Additional Comments:\n--\n-- Notes: \n-- This testbench has been automatically generated using types std_logic and\n-- std_logic_vector for the ports of the unit under test. Xilinx recommends\n-- that these types always be used for the top-level I/O of a design in order\n-- to guarantee that the testbench will bind correctly to the post-implementation \n-- simulation model.\n--------------------------------------------------------------------------------\nLIBRARY ieee;\nUSE ieee.std_logic_1164.ALL;\n\nuse work.constants.all;\n \n-- Uncomment the following library declaration if using\n-- arithmetic functions with Signed or Unsigned values\n--USE ieee.numeric_std.ALL;\n \nENTITY tb_unit_alu_RV32I_01 IS\nEND tb_unit_alu_RV32I_01;\n \nARCHITECTURE behavior OF tb_unit_alu_RV32I_01 IS \n \n -- Component Declaration for the Unit Under Test (UUT)\n \n COMPONENT alu_RV32I\n PORT(\n I_clk : IN std_logic;\n I_en : IN std_logic;\n I_dataA : IN std_logic_vector(31 downto 0);\n I_dataB : IN std_logic_vector(31 downto 0);\n I_dataDwe : IN std_logic;\n I_aluop : IN std_logic_vector(4 downto 0);\n I_aluFunc : IN std_logic_vector(15 downto 0);\n I_PC : IN std_logic_vector(31 downto 0);\n I_dataIMM : IN std_logic_vector(31 downto 0);\n O_dataResult : OUT std_logic_vector(31 downto 0);\n O_branchTarget : OUT std_logic_vector(31 downto 0);\n O_dataWriteReg : OUT std_logic;\n O_shouldBranch : OUT std_logic\n );\n END COMPONENT;\n \n\n --Inputs\n signal I_clk : std_logic := '0';\n signal I_en : std_logic := '0';\n signal I_dataA : std_logic_vector(31 downto 0) := (others => '0');\n signal I_dataB : std_logic_vector(31 downto 0) := (others => '0');\n signal I_dataDwe : std_logic := '0';\n signal I_aluop : std_logic_vector(4 downto 0) := (others => '0');\n signal I_aluFunc : std_logic_vector(15 downto 0) := (others => '0');\n signal I_PC : std_logic_vector(31 downto 0) := (others => '0');\n signal I_dataIMM : std_logic_vector(31 downto 0) := (others => '0');\n\n \t--Outputs\n signal O_dataResult : std_logic_vector(31 downto 0);\n signal O_branchTarget : std_logic_vector(31 downto 0);\n signal O_dataWriteReg : std_logic := '0';\n signal O_shouldBranch : std_logic := '0';\n\n -- Clock period definitions\n constant I_clk_period : time := 10 ns;\n \nBEGIN\n \n\t-- Instantiate the Unit Under Test (UUT)\n uut: alu_RV32I PORT MAP (\n I_clk => I_clk,\n I_en => I_en,\n I_dataA => I_dataA,\n I_dataB => I_dataB,\n I_dataDwe => I_dataDwe,\n I_aluop => I_aluop,\n I_aluFunc => I_aluFunc,\n I_PC => I_PC,\n I_dataIMM => I_dataIMM,\n O_dataResult => O_dataResult,\n O_branchTarget => O_branchTarget,\n O_dataWriteReg => O_dataWriteReg,\n O_shouldBranch => O_shouldBranch\n );\n\n -- Clock process definitions\n I_clk_process :process\n begin\n\t\tI_clk <= '0';\n\t\twait for I_clk_period/2;\n\t\tI_clk <= '1';\n\t\twait for I_clk_period/2;\n end process;\n \n\n -- Stimulus process\n stim_proc: process\n begin\t\t\n -- hold reset state for 100 ns.\n wait for 100 ns;\t\n\n wait for I_clk_period*10;\n -- insert stimulus here \n\n I_dataA <= X\"00001000\";\n\t\tI_dataB <= X\"01A01001\";\n\t\tI_aluOp <= OPCODE_OP;\n\t\tI_aluFunc <= \"000000\" & F7_OP_ADD & F3_OP_ADD;\n\t\tI_dataImm <= X\"00000000\";\n\t\tI_PC <= X\"A0000000\";\n\t\tI_dataDwe <= '1';\n\t\tI_en <= '1';\n\t\t\n", "right_context": "\t\tI_PC <= X\"A0000004\";\n\t\tI_dataDwe <= '1';\n\t\tI_en <= '1';\n\t\t\n wait for I_clk_period*2;\n\n I_dataA <= X\"00346A00\";\n\t\tI_dataB <= X\"120000B6\";\n\t\tI_aluOp <= OPCODE_OP;\n\t\tI_aluFunc <= \"000000\" & F7_OP_OR & F3_OP_OR;\n\t\tI_dataImm <= X\"00000000\";\n\t\tI_PC <= X\"A0000008\";\n\t\tI_dataDwe <= '1';\n\t\tI_en <= '1';\n\t\t\n wait;\n end process;\n\nEND;\n", "groundtruth": " wait for I_clk_period*2;\n\n I_dataA <= X\"00000001\";\n\t\tI_dataB <= X\"00000006\";\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/tests/tb_unit_decoder_RV32_01.vhd", "left_context": "--------------------------------------------------------------------------------\n-- Company: \n-- Engineer:\n--\n-- Create Date: 22:43:26 12/08/2016\n-- Design Name: \n-- Module Name: C:/Users/colin/Desktop/riscy/ise/tb_unit_decoder_RV32_01.vhd\n-- Project Name: riscv32_v1\n-- Target Device: \n-- Tool versions: \n-- Description: \n-- \n-- VHDL Test Bench Created by ISE for module: decoder_RV32\n-- \n-- Dependencies:\n-- \n-- Revision:\n-- Revision 0.01 - File Created\n-- Additional Comments:\n--\n-- Notes: \n-- This testbench has been automatically generated using types std_logic and\n-- std_logic_vector for the ports of the unit under test. Xilinx recommends\n-- that these types always be used for the top-level I/O of a design in order\n-- to guarantee that the testbench will bind correctly to the post-implementation \n-- simulation model.\n--------------------------------------------------------------------------------\nLIBRARY ieee;\nUSE ieee.std_logic_1164.ALL;\n \n-- Uncomment the following library declaration if using\n-- arithmetic functions with Signed or Unsigned values\n--USE ieee.numeric_std.ALL;\n \nENTITY tb_unit_decoder_RV32_01 IS\nEND tb_unit_decoder_RV32_01;\n \nARCHITECTURE behavior OF tb_unit_decoder_RV32_01 IS \n \n -- Component Declaration for the Unit Under Test (UUT)\n \n COMPONENT decoder_RV32\n PORT(\n I_clk : IN std_logic;\n I_en : IN std_logic;\n I_dataInst : IN std_logic_vector(31 downto 0);\n O_selRS1 : OUT std_logic_vector(4 downto 0);\n O_selRS2 : OUT std_logic_vector(4 downto 0);\n O_selD : OUT std_logic_vector(4 downto 0);\n O_dataIMM : OUT std_logic_vector(31 downto 0);\n O_regDwe : OUT std_logic;\n O_aluOp : OUT std_logic_vector(6 downto 0);\n O_aluFunc : OUT std_logic_vector(15 downto 0); -- ALU function\n\t\t\tO_memOp : out STD_LOGIC_VECTOR(4 downto 0) \n );\n END COMPONENT;\n \n\n --Inputs\n signal I_clk : std_logic := '0';\n signal I_en : std_logic := '0';\n signal I_dataInst : std_logic_vector(31 downto 0) := (others => '0');\n\n \t--Outputs\n signal O_selRS1 : std_logic_vector(4 downto 0);\n signal O_selRS2 : std_logic_vector(4 downto 0);\n signal O_selD : std_logic_vector(4 downto 0);\n signal O_dataIMM : std_logic_vector(31 downto 0);\n signal O_regDwe : std_logic;\n signal O_aluOp : std_logic_vector(6 downto 0);\n signal O_aluFunc : std_logic_vector(15 downto 0);\n\tsignal O_memOp : STD_LOGIC_VECTOR(4 downto 0);\n\n -- Clock period definitions\n constant I_clk_period : time := 10 ns;\n \nBEGIN\n \n\t-- Instantiate the Unit Under Test (UUT)\n uut: decoder_RV32 PORT MAP (\n I_clk => I_clk,\n I_en => I_en,\n I_dataInst => I_dataInst,\n O_selRS1 => O_selRS1,\n O_selRS2 => O_selRS2,\n O_selD => O_selD,\n O_dataIMM => O_dataIMM,\n O_regDwe => O_regDwe,\n O_aluOp => O_aluOp,\n O_aluFunc => O_aluFunc,\n\t\t\t O_memOp => O_memOp\n );\n\n -- Clock process definitions\n I_clk_process :process\n", "right_context": " stim_proc: process\n begin\t\t\n -- hold reset state for 100 ns.\n wait for 100 ns;\t\n\n wait for I_clk_period*10;\n\n -- insert stimulus here \n\t\tI_dataInst <= \"0000000\" & \"00001\" & \"00010\" & \"000\" & \"01001\" & \"0110011\";\n\t\tI_en <= '1';\n\t\t\n\t\twait for I_clk_period*2;\n\t\t\n\t\tI_dataInst <= \"000000000001\" & \"00010\" & \"000\" & \"01001\" & \"0010011\";\n\t\tI_en <= '1';\n\t\t\n\t\twait for I_clk_period*2;\n\t\t\n\t\tI_dataInst <= \"100000000001\" & \"00010\" & \"000\" & \"01001\" & \"0010011\";\n\t\tI_en <= '1';\n\t\t\n\t\twait for I_clk_period*2;\n\t\t\n\t\tI_dataInst <= \"100001000001\" & \"00000\" & \"010\" & \"00001\" & \"0000011\";\n\t\tI_en <= '1';\n\t\t\n\t\twait for I_clk_period*2;\n\n wait;\n end process;\n\nEND;\n", "groundtruth": " begin\n\t\tI_clk <= '0';\n\t\twait for I_clk_period/2;\n\t\tI_clk <= '1';\n\t\twait for I_clk_period/2;\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/alu_int32_div.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RISC-V CPU\n-- Description: ALU unit for 32-bit integer division ops\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\n\n-- Uncomment the following library declaration if using\n-- arithmetic functions with Signed or Unsigned values\nuse IEEE.NUMERIC_STD.all;\nlibrary work;\nuse work.constants.all;\n\nentity alu_int32_div is\n port (\n I_clk : in STD_LOGIC;\n I_exec : in STD_LOGIC;\n I_dividend : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_divisor : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_op : in STD_LOGIC_VECTOR (1 downto 0);\n O_dataResult : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n O_done : out STD_LOGIC;\n O_int : out std_logic\n );\nend alu_int32_div;\n\narchitecture Behavioral of alu_int32_div is\n signal s_done : std_logic := '0';\n signal s_int : std_logic := '0';\n signal s_op : std_logic_vector(1 downto 0) := (others => '0');\n signal s_result : std_logic_vector(XLEN32M1 downto 0) := (others => '0');\n signal s_outsign : std_logic := '0';\n signal s_ur : unsigned(XLEN32M1 downto 0) := (others => '0');\n\n signal s_i : integer := 0;\n signal s_N : unsigned(XLEN32M1 downto 0) := (others => '0');\n signal s_D : unsigned(XLEN32M1 downto 0) := (others => '0');\n signal s_R : unsigned(XLEN32M1 downto 0) := (others => '0');\n signal s_Q : unsigned(XLEN32M1 downto 0) := (others => '0');\n", "right_context": " process (I_clk)\n begin\n if rising_edge(I_clk) then\n if s_state = STATE_IDLE then\n s_done <= '0';\n if I_exec = '1' then\n s_op <= I_op;\n s_done <= '0';\n\n if (I_divisor = X\"00000000\") then\n s_state <= STATE_COMPLETE;\n s_Q <= X\"ffffffff\";\n\n if I_dividend(31) = '1' then\n s_R <= unsigned(-signed(I_dividend));\n else\n s_R <= unsigned(I_dividend);\n end if;\n\n if (I_op = ALU_INT32_DIV_OP_DIV) or (I_op = ALU_INT32_DIV_OP_DIVU) then\n s_outsign <= '0';\n else\n s_outsign <= I_dividend(31);\n end if;\n \n elsif (I_divisor = X\"00000001\") and (I_op = ALU_INT32_DIV_OP_DIV) then\n s_state <= STATE_COMPLETE;\n s_R <= X\"00000000\";\n if I_dividend(31) = '1' then\n s_Q <= unsigned(-signed(I_dividend));\n else\n s_Q <= unsigned(I_dividend);\n end if;\n s_outsign <= I_dividend(31);\n \n else\n if I_op(ALU_INT32_DIV_OP_UNSIGNED_BIT) = '1' then\n s_state <= STATE_INFLIGHTU;\n s_N <= unsigned(I_dividend);\n s_D <= unsigned(I_divisor);\n s_ur <= X\"00000000\";\n s_Q <= X\"00000000\";\n s_R <= X\"00000000\";\n\n s_i <= 31;\n s_outsign <= '0';\n else\n s_state <= STATE_INFLIGHTU;\n\n if (I_op = ALU_INT32_DIV_OP_DIV) then\n s_outsign <= I_dividend(31) xor I_divisor(31);\n else\n s_outsign <= I_dividend(31);\n end if;\n\n if I_dividend(31) = '1' then\n s_N <= unsigned(-signed(I_dividend));\n else\n s_N <= unsigned(I_dividend);\n end if;\n\n if I_divisor(31) = '1' then\n s_D <= unsigned(-signed(I_divisor));\n else\n s_D <= unsigned(I_divisor);\n end if;\n\n s_ur <= X\"00000000\";\n\n s_Q <= X\"00000000\";\n s_R <= X\"00000000\";\n\n s_i <= 31;\n\n end if;\n end if;\n end if;\n \n \n elsif s_state = STATE_INFLIGHTU then\n -- binary integer long division loop\n if (s_R(30 downto 0) & s_N(s_i)) >= s_D then\n s_R <= (s_R(30 downto 0) & s_N(s_i)) - s_D;\n s_Q(s_i) <= '1';\n else\n s_R <= s_R(30 downto 0) & s_N(s_i);\n end if;\n \n if s_i = 0 then\n s_state <= STATE_COMPLETE;\n else\n s_i <= s_i - 1;\n end if;\n \n \n elsif s_state = STATE_COMPLETE then\n\n if (s_op = ALU_INT32_DIV_OP_DIV) or (s_op = ALU_INT32_DIV_OP_DIVU) then\n if (s_outsign = '1') then\n s_result <= std_logic_vector(-signed(std_logic_vector(s_Q)));\n else\n s_result <= std_logic_vector(s_Q);\n end if;\n else\n if (s_outsign = '1') then\n s_result <= std_logic_vector(-signed(std_logic_vector(s_R)));\n else\n s_result <= std_logic_vector(s_R);\n end if;\n end if;\n\n s_done <= '1';\n s_state <= STATE_IDLE;\n end if;\n end if;\n end process;\n\n O_dataResult <= s_result;\n O_done <= s_done;\n O_int <= s_int;\nend Behavioral;", "groundtruth": " constant STATE_IDLE : integer := 0;\n constant STATE_INFLIGHTU : integer := 1;\n constant STATE_COMPLETE : integer := 2;\n\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/constants.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RISC-V CPU\n-- Description: Constants for instruction forms, opcodes, conditional flags, etc.\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2016 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\n\npackage constants is\n\n\nconstant XLEN: integer := 32;\nconstant XLENM1: integer := XLEN - 1;\n\nconstant XLEN32: integer:= 32;\nconstant XLEN32M1: integer:= XLEN32 -1;\n\n\nconstant BWIDTH: integer:= 32;\nconstant BWIDTHM1: integer:= BWIDTH -1;\n\n\nconstant ADDR_RESET: std_logic_vector(XLEN32M1 downto 0) := X\"00000000\";\nconstant ADDR_INTVEC: std_logic_vector(XLEN32M1 downto 0) := X\"00000100\";\n\n\n-- PC unit opcodes\nconstant PCU_OP_NOP: std_logic_vector(1 downto 0):= \"00\";\nconstant PCU_OP_INC: std_logic_vector(1 downto 0):= \"01\";\nconstant PCU_OP_ASSIGN: std_logic_vector(1 downto 0):= \"10\";\nconstant PCU_OP_RESET: std_logic_vector(1 downto 0):= \"11\";\n\n-- Instruction Form Offsets\nconstant OPCODE_START: integer := 6;\nconstant OPCODE_END: integer := 0;\nconstant OPCODE_END_2: integer := 2;\n\nconstant RD_START: integer := 11;\nconstant RD_END: integer := 7;\n\nconstant FUNCT3_START: integer := 14;\nconstant FUNCT3_END: integer := 12;\n\nconstant R1_START: integer := 19;\nconstant R1_END: integer := 15;\n\nconstant R2_START: integer := 24;\nconstant R2_END: integer := 20;\n\nconstant FUNCT7_START: integer := 31;\nconstant FUNCT7_END: integer := 25;\n\nconstant IMM_I_START: integer := 31;\nconstant IMM_I_END: integer := 20;\n\nconstant IMM_U_START: integer := 31;\nconstant IMM_U_END: integer := 12;\n\nconstant IMM_S_A_START: integer := 31;\nconstant IMM_S_A_END: integer := 25;\n\nconstant IMM_S_B_START: integer := 11;\nconstant IMM_S_B_END: integer := 7;\n\n-- Opcodes\nconstant OPCODE_LOAD: std_logic_vector(4 downto 0) := \"00000\";\nconstant OPCODE_STORE: std_logic_vector(4 downto 0) := \"01000\";\nconstant OPCODE_MADD: std_logic_vector(4 downto 0) := \"10000\";\nconstant OPCODE_BRANCH: std_logic_vector(4 downto 0) := \"11000\";\nconstant OPCODE_JALR: std_logic_vector(4 downto 0) := \"11001\";\nconstant OPCODE_JAL: std_logic_vector(4 downto 0) := \"11011\";\nconstant OPCODE_SYSTEM: std_logic_vector(4 downto 0) := \"11100\";\nconstant OPCODE_OP: std_logic_vector(4 downto 0) := \"01100\";\nconstant OPCODE_OPIMM: std_logic_vector(4 downto 0) := \"00100\";\nconstant OPCODE_MISCMEM: std_logic_vector(4 downto 0) := \"00011\";\nconstant OPCODE_AUIPC: std_logic_vector(4 downto 0) := \"00101\";\nconstant OPCODE_LUI: std_logic_vector(4 downto 0) := \"01101\";\n\n-- Flags\nconstant F3_BRANCH_BEQ: std_logic_vector(2 downto 0) := \"000\";\nconstant F3_BRANCH_BNE: std_logic_vector(2 downto 0) := \"001\";\nconstant F3_BRANCH_BLT: std_logic_vector(2 downto 0) := \"100\";\nconstant F3_BRANCH_BGE: std_logic_vector(2 downto 0) := \"101\";\nconstant F3_BRANCH_BLTU: std_logic_vector(2 downto 0) := \"110\";\nconstant F3_BRANCH_BGEU: std_logic_vector(2 downto 0) := \"111\";\n\nconstant F3_JALR: std_logic_vector(2 downto 0) := \"000\";\n\nconstant F3_LOAD_LB: std_logic_vector(2 downto 0) := \"000\";\nconstant F3_LOAD_LH: std_logic_vector(2 downto 0) := \"001\";\nconstant F3_LOAD_LW: std_logic_vector(2 downto 0) := \"010\";\nconstant F3_LOAD_LBU: std_logic_vector(2 downto 0) := \"100\";\nconstant F3_LOAD_LHU: std_logic_vector(2 downto 0) := \"101\";\n\nconstant F2_MEM_LS_SIZE_B: std_logic_vector(1 downto 0) := \"00\";\nconstant F2_MEM_LS_SIZE_H: std_logic_vector(1 downto 0) := \"01\";\nconstant F2_MEM_LS_SIZE_W: std_logic_vector(1 downto 0) := \"10\";\n\nconstant F3_STORE_SB: std_logic_vector(2 downto 0) := \"000\";\nconstant F3_STORE_SH: std_logic_vector(2 downto 0) := \"001\";\nconstant F3_STORE_SW: std_logic_vector(2 downto 0) := \"010\";\n\nconstant F3_OPIMM_ADDI: std_logic_vector(2 downto 0) := \"000\";\nconstant F3_OPIMM_SLTI: std_logic_vector(2 downto 0) := \"010\";\nconstant F3_OPIMM_SLTIU: std_logic_vector(2 downto 0) := \"011\";\nconstant F3_OPIMM_XORI: std_logic_vector(2 downto 0) := \"100\";\nconstant F3_OPIMM_ORI: std_logic_vector(2 downto 0) := \"110\";\nconstant F3_OPIMM_ANDI: std_logic_vector(2 downto 0) := \"111\";\n\nconstant F3_OPIMM_SLLI: std_logic_vector(2 downto 0) := \"001\";\nconstant F7_OPIMM_SLLI: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OPIMM_SRLI: std_logic_vector(2 downto 0) := \"101\";\nconstant F7_OPIMM_SRLI: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OPIMM_SRAI: std_logic_vector(2 downto 0) := \"101\";\nconstant F7_OPIMM_SRAI: std_logic_vector(6 downto 0) := \"0100000\";\n\nconstant F3_OP_ADD: std_logic_vector(2 downto 0) := \"000\";\nconstant F7_OP_ADD: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OP_SUB: std_logic_vector(2 downto 0) := \"000\";\nconstant F7_OP_SUB: std_logic_vector(6 downto 0) := \"0100000\";\nconstant F3_OP_SLL: std_logic_vector(2 downto 0) := \"001\";\nconstant F7_OP_SLL: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OP_SLT: std_logic_vector(2 downto 0) := \"010\";\nconstant F7_OP_SLT: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OP_SLTU: std_logic_vector(2 downto 0) := \"011\";\nconstant F7_OP_SLTU: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OP_XOR: std_logic_vector(2 downto 0) := \"100\";\nconstant F7_OP_XOR: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OP_SRL: std_logic_vector(2 downto 0) := \"101\";\nconstant F7_OP_SRL: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OP_SRA: std_logic_vector(2 downto 0) := \"101\";\nconstant F7_OP_SRA: std_logic_vector(6 downto 0) := \"0100000\";\nconstant F3_OP_OR: std_logic_vector(2 downto 0) := \"110\";\nconstant F7_OP_OR: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F3_OP_AND: std_logic_vector(2 downto 0) := \"111\";\nconstant F7_OP_AND: std_logic_vector(6 downto 0) := \"0000000\";\n\n-- RV32M Extension\nconstant F7_OP_M_EXT: std_logic_vector(6 downto 0) := \"0000001\";\nconstant F3_OP_M_MUL: std_logic_vector(2 downto 0) := \"000\";\nconstant F3_OP_M_MULH: std_logic_vector(2 downto 0) := \"001\";\nconstant F3_OP_M_MULHSU: std_logic_vector(2 downto 0) := \"010\";\nconstant F3_OP_M_MULHU: std_logic_vector(2 downto 0) := \"011\";\nconstant F3_OP_M_DIV: std_logic_vector(2 downto 0) := \"100\";\nconstant F3_OP_M_DIVU: std_logic_vector(2 downto 0) := \"101\";\nconstant F3_OP_M_REM: std_logic_vector(2 downto 0) := \"110\";\nconstant F3_OP_M_REMU: std_logic_vector(2 downto 0) := \"111\";\n\n-- bit 0 of the OP definitions denote unsigned ops; same as above\nconstant ALU_INT32_DIV_OP_UNSIGNED_BIT: integer := 0;\nconstant ALU_INT32_DIV_OP_DIV: std_logic_vector(1 downto 0) := \"00\";\nconstant ALU_INT32_DIV_OP_DIVU: std_logic_vector(1 downto 0) := \"01\";\nconstant ALU_INT32_DIV_OP_REM: std_logic_vector(1 downto 0) := \"10\";\nconstant ALU_INT32_DIV_OP_REMU: std_logic_vector(1 downto 0) := \"11\";\n\nconstant F3_MISCMEM_FENCE: std_logic_vector(2 downto 0) := \"000\";\nconstant F3_MISCMEM_FENCEI: std_logic_vector(2 downto 0) := \"001\";\n\nconstant F3_SYSTEM_ECALL: std_logic_vector(2 downto 0) := \"000\";\nconstant IMM_I_SYSTEM_ECALL: std_logic_vector(11 downto 0) := \"000000000000\";\nconstant F3_SYSTEM_EBREAK: std_logic_vector(2 downto 0) := \"000\";\nconstant IMM_I_SYSTEM_EBREAK: std_logic_vector(11 downto 0) := \"000000000001\";\nconstant F3_SYSTEM_CSRRW: std_logic_vector(2 downto 0) := \"001\";\nconstant F3_SYSTEM_CSRRS: std_logic_vector(2 downto 0) := \"010\";\nconstant F3_SYSTEM_CSRRC: std_logic_vector(2 downto 0) := \"011\";\nconstant F3_SYSTEM_CSRRWI: std_logic_vector(2 downto 0) := \"101\";\nconstant F3_SYSTEM_CSRRSI: std_logic_vector(2 downto 0) := \"110\";\nconstant F3_SYSTEM_CSRRCI: std_logic_vector(2 downto 0) := \"111\";\n\n\nconstant F3_PRIVOP: std_logic_vector(2 downto 0) := \"000\";\n\nconstant F7_PRIVOP_URET: std_logic_vector(6 downto 0) := \"0000000\";\nconstant F7_PRIVOP_SRET_WFI: std_logic_vector(6 downto 0) := \"0001000\";\nconstant F7_PRIVOP_MRET: std_logic_vector(6 downto 0) := \"0011000\";\nconstant F7_PRIVOP_SFENCE_VMA: std_logic_vector(6 downto 0) := \"0001001\";\n\nconstant RD_PRIVOP: std_logic_vector(4 downto 0) := \"00000\";\n\nconstant R2_PRIV_RET: std_logic_vector(4 downto 0) := \"00010\";\nconstant R2_PRIV_WFI: std_logic_vector(4 downto 0) := \"00101\";\n\n\nconstant EXCEPTION_INT_USER_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X\"80000000\";\nconstant EXCEPTION_INT_SUPERVISOR_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X\"80000001\";\n--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X\"80000002\";\nconstant EXCEPTION_INT_MACHINE_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X\"80000003\";\nconstant EXCEPTION_INT_USER_TIMER: std_logic_vector(XLEN32M1 downto 0):= X\"80000004\";\nconstant EXCEPTION_INT_SUPERVISOR_TIMER: std_logic_vector(XLEN32M1 downto 0):= X\"80000005\";\n--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X\"80000006\";\nconstant EXCEPTION_INT_MACHINE_TIMER: std_logic_vector(XLEN32M1 downto 0):= X\"80000007\";\nconstant EXCEPTION_INT_USER_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X\"80000008\";\nconstant EXCEPTION_INT_SUPERVISOR_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X\"80000009\";\n--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X\"8000000a\";\nconstant EXCEPTION_INT_MACHINE_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X\"8000000b\";\n\nconstant EXCEPTION_INSTRUCTION_ADDR_MISALIGNED: std_logic_vector(XLEN32M1 downto 0):= X\"00000000\";\nconstant EXCEPTION_INSTRUCTION_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"00000001\";\nconstant EXCEPTION_INSTRUCTION_ILLEGAL: std_logic_vector(XLEN32M1 downto 0):= X\"00000002\";\nconstant EXCEPTION_BREAKPOINT: std_logic_vector(XLEN32M1 downto 0):= X\"00000003\";\nconstant EXCEPTION_LOAD_ADDRESS_MISALIGNED: std_logic_vector(XLEN32M1 downto 0):= X\"00000004\";\nconstant EXCEPTION_LOAD_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"00000005\";\nconstant EXCEPTION_STORE_AMO_ADDRESS_MISALIGNED:std_logic_vector(XLEN32M1 downto 0):= X\"00000006\";\nconstant EXCEPTION_STORE_AMO_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"00000007\";\nconstant EXCEPTION_ENVIRONMENT_CALL_FROM_UMODE: std_logic_vector(XLEN32M1 downto 0):= X\"00000008\";\nconstant EXCEPTION_ENVIRONMENT_CALL_FROM_SMODE: std_logic_vector(XLEN32M1 downto 0):= X\"00000009\";\n--constant EXCEPTION_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X\"0000000a\";\nconstant EXCEPTION_ENVIRONMENT_CALL_FROM_MMODE: std_logic_vector(XLEN32M1 downto 0):= X\"0000000b\";\nconstant EXCEPTION_INSTRUCTION_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"0000000c\";\nconstant EXCEPTION_LOAD_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"0000000d\";\n--constant EXCEPTION_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X\"0000000e\";\n", "right_context": "\nconstant CSR_ADDR_PRIVILEGE_BIT_START: integer := 9;\nconstant CSR_ADDR_PRIVILEGE_BIT_END: integer := 8;\nconstant CSR_ADDR_PRIVILEGE_USER: std_logic_vector(1 downto 0):= \"00\";\nconstant CSR_ADDR_PRIVILEGE_SUPERVISOR: std_logic_vector(1 downto 0):= \"01\";\nconstant CSR_ADDR_PRIVILEGE_RESERVED: std_logic_vector(1 downto 0):= \"10\";\nconstant CSR_ADDR_PRIVILEGE_MACHINE: std_logic_vector(1 downto 0):= \"11\";\n\nconstant CSR_ADDR_ACCESS_BIT_START: integer := 11;\nconstant CSR_ADDR_ACCESS_BIT_END: integer := 10;\nconstant CSR_ADDR_ACCESS_READONLY: std_logic_vector(1 downto 0):= \"11\";\n\n\n-- CSR Opcodes:\n-- 0 - CSR Written\n-- 1 - CSR Read\n-- 2..3 0 operation\n-- 01 - read or write whole XLEN\n-- 10 - Set bits\n-- 11 - clear bits\n-- 4 - immediate or register\n\nconstant CSR_OP_BITS_READ: integer := 0;\nconstant CSR_OP_BITS_WRITTEN: integer := 1;\nconstant CSR_OP_BITS_OPA: integer := 2;\nconstant CSR_OP_BITS_OPB: integer := 3;\nconstant CSR_OP_BITS_IMM: integer := 4;\n\nconstant CSR_MAINOP_WR: std_logic_vector(1 downto 0) := \"01\";\nconstant CSR_MAINOP_SET: std_logic_vector(1 downto 0) := \"10\";\nconstant CSR_MAINOP_CLEAR: std_logic_vector(1 downto 0) := \"11\";\n\nconstant CSR_OP_WR: std_logic_vector(4 downto 0) := \"00100\";\nconstant CSR_OP_W: std_logic_vector(4 downto 0) := \"00101\";\nconstant CSR_OP_R: std_logic_vector(4 downto 0) := \"00110\";\n\nconstant CSR_OP_SET_WR: std_logic_vector(4 downto 0) := \"01000\";\nconstant CSR_OP_SET_W: std_logic_vector(4 downto 0) := \"01001\";\nconstant CSR_OP_SET_R: std_logic_vector(4 downto 0) := \"01010\";\n\nconstant CSR_OP_CLEAR_WR: std_logic_vector(4 downto 0) := \"01100\";\nconstant CSR_OP_CLEAR_W: std_logic_vector(4 downto 0) := \"01101\";\nconstant CSR_OP_CLEAR_R: std_logic_vector(4 downto 0) := \"01110\";\n\nconstant CSR_OP_IMM_WR: std_logic_vector(4 downto 0) := \"10100\";\nconstant CSR_OP_IMM_W: std_logic_vector(4 downto 0) := \"10101\";\nconstant CSR_OP_IMM_R: std_logic_vector(4 downto 0) := \"10110\";\n\nconstant CSR_OP_IMM_SET_WR: std_logic_vector(4 downto 0) := \"11000\";\nconstant CSR_OP_IMM_SET_W: std_logic_vector(4 downto 0) := \"11001\";\nconstant CSR_OP_IMM_SET_R: std_logic_vector(4 downto 0) := \"11010\";\n\nconstant CSR_OP_IMM_CLEAR_WR: std_logic_vector(4 downto 0) := \"11100\";\nconstant CSR_OP_IMM_CLEAR_W: std_logic_vector(4 downto 0) := \"11101\";\nconstant CSR_OP_IMM_CLEAR_R: std_logic_vector(4 downto 0) := \"11110\";\n\n\n\nend constants;\n\npackage body constants is\n \nend constants;\n", "groundtruth": "constant EXCEPTION_STORE_AMO_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X\"0000000f\";\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/control_unit.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RPU\n-- Description: control unit\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2016,2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\n\nlibrary work;\nuse work.constants.all;\n\nentity control_unit is\n port (\n I_clk : in STD_LOGIC;\n I_reset : in STD_LOGIC;\n I_halt : in STD_LOGIC;\n I_aluop : in STD_LOGIC_VECTOR (6 downto 0);\n\n -- interrupts\n I_int_enabled : in std_logic;\n I_int : in STD_LOGIC;\n O_int_ack : out STD_LOGIC;\n I_int_mem_data : in STD_LOGIC_VECTOR(XLENM1 downto 0);\n O_idata : out STD_LOGIC_VECTOR(XLENM1 downto 0);\n O_set_idata : out STD_LOGIC;\n O_set_ipc : out STD_LOGIC;\n O_set_irpc : out STD_LOGIC;\n O_instTick : out STD_LOGIC;\n -- mem controller state and control \n I_misalignment : in STD_LOGIC;\n I_ready : in STD_LOGIC;\n O_execute : out STD_LOGIC;\n I_dataReady : in STD_LOGIC;\n\n -- alu stall input\n I_aluWait : in STD_LOGIC;\n I_aluMultiCy : in STD_LOGIC;\n O_state : out STD_LOGIC_VECTOR (6 downto 0)\n );\nend control_unit;\n\narchitecture Behavioral of control_unit is\n signal s_state : STD_LOGIC_VECTOR(6 downto 0) := \"0000001\";\n\n signal mem_ready : std_logic;\n signal mem_execute : std_logic := '0';\n signal mem_dataReady : std_logic;\n\n signal mem_cycles : integer := 0;\n\n signal next_s_state : STD_LOGIC_VECTOR(6 downto 0) := \"0000001\";\n\n signal interrupt_state : STD_LOGIC_VECTOR(2 downto 0) := \"000\";\n signal interrupt_ack : STD_LOGIC := '0';\n signal interrupt_was_inactive : STD_LOGIC := '1';\n signal set_idata : STD_LOGIC := '0';\n signal set_ipc : STD_LOGIC := '0';\n signal instTick : STD_LOGIC := '0';\n signal s_hasWaited : STD_LOGIC := '0';\n\n signal s_check_alignint : integer := 0;\nbegin\n\n O_execute <= mem_execute;\n mem_ready <= I_ready;\n mem_dataReady <= I_dataReady;\n O_int_ack <= interrupt_ack;\n O_set_idata <= set_idata;\n O_set_irpc <= set_idata;\n O_set_ipc <= set_ipc;\n O_instTick <= instTick;\n\n process (I_clk)\n begin\n if rising_edge(I_clk) and I_halt = '0' then\n\n if I_reset = '1' then\n s_state <= \"0000001\";\n next_s_state <= \"0000001\";\n mem_cycles <= 0;\n mem_execute <= '0';\n interrupt_was_inactive <= '1';\n interrupt_ack <= '0';\n interrupt_state <= \"000\";\n set_ipc <= '0';\n O_idata <= X\"00000000\";\n set_idata <= '0';\n instTick <= '0';\n else\n case s_state is\n ---------------------------\n -- FETCH \n when \"0000001\" => -- fetch\n\n if s_check_alignint /= 0 then\n -- If we've seen an alignment hint we need to stall here for s_check_alignint\n -- cycles, checking for an interrupt each time. When it's 0 we give up.\n if I_int_enabled = '1' and interrupt_was_inactive = '1' and I_int = '1' then\n interrupt_ack <= '1';\n", "right_context": " else\n s_check_alignint <= s_check_alignint - 1;\n end if;\n else\n\n if I_int = '0' then\n interrupt_was_inactive <= '1';\n end if;\n instTick <= '0';\n if mem_cycles = 0 and mem_ready = '1' then\n mem_execute <= '1';\n mem_cycles <= 1;\n\n elsif mem_cycles = 1 then\n mem_execute <= '0';\n mem_cycles <= 2;\n\n elsif mem_cycles = 2 then\n mem_execute <= '0';\n if mem_dataReady = '1' then\n mem_cycles <= 0;\n s_state <= \"0000010\";\n end if;\n end if;\n\n end if;\n\n ---------------------------\n -- DECODE \n when \"0000010\" => --- decode\n if I_int = '0' then\n interrupt_was_inactive <= '1';\n end if;\n s_hasWaited <= '0';\n s_state <= \"0001000\"; --E \"0000100\"; --R\n \n \n ---------------------------\n -- EXECUTE\n when \"0001000\" => -- execute\n if I_int = '0' then\n interrupt_was_inactive <= '1';\n end if;\n --MEM/WB\n -- if it's not a memory alu op, goto writeback\n if (I_aluop(6 downto 2) = OPCODE_LOAD or\n I_aluop(6 downto 2) = OPCODE_STORE) then\n s_state <= \"0010000\"; -- MEM\n\n -- -- mem load short cut\n -- ISSUE - this fails to take into account the type of request, sizing, address correctly\n -- and therefore needs removed for compliance to pass.\n -- if I_misalignment = '0' and mem_cycles = 0 and mem_ready = '1' then\n -- mem_execute <= '1';\n -- mem_cycles <= 1;\n -- end if;\n\n else\n if I_aluWait = '0' then\n if I_aluMultiCy = '1' then\n if s_hasWaited = '1' then\n s_state <= \"0100000\"; -- WB\n end if;\n else\n s_state <= \"0100000\"; -- WB\n end if;\n s_hasWaited <= '1';\n end if;\n end if;\n\n ---------------------------\n -- MEMORY\n when \"0010000\" => -- mem\n if I_int = '0' then\n interrupt_was_inactive <= '1';\n end if;\n\n -- alignment traps here are tricky.\n -- if we see the misalignment hint, wait 6 cycles and then test interrupt stall.\n -- if no interrupt we need to re-run the stage.\n\n if I_misalignment = '1' and s_check_alignint = 0 then\n s_check_alignint <= 6;\n elsif s_check_alignint > 0 then\n if I_int_enabled = '1' and interrupt_was_inactive = '1' and I_int = '1' then\n interrupt_ack <= '1';\n interrupt_was_inactive <= '0';\n interrupt_state <= \"001\";\n next_s_state <= \"0000001\"; --F\n s_state <= \"1000000\"; --F\n s_check_alignint <= 0;\n else\n s_check_alignint <= s_check_alignint - 1;\n end if;\n\n else\n if mem_cycles = 0 and mem_ready = '1' then\n\n mem_execute <= '1';\n mem_cycles <= 1;\n\n elsif mem_cycles = 1 then\n mem_execute <= '0';\n -- if it's a write, go through\n if I_aluop(6 downto 2) = OPCODE_STORE then\n mem_cycles <= 0;\n s_state <= \"0100000\"; -- WB\n elsif mem_dataReady = '1' then\n -- if read, wait for data\n mem_cycles <= 0;\n s_state <= \"0100000\"; -- WB\n end if;\n end if;\n end if;\n\n\n ---------------------------\n -- WRITEBACK\n when \"0100000\" => -- writeback\n -- check interrupt?\n if I_int_enabled = '1' and interrupt_was_inactive = '1' and I_int = '1' then\n interrupt_ack <= '1';\n interrupt_was_inactive <= '0';\n interrupt_state <= \"001\";\n next_s_state <= \"0000001\"; --F\n s_state <= \"1000000\"; --F\n else\n if I_int = '0' then\n interrupt_was_inactive <= '1';\n end if;\n if I_misalignment = '1' and s_check_alignint = 0 then\n s_check_alignint <= 3;\n end if;\n\n -- misalign interrupts take a while to propagate\n -- this signal short cuts to ensure we can catch any misalignments before fetch.\n\n s_state <= \"0000001\"; --F\n\n -- if the mem system is ready, shortcut the fetch\n -- at this point, the next PC/Branch should be set.\n -- need to ensure the sizing is correct.\n if I_misalignment = '0' and mem_cycles = 0 and mem_ready = '1' then -- shortcut\n mem_execute <= '1'; -- shortcut\n mem_cycles <= 2; -- shortcut \n end if; -- shortcut\n\n end if;\n instTick <= '1';\n when \"1000000\" => -- stalls\n if I_int = '0' then\n interrupt_was_inactive <= '1';\n end if;\n instTick <= '0';\n -- interrupt stall\n if interrupt_state = \"001\" then\n -- give a cycle of latency\n -- set PC to interrupt vector.\n\n set_ipc <= '1';\n interrupt_state <= \"101\";\n\n elsif interrupt_state = \"101\" then\n set_ipc <= '0';\n interrupt_ack <= '0';\n interrupt_state <= \"111\";\n elsif interrupt_state = \"111\" then\n interrupt_state <= \"000\";\n s_state <= \"0000001\"; --F\n end if;\n when \"1001000\" =>\n -- alu 1 cycle stall\n s_state <= \"0100000\"; -- WB\n when others =>\n s_state <= \"0000001\";\n end case;\n end if;\n end if;\n end process;\n\n O_state <= s_state;\nend Behavioral;", "groundtruth": " interrupt_was_inactive <= '0';\n interrupt_state <= \"001\";\n next_s_state <= \"0000001\"; --F\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/core.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RPU\n-- Description: RPU core glue entity\n--\n-- Brings all core components together with a little logic.\n-- This is the CPU interface required.\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\n\nlibrary work;\nuse work.constants.all;\n\nentity core is\n port (\n I_clk : in STD_LOGIC;\n I_reset : in STD_LOGIC;\n I_halt : in STD_LOGIC;\n\n -- External Interrupt interface\n", "right_context": " -- Will be fixed when memory swizzling is brought core-size\n MEM_O_byteEnable : out std_logic_vector(1 downto 0);\n MEM_O_addr : out std_logic_vector(XLEN32M1 downto 0);\n MEM_O_data : out std_logic_vector(XLEN32M1 downto 0);\n MEM_I_data : in std_logic_vector(XLEN32M1 downto 0);\n MEM_I_dataReady : in std_logic\n\n ; -- This debug output contains some internal state for debugging\n O_halted : out std_logic;\n O_DBG : out std_logic_vector(63 downto 0)\n );\nend core;\n\narchitecture Behavioral of core is\n component pc_unit\n port (\n I_clk : in std_logic;\n I_nPC : in std_logic_vector(XLENM1 downto 0);\n I_nPCop : in std_logic_vector(1 downto 0);\n I_intVec : in std_logic;\n O_PC : out std_logic_vector(XLENM1 downto 0)\n );\n end component;\n\n component control_unit\n port (\n I_clk : in STD_LOGIC;\n I_halt : in STD_LOGIC;\n I_reset : in STD_LOGIC;\n I_aluop : in STD_LOGIC_VECTOR (6 downto 0);\n O_state : out STD_LOGIC_VECTOR (6 downto 0);\n\n I_int : in STD_LOGIC;\n O_int_ack : out STD_LOGIC;\n\n I_int_enabled : in STD_LOGIC;\n I_int_mem_data : in STD_LOGIC_VECTOR(XLENM1 downto 0);\n O_idata : out STD_LOGIC_VECTOR(XLENM1 downto 0);\n O_set_idata : out STD_LOGIC;\n O_set_ipc : out STD_LOGIC;\n O_set_irpc : out STD_LOGIC;\n O_instTick : out STD_LOGIC;\n\n I_misalignment : in STD_LOGIC;\n I_ready : in STD_LOGIC;\n O_execute : out STD_LOGIC;\n I_dataReady : in STD_LOGIC;\n I_aluMultiCy : in STD_LOGIC;\n I_aluWait : in STD_LOGIC\n );\n end component;\n component decoder_RV32\n port (\n I_clk : in std_logic;\n I_en : in std_logic;\n I_dataInst : in std_logic_vector(31 downto 0);\n O_selRS1 : out std_logic_vector(4 downto 0);\n O_selRS2 : out std_logic_vector(4 downto 0);\n O_selD : out std_logic_vector(4 downto 0);\n O_dataIMM : out std_logic_vector(31 downto 0);\n O_regDwe : out std_logic;\n O_aluOp : out std_logic_vector(6 downto 0);\n O_aluFunc : out std_logic_vector(15 downto 0);\n O_memOp : out STD_LOGIC_VECTOR(4 downto 0);\n O_csrOP : out STD_LOGIC_VECTOR(4 downto 0);\n O_csrAddr : out STD_LOGIC_VECTOR(11 downto 0);\n O_trapExit : out STD_LOGIC;\n O_multycyAlu : out STD_LOGIC;\n O_int : out STD_LOGIC;\n O_int_data : out STD_LOGIC_VECTOR (31 downto 0);\n I_int_ack : in STD_LOGIC\n );\n end component;\n component alu_RV32I is\n port (\n I_clk : in STD_LOGIC;\n I_en : in STD_LOGIC;\n I_dataA : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_dataB : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_dataDwe : in STD_LOGIC;\n I_aluop : in STD_LOGIC_VECTOR (4 downto 0);\n I_aluFunc : in STD_LOGIC_VECTOR (15 downto 0);\n I_PC : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_epc : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_dataIMM : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_clear : in STD_LOGIC;\n O_dataResult : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n O_branchTarget : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n O_dataWriteReg : out STD_LOGIC;\n O_lastPC : out STD_LOGIC_VECTOR(XLEN32M1 downto 0);\n O_shouldBranch : out std_logic;\n O_wait : out std_logic\n\n );\n end component;\n\n component register_set\n port (\n I_clk : in std_logic;\n I_en : in std_logic;\n I_dataD : in std_logic_vector(31 downto 0);\n I_selRS1 : in std_logic_vector(4 downto 0);\n I_selRS2 : in std_logic_vector(4 downto 0);\n I_selD : in std_logic_vector(4 downto 0);\n I_we : in std_logic;\n O_dataA : out std_logic_vector(31 downto 0);\n O_dataB : out std_logic_vector(31 downto 0)\n );\n end component;\n\n component csr_unit\n port (\n I_clk : in STD_LOGIC;\n I_en : in STD_LOGIC;\n\n I_dataIn : in STD_LOGIC_VECTOR(XLENM1 downto 0);\n O_dataOut : out STD_LOGIC_VECTOR(XLENM1 downto 0);\n\n I_csrOp : in STD_LOGIC_VECTOR (4 downto 0);\n I_csrAddr : in STD_LOGIC_VECTOR (11 downto 0);\n\n -- This unit can raise exceptions\n O_int : out STD_LOGIC;\n O_int_data : out STD_LOGIC_VECTOR (31 downto 0);\n\n I_instRetTick : in STD_LOGIC;\n -- interrupt handling causes many data dependencies\n -- mcause has a fast path in from other units\n I_int_cause : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_int_pc : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_int_mtval : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n -- We need to know when an interrupt occurs as to perform the\n -- relevant csr modifications. Same with exit.\n I_int_entry : in STD_LOGIC;\n I_int_exit : in STD_LOGIC;\n\n -- Currently just feeds machine level CSR values\n O_csr_status : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_cause : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_ie : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_tvec : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_epc : out STD_LOGIC_VECTOR (XLENM1 downto 0)\n );\n end component;\n\n component lint_unit\n port (\n I_clk : in STD_LOGIC;\n I_reset : in STD_LOGIC;\n I_nextPc : in STD_LOGIC_VECTOR (31 downto 0);\n I_enMask : in STD_LOGIC_VECTOR (3 downto 0);\n I_pc : in STD_LOGIC_VECTOR (31 downto 0);\n I_int0 : in STD_LOGIC;\n I_int_data0 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int0_ack : out STD_LOGIC;\n I_int1 : in STD_LOGIC;\n I_int_data1 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int1_ack : out STD_LOGIC;\n I_int2 : in STD_LOGIC;\n I_int_data2 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int2_ack : out STD_LOGIC;\n I_int3 : in STD_LOGIC;\n I_int_data3 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int3_ack : out STD_LOGIC;\n O_int : out STD_LOGIC;\n O_int_data : out STD_LOGIC_VECTOR (31 downto 0);\n O_int_epc : out STD_LOGIC_VECTOR (31 downto 0)\n );\n end component;\n\n component mem_controller\n port (\n I_clk : in std_logic;\n I_reset : in std_logic;\n O_ready : out std_logic;\n I_execute : in std_logic;\n I_dataWe : in std_logic;\n I_address : in std_logic_vector(XLENM1 downto 0);\n I_data : in std_logic_vector(XLENM1 downto 0);\n I_dataByteEn : in std_logic_vector(1 downto 0);\n I_signExtend : in STD_LOGIC;\n O_data : out std_logic_vector(XLENM1 downto 0);\n O_dataReady : out std_logic;\n MEM_I_ready : in std_logic;\n MEM_O_cmd : out std_logic;\n MEM_O_we : out std_logic;\n MEM_O_byteEnable : out std_logic_vector(1 downto 0);\n MEM_O_addr : out std_logic_vector(XLENM1 downto 0);\n MEM_O_data : out std_logic_vector(XLENM1 downto 0);\n MEM_I_data : in std_logic_vector(XLENM1 downto 0);\n MEM_I_dataReady : in std_logic\n );\n end component;\n signal state : std_logic_vector(6 downto 0) := (others => '0');\n signal pcop : std_logic_vector(1 downto 0);\n signal in_pc : std_logic_vector(XLENM1 downto 0);\n\n signal aluFunc : std_logic_vector(15 downto 0);\n signal memOp : std_logic_vector(4 downto 0);\n signal branchTarget : std_logic_vector(XLENM1 downto 0) := (others => '0');\n\n signal instruction : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal dataA : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal dataB : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal dataDwe : std_logic := '0';\n signal aluop : std_logic_vector(6 downto 0) := (others => '0');\n signal dataIMM : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal selRS1 : std_logic_vector(4 downto 0) := (others => '0');\n signal selRS2 : std_logic_vector(4 downto 0) := (others => '0');\n signal selD : std_logic_vector(4 downto 0) := (others => '0');\n signal dataregWrite : std_logic := '0';\n signal dataResult : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal latchedDataResult : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal dataWriteReg : std_logic := '0';\n signal shouldBranch : std_logic := '0';\n signal memMode : std_logic := '0';\n signal ram_req_size : std_logic := '0';\n signal alu_wait : std_logic := '0';\n signal alutobemulticycle : std_logic := '0';\n\n signal decoder_int : STD_LOGIC;\n signal decoder_int_data : STD_LOGIC_VECTOR(XLENM1 downto 0);\n signal decoder_int_ack : STD_LOGIC := '0';\n signal decoder_trap_exit : STD_LOGIC := '0';\n signal reg_en : std_logic := '0';\n signal reg_we : std_logic := '0';\n\n signal registerWriteData : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal alu_or_csr_output : std_logic_vector(XLENM1 downto 0) := (others => '0');\n\n signal en_fetch : std_logic := '0';\n signal en_decode : std_logic := '0';\n signal en_alu : std_logic := '0';\n signal en_csru : std_logic := '0';\n signal en_memory : std_logic := '0';\n signal en_regwrite : std_logic := '0';\n signal en_stall : std_logic := '0';\n\n signal PC : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal PC_at_int : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal lastPC_dec : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal lastPC_alu : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal nextPC_stall : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal mtval : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal memctl_ready : std_logic;\n signal memctl_execute : std_logic := '0';\n signal memctl_dataWe : std_logic;\n signal memctl_address : std_logic_vector(XLENM1 downto 0);\n signal memctl_in_data : std_logic_vector(XLENM1 downto 0);\n signal memctl_dataByteEn : std_logic_vector(1 downto 0);\n signal memctl_out_data : std_logic_vector(XLENM1 downto 0) := (others => '0');\n signal memctl_dataReady : std_logic := '0';\n signal memctl_size : std_logic_vector(1 downto 0);\n signal memctl_signExtend : std_logic := '0';\n\n signal PCintVec : STD_LOGIC := '0';\n\n signal int_idata : STD_LOGIC_VECTOR(XLENM1 downto 0);\n signal int_set_idata : STD_LOGIC;\n signal int_enabled : std_logic := '1';\n signal int_set_irpc : STD_LOGIC;\n\n signal I_int_entry : STD_LOGIC := '0';\n signal I_int_exit : STD_LOGIC := '0';\n\n signal csru_int : STD_LOGIC;\n signal csru_int_data : STD_LOGIC_VECTOR(XLENM1 downto 0);\n signal csru_int_ack : STD_LOGIC := '0';\n\n signal csru_dataIn : STD_LOGIC_VECTOR(XLENM1 downto 0);\n signal csru_dataOut : STD_LOGIC_VECTOR(XLENM1 downto 0);\n\n signal csru_csrOp : STD_LOGIC_VECTOR (4 downto 0);\n signal csru_csrAddr : STD_LOGIC_VECTOR (11 downto 0);\n\n signal csru_instRetTick : STD_LOGIC;\n\n -- Some CSRs are needed in various places easily, so they are distributed\n signal csr_status : STD_LOGIC_VECTOR(XLENM1 downto 0);\n signal csr_tvec : STD_LOGIC_VECTOR(XLENM1 downto 0);\n signal csr_cause : STD_LOGIC_VECTOR (XLENM1 downto 0);\n signal csr_ie : STD_LOGIC_VECTOR (XLENM1 downto 0);\n signal csr_epc : STD_LOGIC_VECTOR (XLENM1 downto 0);\n signal core_clock : STD_LOGIC := '0';\n\n signal lint_reset : STD_LOGIC := '0';\n\n signal misalign_hint : STD_LOGIC := '0'; -- a signal that is early for use by the control unit to stop the next fetch\n signal misalign_branch_hint : STD_LOGIC := '0'; -- a signal that is early for use by the control unit to stop the next fetch\n signal misalign_mem_hint : STD_LOGIC := '0'; -- a signal that is early for use by the control unit \n\n signal misalign_int : STD_LOGIC := '0';\n signal misalign_int_data : STD_LOGIC_VECTOR(XLENM1 downto 0) := (others => '0');\n signal misalign_int_ack : STD_LOGIC := '0';\n signal lint_int : STD_LOGIC;\n signal lint_int_data : STD_LOGIC_VECTOR(XLENM1 downto 0);\n\n signal lint_enable_mask : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');\n\n signal external_int_ack : STD_LOGIC := '0';\n\n signal dbg_data_line : STD_LOGIC_VECTOR(XLENM1 downto 0);\n\n signal is_illegal : std_logic := '0';\n\n signal should_halt : STD_LOGIC := '0';\nbegin\n\n should_halt <= I_halt;\n O_halted <= should_halt;\n core_clock <= I_clk;\n\n memctl : mem_controller port map(\n I_clk => I_clk,\n I_reset => I_reset,\n\n O_ready => memctl_ready,\n I_execute => memctl_execute,\n I_dataWe => memctl_dataWe,\n I_address => memctl_address,\n I_data => memctl_in_data,\n I_dataByteEn => memctl_dataByteEn,\n I_signExtend => memctl_signExtend,\n O_data => memctl_out_data,\n O_dataReady => memctl_dataReady,\n\n MEM_I_ready => MEM_I_ready,\n MEM_O_cmd => MEM_O_cmd,\n MEM_O_we => MEM_O_we,\n MEM_O_byteEnable => MEM_O_byteEnable,\n MEM_O_addr => MEM_O_addr,\n MEM_O_data => MEM_O_data,\n MEM_I_data => MEM_I_data,\n MEM_I_dataReady => MEM_I_dataReady\n );\n\n pcunit : pc_unit port map(\n I_clk => core_clock,\n I_nPC => in_pc,\n I_nPCop => pcop,\n I_intVec => PCintVec,\n O_PC => PC\n );\n\n control : control_unit port map(\n I_clk => core_clock,\n I_reset => I_reset,\n I_halt => should_halt,\n I_aluop => aluop,\n\n I_int => lint_int,\n O_int_ack => lint_reset,\n I_int_enabled => int_enabled,\n I_int_mem_data => lint_int_data,\n O_idata => int_idata,\n O_set_idata => int_set_idata,\n O_set_ipc => PCintVec,\n O_set_irpc => int_set_irpc,\n O_instTick => csru_instRetTick,\n I_misalignment => misalign_hint,\n I_ready => memctl_ready,\n O_execute => memctl_execute,\n I_dataReady => memctl_dataReady,\n I_aluWait => alu_wait,\n I_aluMultiCy => alutobemulticycle,\n O_state => state\n\n );\n\n decoder : decoder_RV32 port map(\n I_clk => core_clock,\n I_en => en_decode,\n I_dataInst => instruction,\n O_selRS1 => selRS1,\n O_selRS2 => selRS2,\n O_selD => selD,\n O_dataIMM => dataIMM,\n O_regDwe => dataDwe,\n O_aluOp => aluOp,\n O_aluFunc => aluFunc,\n O_memOp => memOp,\n O_csrOp => csru_csrOp,\n O_csrAddr => csru_csrAddr,\n O_trapExit => decoder_trap_exit,\n O_multycyAlu => alutobemulticycle,\n -- This unit can raise exceptions\n O_int => decoder_int,\n O_int_data => decoder_int_data,\n I_int_ack => decoder_int_ack\n );\n\n alu : alu_RV32I port map(\n I_clk => core_clock,\n I_en => en_alu,\n I_dataA => dataA,\n I_dataB => dataB,\n I_dataDwe => dataDwe,\n I_aluop => aluop(6 downto 2),\n I_aluFunc => aluFunc,\n I_PC => PC,\n I_epc => csr_epc,\n I_dataIMM => dataIMM,\n I_clear => misalign_int,\n O_dataResult => dataResult,\n O_branchTarget => branchTarget,\n O_dataWriteReg => dataWriteReg,\n O_lastPC => lastPC_alu,\n O_shouldBranch => shouldBranch,\n O_wait => alu_wait\n );\n\n reg : register_set port map(\n I_clk => core_clock,\n I_en => reg_en,\n I_dataD => registerWriteData,\n O_dataA => dataA,\n O_dataB => dataB,\n I_selRS1 => selRS1,\n I_selRS2 => selRS2,\n I_selD => selD,\n I_we => reg_we\n );\n\n csru : csr_unit port map(\n\n I_clk => core_clock,\n I_en => en_csru,\n\n I_dataIn => csru_dataIn,\n O_dataOut => csru_dataOut,\n\n I_csrOp => csru_csrOp,\n I_csrAddr => csru_csrAddr,\n\n -- This unit can raise exceptions\n O_int => csru_int,\n O_int_data => csru_int_data,\n --I_int_ack => csru_int_ack,\n\n I_instRetTick => csru_instRetTick,\n\n I_int_cause => lint_int_data,\n I_int_pc => PC_at_int,\n I_int_mtval => mtval,\n\n I_int_entry => I_int_entry,\n I_int_exit => I_int_exit,\n\n O_csr_status => csr_status,\n O_csr_tvec => csr_tvec,\n O_csr_cause => csr_cause,\n O_csr_ie => csr_ie,\n O_csr_epc => csr_epc\n );\n\n lint : lint_unit port map(\n I_clk => core_clock,\n I_reset => lint_reset,\n I_nextPc => nextPC_stall,\n\n I_enMask => lint_enable_mask,\n I_pc => lastPC_dec,\n\n I_int0 => decoder_int,\n I_int_data0 => decoder_int_data,\n O_int0_ack => decoder_int_ack,\n\n I_int1 => csru_int,\n I_int_data1 => csru_int_data,\n O_int1_ack => csru_int_ack,\n\n I_int2 => I_int,\n I_int_data2 => I_int_data,\n O_int2_ack => external_int_ack,\n I_int3 => misalign_int, -- this should be used for misaligned jump and misaligned memory op\n I_int_data3 => misalign_int_data,\n O_int3_ack => misalign_int_ack,\n\n O_int => lint_int,\n O_int_data => lint_int_data--,\n -- O_int_epc => PC_at_int\n );\n\n O_int_ack <= external_int_ack;\n\n\n state_latcher : process (core_clock)\n begin\n if rising_edge(core_clock) then\n if en_decode = '1' then\n lastPC_dec <= PC;\n end if;\n if state(6) = '1' then\n nextPC_stall <= PC;\n end if;\n if state(0) = '1' then\n instruction <= memctl_out_data;\n end if;\n end if;\n end process;\n\n -- Register file controls\n reg_en <= en_decode or en_regwrite;\n reg_we <= dataWriteReg and en_regwrite;-- and not misalign_mem_hint;\n\n -- These are the pipeline stage enable bits\n en_fetch <= state(0);\n en_decode <= state(1);\n en_alu <= state(3);\n en_csru <= state(3) when (aluop(6 downto 2) = OPCODE_SYSTEM and aluFunc(2 downto 0) /= \"000\") else '0';\n en_memory <= state(4);\n en_regwrite <= state(5);\n en_stall <= state(6);\n\n -- This decides what the next PC should be\n pcop <= PCU_OP_RESET when I_reset = '1' else\n PCU_OP_ASSIGN when shouldBranch = '1' and state(5) = '1' else\n PCU_OP_INC when shouldBranch = '0' and state(5) = '1' else\n PCU_OP_ASSIGN when PCintvec = '1' else\n PCU_OP_NOP;\n\n -- this is lint interrupt enable for consuming the interrupt\t\t\n -- misalignment/external/crsu/decoder\n -- Only accept external on ALU stage to prevent issues with externals taking decode int's in fetch cycles\n -- externals are also programmable via csr register bit\n lint_enable_mask <= '1' & (csr_status(3)and state(3)) & '1' & '1';\n -- interrupts are controlled by mstatus.mie - this is proper control unit acceptance\n int_enabled <= '1' when (lint_int_data(31) = '0' and lint_int = '1') else csr_status(3);\n\n PC_at_int <= branchTarget when (shouldBranch = '1' and lint_int_data(31) = '1' and state(6) = '1' and lint_int = '1') else PC when (lint_int_data(31) = '1' and lint_int = '1') else lastPC_dec;\n\n -- This tries to find misaligned access issues and forward data to the LINT\n -- theres a hacky thing here in that we ignore misaligned memory ops if the\n -- address has first 4 bits set; as this is the mmio space, and I've got some\n -- misaligned legacy devices/code in various places\n -- additionally, misaligned traps can't handle the latency that the LINT incurs whilst\n -- dealing with priorities, so we have hint signals to insert dummy \"int stalls\" into the pipeline.\n misalign_branch_hint <= lint_enable_mask(3) when (I_reset = '0' and misalign_int = '0' and en_regwrite = '1' and shouldBranch = '1' and branchTarget(1 downto 0) /= \"00\") else '0';\n misalign_mem_hint <= lint_enable_mask(3) when (I_reset = '0' and en_memory = '1' and memctl_address(31 downto 28) /= X\"F\" and ((memctl_dataByteEn = F2_MEM_LS_SIZE_H and memctl_address(0) = '1') or (memctl_dataByteEn = F2_MEM_LS_SIZE_W and memctl_address(1 downto 0) /= \"00\"))) else '0';\n misalign_hint <= misalign_branch_hint or misalign_mem_hint;\n\n misalign_int_finder : process (core_clock)\n begin\n if rising_edge(core_clock) then\n if I_reset = '0' and misalign_int = '0' and en_regwrite = '1' and shouldBranch = '1' and branchTarget(1 downto 0) /= \"00\" then\n -- jump misalign\n misalign_int <= lint_enable_mask(3);\n misalign_int_data <= EXCEPTION_INSTRUCTION_ADDR_MISALIGNED;\n mtval <= branchTarget;\n\n elsif I_reset = '0' and misalign_int = '0' and en_memory = '1' and memctl_dataByteEn = F2_MEM_LS_SIZE_H and memctl_address(0) = '1' and memctl_address(31 downto 28) /= X\"F\" then -- dont misalign trap on MMIO (Fxxxxxx addr)\n -- half load misalign\n misalign_int <= lint_enable_mask(3);\n if memctl_dataWe = '0' then\n misalign_int_data <= EXCEPTION_LOAD_ADDRESS_MISALIGNED;\n else\n misalign_int_data <= EXCEPTION_STORE_AMO_ADDRESS_MISALIGNED;\n end if;\n mtval <= memctl_address;\n \n elsif I_reset = '0' and misalign_int = '0' and en_memory = '1' and memctl_dataByteEn = F2_MEM_LS_SIZE_W and memctl_address(1 downto 0) /= \"00\" and memctl_address(31 downto 28) /= X\"F\" then -- dont misalign trap on MMIO (Fxxxxxx addr)\n -- word load misalign\n misalign_int <= lint_enable_mask(3);\n if memctl_dataWe = '0' then\n misalign_int_data <= EXCEPTION_LOAD_ADDRESS_MISALIGNED;\n else\n misalign_int_data <= EXCEPTION_STORE_AMO_ADDRESS_MISALIGNED;\n end if;\n mtval <= memctl_address;\n\n elsif misalign_int = '1' and misalign_int_ack = '1' then\n misalign_int <= '0';\n end if;\n end if;\n end process;\n \n -- On Interrupt service entry, CSRs need some maintenance.\n -- We need to strobe the CSR unit on this event.\n I_int_entry <= PCintvec;\n -- To detect exit, we strobe using the ALU enable with the decoder trap request bit\n I_int_exit <= decoder_trap_exit and en_alu;\n\n -- The input PC is just always the branch target output from ALU\n -- todo: tvec needs modified for vectored exceptions\n in_pc <= csr_tvec when PCintvec = '1' else branchTarget;\n\n -- input data from the register file, or use immediate if the OP specifies it\n csru_dataIn <= dataIMM when csru_csrOp(CSR_OP_BITS_IMM) = '1' else dataA;\n\n --dbg_data_line can be used to aid debugging cpu issues using trace dumps.\n --dbg_data_line <= csr_tvec when memctl_execute = '1' else csru_dataIn when en_csru = '1' else registerWriteData when state(5) = '1' else X\"000000\" & \"000\" & selD when state(3) = '1' else instruction when state(1)='1' else memctl_address;\n --dbg_data_line <= memctl_address when memctl_execute = '1' else MEM_I_data;\n dbg_data_line <= X\"ABCDEF01\" when (decoder_int_data = EXCEPTION_INSTRUCTION_ILLEGAL and X\"00000010\" = csr_epc) else csru_dataIn when en_csru = '1' else registerWriteData when state(5) = '1' else X\"000000\" & \"000\" & selD when state(3) = '1' else instruction when state(1) = '1' else memctl_address;\n --dbg_data_line <= PC_at_int;--registerWriteData when state(5) = '1' else X\"000000\" & \"000\" & selD when state(3) = '1' else instruction when state(1)='1' else csr_epc when ( lint_reset = '1') else memctl_address;\n\n is_illegal <= '1' when decoder_int_data = EXCEPTION_INSTRUCTION_ILLEGAL else '0';\n\n -- The debug output just allows some internal state to be visible outside the core black box\n -- byte 1 - memctrl&dataready\n -- byte 2 - dataWriteReg, int_en, lint_reset, lint_int, interrupt_type_ decoder and csru_int\n -- byte 3 - aluop\n -- byte 4 - state\n -- uint32 - data\n O_DBG <= \"0000\" & \"0\" & memctl_execute & memctl_ready & memctl_dataReady & --alutobemulticycle & alu_wait & --\n -- dataWriteReg & int_enabled & lint_reset & lint_int & lint_int_data(31) & PCintvec & decoder_int & decoder_int_ack &--&csru_int & --I_int & -- \n dataWriteReg & int_enabled & lint_reset & lint_int & I_int & external_int_ack & decoder_int & decoder_int_ack & --&csru_int & --I_int & -- \n is_illegal & \"00\" & aluop(6 downto 2) &\n \"0\" & state &\n dbg_data_line;\n\n -- Below statements are for memory interface use.\n memctl_address <= dataResult when en_memory = '1' else PC;\n ram_req_size <= memMode when en_memory = '1' else '0';\n memctl_dataByteEn <= memctl_size when en_memory = '1' else F2_MEM_LS_SIZE_W;\n memctl_in_data <= dataB;\n memctl_dataWe <= '1' when en_memory = '1' and memOp(4 downto 3) = \"11\" else '0';\n memctl_size <= memOp(1 downto 0);\n memctl_signExtend <= not memOp(2);\n\n -- This chooses to write registers with memory data or ALU/csr data\n registerWriteData <= memctl_out_data when memOp(4 downto 3) = \"10\" else dataB when (aluop(6 downto 2) = OPCODE_STORE) else csru_dataOut when (aluop(6 downto 2) = OPCODE_SYSTEM and aluFunc(2 downto 0) /= \"000\") else dataResult;\nend Behavioral;", "groundtruth": " I_int_data : in STD_LOGIC_VECTOR(31 downto 0);\n I_int : in STD_LOGIC;\n O_int_ack : out STD_LOGIC;\n\n -- memory interface\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/csr_unit.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RISC-V CPU\n-- Description: CSR unit RV32I\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\nuse IEEE.NUMERIC_STD.all;\n\nlibrary work;\nuse work.constants.all;\n\nentity csr_unit is\n port (\n I_clk : in STD_LOGIC;\n I_en : in STD_LOGIC;\n I_dataIn : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_dataOut : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_csrOp : in STD_LOGIC_VECTOR (4 downto 0);\n I_csrAddr : in STD_LOGIC_VECTOR (11 downto 0);\n O_int : out STD_LOGIC;\n O_int_data : out STD_LOGIC_VECTOR (31 downto 0);\n I_instRetTick : in STD_LOGIC;\n\n -- interrupt handling causes many data dependencies\n -- mcause has a fast path in from other units\n I_int_cause : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_int_pc : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_int_mtval : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n -- We need to know when an interrupt occurs as to perform the\n -- relevant csr modifications. Same with exit.\n I_int_entry : in STD_LOGIC;\n I_int_exit : in STD_LOGIC;\n\n -- Currently just feeds machine level CSR values\n O_csr_status : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_cause : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_ie : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_tvec : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_csr_epc : out STD_LOGIC_VECTOR (XLENM1 downto 0)\n );\nend csr_unit;\n\narchitecture Behavioral of csr_unit is\n\n constant CSR_ADDR_USTATUS : STD_LOGIC_VECTOR (11 downto 0) := X\"000\";\n constant CSR_ADDR_UIE : STD_LOGIC_VECTOR (11 downto 0) := X\"004\";\n constant CSR_ADDR_UTVEC : STD_LOGIC_VECTOR (11 downto 0) := X\"005\";\n\n constant CSR_ADDR_USCRATCH : STD_LOGIC_VECTOR (11 downto 0) := X\"040\";\n constant CSR_ADDR_UEPC : STD_LOGIC_VECTOR (11 downto 0) := X\"041\";\n constant CSR_ADDR_UCAUSE : STD_LOGIC_VECTOR (11 downto 0) := X\"042\";\n constant CSR_ADDR_UTVAL : STD_LOGIC_VECTOR (11 downto 0) := X\"043\";\n constant CSR_ADDR_UIP : STD_LOGIC_VECTOR (11 downto 0) := X\"044\";\n\n constant CSR_ADDR_CYCLE : STD_LOGIC_VECTOR (11 downto 0) := X\"C00\";\n constant CSR_ADDR_TIME : STD_LOGIC_VECTOR (11 downto 0) := X\"C01\";\n constant CSR_ADDR_INSTRET : STD_LOGIC_VECTOR (11 downto 0) := X\"C02\";\n\n constant CSR_ADDR_CYCLEH : STD_LOGIC_VECTOR (11 downto 0) := X\"C80\";\n constant CSR_ADDR_TIMEH : STD_LOGIC_VECTOR (11 downto 0) := X\"C81\";\n constant CSR_ADDR_INSTRETH : STD_LOGIC_VECTOR (11 downto 0) := X\"C82\";\n constant CSR_ADDR_TEST_400 : STD_LOGIC_VECTOR (11 downto 0) := X\"400\";\n constant CSR_ADDR_TEST_401 : STD_LOGIC_VECTOR (11 downto 0) := X\"401\";\n\n constant CSR_ADDR_MSTATUS : STD_LOGIC_VECTOR (11 downto 0) := X\"300\";\n constant CSR_ADDR_MISA : STD_LOGIC_VECTOR (11 downto 0) := X\"301\";\n constant CSR_ADDR_MEDELEG : STD_LOGIC_VECTOR (11 downto 0) := X\"302\";\n constant CSR_ADDR_MIDELEG : STD_LOGIC_VECTOR (11 downto 0) := X\"303\";\n constant CSR_ADDR_MIE : STD_LOGIC_VECTOR (11 downto 0) := X\"304\";\n constant CSR_ADDR_MTVEC : STD_LOGIC_VECTOR (11 downto 0) := X\"305\";\n constant CSR_ADDR_MCOUNTEREN : STD_LOGIC_VECTOR (11 downto 0) := X\"306\";\n\n constant CSR_ADDR_MSCRATCH : STD_LOGIC_VECTOR (11 downto 0) := X\"340\";\n constant CSR_ADDR_MEPC : STD_LOGIC_VECTOR (11 downto 0) := X\"341\";\n constant CSR_ADDR_MCAUSE : STD_LOGIC_VECTOR (11 downto 0) := X\"342\";\n constant CSR_ADDR_MTVAL : STD_LOGIC_VECTOR (11 downto 0) := X\"343\";\n constant CSR_ADDR_MIP : STD_LOGIC_VECTOR (11 downto 0) := X\"344\";\n\n constant CSR_ADDR_MCYCLE : STD_LOGIC_VECTOR (11 downto 0) := X\"B00\";\n constant CSR_ADDR_MINSTRET : STD_LOGIC_VECTOR (11 downto 0) := X\"B02\";\n\n constant CSR_ADDR_MCYCLEH : STD_LOGIC_VECTOR (11 downto 0) := X\"B80\";\n constant CSR_ADDR_MINSTRETH : STD_LOGIC_VECTOR (11 downto 0) := X\"B82\";\n\n constant CSR_ADDR_MVENDORID : STD_LOGIC_VECTOR (11 downto 0) := X\"F11\";\n constant CSR_ADDR_MARCHID : STD_LOGIC_VECTOR (11 downto 0) := X\"F12\";\n constant CSR_ADDR_MIMPID : STD_LOGIC_VECTOR (11 downto 0) := X\"F13\";\n constant CSR_ADDR_MHARDID : STD_LOGIC_VECTOR (11 downto 0) := X\"F14\";\n signal csr_cycles : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');\n signal csr_instret : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');\n\n signal csr_mstatus : STD_LOGIC_VECTOR (XLENM1 downto 0) := X\"00000000\";\n signal csr_mie : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n signal csr_mtvec : STD_LOGIC_VECTOR (XLENM1 downto 0) := X\"00000004\";\n signal csr_mscratch : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n signal csr_mepc : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n signal csr_mcause : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n signal csr_mtval : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n signal csr_mip : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n\n signal csr_vexrisc_irq_mask : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n signal csr_vexrisc_irq_pending : STD_LOGIC_VECTOR (XLENM1 downto 0) := (others => '0');\n\n signal curr_csr_value : STD_LOGIC_VECTOR(XLENM1 downto 0) := (others => '0');\n signal next_csr_value : STD_LOGIC_VECTOR(XLENM1 downto 0) := (others => '0');\n\n signal test0_CSR : STD_LOGIC_VECTOR(XLENM1 downto 0) := X\"FEFbbEF0\";\n signal test1_CSR : STD_LOGIC_VECTOR(XLENM1 downto 0) := X\"FEFbbEF1\";\n\n signal csr_op : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');\n signal opState : integer := 0;\n\n signal raise_int : std_logic := '0';\n\n constant STEP_READ_OR_IDLE : integer := 0;\n constant STEP_MODIFY : integer := 1;\n constant STEP_WRITE : integer := 2;\nbegin\n\n O_int <= raise_int;\n O_int_data <= X\"00000000\";\n O_csr_status <= csr_mstatus;\n O_csr_tvec <= csr_mtvec;\n O_csr_cause <= csr_mcause;\n O_csr_ie <= csr_mie;\n O_csr_epc <= csr_mepc;\n\n O_dataOut <= curr_csr_value;\n\n cycles : process (I_clk)\n begin\n if rising_edge(I_clk) then\n csr_cycles <= std_logic_vector(unsigned(csr_cycles) + 1);\n end if;\n end process;\n\n instret : process (I_clk)\n begin\n if rising_edge(I_clk) and I_instRetTick = '1' then\n", "right_context": "\n protection : process (I_clk, I_en)\n begin\n if rising_edge(I_clk) then\n if (I_csrAddr(CSR_ADDR_ACCESS_BIT_START downto CSR_ADDR_ACCESS_BIT_END) = CSR_ADDR_ACCESS_READONLY) and\n (I_csrOp(CSR_OP_BITS_WRITTEN) = '1') then\n --todo: raise exception\n raise_int <= '1';\n else\n raise_int <= '0';\n end if;\n end if;\n end process;\n\n -- Read data is available next cycle, with an additional cycle before another op can be processed\n -- Write to CSR occurs 3 cycles later.\n -- cycle 1: read of existing csr available\n -- cycle 2: update value calculates (whole write, set/clear bit read-modify-write)\n -- cycle 3: actual write to csr occurs.\n datamain : process (I_clk, I_en)\n begin\n if rising_edge(I_clk) then\n\n if I_int_entry = '1' then\n -- on entry:\n -- mstatus.mpie = mstatus.mie\n csr_mstatus(7) <= csr_mstatus(3);\n -- mstatus.mie = 0\n csr_mstatus(3) <= '0';\n -- mstatus.mpp = current privilege mode \n csr_mstatus(12 downto 11) <= \"11\";\n\n csr_mcause <= I_int_cause;\n csr_mepc <= I_int_pc;\n csr_mtval <= I_int_mtval;\n \n elsif I_int_exit = '1' then\n -- privilege set to mstatus.mpp\n -- mstatus.mie = mstatus.mpie\n csr_mstatus(3) <= csr_mstatus(7);\n csr_mstatus(7) <= '1';\n csr_mstatus(12 downto 11) <= \"00\";\n\n -- interrupt data changes take all priority\n \n elsif I_en = '1' and opState = STEP_READ_OR_IDLE then\n csr_op <= I_csrOp;\n case I_csrAddr is\n when CSR_ADDR_MVENDORID =>\n curr_csr_value <= X\"00000000\"; -- JEDEC non-commercial\n when CSR_ADDR_MARCHID =>\n curr_csr_value <= X\"00000000\";\n when CSR_ADDR_MIMPID =>\n curr_csr_value <= X\"52505531\"; -- \"RPU1\"\n when CSR_ADDR_MHARDID =>\n curr_csr_value <= X\"00000000\";\n when CSR_ADDR_MISA =>\n curr_csr_value <= X\"40001100\"; -- XLEN 32, RV32IM\n\n when CSR_ADDR_MSTATUS =>\n curr_csr_value <= csr_mstatus;\n when CSR_ADDR_MTVEC =>\n curr_csr_value <= csr_mtvec;\n when CSR_ADDR_MIE =>\n curr_csr_value <= csr_mie;\n when CSR_ADDR_MIP =>\n curr_csr_value <= csr_mip;\n when CSR_ADDR_MCAUSE =>\n curr_csr_value <= csr_mcause;\n when CSR_ADDR_MEPC =>\n curr_csr_value <= csr_mepc;\n when CSR_ADDR_MTVAL =>\n curr_csr_value <= csr_mtval;\n when CSR_ADDR_MSCRATCH =>\n curr_csr_value <= csr_mscratch;\n\n when CSR_ADDR_CYCLE =>\n curr_csr_value <= csr_cycles(31 downto 0);\n when CSR_ADDR_CYCLEH =>\n curr_csr_value <= csr_cycles(63 downto 32);\n\n when CSR_ADDR_INSTRET =>\n curr_csr_value <= csr_instret(31 downto 0);\n when CSR_ADDR_INSTRETH =>\n curr_csr_value <= csr_instret(63 downto 32);\n\n when CSR_ADDR_MCYCLE =>\n curr_csr_value <= csr_cycles(31 downto 0);\n when CSR_ADDR_MCYCLEH =>\n curr_csr_value <= csr_cycles(63 downto 32);\n\n when CSR_ADDR_MINSTRET =>\n curr_csr_value <= csr_instret(31 downto 0);\n when CSR_ADDR_MINSTRETH =>\n curr_csr_value <= csr_instret(63 downto 32);\n\n when others =>\n -- raise exception for unsupported CSR\n end case;\n opState <= STEP_MODIFY;\n\n elsif opState = STEP_MODIFY then\n -- update stage for sets, clears and writes\n case csr_op(3 downto 2) is\n when CSR_MAINOP_WR =>\n next_csr_value <= I_dataIn;\n when CSR_MAINOP_SET =>\n next_csr_value <= curr_csr_value or I_dataIn;\n when CSR_MAINOP_CLEAR =>\n next_csr_value <= curr_csr_value and (not I_dataIn);\n when others =>\n end case;\n\n if I_csrOp(CSR_OP_BITS_WRITTEN) = '1' then\n opState <= STEP_WRITE;\n else\n opState <= STEP_READ_OR_IDLE;\n end if;\n\n elsif opState = STEP_WRITE then\n -- write stage\n opState <= STEP_READ_OR_IDLE;\n case I_csrAddr is\n\n when CSR_ADDR_MSTATUS =>\n csr_mstatus <= next_csr_value;\n when CSR_ADDR_MTVEC =>\n csr_mtvec <= next_csr_value;\n when CSR_ADDR_MIE =>\n csr_mie <= next_csr_value;\n when CSR_ADDR_MIP =>\n csr_mip <= next_csr_value;\n when CSR_ADDR_MEPC =>\n csr_mepc <= next_csr_value;\n when CSR_ADDR_MSCRATCH =>\n csr_mscratch <= next_csr_value;\n when others =>\n end case;\n end if;\n end if;\n\n end process;\n\nend Behavioral;", "groundtruth": " csr_instret <= std_logic_vector(unsigned(csr_instret) + 1);\n end if;\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/lint_unit.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RISC-V CPU\n-- Description: Local Interrupt unit\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\nuse IEEE.NUMERIC_STD.all;\n\nlibrary work;\nuse work.constants.all;\n\nentity lint_unit is\n port (\n I_clk : in STD_LOGIC;\n I_reset : in STD_LOGIC;\n I_nextPc : in STD_LOGIC_VECTOR (31 downto 0);\n I_pc : in STD_LOGIC_VECTOR (31 downto 0);\n I_enMask : in STD_LOGIC_VECTOR (3 downto 0);\n I_int0 : in STD_LOGIC;\n I_int_data0 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int0_ack : out STD_LOGIC;\n I_int1 : in STD_LOGIC;\n I_int_data1 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int1_ack : out STD_LOGIC;\n I_int2 : in STD_LOGIC;\n I_int_data2 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int2_ack : out STD_LOGIC;\n I_int3 : in STD_LOGIC;\n I_int_data3 : in STD_LOGIC_VECTOR (31 downto 0);\n O_int3_ack : out STD_LOGIC;\n O_int : out STD_LOGIC;\n O_int_data : out STD_LOGIC_VECTOR (31 downto 0);\n O_int_epc : out STD_LOGIC_VECTOR (31 downto 0)\n );\nend lint_unit;\n\narchitecture Behavioral of lint_unit is\n\n signal actual_int : std_logic := '0';\n signal actual_int_data : std_logic_vector (31 downto 0) := X\"00000000\";\n signal actual_int_epc : std_logic_vector (31 downto 0) := X\"00000000\";\n\n signal int0_ack : std_logic := '0';\n signal int1_ack : std_logic := '0';\n signal int2_ack : std_logic := '0';\n signal int3_ack : std_logic := '0';\n\n signal reset_counter : integer := 0;\n\nbegin\n\n O_int <= actual_int;\n O_int_data <= actual_int_data;\n O_int_epc <= actual_int_epc;\n\n O_int0_ack <= int0_ack;\n O_int1_ack <= int1_ack;\n O_int2_ack <= int2_ack;\n O_int3_ack <= int3_ack;\n\n -- This simply filters one of the 4 int sources to a single one in\n -- decreasing priority, latching the data until a reset.\n arb : process (I_clk)\n begin\n if rising_edge(I_clk) then\n if I_reset = '1' then\n reset_counter <= 1;\n int0_ack <= '0';\n int1_ack <= '0';\n int2_ack <= '0';\n int3_ack <= '0';\n elsif reset_counter = 1 then\n reset_counter <= 2;\n elsif reset_counter = 2 then\n reset_counter <= 3;\n elsif reset_counter = 3 then\n actual_int <= '0';\n reset_counter <= 0;\n elsif reset_counter = 0 and actual_int = '0' then\n\n if I_enMask(0) = '1' and I_int0 = '1' and int0_ack = '0' then\n actual_int <= '1';\n actual_int_data <= I_int_data0;\n int0_ack <= '1';\n elsif I_enMask(1) = '1' and I_int1 = '1' and int1_ack = '0'then\n", "right_context": " actual_int_data <= I_int_data3;\n int3_ack <= '1';\n end if;\n end if;\n end if;\n end process;\nend Behavioral;", "groundtruth": " actual_int <= '1';\n actual_int_data <= I_int_data1;\n int1_ack <= '1';\n elsif I_enMask(2) = '1' and I_int2 = '1' and int2_ack = '0' then\n actual_int <= '1';\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/mem_controller.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RPU\n-- Description: Memory controller unit of RPU\n--\n-- Very simple. Allows for delays in reads, whilsts writes go through immediately.\n-- MEM_ signals are expected to be exposted to any SoC fabric.\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2016,2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\n\nuse ieee.numeric_std.all;\n\nlibrary work;\nuse work.constants.all;\nentity mem_controller is\n port (\n I_clk : in STD_LOGIC;\n I_reset : in STD_LOGIC;\n\n O_ready : out STD_LOGIC;\n I_execute : in STD_LOGIC;\n I_dataWe : in STD_LOGIC;\n I_address : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_data : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_dataByteEn : in STD_LOGIC_VECTOR(1 downto 0);\n I_signExtend : in STD_LOGIC;\n O_data : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n O_dataReady : out STD_LOGIC;\n\n MEM_I_ready : in STD_LOGIC;\n MEM_O_cmd : out STD_LOGIC;\n MEM_O_we : out STD_LOGIC;\n MEM_O_byteEnable : out STD_LOGIC_VECTOR (1 downto 0);\n MEM_O_addr : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n MEM_O_data : out STD_LOGIC_VECTOR (XLENM1 downto 0);\n MEM_I_data : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n MEM_I_dataReady : in STD_LOGIC\n );\nend mem_controller;\n\narchitecture Behavioral of mem_controller is\n\n signal we : std_logic := '0';\n signal addr : STD_LOGIC_VECTOR (XLENM1 downto 0) := X\"00000000\";\n signal indata : STD_LOGIC_VECTOR (XLENM1 downto 0) := X\"00000000\";\n signal outdata : STD_LOGIC_VECTOR (XLENM1 downto 0) := X\"00000000\";\n\n signal byteEnable : STD_LOGIC_VECTOR (1 downto 0) := \"11\";\n signal cmd : STD_LOGIC := '0';\n signal state : integer := 0;\n\n signal ready : STD_LOGIC := '0';\n\nbegin\n\n process (I_clk, I_execute)\n begin\n if rising_edge(I_clk) then\n if I_reset = '1' then\n we <= '0';\n cmd <= '0';\n state <= 0;\n O_dataReady <= '0';\n elsif state = 0 and I_execute = '1' and MEM_I_ready = '1' then\n we <= I_dataWe;\n addr <= I_address;\n indata <= I_data;\n byteEnable <= I_dataByteEn;\n cmd <= '1';\n O_dataReady <= '0';\n outdata <= X\"ABCDEFEE\";\n if I_dataWe = '0' then\n state <= 1;-- read\n else\n state <= 2;-- write\n end if;\n elsif state = 1 then\n cmd <= '0';\n if MEM_I_dataReady = '1' then\n O_dataReady <= '1';\n -- sign extend, if required\n if I_signExtend = '1' then\n if I_dataByteEn = F2_MEM_LS_SIZE_W then\n outdata <= MEM_I_data;\n elsif I_dataByteEn = F2_MEM_LS_SIZE_H then\n outdata <= std_logic_vector(resize(signed(MEM_I_data(15 downto 0)), XLEN));\n elsif I_dataByteEn = F2_MEM_LS_SIZE_B then\n outdata <= std_logic_vector(resize(signed(MEM_I_data(7 downto 0)), XLEN));\n end if;\n else\n outdata <= MEM_I_data;\n end if;\n state <= 2;\n", "right_context": " end process;\n\n O_data <= outdata;\n O_ready <= (MEM_I_ready and not I_execute) when state = 0 else '0';\n\n MEM_O_cmd <= cmd;\n MEM_O_byteEnable <= byteEnable;\n MEM_O_data <= indata;\n MEM_O_addr <= addr;\n MEM_O_we <= we;\n\nend Behavioral;", "groundtruth": " end if;\n elsif state = 2 then\n cmd <= '0';\n state <= 0;\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/pc_unit.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RPU\n-- Description: Program Counter unit of RPU\n--\n-- Simple black box for holding and manipulating the PC\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2016,2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nuse IEEE.NUMERIC_STD.ALL;\n\nlibrary work;\nuse work.constants.all;\n\nentity pc_unit is\n Port ( \n I_clk : in STD_LOGIC;\n I_nPC : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_nPCop : in STD_LOGIC_VECTOR (1 downto 0);\n I_intVec: in STD_LOGIC;\n O_PC : out STD_LOGIC_VECTOR (XLENM1 downto 0)\n );\nend pc_unit;\n\narchitecture Behavioral of pc_unit is\n signal current_pc: std_logic_vector( XLENM1 downto 0) := ADDR_RESET;\nbegin\n\n\tprocess (I_clk)\n", "right_context": "\t\t\t\t\tcurrent_pc <= std_logic_vector(unsigned(current_pc) + 4); -- 32bit byte addressing\n\t\t\t\twhen PCU_OP_ASSIGN => \t-- set from external input\n\t\t\t\t\tcurrent_pc <= I_nPC;\n\t\t\t\twhen PCU_OP_RESET => \t-- Reset\n\t\t\t\t\tcurrent_pc <= ADDR_RESET;\n\t\t\t\twhen others =>\n\t\t\tend case;\n\t\tend if;\n\tend process;\n\n\tO_PC <= current_pc;\n\t\nend Behavioral;\n\n", "groundtruth": "\tbegin\n\t\tif rising_edge(I_clk) then\n\t\t\tcase I_nPCop is\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/register_set.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RISC-V CPU\n-- Description: Register file unit\n--\n----------------------------------------------------------------------------------\n-- Copyright 2016 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\nlibrary work;\nuse work.constants.all;\n\nentity register_set is\n Port ( \n I_clk : in STD_LOGIC;\n I_en : in STD_LOGIC;\n I_dataD : in STD_LOGIC_VECTOR (XLENM1 downto 0); -- Data to write to regD\n I_selRS1 : in STD_LOGIC_VECTOR (4 downto 0); -- Select line for regRS1\n I_selRS2 : in STD_LOGIC_VECTOR (4 downto 0); -- Select line for regRS2\n I_selD : in STD_LOGIC_VECTOR (4 downto 0); -- Select line for regD\n I_we : in STD_LOGIC; -- Write enable for regD\n", "right_context": "end register_set;\n\narchitecture Behavioral of register_set is\n type store_t is array (0 to 31) of std_logic_vector(XLENM1 downto 0);\n signal regsA: store_t := (others => X\"00000000\");\n signal regsB: store_t := (others => X\"00000000\");\n signal dataAout: STD_LOGIC_VECTOR (XLENM1 downto 0) := (others=>'0');\n signal dataBout: STD_LOGIC_VECTOR (XLENM1 downto 0) := (others=>'0');\nbegin\n\n\tprocess(I_clk, I_en)\n\tbegin\n\t\tif rising_edge(I_clk) and I_en='1' then\n\t\t\tdataAout <= regsA(to_integer(unsigned(I_selRS1)));\n\t\t\tdataBout <= regsB(to_integer(unsigned(I_selRS2)));\n\t\t\tif (I_we = '1') then\n\t\t\t\tregsA(to_integer(unsigned(I_selD))) <= I_dataD;\n regsB(to_integer(unsigned(I_selD))) <= I_dataD;\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\t\n\tO_dataA <= dataAout when I_selRS1 /= \"00000\" else X\"00000000\";\n\tO_dataB <= dataBout when I_selRS2 /= \"00000\" else X\"00000000\";\n\nend Behavioral;\n\n", "groundtruth": " O_dataA : out STD_LOGIC_VECTOR (XLENM1 downto 0);-- regRS1 data out\n O_dataB : out STD_LOGIC_VECTOR (XLENM1 downto 0) -- regRS2 data out\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/unit_alu_RV32_I.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RISC-V CPU\n-- Description: ALU unit suitable for RV32I operational use\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2016,2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\n\nuse IEEE.NUMERIC_STD.all;\n\nlibrary work;\nuse work.constants.all;\n\nentity alu_RV32I is\n port (\n I_clk : in STD_LOGIC;\n I_en : in STD_LOGIC;\n I_dataA : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_dataB : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_dataDwe : in STD_LOGIC;\n I_aluop : in STD_LOGIC_VECTOR (4 downto 0);\n I_aluFunc : in STD_LOGIC_VECTOR (15 downto 0);\n I_PC : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_epc : in STD_LOGIC_VECTOR (XLENM1 downto 0);\n I_dataIMM : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_clear : in STD_LOGIC;\n O_dataResult : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n O_branchTarget : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n O_dataWriteReg : out STD_LOGIC;\n O_lastPC : out STD_LOGIC_VECTOR(XLEN32M1 downto 0);\n O_shouldBranch : out std_logic;\n O_wait : out std_logic\n );\nend alu_RV32I;\n\narchitecture Behavioral of alu_RV32I is\n -- The internal register for results of operations. \n -- 32 bit + carry/overflow\n signal s_aluFunc : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');\n signal s_branchTarget : STD_LOGIC_VECTOR (XLEN32M1 downto 0) := (others => '0');\n\n signal s_result : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');\n signal s_resultms : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');\n signal s_resultmu : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');\n signal s_resultmsu : STD_LOGIC_VECTOR(65 downto 0) := (others => '0'); -- result has 66 bits to accomodate mulhsu with it's additional-bit-fakery\n signal s_shouldBranch : STD_LOGIC := '0';\n signal s_lastPC : STD_LOGIC_VECTOR(XLEN32M1 downto 0) := (others => '0');\n signal s_wait : std_logic := '0';\n component alu_int32_div is\n port (\n I_clk : in STD_LOGIC;\n I_exec : in STD_LOGIC;\n I_dividend : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_divisor : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n I_op : in STD_LOGIC_VECTOR (1 downto 0);\n O_dataResult : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);\n O_done : out STD_LOGIC;\n O_int : out std_logic\n );\n end component;\n signal s_div_exec : std_logic := '0';\n signal s_div_dividend : std_logic_vector(31 downto 0) := (others => '0');\n signal s_div_divisor : std_logic_vector(31 downto 0) := (others => '0');\n signal s_div_op : std_logic_vector(1 downto 0) := (others => '0');\n signal s_div_dataResult : std_logic_vector(31 downto 0) := (others => '0');\n signal s_div_done : std_logic := '0';\n signal s_div_int : std_logic := '0';\n constant DIVUNIT_STATE_IDLE : integer := 0;\n constant DIVUNIT_STATE_INFLIGHT : integer := 1;\n constant DIVUNIT_STATE_COMPLETE : integer := 2;\n\n constant MUL_STATE_IDLE : integer := 0;\n constant MUL_STATE_COMPLETE : integer := 2;\n\n signal s_mul_state : integer := 0;\n signal s_divunit_state : integer := 0;\n\nbegin\n div_rem_unit : alu_int32_div port map(\n I_clk => I_clk,\n I_exec => s_div_exec,\n I_dividend => s_div_dividend,\n I_divisor => s_div_divisor,\n I_op => s_div_op,\n O_dataResult => s_div_dataResult,\n O_done => s_div_done,\n O_int => s_div_int\n );\n\n s_div_dividend <= I_dataA;\n s_div_divisor <= I_dataB;\n\n process (I_clk, I_en)\n begin\n if rising_edge(I_clk) then\n if I_clear = '1' and I_en = '0' then\n s_branchTarget <= X\"00000000\";\n s_result <= X\"0000000000000000\";\n\n elsif I_en = '1' then\n s_lastPC <= I_PC;\n O_dataWriteReg <= I_dataDwe;\n s_aluFunc <= I_aluFunc;\n case I_aluop is\n when OPCODE_OPIMM =>\n s_wait <= '0';\n s_shouldBranch <= '0';\n case I_aluFunc(2 downto 0) is\n when F3_OPIMM_ADDI =>\n s_result(31 downto 0) <= std_logic_vector(signed(I_dataA) + signed(I_dataIMM));\n\n when F3_OPIMM_XORI =>\n s_result(31 downto 0) <= I_dataA xor I_dataIMM;\n\n when F3_OPIMM_ORI =>\n s_result(31 downto 0) <= I_dataA or I_dataIMM;\n\n when F3_OPIMM_ANDI =>\n s_result(31 downto 0) <= I_dataA and I_dataIMM;\n\n when F3_OPIMM_SLTI =>\n if signed(I_dataA) < signed(I_dataIMM) then\n s_result(31 downto 0) <= X\"00000001\";\n else\n s_result(31 downto 0) <= X\"00000000\";\n end if;\n\n", "right_context": " if unsigned(I_dataA) < unsigned(I_dataIMM) then\n s_result(31 downto 0) <= X\"00000001\";\n else\n s_result(31 downto 0) <= X\"00000000\";\n end if;\n\n when F3_OPIMM_SLLI =>\n s_result(31 downto 0) <= std_logic_vector(shift_left(unsigned(I_dataA), to_integer(unsigned(I_dataIMM(4 downto 0)))));\n\n when F3_OPIMM_SRLI =>\n case I_aluFunc(9 downto 3) is\n when F7_OPIMM_SRLI =>\n s_result(31 downto 0) <= std_logic_vector(shift_right(unsigned(I_dataA), to_integer(unsigned(I_dataIMM(4 downto 0)))));\n when F7_OPIMM_SRAI =>\n s_result(31 downto 0) <= std_logic_vector(shift_right(signed(I_dataA), to_integer(unsigned(I_dataIMM(4 downto 0)))));\n when others =>\n end case;\n when others =>\n end case;\n\n when OPCODE_OP =>\n\n if I_aluFunc(9 downto 3) = F7_OP_M_EXT then\n\n if I_aluFunc(2) = '0' then -- mul ops\n if s_mul_state = MUL_STATE_IDLE then\n s_resultms(63 downto 0) <= std_logic_vector(signed(I_dataA) * signed(I_dataB));\n s_resultmu(63 downto 0) <= std_logic_vector(unsigned(I_dataA) * unsigned(I_dataB));\n s_resultmsu(65 downto 0) <= std_logic_vector(signed(I_dataA(31) & I_dataA) * signed('0' & I_dataB));\n\n s_wait <= '0'; -- there is _always_ a 1 cycle additional wait for a multicycle alu, so immediately flag complete\n s_mul_state <= MUL_STATE_COMPLETE;\n\n elsif s_mul_state = MUL_STATE_COMPLETE then\n\n if I_aluFunc(2 downto 0) = F3_OP_M_MUL then\n s_result(31 downto 0) <= s_resultms(31 downto 0);\n\n elsif I_aluFunc(2 downto 0) = F3_OP_M_MULH then\n s_result(31 downto 0) <= s_resultms(63 downto 32);\n\n elsif I_aluFunc(2 downto 0) = F3_OP_M_MULHU then\n s_result(31 downto 0) <= s_resultmu(63 downto 32);\n\n elsif I_aluFunc(2 downto 0) = F3_OP_M_MULHSU then\n s_result(31 downto 0) <= s_resultmsu(63 downto 32);\n end if;\n\n s_mul_state <= MUL_STATE_IDLE;\n\n end if;\n else\n -- div & rem\n if s_divunit_state = DIVUNIT_STATE_IDLE then\n s_div_exec <= '1';\n s_div_op <= I_aluFunc(1 downto 0);\n s_divunit_state <= DIVUNIT_STATE_INFLIGHT;\n\n s_wait <= '1'; -- stall the cpu until done\n elsif s_divunit_state = DIVUNIT_STATE_INFLIGHT then\n s_div_exec <= '0';\n\n if s_div_done = '1' then\n s_divunit_state <= DIVUNIT_STATE_COMPLETE;\n s_wait <= '0';\n end if;\n elsif s_divunit_state = DIVUNIT_STATE_COMPLETE then\n\n s_divunit_state <= DIVUNIT_STATE_IDLE;\n s_result(31 downto 0) <= s_div_dataResult;\n end if;\n\n end if;\n else\n s_wait <= '0';\n case I_aluFunc(9 downto 0) is\n when F7_OP_ADD & F3_OP_ADD =>\n s_result(31 downto 0) <= std_logic_vector(signed(I_dataA) + signed(I_dataB));\n\n when F7_OP_SUB & F3_OP_SUB =>\n s_result(31 downto 0) <= std_logic_vector(signed(I_dataA) - signed(I_dataB));\n\n when F7_OP_SLT & F3_OP_SLT =>\n if signed(I_dataA) < signed(I_dataB) then\n s_result(31 downto 0) <= X\"00000001\";\n else\n s_result(31 downto 0) <= X\"00000000\";\n end if;\n\n when F7_OP_SLTU & F3_OP_SLTU =>\n if unsigned(I_dataA) < unsigned(I_dataB) then\n s_result(31 downto 0) <= X\"00000001\";\n else\n s_result(31 downto 0) <= X\"00000000\";\n end if;\n\n when F7_OP_XOR & F3_OP_XOR =>\n s_result(31 downto 0) <= I_dataA xor I_dataB;\n\n when F7_OP_OR & F3_OP_OR =>\n s_result(31 downto 0) <= I_dataA or I_dataB;\n\n when F7_OP_AND & F3_OP_AND =>\n s_result(31 downto 0) <= I_dataA and I_dataB;\n\n when F7_OP_SLL & F3_OP_SLL =>\n s_result(31 downto 0) <= std_logic_vector(shift_left(unsigned(I_dataA), to_integer(unsigned(I_dataB(4 downto 0)))));\n\n when F7_OP_SRL & F3_OP_SRL =>\n s_result(31 downto 0) <= std_logic_vector(shift_right(unsigned(I_dataA), to_integer(unsigned(I_dataB(4 downto 0)))));\n\n when F7_OP_SRA & F3_OP_SRA =>\n s_result(31 downto 0) <= std_logic_vector(shift_right(signed(I_dataA), to_integer(unsigned(I_dataB(4 downto 0)))));\n\n when others =>\n s_result <= X\"00000000\" & X\"CDC1FEF1\";\n end case;\n end if;\n s_shouldBranch <= '0';\n\n when OPCODE_LOAD | OPCODE_STORE =>\n s_wait <= '0';\n s_shouldBranch <= '0';\n s_result(31 downto 0) <= std_logic_vector(signed(I_dataA) + signed(I_dataIMM));\n\n when OPCODE_JALR =>\n s_wait <= '0';\n s_branchTarget <= std_logic_vector(signed(I_dataA) + signed(I_dataIMM)) and X\"FFFFFFFE\"; -- jalr clears the lowest bit\n s_shouldBranch <= '1';\n s_result(31 downto 0) <= std_logic_vector(signed(I_PC) + 4);\n\n when OPCODE_JAL =>\n s_wait <= '0';\n s_branchTarget <= std_logic_vector(signed(I_PC) + signed(I_dataIMM));\n s_shouldBranch <= '1';\n s_result(31 downto 0) <= std_logic_vector(signed(I_PC) + 4);\n\n when OPCODE_SYSTEM =>\n s_wait <= '0';\n if I_aluFunc(9 downto 0) = F7_PRIVOP_MRET & F3_PRIVOP then\n s_branchTarget <= I_epc;\n s_shouldBranch <= '1';\n s_result(31 downto 0) <= std_logic_vector(signed(I_PC) + 4);\n elsif I_aluFunc(2 downto 0) /= F3_PRIVOP then\n -- do not branch on CSR unit work\n s_shouldBranch <= '0';\n end if;\n when OPCODE_LUI =>\n s_wait <= '0';\n s_shouldBranch <= '0';\n s_result(31 downto 0) <= I_dataIMM;\n\n when OPCODE_AUIPC =>\n s_wait <= '0';\n s_shouldBranch <= '0';\n s_result(31 downto 0) <= std_logic_vector(signed(I_PC) + signed(I_dataIMM));\n\n when OPCODE_BRANCH =>\n s_wait <= '0';\n s_branchTarget <= std_logic_vector(signed(I_PC) + signed(I_dataIMM));\n case I_aluFunc(2 downto 0) is\n when F3_BRANCH_BEQ =>\n if I_dataA = I_dataB then\n s_shouldBranch <= '1';\n else\n s_shouldBranch <= '0';\n end if;\n\n when F3_BRANCH_BNE =>\n if I_dataA /= I_dataB then\n s_shouldBranch <= '1';\n else\n s_shouldBranch <= '0';\n end if;\n\n when F3_BRANCH_BLT =>\n if signed(I_dataA) < signed(I_dataB) then\n s_shouldBranch <= '1';\n else\n s_shouldBranch <= '0';\n end if;\n\n when F3_BRANCH_BGE =>\n if signed(I_dataA) >= signed(I_dataB) then\n s_shouldBranch <= '1';\n else\n s_shouldBranch <= '0';\n end if;\n\n when F3_BRANCH_BLTU =>\n if unsigned(I_dataA) < unsigned(I_dataB) then\n s_shouldBranch <= '1';\n else\n s_shouldBranch <= '0';\n end if;\n\n when F3_BRANCH_BGEU =>\n if unsigned(I_dataA) >= unsigned(I_dataB) then\n s_shouldBranch <= '1';\n else\n s_shouldBranch <= '0';\n end if;\n\n when others =>\n end case;\n\n when others =>\n s_result <= X\"00000000\" & X\"CDCDFEFE\";\n end case;\n end if;\n end if;\n end process;\n\n O_wait <= s_wait;\n\n O_dataResult <= s_result(XLEN32M1 downto 0);\n O_shouldBranch <= s_shouldBranch;\n O_branchTarget <= s_branchTarget;\n O_lastPC <= s_lastPC;\n\nend Behavioral;", "groundtruth": " when F3_OPIMM_SLTIU =>\n", "crossfile_context": ""} {"task_id": "RPU", "path": "RPU/vhdl/unit_decoder_RV32I.vhd", "left_context": "----------------------------------------------------------------------------------\n-- Project Name: RISC-V CPU\n-- Description: decoder unit RV32I\n-- \n----------------------------------------------------------------------------------\n-- Copyright 2016,2018,2019,2020 Colin Riley\n--\n-- Licensed under the Apache License, Version 2.0 (the \"License\");\n-- you may not use this file except in compliance with the License.\n-- You may obtain a copy of the License at\n--\n-- http://www.apache.org/licenses/LICENSE-2.0\n--\n-- Unless required by applicable law or agreed to in writing, software\n-- distributed under the License is distributed on an \"AS IS\" BASIS,\n-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n-- See the License for the specific language governing permissions and\n-- limitations under the License.\n----------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\nuse IEEE.NUMERIC_STD.all;\n\nlibrary work;\nuse work.constants.all;\n\nentity decoder_RV32 is\n port (\n I_clk : in STD_LOGIC;\n I_en : in STD_LOGIC;\n I_dataInst : in STD_LOGIC_VECTOR (31 downto 0); -- Instruction to be decoded\n O_selRS1 : out STD_LOGIC_VECTOR (4 downto 0); -- Selection out for regrs1\n O_selRS2 : out STD_LOGIC_VECTOR (4 downto 0); -- Selection out for regrs2\n O_selD : out STD_LOGIC_VECTOR (4 downto 0); -- Selection out for regD\n O_dataIMM : out STD_LOGIC_VECTOR (31 downto 0); -- Immediate value out\n O_regDwe : out STD_LOGIC; -- RegD wrtite enable\n O_aluOp : out STD_LOGIC_VECTOR (6 downto 0); -- ALU opcode\n O_aluFunc : out STD_LOGIC_VECTOR (15 downto 0); -- ALU function\n", "right_context": " I_int_ack : in STD_LOGIC -- our int is now being serviced\n );\nend decoder_RV32;\n\narchitecture Behavioral of decoder_RV32 is\n signal s_trapExit : STD_LOGIC := '0';\n signal s_csrOP : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');\n signal s_csrAddr : STD_LOGIC_VECTOR(11 downto 0) := (others => '0');\n signal s_int : STD_LOGIC := '0';\n signal s_intdata : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');\n signal s_multicy : std_logic := '0';\nbegin\n O_multycyAlu <= s_multicy;\n O_int <= s_int;\n O_int_data <= s_intdata;\n O_csrOP <= s_csrOP;\n O_csrAddr <= s_csrAddr;\n O_trapExit <= s_trapExit;\n\n -- Register selects for reads are async\n O_selRS1 <= I_dataInst(R1_START downto R1_END);\n O_selRS2 <= I_dataInst(R2_START downto R2_END);\n\n process (I_clk, I_en)\n begin\n\n if rising_edge(I_clk) then\n if I_en = '1' then\n\n O_selD <= I_dataInst(RD_START downto RD_END);\n\n O_aluOp <= I_dataInst(OPCODE_START downto OPCODE_END);\n\n O_aluFunc <= \"000000\" & I_dataInst(FUNCT7_START downto FUNCT7_END)\n & I_dataInst(FUNCT3_START downto FUNCT3_END);\n\n case I_dataInst(OPCODE_START downto OPCODE_END_2) is\n when OPCODE_LUI =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '1';\n O_memOp <= \"00000\";\n O_dataIMM <= I_dataInst(IMM_U_START downto IMM_U_END)\n & \"000000000000\";\n \n when OPCODE_AUIPC =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '1';\n O_memOp <= \"00000\";\n O_dataIMM <= I_dataInst(IMM_U_START downto IMM_U_END)\n & \"000000000000\";\n \n when OPCODE_JAL =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n if I_dataInst(RD_START downto RD_END) = \"00000\" then\n O_regDwe <= '0';\n else\n O_regDwe <= '1';\n end if;\n O_memOp <= \"00000\";\n if I_dataInst(IMM_U_START) = '1' then\n O_dataIMM <= \"111111111111\" & I_dataInst(19 downto 12) & I_dataInst(20) & I_dataInst(30 downto 21) & '0';\n else\n O_dataIMM <= \"000000000000\" & I_dataInst(19 downto 12) & I_dataInst(20) & I_dataInst(30 downto 21) & '0';\n end if;\n \n when OPCODE_JALR =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n if I_dataInst(RD_START downto RD_END) = \"00000\" then\n O_regDwe <= '0';\n else\n O_regDwe <= '1';\n end if;\n O_memOp <= \"00000\";\n if I_dataInst(IMM_U_START) = '1' then\n O_dataIMM <= X\"FFFF\" & \"1111\" & I_dataInst(IMM_I_START downto IMM_I_END);\n else\n O_dataIMM <= X\"0000\" & \"0000\" & I_dataInst(IMM_I_START downto IMM_I_END);\n end if;\n \n when OPCODE_OPIMM =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '1';\n O_memOp <= \"00000\";\n if I_dataInst(IMM_U_START) = '1' then\n O_dataIMM <= X\"FFFF\" & \"1111\" & I_dataInst(IMM_I_START downto IMM_I_END);\n else\n O_dataIMM <= X\"0000\" & \"0000\" & I_dataInst(IMM_I_START downto IMM_I_END);\n end if;\n\n when OPCODE_OP =>\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n O_memOp <= \"00000\";\n\n -- M based extension ops are multicycle, otherwise they are single-cycle\n if (I_dataInst(FUNCT7_START downto FUNCT7_END) = F7_OP_M_EXT) then\n s_multicy <= '1';\n else\n s_multicy <= '0';\n end if;\n\n s_int <= '0';\n O_regDwe <= '1';\n\n when OPCODE_LOAD =>\n s_multicy <= '0';\n -- Load's opcode is all 0s - but the first two bits of the word should be '11'\n -- we check this here, because if we do not, null instructions will be treated as loads...\n if I_dataInst(1 downto 0) = \"11\" then\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '1';\n O_memOp <= \"10\" & I_dataInst(FUNCT3_START downto FUNCT3_END);\n if I_dataInst(IMM_U_START) = '1' then\n O_dataIMM <= X\"FFFF\" & \"1111\" & I_dataInst(IMM_I_START downto IMM_I_END);\n else\n O_dataIMM <= X\"0000\" & \"0000\" & I_dataInst(IMM_I_START downto IMM_I_END);\n end if;\n else\n -- likely a null instruction - fault!\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '1'; ---------------\n s_intdata <= EXCEPTION_INSTRUCTION_ILLEGAL;\n O_memOp <= \"00000\";\n O_regDwe <= '0';\n O_dataIMM <= I_dataInst(IMM_I_START downto IMM_S_B_END)\n & \"0000000\";\n end if;\n \n when OPCODE_STORE =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '0';\n O_memOp <= \"11\" & I_dataInst(FUNCT3_START downto FUNCT3_END);\n if I_dataInst(IMM_U_START) = '1' then\n O_dataIMM <= X\"FFFF\" & \"1111\" & I_dataInst(IMM_S_A_START downto IMM_S_A_END) & I_dataInst(IMM_S_B_START downto IMM_S_B_END);\n else\n O_dataIMM <= X\"0000\" & \"0000\" & I_dataInst(IMM_S_A_START downto IMM_S_A_END) & I_dataInst(IMM_S_B_START downto IMM_S_B_END);\n end if;\n \n when OPCODE_BRANCH =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '0';\n O_memOp <= \"00000\";\n if I_dataInst(IMM_U_START) = '1' then\n O_dataIMM <= X\"FFFF\" & \"1111\" & I_dataInst(7) & I_dataInst(30 downto 25) & I_dataInst(11 downto 8) & '0';\n else\n O_dataIMM <= X\"0000\" & \"0000\" & I_dataInst(7) & I_dataInst(30 downto 25) & I_dataInst(11 downto 8) & '0';\n end if;\n \n when OPCODE_MISCMEM =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '0';\n O_memOp <= \"01000\";\n O_dataIMM <= I_dataInst;\n \n when OPCODE_SYSTEM =>\n s_multicy <= '0';\n O_memOp <= \"00000\";\n if I_dataInst(FUNCT3_START downto FUNCT3_END) = F3_PRIVOP then\n -- ECALL or EBREAK\n case I_dataInst(IMM_I_START downto IMM_I_END) is\n when IMM_I_SYSTEM_ECALL =>\n -- raise trap, save pc, perform requiredCSR operations\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '1';\n O_regDwe <= '0';\n s_intdata <= EXCEPTION_ENVIRONMENT_CALL_FROM_MMODE;\n --todo: Priv level needs checked as to mask this to user/supervisor/machine level\n when IMM_I_SYSTEM_EBREAK =>\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '1';\n s_intdata <= EXCEPTION_BREAKPOINT;\n O_regDwe <= '0';\n when F7_PRIVOP_MRET & R2_PRIV_RET =>\n s_trapExit <= '1';\n s_csrOP <= \"00000\";\n s_int <= '0';\n O_regDwe <= '0';\n -- return from interrupt. implement as a branch - alu will branch to epc.\n when others =>\n end case;\n else\n s_trapExit <= '0';\n s_int <= '0';\n -- CSR\n -- The immediate output is the zero-extended R1 value for Imm-form CSR ops\n O_dataIMM <= X\"000000\" & \"000\" & I_dataInst(R1_START downto R1_END);\n\n -- The 12bit immediate in the instruction forms the csr address.\n s_csrAddr <= I_dataInst(IMM_I_START downto IMM_I_END);\n\n -- is there a destination? if not, CSR is not read\n if I_dataInst(RD_START downto RD_END) = \"00000\" then\n s_csrOP(0) <= '0';\n O_regDwe <= '0';\n else\n O_regDwe <= '1';\n s_csrOP(0) <= '1';\n end if;\n\n -- is there source data? if not, CSR value is not written\n -- is it's CSRRS/CSRRC/CSRRSI/CSRRCI ONLY! I.E (Func3 and 010) != 0\n if (I_dataInst(FUNCT3_END + 1) = '1') and I_dataInst(R1_START downto R1_END) = \"00000\" then\n s_csrOP(1) <= '0';\n else\n s_csrOP(1) <= '1';\n end if;\n\n s_csrOp(4 downto 2) <= I_dataInst(FUNCT3_START downto FUNCT3_END);\n\n end if;\n when others =>\n s_multicy <= '0';\n s_trapExit <= '0';\n s_csrOP <= \"00000\";\n s_int <= '1'; ---------------\n s_intdata <= EXCEPTION_INSTRUCTION_ILLEGAL;\n O_memOp <= \"00000\";\n O_regDwe <= '0';\n O_dataIMM <= I_dataInst(IMM_I_START downto IMM_S_B_END)\n & \"0000000\";\n end case;\n elsif I_int_ack = '1' then\n s_int <= '0';\n end if;\n end if;\n end process;\n\nend Behavioral;", "groundtruth": " O_memOp : out STD_LOGIC_VECTOR(4 downto 0); -- Memory operation \n O_csrOP : out STD_LOGIC_VECTOR(4 downto 0); -- CSR operations\n O_csrAddr : out STD_LOGIC_VECTOR(11 downto 0); -- CSR address\n O_trapExit : out STD_LOGIC; -- request to exit trap handler\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/PKG_RiscV_Klessydra.vhd", "left_context": "-- ieee packages\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\nuse ieee.math_real.all;\n\n-- local packages\n\npackage riscv_klessydra is\n\n -- package parameters is new work.klessydra_parameters\n -- generic (\n -- RV32E : natural -- Regfile size, Can be set to 32 for RV32E being 0 else 16 for RV32E being set to 1\n -- );\n -- generic map (\n -- RV32E => RV32E\n -- );\n --\n -- constant RF_SIZE : natural := 32-16*RV32E;\n -- constant RF_CEIL : natural := integer(ceil(log2(real(RF_SIZE))));\n\n -- instruction trace file\n file file_handler : text open write_mode is \"execution_trace.txt\";\n\n file file_handler0 : text open write_mode is \"execution_0.txt\";\n\n file file_handler1 : text open write_mode is \"execution_1.txt\";\n\n file file_handler2 : text open write_mode is \"execution_2.txt\";\n\n\n------------------------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•šā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā•”ā• ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n-- ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n-- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n------------------------------------------------------------------------------------------------------------\n\n type array_2d is array (integer range<>) of std_logic_vector;\n type array_3d is array (integer range<>) of array_2d;\n type array_2d_int is array (integer range<>) of integer;\n\n type fsm_IE_states is (sleep, reset, normal, csr_instr_wait_state, debug);\n type mulh_states is (init, mult, accum);\n type mul_states is (mult, accum);\n type div_states is (init, divide);\n type fsm_LS_states is (normal , data_valid_waiting);\n\n -- The DSP unit states are defined here\n constant dsp_init : std_logic_vector(1 downto 0) := \"00\";\n constant dsp_halt_hart : std_logic_vector(1 downto 0) := \"01\";\n constant dsp_exec : std_logic_vector(1 downto 0) := \"10\";\n\n constant THREAD_ID_SIZE : integer := 4;\n constant NOP_POOL_SIZE : integer := 2;\n constant BRANCHING_DELAY_SLOT : integer := 3;\n --constant HARC_SIZE : integer := THREAD_POOL_SIZE;\n\n\n-------------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•”ā• ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n-- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n-------------------------------------------------------------------------------------------------\n\n constant EXEC_UNIT_INSTR_SET_SIZE : natural := 52; -- total number of instructions in the exec unit\n constant LS_UNIT_INSTR_SET_SIZE : natural := 12; -- total number of instructions in the ld_str unit\n constant DSP_UNIT_INSTR_SET_SIZE : natural := 17; -- total number of instructions in the dsp unit\n\n\n -- EXEC UNIT INSTR SET --------------------------------------------------------------------------------------------------------------------\n constant ADDI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000000000001\";\n constant SLTI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000000000010\";\n constant SLTIU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000000000100\";\n constant ANDI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000000001000\";\n constant ORI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000000010000\";\n constant XORI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000000100000\";\n constant SLLI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000001000000\";\n constant SRLI7_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000010000000\";\n constant SRAI7_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000000100000000\";\n constant LUI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000001000000000\";\n constant AUIPC_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000010000000000\";\n constant ADD7_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000000100000000000\";\n constant SUB7_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000001000000000000\";\n constant SLT_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000010000000000000\";\n constant SLTU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000000100000000000000\";\n constant ANDD_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000001000000000000000\";\n constant ORR_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000010000000000000000\";\n constant XORR_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000000100000000000000000\";\n constant SLLL_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000001000000000000000000\";\n constant SRLL7_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000010000000000000000000\";\n constant SRAA7_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000000100000000000000000000\";\n constant JAL_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000001000000000000000000000\";\n constant JALR_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000010000000000000000000000\";\n constant BEQ_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000000100000000000000000000000\";\n constant BNE_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000001000000000000000000000000\";\n constant BLT_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000010000000000000000000000000\";\n constant BLTU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000000100000000000000000000000000\";\n constant BGE_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000001000000000000000000000000000\";\n constant BGEU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000010000000000000000000000000000\";\n constant FENCE_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000000100000000000000000000000000000\";\n constant FENCEI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000001000000000000000000000000000000\";\n constant ECALL_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000010000000000000000000000000000000\";\n constant EBREAK_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000000100000000000000000000000000000000\";\n constant MRET_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000001000000000000000000000000000000000\";\n constant WFI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000010000000000000000000000000000000000\";\n constant CSRRW_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000000100000000000000000000000000000000000\";\n constant CSRRS_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000001000000000000000000000000000000000000\";\n constant CSRRC_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000010000000000000000000000000000000000000\";\n constant CSRRWI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000000100000000000000000000000000000000000000\";\n constant CSRRSI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000001000000000000000000000000000000000000000\";\n constant CSRRCI_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000010000000000000000000000000000000000000000\";\n constant SW_MIP_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000000100000000000000000000000000000000000000000\";\n constant ILL_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000001000000000000000000000000000000000000000000\";\n constant NOP_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000010000000000000000000000000000000000000000000\";\n constant MUL_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000000100000000000000000000000000000000000000000000\";\n constant MULH_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000001000000000000000000000000000000000000000000000\";\n constant MULHSU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000010000000000000000000000000000000000000000000000\";\n constant MULHU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0000100000000000000000000000000000000000000000000000\";\n constant DIV_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0001000000000000000000000000000000000000000000000000\";\n constant DIVU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0010000000000000000000000000000000000000000000000000\";\n constant REM_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"0100000000000000000000000000000000000000000000000000\";\n constant REMU_pattern : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0) := \"1000000000000000000000000000000000000000000000000000\";\n -------------------------------------------------------------------------------------------------------------------------------------------\n\n -- LOAD STORE UNIT INSTR SET ---------------------------------------------------------------------\n constant LW_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000000000001\";\n constant LH_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000000000010\";\n constant LHU_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000000000100\";\n constant LB_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000000001000\";\n constant LBU_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000000010000\";\n constant SW_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000000100000\";\n constant SH_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000001000000\";\n constant SB_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000010000000\";\n constant AMOSWAP_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"000100000000\";\n constant KMEMLD_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"001000000000\";\n constant KMEMSTR_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"010000000000\";\n constant KBCASTLD_pattern : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0) := \"100000000000\";\n --------------------------------------------------------------------------------------------------\n\n -- DSP UNIT INSTR SET-------------------------------------------------------------------------------------\n constant KADDV_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000000000001\";\n constant KSUBV_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000000000010\";\n constant KVMUL_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000000000100\";\n constant KVRED_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000000001000\";\n constant KDOTP_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000000010000\";\n constant KSVADDSC_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000000100000\";\n constant KSVADDRF_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000001000000\";\n constant KSVMULSC_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000010000000\";\n constant KSVMULRF_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000000100000000\";\n constant KSRAV_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000001000000000\";\n constant KSRLV_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000010000000000\";\n constant KBCAST_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00000100000000000\";\n constant KRELU_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00001000000000000\";\n constant KDOTPPS_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00010000000000000\";\n constant KVSLT_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"00100000000000000\";\n constant KSVSLT_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"01000000000000000\";\n constant KVCP_pattern : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0) := \"10000000000000000\";\n ----------------------------------------------------------------------------------------------------------\n\n constant ADDI_bit_position : natural := 0;\n constant SLTI_bit_position : natural := 1;\n constant SLTIU_bit_position : natural := 2;\n constant ANDI_bit_position : natural := 3;\n constant ORI_bit_position : natural := 4;\n constant XORI_bit_position : natural := 5;\n constant SLLI_bit_position : natural := 6;\n constant SRLI7_bit_position : natural := 7;\n constant SRAI7_bit_position : natural := 8;\n constant LUI_bit_position : natural := 9;\n constant AUIPC_bit_position : natural := 10;\n constant ADD7_bit_position : natural := 11;\n constant SUB7_bit_position : natural := 12;\n constant SLT_bit_position : natural := 13;\n constant SLTU_bit_position : natural := 14;\n constant ANDD_bit_position : natural := 15;\n constant ORR_bit_position : natural := 16;\n constant XORR_bit_position : natural := 17;\n constant SLLL_bit_position : natural := 18;\n constant SRLL7_bit_position : natural := 19;\n constant SRAA7_bit_position : natural := 20;\n constant JAL_bit_position : natural := 21;\n constant JALR_bit_position : natural := 22;\n constant BEQ_bit_position : natural := 23;\n constant BNE_bit_position : natural := 24;\n constant BLT_bit_position : natural := 25;\n constant BLTU_bit_position : natural := 26;\n constant BGE_bit_position : natural := 27;\n constant BGEU_bit_position : natural := 28;\n constant FENCE_bit_position : natural := 29;\n constant FENCEI_bit_position : natural := 30;\n constant ECALL_bit_position : natural := 31;\n constant EBREAK_bit_position : natural := 32;\n constant MRET_bit_position : natural := 33;\n constant WFI_bit_position : natural := 34;\n constant CSRRW_bit_position : natural := 35;\n constant CSRRS_bit_position : natural := 36;\n constant CSRRC_bit_position : natural := 37;\n constant CSRRWI_bit_position : natural := 38;\n constant CSRRSI_bit_position : natural := 39;\n constant CSRRCI_bit_position : natural := 40;\n constant SW_MIP_bit_position : natural := 41;\n constant ILL_bit_position : natural := 42;\n constant NOP_bit_position : natural := 43;\n constant MUL_bit_position : natural := 44;\n constant MULH_bit_position : natural := 45;\n constant MULHSU_bit_position : natural := 46;\n constant MULHU_bit_position : natural := 47;\n constant DIV_bit_position : natural := 48;\n constant DIVU_bit_position : natural := 49;\n constant REM_bit_position : natural := 50;\n constant REMU_bit_position : natural := 51;\n\n constant LW_bit_position : natural := 0;\n constant LH_bit_position : natural := 1;\n constant LHU_bit_position : natural := 2;\n constant LB_bit_position : natural := 3;\n constant LBU_bit_position : natural := 4;\n constant SW_bit_position : natural := 5;\n constant SH_bit_position : natural := 6;\n constant SB_bit_position : natural := 7;\n constant AMOSWAP_bit_position : natural := 8;\n constant KMEMLD_bit_position : natural := 9;\n constant KMEMSTR_bit_position : natural := 10;\n constant KBCASTLD_bit_position : natural := 11;\n\n constant KADDV_bit_position : natural := 0;\n constant KSUBV_bit_position : natural := 1;\n constant KVMUL_bit_position : natural := 2;\n constant KVRED_bit_position : natural := 3;\n constant KDOTP_bit_position : natural := 4;\n constant KSVADDSC_bit_position : natural := 5;\n constant KSVADDRF_bit_position : natural := 6;\n constant KSVMULSC_bit_position : natural := 7;\n constant KSVMULRF_bit_position : natural := 8;\n constant KSRAV_bit_position : natural := 9;\n constant KSRLV_bit_position : natural := 10;\n constant KBCAST_bit_position : natural := 11;\n constant KRELU_bit_position : natural := 12;\n constant KDOTPPS_bit_position : natural := 13;\n constant KVSLT_bit_position : natural := 14;\n constant KSVSLT_bit_position : natural := 15;\n constant KVCP_bit_position : natural := 16;\n\n-----------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n-- ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n-- ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n-----------------------------------------------------------------------------------------\n\n -- CSRs addresses\n constant MSTATUS_addr : std_logic_vector (11 downto 0) := x\"300\";\n constant MEPC_addr : std_logic_vector (11 downto 0) := x\"341\";\n constant MCAUSE_addr : std_logic_vector (11 downto 0) := x\"342\";\n constant MTVEC_addr : std_logic_vector (11 downto 0) := x\"305\";\n constant MIP_addr : std_logic_vector (11 downto 0) := x\"344\";\n constant PCER_addr : std_logic_vector (11 downto 0) := x\"7A0\";\n constant MESTATUS_addr : std_logic_vector (11 downto 0) := x\"7B8\";\n constant MCPUID_addr : std_logic_vector (11 downto 0) := x\"F00\";\n constant MIMPID_addr : std_logic_vector (11 downto 0) := x\"F01\";\n constant MHARTID_addr : std_logic_vector (11 downto 0) := x\"F14\";\n constant BADADDR_addr : std_logic_vector (11 downto 0) := x\"343\";\n constant MIRQ_addr : std_logic_vector (11 downto 0) := x\"FC0\";\n --Performance Counters CSR addresses\n constant MCYCLE_addr : std_logic_vector (11 downto 0) := x\"B00\";\n constant MINSTRET_addr : std_logic_vector (11 downto 0) := x\"B02\";\n constant MHPMCOUNTER3_addr : std_logic_vector (11 downto 0) := x\"B03\";\n constant MHPMCOUNTER4_addr : std_logic_vector (11 downto 0) := x\"B04\";\n constant MHPMCOUNTER5_addr : std_logic_vector (11 downto 0) := x\"B05\";\n constant MHPMCOUNTER6_addr : std_logic_vector (11 downto 0) := x\"B06\";\n constant MHPMCOUNTER7_addr : std_logic_vector (11 downto 0) := x\"B07\";\n constant MHPMCOUNTER8_addr : std_logic_vector (11 downto 0) := x\"B08\";\n constant MHPMCOUNTER9_addr : std_logic_vector (11 downto 0) := x\"B09\";\n constant MHPMCOUNTER10_addr : std_logic_vector (11 downto 0) := x\"B0A\";\n constant MHPMCOUNTER11_addr : std_logic_vector (11 downto 0) := x\"B0B\";\n constant MHPMCOUNTER12_addr : std_logic_vector (11 downto 0) := x\"B0C\";\n constant MHPMCOUNTER13_addr : std_logic_vector (11 downto 0) := x\"B0D\";\n constant MHPMCOUNTER14_addr : std_logic_vector (11 downto 0) := x\"B0E\";\n constant MHPMCOUNTER15_addr : std_logic_vector (11 downto 0) := x\"B0F\";\n constant MHPMCOUNTER16_addr : std_logic_vector (11 downto 0) := x\"B10\";\n constant MHPMCOUNTER17_addr : std_logic_vector (11 downto 0) := x\"B11\";\n constant MHPMCOUNTER18_addr : std_logic_vector (11 downto 0) := x\"B12\";\n constant MHPMCOUNTER19_addr : std_logic_vector (11 downto 0) := x\"B13\";\n constant MHPMCOUNTER20_addr : std_logic_vector (11 downto 0) := x\"B14\";\n constant MHPMCOUNTER21_addr : std_logic_vector (11 downto 0) := x\"B15\";\n constant MHPMCOUNTER22_addr : std_logic_vector (11 downto 0) := x\"B16\";\n constant MHPMCOUNTER23_addr : std_logic_vector (11 downto 0) := x\"B17\";\n constant MHPMCOUNTER24_addr : std_logic_vector (11 downto 0) := x\"B18\";\n constant MHPMCOUNTER25_addr : std_logic_vector (11 downto 0) := x\"B19\";\n constant MHPMCOUNTER26_addr : std_logic_vector (11 downto 0) := x\"B1A\";\n constant MHPMCOUNTER27_addr : std_logic_vector (11 downto 0) := x\"B1B\";\n constant MHPMCOUNTER28_addr : std_logic_vector (11 downto 0) := x\"B1C\";\n constant MHPMCOUNTER29_addr : std_logic_vector (11 downto 0) := x\"B1D\";\n constant MHPMCOUNTER30_addr : std_logic_vector (11 downto 0) := x\"B1E\";\n constant MHPMCOUNTER31_addr : std_logic_vector (11 downto 0) := x\"B1F\";\n constant MCYCLEH_addr : std_logic_vector (11 downto 0) := x\"B80\";\n constant MINSTRETH_addr : std_logic_vector (11 downto 0) := x\"B82\";\n constant MHPMEVENT3_addr : std_logic_vector (11 downto 0) := x\"323\";\n constant MHPMEVENT4_addr : std_logic_vector (11 downto 0) := x\"324\";\n constant MHPMEVENT5_addr : std_logic_vector (11 downto 0) := x\"325\";\n constant MHPMEVENT6_addr : std_logic_vector (11 downto 0) := x\"326\";\n constant MHPMEVENT7_addr : std_logic_vector (11 downto 0) := x\"327\";\n constant MHPMEVENT8_addr : std_logic_vector (11 downto 0) := x\"328\";\n constant MHPMEVENT9_addr : std_logic_vector (11 downto 0) := x\"329\";\n constant MHPMEVENT10_addr : std_logic_vector (11 downto 0) := x\"32A\";\n constant MHPMEVENT11_addr : std_logic_vector (11 downto 0) := x\"32B\";\n constant MHPMEVENT12_addr : std_logic_vector (11 downto 0) := x\"32C\";\n constant MHPMEVENT13_addr : std_logic_vector (11 downto 0) := x\"32D\";\n constant MHPMEVENT14_addr : std_logic_vector (11 downto 0) := x\"32E\";\n constant MHPMEVENT15_addr : std_logic_vector (11 downto 0) := x\"32F\";\n constant MHPMEVENT16_addr : std_logic_vector (11 downto 0) := x\"330\";\n constant MHPMEVENT17_addr : std_logic_vector (11 downto 0) := x\"331\";\n constant MHPMEVENT18_addr : std_logic_vector (11 downto 0) := x\"332\";\n constant MHPMEVENT19_addr : std_logic_vector (11 downto 0) := x\"333\";\n constant MHPMEVENT20_addr : std_logic_vector (11 downto 0) := x\"334\";\n constant MHPMEVENT21_addr : std_logic_vector (11 downto 0) := x\"335\";\n constant MHPMEVENT22_addr : std_logic_vector (11 downto 0) := x\"336\";\n constant MHPMEVENT23_addr : std_logic_vector (11 downto 0) := x\"337\";\n constant MHPMEVENT24_addr : std_logic_vector (11 downto 0) := x\"338\";\n constant MHPMEVENT25_addr : std_logic_vector (11 downto 0) := x\"339\";\n constant MHPMEVENT26_addr : std_logic_vector (11 downto 0) := x\"33A\";\n constant MHPMEVENT27_addr : std_logic_vector (11 downto 0) := x\"33B\";\n constant MHPMEVENT28_addr : std_logic_vector (11 downto 0) := x\"33C\";\n constant MHPMEVENT29_addr : std_logic_vector (11 downto 0) := x\"33D\";\n constant MHPMEVENT30_addr : std_logic_vector (11 downto 0) := x\"33E\";\n constant MHPMEVENT31_addr : std_logic_vector (11 downto 0) := x\"33F\";\n -- Custom Klessydra CSR addresses\n constant MPSCLFAC_addr : std_logic_vector (11 downto 0) := x\"BE0\";\n constant MVSIZE_addr : std_logic_vector (11 downto 0) := x\"BF0\";\n constant MVTYPE_addr : std_logic_vector (11 downto 0) := x\"BF8\";\n\n\n -- reset values of CSR Registers\n constant MTVEC_RESET_VALUE : std_logic_vector(31 downto 0) := x\"00000094\";\n constant PCER_RESET_VALUE : std_logic_vector(31 downto 0) := x\"00000000\";\n constant MSTATUS_RESET_VALUE : std_logic_vector(1 downto 0) := \"00\";\n constant MESTATUS_RESET_VALUE : std_logic_vector(2 downto 0) := \"000\";\n constant MEPC_RESET_VALUE : std_logic_vector(31 downto 0) := x\"00000000\"; -- label to decode the kind of misaligned access\n constant MCAUSE_RESET_VALUE : std_logic_vector(31 downto 0) := x\"00000000\";\n constant MIP_RESET_VALUE : std_logic_vector(31 downto 0) := x\"00000000\";\n --constant MVSIZE_RESET_VALUE : std_logic_vector(Addr_Width downto 0) := (1 to Addr_Width => '0') & '1';\n constant MVTYPE_RESET_VALUE : std_logic_vector(3 downto 0) := \"1000\";\n constant MPSCLFAC_RESET_VALUE : std_logic_vector(4 downto 0) := (others => '0');\t\t\t\t\t\t\t \n\n -- csr bits for instructions SYSTEM -> CSRRS\n --constant RDCYCLE : std_logic_vector(11 downto 0) := \"110000000000\";\n --constant RDCYCLEH : std_logic_vector(11 downto 0) := \"110010000000\";\n --constant RDTIME : std_logic_vector(11 downto 0) := \"110000000001\";\n --constant RDTIMEH : std_logic_vector(11 downto 0) := \"110010000001\";\n --constant RDINSTRET : std_logic_vector(11 downto 0) := \"110000000010\";\n --constant RDINSTRETH : std_logic_vector(11 downto 0) := \"110010000010\";\n\n-------------------------------------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n-- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n------------------------------------------------------------------------------------------------------------------------- \n\n -- opcodes\n constant OP_IMM : std_logic_vector(6 downto 0) := \"0010011\";\n constant LUI : std_logic_vector(6 downto 0) := \"0110111\";\n constant AUIPC : std_logic_vector(6 downto 0) := \"0010111\";\n constant OP : std_logic_vector(6 downto 0) := \"0110011\";\n constant JAL : std_logic_vector(6 downto 0) := \"1101111\";\n constant JALR : std_logic_vector(6 downto 0) := \"1100111\";\n constant BRANCH : std_logic_vector(6 downto 0) := \"1100011\";\n constant LOAD : std_logic_vector(6 downto 0) := \"0000011\";\n constant STORE : std_logic_vector(6 downto 0) := \"0100011\";\n constant MISC_MEM : std_logic_vector(6 downto 0) := \"0001111\";\n", "right_context": " constant AMO : std_logic_vector(6 downto 0) := \"0101111\";\n constant KMEM : std_logic_vector(6 downto 0) := \"0001011\";\n constant KDSP : std_logic_vector(6 downto 0) := \"0101011\";\n\n -- funct3 bits of OP_IMM opcode\n constant ADDI : std_logic_vector(2 downto 0) := \"000\";\n constant SLTI : std_logic_vector(2 downto 0) := \"010\";\n constant SLTIU : std_logic_vector(2 downto 0) := \"011\";\n constant ANDI : std_logic_vector(2 downto 0) := \"111\";\n constant ORI : std_logic_vector(2 downto 0) := \"110\";\n constant XORI : std_logic_vector(2 downto 0) := \"100\";\n constant SLLI : std_logic_vector(2 downto 0) := \"001\";\n constant SRLI_SRAI : std_logic_vector(2 downto 0) := \"101\";\n\n -- funct3 bits of OP opcode -- chiedere conferma su xorr-orr-andd ecc ecc\n constant ADD : std_logic_vector(2 downto 0) := \"000\";\n constant SLT : std_logic_vector(2 downto 0) := \"010\";\n constant SLTU : std_logic_vector(2 downto 0) := \"011\";\n constant ANDD : std_logic_vector(2 downto 0) := \"111\";\n constant ORR : std_logic_vector(2 downto 0) := \"110\";\n constant XORR : std_logic_vector(2 downto 0) := \"100\";\n constant SLLL : std_logic_vector(2 downto 0) := \"001\";\n constant SRLL : std_logic_vector(2 downto 0) := \"101\";\n\n -- funct3 bits of OP opcode -- chiedere conferma su xorr-orr-andd ecc ecc\n constant SUB7 : std_logic_vector(2 downto 0) := \"000\";\n constant SRAA : std_logic_vector(2 downto 0) := \"101\";\n\n -- funct3 bits of OP opcode -- chiedere conferma su xorr-orr-andd ecc ecc\n constant MUL : std_logic_vector(2 downto 0) := \"000\";\n constant MULH : std_logic_vector(2 downto 0) := \"001\";\n constant MULHSU : std_logic_vector(2 downto 0) := \"010\";\n constant MULHU : std_logic_vector(2 downto 0) := \"011\";\n constant DIV : std_logic_vector(2 downto 0) := \"100\";\n constant DIVU : std_logic_vector(2 downto 0) := \"101\";\n constant REMD : std_logic_vector(2 downto 0) := \"110\";\n constant REMDU : std_logic_vector(2 downto 0) := \"111\";\n\n -- funct3 bits of BRANCH opcode\n constant BEQ : std_logic_vector(2 downto 0) := \"000\";\n constant BNE : std_logic_vector(2 downto 0) := \"001\";\n constant BLT : std_logic_vector(2 downto 0) := \"100\";\n constant BGE : std_logic_vector(2 downto 0) := \"101\";\n constant BLTU : std_logic_vector(2 downto 0) := \"110\";\n constant BGEU : std_logic_vector(2 downto 0) := \"111\";\n\n -- funct3 bits of LOAD opcode\n constant LW : std_logic_vector(2 downto 0) := \"010\";\n constant LH : std_logic_vector(2 downto 0) := \"001\";\n constant LHU : std_logic_vector(2 downto 0) := \"101\";\n constant LB : std_logic_vector(2 downto 0) := \"000\";\n constant LBU : std_logic_vector(2 downto 0) := \"100\";\n\n -- funct3 bits of STORE opcode\n constant SW : std_logic_vector(2 downto 0) := \"010\";\n constant SH : std_logic_vector(2 downto 0) := \"001\";\n constant SB : std_logic_vector(2 downto 0) := \"000\";\n\n -- funct3 bits of MISC_MEM opcode\n constant FENCE : std_logic_vector(2 downto 0) := \"000\";\n constant FENCEI : std_logic_vector(2 downto 0) := \"001\";\n\n -- funct3 bits of AMO opcode\n constant SINGLE : std_logic_vector(2 downto 0) := \"010\";\n\n -- funct3 bits of KLESS opcode\n constant KARITH8 : std_logic_vector(2 downto 0) := \"000\";\n constant KARITH16 : std_logic_vector(2 downto 0) := \"001\";\n constant KARITH32 : std_logic_vector(2 downto 0) := \"010\";\n\n -- instructions to access CSRs\n -- funct3 bits of SYSTEM opcode:\n constant PRIV : std_logic_vector(2 downto 0) := \"000\";\n constant CSRRW : std_logic_vector(2 downto 0) := \"001\";\n constant CSRRS : std_logic_vector(2 downto 0) := \"010\";\n constant CSRRC : std_logic_vector(2 downto 0) := \"011\";\n constant CSRRWI : std_logic_vector(2 downto 0) := \"101\";\n constant CSRRSI : std_logic_vector(2 downto 0) := \"110\";\n constant CSRRCI : std_logic_vector(2 downto 0) := \"111\";\n\n --funct5 bits of AMO opcode\n constant LRW : std_logic_vector(4 downto 0) := \"00010\";\n constant SCW : std_logic_vector(4 downto 0) := \"00011\";\n constant AMOSWAP : std_logic_vector(4 downto 0) := \"00001\";\n constant AMOADD : std_logic_vector(4 downto 0) := \"00000\";\n constant AMOXOR : std_logic_vector(4 downto 0) := \"00100\";\n constant AMOAND : std_logic_vector(4 downto 0) := \"01100\";\n constant AMOOR : std_logic_vector(4 downto 0) := \"01000\";\n constant AMOMIN : std_logic_vector(4 downto 0) := \"10000\";\n constant AMOMAX : std_logic_vector(4 downto 0) := \"10100\";\n constant AMOMINU : std_logic_vector(4 downto 0) := \"11000\";\n constant AMOMAXU : std_logic_vector(4 downto 0) := \"11100\";\n\n -- funct7 bits\n constant SRLI7 : std_logic_vector(6 downto 0) := \"0000000\";\n constant SRAI7 : std_logic_vector(6 downto 0) := \"0100000\";\n constant OP_I1 : std_logic_vector(6 downto 0) := \"0000000\";\n constant OP_I2 : std_logic_vector(6 downto 0) := \"0100000\";\n constant OP_M : std_logic_vector(6 downto 0) := \"0000001\";\n\n\n --funct7 bits for KMEM Instr\n constant KMEMLD : std_logic_vector(6 downto 0) := \"0000000\";\n constant KMEMSTR : std_logic_vector(6 downto 0) := \"0000001\";\n constant KBCASTLD : std_logic_vector(6 downto 0) := \"0000010\";\n\n --funct7 bits for KREG Instr\n constant KADDV : std_logic_vector(6 downto 0) := \"0000001\";\n constant KSUBV : std_logic_vector(6 downto 0) := \"0000010\";\n constant KVMUL : std_logic_vector(6 downto 0) := \"0000100\";\n constant KVRED : std_logic_vector(6 downto 0) := \"0000110\";\n constant KDOTP : std_logic_vector(6 downto 0) := \"0001000\";\n constant KSVADDSC : std_logic_vector(6 downto 0) := \"0001100\";\n constant KSVADDRF : std_logic_vector(6 downto 0) := \"0001101\";\n constant KSVMULSC : std_logic_vector(6 downto 0) := \"0001110\";\n constant KSVMULRF : std_logic_vector(6 downto 0) := \"0001111\";\n constant KSRAV : std_logic_vector(6 downto 0) := \"0010000\";\n constant KSRLV : std_logic_vector(6 downto 0) := \"0010001\";\n constant KRELU : std_logic_vector(6 downto 0) := \"0011000\";\n constant KDOTPPS : std_logic_vector(6 downto 0) := \"0011001\";\n constant KVSLT : std_logic_vector(6 downto 0) := \"0011010\";\n constant KSVSLT : std_logic_vector(6 downto 0) := \"0011100\";\n constant KBCAST : std_logic_vector(6 downto 0) := \"0011110\";\n constant KVCP : std_logic_vector(6 downto 0) := \"0011111\";\n\n -- instr. to change privilege level & interrupt-management instruction\n -- funct12 bits for instructions SYSTEM -> PRIV:\n constant ECALL : std_logic_vector(11 downto 0) := \"000000000000\";\n constant EBREAK : std_logic_vector(11 downto 0) := \"000000000001\";\n constant MRET : std_logic_vector(11 downto 0) := \"001100000010\";\n constant WFI : std_logic_vector(11 downto 0) := \"000100000101\";\n\n----------------------------------------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•”ā• ā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n-- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n----------------------------------------------------------------------------------------------------------------------------\n\n\n -- exception codes (riscv mcause register priv isa 1.10)\n constant ILLEGAL_INSN_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000002\";\n constant LOAD_ERROR_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000005\";\n constant STORE_ERROR_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000007\";\n constant ECALL_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"0000000B\";\n constant LOAD_MISALIGNED_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000004\";\n constant STORE_MISALIGNED_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000006\";\n constant ILLEGAL_VECTOR_SIZE_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000100\"; -- Custom codes\n constant ILLEGAL_ADDRESS_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000101\"; -- Custom codes\n constant SCRATCHPAD_OVERFLOW_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000102\"; -- Custom codes\n constant READ_SAME_SCARTCHPAD_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000103\"; -- Custom codes\n constant WRITE_SAME_SCARTCHPAD_EXCEPT_CODE : std_logic_vector(31 downto 0) := x\"00000104\"; -- Custom codes\n\n\n----------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n-- ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n-- ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n---------------------------------------------------------------------------------- \n\n -- functions --\n\n --function aq(signal instr : in std_logic_vector(31 downto 0)) return std_logic;\n --function rl(signal instr : in std_logic_vector(31 downto 0)) return std_logic;\n\n-- function rs1(signal instr : in std_logic_vector(31 downto 0)) return integer;\n-- function rs2(signal instr : in std_logic_vector(31 downto 0)) return integer;\n-- function rd(signal instr : in std_logic_vector(31 downto 0)) return integer;\n\n function I_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function S_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function B_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function U_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function UJ_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function I_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function S_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function B_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function U_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function UJ_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function shamt(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function OPCODE(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function FUNCT3(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function FUNCT7(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function FUNCT12(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n function CSR_ADDR(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector;\n\nend package;\n\npackage body riscv_klessydra is\n\n --function aq (signal instr : in std_logic_vector(31 downto 0)) return std_logic is\n --begin\n -- return instr(26);\n --end;\n\n --function rl (signal instr : in std_logic_vector(31 downto 0)) return std_logic is\n --begin\n -- return instr(25);\n --end;\n\n --function rs1 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n --begin\n -- return to_integer(unsigned(instr(15+(RF_CEIL-1) downto 15)));\n --end;\n\n --function rs2 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n --begin\n -- return to_integer(unsigned(instr(20+(RF_CEIL-1) downto 20)));\n --end;\n\n --function rd (signal instr : in std_logic_vector(31 downto 0)) return integer is\n --begin\n -- return to_integer(unsigned(instr(11+(RF_CEIL-1) downto 7)));\n --end;\n\n function I_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(resize(signed(instr(31) & instr(30 downto 20)), 32));\n end;\n\n function S_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(resize(signed(instr(31 downto 25) & instr(11 downto 8) & instr(7)), 32));\n end;\n\n function B_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(resize(signed(instr(31) & instr(7) & instr(30 downto 25)\n & instr(11 downto 8) & '0'), 32));\n end;\n\n function U_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(31 downto 12) & std_logic_vector(to_unsigned(0, 12));\n end;\n\n function UJ_immediate(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(resize(signed(instr(31) & instr(19 downto 12) & instr(20)\n & instr(30 downto 21) & '0'), 32));\n end;\n\n function I_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(signed(instr(31) & instr(30 downto 20)));\n end;\n\n function S_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(signed(instr(31 downto 25) & instr(11 downto 8) & instr(7)));\n end;\n\n function B_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(signed(instr(31) & instr(7) & instr(30 downto 25)\n & instr(11 downto 8) & '0'));\n end;\n\n function U_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(31 downto 12);\n end;\n\n function UJ_imm(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return std_logic_vector(signed(instr(31) & instr(19 downto 12) & instr(20)\n & instr(30 downto 21) & '0'));\n end;\n\n function shamt(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(24 downto 20);\n end;\n\n function OPCODE(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(6 downto 0);\n end;\n\n function FUNCT3(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(14 downto 12);\n end;\n\n function FUNCT7(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(31 downto 25);\n end;\n\n function FUNCT12(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(31 downto 20);\n end;\n\n function CSR_ADDR(signal instr : in std_logic_vector(31 downto 0)) return std_logic_vector is\n begin\n return instr(31 downto 20);\n end;\n\nend package body;\n", "groundtruth": " constant SYSTEM : std_logic_vector(6 downto 0) := \"1110011\";\r\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Accumulator.vhd", "left_context": "--------------------------------------------------------------------------------------------------------\n-- Accumulator -- --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 17-11-2019 --\n--------------------------------------------------------------------------------------------------------\n-- The accumuator performs a a reduction using addition on three instructions. KVRED, KDOTP, and --\n-- KDOTPPS. Eacj SIMD configuration has it's own accumulator, repllicating the dsp will also --\n-- replicate the accumulator as well. --\n--------------------------------------------------------------------------------------------------------\n\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\nentity ACCUMULATOR is\n generic(\n multithreaded_accl_en : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n FU_NUM : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n\tport(\n clk_i : in std_logic;\n rst_ni : in std_logic;\n MVTYPE_DSP : in array_2d(ACCL_NUM-1 downto 0)(1 downto 0);\n accum_stage_1_en : in std_logic_vector(ACCL_NUM-1 downto 0);\n accum_stage_2_en : in std_logic_vector(ACCL_NUM-1 downto 0);\n recover_state_wires : in std_logic_vector(ACCL_NUM-1 downto 0);\n halt_dsp_lat : in std_logic_vector(ACCL_NUM-1 downto 0);\n state_DSP : in array_2d(ACCL_NUM-1 downto 0)(1 downto 0);\n decoded_instruction_DSP_lat : in array_2d(ACCL_NUM-1 downto 0)(DSP_UNIT_INSTR_SET_SIZE -1 downto 0);\n dsp_in_accum_operands : in array_2d(FU_NUM-1 downto 0)(SIMD_Width-1 downto 0);\n dsp_out_accum_results : out array_2d(FU_NUM-1 downto 0)(31 downto 0)\n\t);\nend entity;\narchitecture ACCUM_STG of ACCUMULATOR is\n \n subtype accl_range is integer range ACCL_NUM-1 downto 0;\n subtype fu_range is integer range FU_NUM-1 downto 0;\n\n signal accum_partial_results_stg_1 : array_2d(fu_range)(127 downto 0);\nbegin\n\n -- The accumulator for the DSP unit written below for all SIMD widths\n\n ACCUM_replicated : for f in fu_range generate\n\n ACCUM_SIMD_1 : if SIMD=1 generate\n fsm_ACCUM_STAGE : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n dsp_out_accum_results(f) <= (others => '0');\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n case state_DSP(h) is\t\n when dsp_exec =>\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 32-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n MVTYPE_DSP(h) = \"10\" then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(31 downto 0) <= dsp_in_accum_operands(f)(31 downto 0);\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(31 downto 0)) +\n unsigned(dsp_out_accum_results(f)));\n end if;\n elsif (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 8-bit and 16-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"00\") then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(15 downto 0) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(15 downto 0)) + unsigned(dsp_in_accum_operands(f)(31 downto 16)));\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(15 downto 0)) + \n unsigned(dsp_out_accum_results(f))); \n end if;\n end if;\n when others =>\n null;\n end case;\n end loop;\n end if;\n end process;\n end generate ACCUM_SIMD_1;\n\n ACCUM_SIMD_2 : if SIMD=2 generate\n fsm_ACCUM_STAGE : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n dsp_out_accum_results(f) <= (others => '0');\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n case state_DSP(h) is\n when dsp_exec =>\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 32-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n MVTYPE_DSP(h) = \"10\" then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(31 downto 0) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(31 downto 0)) + unsigned(dsp_in_accum_operands(f)(63 downto 32)));\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(31 downto 0)) +\n unsigned(dsp_out_accum_results(f)));\n end if;\n elsif (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 8-bit and 16-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"00\") then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(15 downto 0) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(15 downto 0)) + unsigned(dsp_in_accum_operands(f)(31 downto 16)));\n accum_partial_results_stg_1(f)(31 downto 16) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(47 downto 32)) + unsigned(dsp_in_accum_operands(f)(63 downto 48)));\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n", "right_context": " end if;\n end if;\n when others =>\n null;\n end case;\n end loop;\n end if;\n end process; \n end generate ACCUM_SIMD_2;\n\n ACCUM_SIMD_4 : if SIMD=4 generate\n fsm_ACCUM_STAGE : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n dsp_out_accum_results(f) <= (others => '0');\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n case state_DSP(h) is\n when dsp_exec =>\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 32-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n MVTYPE_DSP(h) = \"10\" then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(31 downto 0) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(31 downto 0)) + unsigned(dsp_in_accum_operands(f)(63 downto 32)));\n accum_partial_results_stg_1(f)(63 downto 32) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(95 downto 64)) + unsigned(dsp_in_accum_operands(f)(127 downto 96)));\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(31 downto 0)) + \n unsigned(accum_partial_results_stg_1(f)(63 downto 32)) +\n unsigned(dsp_out_accum_results(f)));\n end if;\n elsif (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 8-bit and 16-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"00\") then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(15 downto 0) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(15 downto 0)) + unsigned(dsp_in_accum_operands(f)(31 downto 16)));\n accum_partial_results_stg_1(f)(31 downto 16) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(47 downto 32)) + unsigned(dsp_in_accum_operands(f)(63 downto 48)));\n accum_partial_results_stg_1(f)(47 downto 32) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(79 downto 64)) + unsigned(dsp_in_accum_operands(f)(95 downto 80)));\n accum_partial_results_stg_1(f)(63 downto 48) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(111 downto 96)) + unsigned(dsp_in_accum_operands(f)(127 downto 112)));\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(15 downto 0)) + \n unsigned(accum_partial_results_stg_1(f)(31 downto 16)) +\n unsigned(accum_partial_results_stg_1(f)(47 downto 32)) +\n unsigned(accum_partial_results_stg_1(f)(63 downto 48)) +\n unsigned(dsp_out_accum_results(f))); \n end if;\n end if;\n when others =>\n null;\n end case;\n end loop;\n end if;\n end process;\n end generate ACCUM_SIMD_4;\n\n ACCUM_SIMD_8 : if SIMD=8 generate\n fsm_ACCUM_STAGE : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n dsp_out_accum_results(f) <= (others => '0');\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n case state_DSP(h) is\n when dsp_exec =>\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 32-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n MVTYPE_DSP(h) = \"10\" then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(31 downto 0) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(31 downto 0)) + unsigned(dsp_in_accum_operands(f)(63 downto 32)));\n accum_partial_results_stg_1(f)(63 downto 32) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(95 downto 64)) + unsigned(dsp_in_accum_operands(f)(127 downto 96)));\n accum_partial_results_stg_1(f)(95 downto 64) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(159 downto 128)) + unsigned(dsp_in_accum_operands(f)(191 downto 160)));\n accum_partial_results_stg_1(f)(127 downto 96) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(223 downto 192)) + unsigned(dsp_in_accum_operands(f)(255 downto 224)));\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(31 downto 0)) + \n unsigned(accum_partial_results_stg_1(f)(63 downto 32)) +\n unsigned(accum_partial_results_stg_1(f)(95 downto 64)) +\n unsigned(accum_partial_results_stg_1(f)(127 downto 96)) +\n unsigned(dsp_out_accum_results(f)));\n end if;\n elsif (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or -- acccumulate 8-bit and 16-bit types\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"00\") then\n if (accum_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n accum_partial_results_stg_1(f)(15 downto 0) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(15 downto 0)) + unsigned(dsp_in_accum_operands(f)(31 downto 16)));\n accum_partial_results_stg_1(f)(31 downto 16) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(47 downto 32)) + unsigned(dsp_in_accum_operands(f)(63 downto 48)));\n accum_partial_results_stg_1(f)(47 downto 32) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(79 downto 64)) + unsigned(dsp_in_accum_operands(f)(95 downto 80)));\n accum_partial_results_stg_1(f)(63 downto 48) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(111 downto 96)) + unsigned(dsp_in_accum_operands(f)(127 downto 112)));\n accum_partial_results_stg_1(f)(79 downto 64) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(143 downto 128)) + unsigned(dsp_in_accum_operands(f)(159 downto 144)));\n accum_partial_results_stg_1(f)(95 downto 80) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(175 downto 160)) + unsigned(dsp_in_accum_operands(f)(191 downto 176)));\n accum_partial_results_stg_1(f)(111 downto 96) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(207 downto 192)) + unsigned(dsp_in_accum_operands(f)(223 downto 208)));\n accum_partial_results_stg_1(f)(127 downto 112) <= std_logic_vector(unsigned(dsp_in_accum_operands(f)(239 downto 224)) + unsigned(dsp_in_accum_operands(f)(255 downto 240)));\n end if;\n if (accum_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(15 downto 0)) + \n unsigned(accum_partial_results_stg_1(f)(31 downto 16)) +\n unsigned(accum_partial_results_stg_1(f)(47 downto 32)) +\n unsigned(accum_partial_results_stg_1(f)(63 downto 48)) +\n unsigned(accum_partial_results_stg_1(f)(79 downto 64)) +\n unsigned(accum_partial_results_stg_1(f)(95 downto 80)) +\n unsigned(accum_partial_results_stg_1(f)(111 downto 96)) +\n unsigned(accum_partial_results_stg_1(f)(127 downto 112)) +\n unsigned(dsp_out_accum_results(f))); \n end if;\n end if;\n when others =>\n null;\n end case;\n end loop;\n end if;\n end process;\n end generate ACCUM_SIMD_8;\n\n end generate ACCUM_replicated;\n\n------------------------------------------------------------------------ end of ACCUM Unit -------\n-------------------------------------------------------------------------------------------------- \n\nend ACCUM_STG;\n--------------------------------------------------------------------------------------------------\n-- END of ACCUM Unit architecture ----------------------------------------------------------------\n--------------------------------------------------------------------------------------------------\n", "groundtruth": " dsp_out_accum_results(f) <= std_logic_vector(unsigned(accum_partial_results_stg_1(f)(15 downto 0)) + \n unsigned(accum_partial_results_stg_1(f)(31 downto 16)) +\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-CSR_Unit.vhd", "left_context": "--------------------------------------------------------------------------------------------------------\n-- Control and Status Units -- --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- Gianmarco Cerutti --\n-- --\n-- Date Modified: 02-04-2020 --\n--------------------------------------------------------------------------------------------------------\n-- Manages CSR instructions and CSR automatic updates following traps and special instructions. --\n-- Note: In the present version, gives priority to CSR automatic updates over CSR instr. execution --\n-- Note: The CSRegisters are replicated along with the related logic, as in the pc update logic. --\n-- The CSR has a set of performance counters such that when enabled can count the number of cycles, --\n-- instructions, load-store instructions, jumps, branches, and taken branches --\n-- Custom CSRs are implemented for the accelerator unit --\n--------------------------------------------------------------------------------------------------------\n\n--package riscv_kless is new work.riscv_klessydra;\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.riscv_kless.all;\n\n\nentity CSR_Unit is\n generic (\n THREAD_POOL_SIZE : integer;\n ACCL_NUM : natural;\n Addr_Width : natural;\n replicate_accl_en : natural;\n accl_en : natural;\n MCYCLE_EN : natural;\n MINSTRET_EN : natural;\n MHPMCOUNTER_EN : natural;\n RF_CEIL : natural;\n count_all : natural\n );\n port (\n pc_IE : in std_logic_vector(31 downto 0);\n ie_except_data : in std_logic_vector(31 downto 0);\n ls_except_data : in std_logic_vector(31 downto 0);\n dsp_except_data : in array_2d(ACCL_NUM - 1 downto 0)(31 downto 0);\n served_ie_except_condition : in std_logic_vector(THREAD_POOL_SIZE -1 downto 0);\n served_ls_except_condition : in std_logic_vector(THREAD_POOL_SIZE -1 downto 0);\n served_dsp_except_condition : in std_logic_vector(THREAD_POOL_SIZE -1 downto 0);\n harc_EXEC : in integer range THREAD_POOL_SIZE -1 downto 0;\n harc_to_csr : in integer range THREAD_POOL_SIZE -1 downto 0;\n instr_word_IE : in std_logic_vector(31 downto 0);\n served_except_condition : in std_logic_vector(THREAD_POOL_SIZE -1 downto 0);\n served_mret_condition : in std_logic_vector(THREAD_POOL_SIZE -1 downto 0);\n served_irq : in std_logic_vector(THREAD_POOL_SIZE -1 downto 0);\n pc_except_value_wire : in array_2d(THREAD_POOL_SIZE -1 downto 0)(31 downto 0);\n dbg_req_o : in std_logic;\n data_addr_internal : in std_logic_vector(31 downto 0);\n jump_instr : in std_logic;\n branch_instr : in std_logic;\n set_branch_condition : in std_logic;\n csr_instr_req : in std_logic;\n misaligned_err : in std_logic;\n WFI_Instr : in std_logic;\n csr_wdata_i : in std_logic_vector (31 downto 0);\n csr_op_i : in std_logic_vector (2 downto 0);\n csr_addr_i : in std_logic_vector (11 downto 0);\n csr_instr_done : out std_logic;\n csr_access_denied_o : out std_logic;\n csr_rdata_o : out std_logic_vector (31 downto 0);\n MVSIZE : out array_2d(THREAD_POOL_SIZE-1 downto 0)(Addr_Width downto 0); \n MVTYPE : out array_2d(THREAD_POOL_SIZE-1 downto 0)(3 downto 0); -- CSR Size follows the RVV standard\n MPSCLFAC : out array_2d(THREAD_POOL_SIZE-1 downto 0)(4 downto 0);\n MSTATUS : out array_2d(THREAD_POOL_SIZE-1 downto 0)(1 downto 0);\n MEPC : out array_2d(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n MCAUSE : out array_2d(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n MIP : out array_2d(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n MTVEC : out array_2d(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n PCER : out array_2d(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n fetch_enable_i : in std_logic;\n clk_i : in std_logic;\n rst_ni : in std_logic;\n cluster_id_i : in std_logic_vector(5 downto 0);\n instr_rvalid_i : in std_logic;\n instr_rvalid_IE : in std_logic;\n data_we_o : in std_logic;\n data_req_o : in std_logic;\n data_gnt_i : in std_logic;\n irq_i : in std_logic;\n irq_id_i : in std_logic_vector(4 downto 0);\n irq_id_o : out std_logic_vector(4 downto 0);\n irq_ack_o : out std_logic\n );\nend entity;\n\n\narchitecture CSR of CSR_Unit is\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0;\n subtype accl_range is integer range ACCL_NUM - 1 downto 0;\n\n signal pc_IE_replicated\t: array_2d(harc_range)(31 downto 0);\t\n\t\n -- Control Status Register (CSR) signals \n signal PCCRs : array_2d(harc_range)(31 downto 0); -- still not implemented\n signal PCMR : array_2d(harc_range)(31 downto 0); -- still not implemented\n signal MESTATUS : array_2d(harc_range)(2 downto 0);\n signal MCPUID : array_2d(harc_range)(8 downto 0);\n signal MIMPID : array_2d(harc_range)(15 downto 0);\n signal MHARTID : array_2d(harc_range)(9 downto 0);\n signal MIRQ : array_2d(harc_range)(31 downto 0); -- extension, maps external irqs\n signal MBADADDR : array_2d(harc_range)(31 downto 0); -- misaligned address containers\n\n signal MCYCLE : array_2d(harc_range)(31 downto 0);\n signal MINSTRET : array_2d(harc_range)(31 downto 0);\n signal MHPMCOUNTER3 : array_2d(harc_range)(31 downto 0);\n signal MHPMCOUNTER6 : array_2d(harc_range)(31 downto 0);\n signal MHPMCOUNTER7 : array_2d(harc_range)(31 downto 0);\n signal MHPMCOUNTER8 : array_2d(harc_range)(31 downto 0);\n signal MHPMCOUNTER9 : array_2d(harc_range)(31 downto 0);\n signal MHPMCOUNTER10 : array_2d(harc_range)(31 downto 0);\n signal MHPMCOUNTER11 : array_2d(harc_range)(31 downto 0);\n signal MCYCLEH : array_2d(harc_range)(31 downto 0);\n signal MINSTRETH : array_2d(harc_range)(31 downto 0);\n signal MHPMEVENT3 : std_logic_vector(harc_range); \n signal MHPMEVENT6 : std_logic_vector(harc_range);\n signal MHPMEVENT7 : std_logic_vector(harc_range);\n signal MHPMEVENT8 : std_logic_vector(harc_range);\n signal MHPMEVENT9 : std_logic_vector(harc_range);\n signal MHPMEVENT10 : std_logic_vector(harc_range);\n signal MHPMEVENT11 : std_logic_vector(harc_range);\n -- auxiliary irq fixed connection signals\n signal MIP_7 : std_logic;\n signal MIP_11 : std_logic;\n\n -- Interface signals from EXEC unit to CSR management unit\n\n -- CSR management unit internal signal\n signal csr_instr_req_replicated : std_logic_vector(harc_range);\n signal csr_instr_done_replicated : std_logic_vector(harc_range);\n signal csr_access_denied_o_replicated : std_logic_vector(harc_range);\n signal csr_rdata_o_replicated : array_2d(harc_range)(31 downto 0);\n\n -- wire only signals (For Synopsis Comaptibility)\n signal MSTATUS_internal : array_2d(harc_range)(1 downto 0);\n signal MEPC_internal : array_2d(harc_range)(31 downto 0);\n signal MCAUSE_internal : array_2d(harc_range)(31 downto 0);\n signal MIP_internal : array_2d(harc_range)(31 downto 0);\n signal MTVEC_internal : array_2d(harc_range)(31 downto 0);\n signal irq_ack_o_internal : std_logic;\n signal trap_hndlr \t: std_logic_vector(harc_range);\n\n function rs1 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(15+(RF_CEIL-1) downto 15)));\n end;\n\n function rs2 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(20+(RF_CEIL-1) downto 20)));\n end;\n\n function rd (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(7+(RF_CEIL-1) downto 7)));\n end;\n\nbegin\n\n\n\n MSTATUS <= MSTATUS_internal;\n MEPC <= MEPC_internal;\n MCAUSE <= MCAUSE_internal;\n MIP <= MIP_internal;\n MTVEC <= MTVEC_internal;\n irq_ack_o <= irq_ack_o_internal;\n\n -- here we start replicating the logic ------------------------------------------------------\n CSR_updating_logic : for h in harc_range generate\n\n -- hardwired read-only connections \n -- note: MCPUID, MIMPID, MHARTID replicated only for easy coding, they return same value for all threads\n MCPUID(h) <= std_logic_vector(to_unsigned(256, 9)); -- xx move init value in pkg\n MIMPID(h) <= std_logic_vector(to_unsigned(32768, 16)); -- xx move init value in pkg\n\n -- irq request vector shifted by 2 bits, used in interrupt handler routine\n MIRQ(h) <= \"0000000000000000000000000\" & irq_id_i & \"00\";\n pc_IE_replicated(h) <= pc_IE when harc_EXEC = h else (others =>'0');\n csr_instr_req_replicated(h) <= '1' when csr_instr_req = '1' and harc_to_csr = h else '0';\n trap_hndlr(h) <= '1' when pc_IE_replicated(h) = MTVEC_RESET_VALUE else '0';\n MHARTID(h) <= std_logic_vector(resize(unsigned(cluster_id_i) & to_unsigned(h, THREAD_ID_SIZE), 10));\n\n CSR_unit_op : process(clk_i, rst_ni) -- single cycle unit, one process, fully synchronous \n begin\n\n if rst_ni = '0' then\n if accl_en = 1 then\n MVSIZE(h) <= (others => '0');\n MVTYPE(h) <= MVTYPE_RESET_VALUE;\n MPSCLFAC(h) <= MPSCLFAC_RESET_VALUE;\n end if;\n MSTATUS_internal(h) <= MSTATUS_RESET_VALUE;\n MESTATUS(h) <= MESTATUS_RESET_VALUE;\n MEPC_internal(h) <= MEPC_RESET_VALUE;\n MCAUSE_internal(h) <= MCAUSE_RESET_VALUE;\n MTVEC_internal(h) <= MTVEC_RESET_VALUE;\n PCER(h) <= PCER_RESET_VALUE;\n --Reset of counters and related registers\n if (MCYCLE_EN = 1) then\n MCYCLE(h) <= x\"00000000\";\n MCYCLEH(h) <= x\"00000000\";\n end if;\n if (MINSTRET_EN = 1) then\n MINSTRET(h) <= x\"00000000\";\n MINSTRETH(h) <= x\"00000000\";\n end if;\n if (MHPMCOUNTER_EN = 1) then\n MHPMCOUNTER3(h) <= x\"00000000\";\n MHPMCOUNTER6(h) <= x\"00000000\";\n MHPMCOUNTER7(h) <= x\"00000000\";\n MHPMCOUNTER8(h) <= x\"00000000\";\n MHPMCOUNTER9(h) <= x\"00000000\";\n MHPMCOUNTER10(h) <= x\"00000000\";\n MHPMEVENT3(h) <= PCER_RESET_VALUE(2);\n MHPMEVENT6(h) <= PCER_RESET_VALUE(5);\n MHPMEVENT7(h) <= PCER_RESET_VALUE(6);\n MHPMEVENT8(h) <= PCER_RESET_VALUE(7);\n MHPMEVENT9(h) <= PCER_RESET_VALUE(8);\n MHPMEVENT10(h) <= PCER_RESET_VALUE(9);\n end if;\n MIP_internal(h) <= MIP_RESET_VALUE;\n\n csr_instr_done_replicated(h) <= '0';\n csr_access_denied_o_replicated(h) <= '0';\n csr_rdata_o_replicated(h) <= (others => '0');\n\n elsif rising_edge(clk_i) then\n -- CSR updating for all possible sources follows.\n -- ext. int., sw int., timer int., exceptions.\n -- We update CSR following this order, the software interrupt vector manager follows\n -- the same order, so that CSRs are consistent with interrupt service.\n -- Interrupt-caused CSR updating ---------------------------------\n -- note: PC just udpdated, MIP_internals can't have been cleared yet.\n\n --------------------------------------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–„ā–„ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•”ā• ā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā–€ā–€ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n -------------------------------------------------------------------------------------------------------------------------------------------------- \n \n -- synchronous assignment to MIP_internal bits:\n -- this is Pulpino-specific assignment, i.e. the timer-related IRQ vector value\n if h = 0 and unsigned(irq_id_i) >= 28 and irq_i = '1' then\n MIP_internal(h)(7) <= '1';\n else\n MIP_internal(h)(7) <= '0'; -- only harc 0 interruptible\n end if;\n -- this detects the other IRQ vector values in Pulpino\n if h = 0 and unsigned(irq_id_i) < 28 and irq_i = '1' then\n MIP_internal(h)(11) <= '1';\n else\n MIP_internal(h)(11) <= '0'; -- only harc 0 interruptible\n end if;\n -- the MIP_internal(h)(3), MSIP bit, software interrupt, is assigned above\n\n if served_irq(h) = '1' and MIP_internal(h)(11) = '1' then\n -- it is the MEIP bit, ext. irq\n MCAUSE_internal(h) <= \"1\" & std_logic_vector(to_unsigned(11, 31)); -- ext. irq\n MESTATUS(h)(2 downto 1) <= MSTATUS_internal(h);\n if trap_hndlr(h) = '0' then\n MEPC_internal(h) <= pc_IE;\n end if; \n if WFI_Instr = '1' then\n MCAUSE_internal(h)(30) <= '1'; -- \n else\n MCAUSE_internal(h)(30) <= '0';\n end if;\n MSTATUS_internal(h)(0) <= '0'; -- interrupt disabled\n MSTATUS_internal(h)(1) <= MSTATUS_internal(h)(0);\n elsif served_irq(h) = '1' and MIP_internal(h)(3) = '1' then\n -- it is the MSIP bit, sw interrupt req\n MCAUSE_internal(h) <= \"1\" & std_logic_vector(to_unsigned(3, 31)); -- sw interrupt\n MIP_internal(h)(3) <= '0'; -- we reset the sw int. request just being served\n MESTATUS(h)(2 downto 1) <= MSTATUS_internal(h);\n if trap_hndlr(h) = '0' then\n MEPC_internal(h) <= pc_IE;\n end if; \n if WFI_Instr = '1' then\n MCAUSE_internal(h)(30) <= '1';\n else\n MCAUSE_internal(h)(30) <= '0';\n end if;\n MSTATUS_internal(h)(0) <= '0'; -- interrupt disabled\n MSTATUS_internal(h)(1) <= MSTATUS_internal(h)(0);\n elsif served_irq(h) = '1' and MIP_internal(h)(7) = '1' then\n -- it is the MSIP bit, timer interrupt req\n MCAUSE_internal(h) <= \"1\" & std_logic_vector(to_unsigned(7, 31)); -- timer interrupt\n MESTATUS(h)(2 downto 1) <= MSTATUS_internal(h);\n if trap_hndlr(h) = '0' then\n MEPC_internal(h) <= pc_IE;\n end if; \n if WFI_Instr = '1' then\n MCAUSE_internal(h)(30) <= '1';\n else\n MCAUSE_internal(h)(30) <= '0';\n end if;\n MSTATUS_internal(h)(0) <= '0'; -- interrupt disabled\n MSTATUS_internal(h)(1) <= MSTATUS_internal(h)(0);\n \n -- Exception-caused CSR updating ----------------------------------\n elsif served_except_condition(h) = '1' then\n if served_dsp_except_condition(h) = '1' then\n if replicate_accl_en = 1 then\n MCAUSE_internal(h) <= dsp_except_data(h); -- passed from DSP Unit\n elsif replicate_accl_en = 0 then\n MCAUSE_internal(h) <= dsp_except_data(0); -- passed from DSP Unit\n end if;\n elsif served_ls_except_condition(h) = '1' then\n MCAUSE_internal(h) <= ls_except_data; -- passed from LS unit\n elsif served_ie_except_condition(h) = '1' then\n MCAUSE_internal(h) <= ie_except_data; -- passed from IE Stage\n end if;\n MESTATUS(h)(2 downto 1) <= MSTATUS_internal(h);\n MEPC_internal(h) <= pc_except_value_wire(h);\n MSTATUS_internal(h)(0) <= '0'; -- interrupt disabled \n MSTATUS_internal(h)(1) <= '1';\n if misaligned_err = '1' then\n MBADADDR(h) <= data_addr_internal;\n end if;\n\n -- mret-caused CSR updating ----------------------------------------\n elsif served_mret_condition(h) = '1' then\n MSTATUS_internal(h)(1) <= '1';\n MSTATUS_internal(h)(0) <= MSTATUS_internal(h)(1);\n -- CSR instruction handling ---------------------------------------- \n elsif(csr_instr_done_replicated(h) = '1') then\n csr_instr_done_replicated(h) <= '0';\n csr_access_denied_o_replicated(h) <= '0';\n elsif csr_instr_req_replicated(h) = '1' then\n csr_instr_done_replicated(h) <= '1';\n\n -----------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā• ā•šā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•šā•ā•ā• ā•šā•ā• ā•šā•ā• --\n -----------------------------------------------------------------------------\n\n if (csr_op_i /= \"000\" and csr_op_i /= \"100\") then -- check for valid operation \n case csr_addr_i is\n\n -- Vector size register, custom CSR reg for the hardware accelerator that defines the vector size in bytes\n when MVSIZE_addr =>\n if accl_en = 1 then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h)(Addr_Width downto 0) <= MVSIZE(h);\n csr_rdata_o_replicated(h)(31 downto Addr_Width +1) <= (others => '0');\n MVSIZE(h) <= csr_wdata_i(Addr_Width downto 0);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h)(Addr_Width downto 0) <= MVSIZE(h);\n csr_rdata_o_replicated(h)(31 downto Addr_Width +1) <= (others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MVSIZE(h) <= (MVSIZE(h) or csr_wdata_i(Addr_Width downto 0));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h)(Addr_Width downto 0) <= MVSIZE(h);\n csr_rdata_o_replicated(h)(31 downto Addr_Width +1) <= (others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MVSIZE(h) <= (MVSIZE(h) and not(csr_wdata_i(Addr_Width downto 0)));\n end if;\n when others =>\n null;\n end case;\n end if;\n\n -- Vector type register, custom CSR reg for the hardware accelerator that defines the vector type (8-bit, 16-bit, 32-bit)\n when MVTYPE_addr =>\n if accl_en = 1 then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h)(3 downto 0) <= MVTYPE(h);\n csr_rdata_o_replicated(h)(31 downto 4) <= (others => '0');\n MVTYPE(h)(3 downto 2) <= csr_wdata_i(1 downto 0);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h)(3 downto 0) <= MVTYPE(h);\n csr_rdata_o_replicated(h)(31 downto 4) <= (others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MVTYPE(h)(3 downto 2) <= (MVTYPE(h)(3 downto 2) or csr_wdata_i(1 downto 0));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h)(3 downto 0) <= MVTYPE(h);\n csr_rdata_o_replicated(h)(31 downto 4) <= (others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MVTYPE(h)(3 downto 2) <= (MVTYPE(h)(3 downto 2) and not(csr_wdata_i(1 downto 0)));\n end if;\n when others =>\n null;\n end case;\n end if;\n\n -- Vector scaling register, custom CSR reg for the hardware accelerator that defines how much the vector needs to be scaled\n when MPSCLFAC_addr =>\n if accl_en = 1 then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h)(4 downto 0) <= MPSCLFAC(h);\n csr_rdata_o_replicated(h)(31 downto 5) <= (others => '0');\n MPSCLFAC(h) <= csr_wdata_i(4 downto 0);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h)(4 downto 0) <= MPSCLFAC(h);\n csr_rdata_o_replicated(h)(31 downto 5) <= (others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MPSCLFAC(h) <= (MPSCLFAC(h) or csr_wdata_i(4 downto 0));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h)(4 downto 0) <= MPSCLFAC(h);\n csr_rdata_o_replicated(h)(31 downto 5) <= (others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MPSCLFAC(h) <= (MPSCLFAC(h) and not(csr_wdata_i(4 downto 0)));\n end if;\n when others =>\n null;\n end case;\n end if;\n\n when MSTATUS_addr =>\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (13 to 31 => '0') & \"11\" & \"000\" & MSTATUS_internal(h)(1) & \"000\" & MSTATUS_internal(h)(0) & \"000\";\n MSTATUS_internal(h)(1) <= csr_wdata_i(7);\n MSTATUS_internal(h)(0) <= csr_wdata_i(3);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (13 to 31 => '0') & \"11\" & \"000\" & MSTATUS_internal(h)(1) & \"000\" & MSTATUS_internal(h)(0) & \"000\";\n if(rs1(instr_word_IE) /= 0) then\n MSTATUS_internal(h)(1) <= (MSTATUS_internal(h)(1) or csr_wdata_i(7));\n MSTATUS_internal(h)(0) <= (MSTATUS_internal(h)(0) or csr_wdata_i(3));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (13 to 31 => '0') & \"11\" & \"000\" & MSTATUS_internal(h)(1) & \"000\" & MSTATUS_internal(h)(0) & \"000\";\n if(rs1(instr_word_IE) /= 0) then\n MSTATUS_internal(h)(1) <= MSTATUS_internal(h)(1) and (not csr_wdata_i(7));\n MSTATUS_internal(h)(0) <= MSTATUS_internal(h)(0) and (not csr_wdata_i(3));\n end if;\n when others =>\n null;\n end case;\n\n when MIP_addr =>\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (11 => MIP_internal(h)(11), 7 => MIP_internal(h)(7), 3 => MIP_internal(h)(3), others => '0');\n MIP_internal(h)(3) <= csr_wdata_i(3);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (11 => MIP_internal(h)(11), 7 => MIP_internal(h)(7), 3 => MIP_internal(h)(3), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MIP_internal(h)(3) <= (MIP_internal(h)(3) or csr_wdata_i(3));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (11 => MIP_internal(h)(11), 7 => MIP_internal(h)(7), 3 => MIP_internal(h)(3), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MIP_internal(h)(3) <= (MIP_internal(h)(3) and (not csr_wdata_i(3)));\n end if;\n when others =>\n null;\n end case;\n\n when MEPC_addr =>\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MEPC_internal(h);\n MEPC_internal(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MEPC_internal(h);\n if(rs1(instr_word_IE) /= 0) then\n MEPC_internal(h) <= (MEPC_internal(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MEPC_internal(h);\n if(rs1(instr_word_IE) /= 0) then\n MEPC_internal(h) <= (MEPC_internal(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n\n when MTVEC_addr =>\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MTVEC_internal(h);\n MTVEC_internal(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MTVEC_internal(h);\n if(rs1(instr_word_IE) /= 0) then\n MTVEC_internal(h) <= (MTVEC_internal(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MTVEC_internal(h);\n if(rs1(instr_word_IE) /= 0) then\n MTVEC_internal(h) <= (MTVEC_internal(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n\n when MCAUSE_addr =>\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MCAUSE_internal(h);\n MCAUSE_internal(h)(31) <= csr_wdata_i(31);\n MCAUSE_internal(h)(4 downto 0) <= csr_wdata_i(4 downto 0);\n MCAUSE_internal(h)(8) <= csr_wdata_i(8);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MCAUSE_internal(h);\n if(rs1(instr_word_IE) /= 0) then\n MCAUSE_internal(h)(31) <= (MCAUSE_internal(h)(31) or csr_wdata_i(31));\n MCAUSE_internal(h)(4 downto 0) <= (MCAUSE_internal(h)(4 downto 0) or csr_wdata_i(4 downto 0));\n MCAUSE_internal(h)(8) <= (MCAUSE_internal(h)(8) or csr_wdata_i(8));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MCAUSE_internal(h);\n if(rs1(instr_word_IE) /= 0) then\n MCAUSE_internal(h)(4 downto 0) <= (MCAUSE_internal(h)(4 downto 0) and not(csr_wdata_i(4 downto 0)));\n MCAUSE_internal(h)(31) <= (MCAUSE_internal(h)(31) and not(csr_wdata_i(31)));\n MCAUSE_internal(h)(8) <= (MCAUSE_internal(h)(8) and not(csr_wdata_i(8)));\n end if;\n when others =>\n null;\n end case;\n\n when MESTATUS_addr =>\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (13 to 31 => '0') & \"11\" & \"000\" & MESTATUS(h)(2) & \"000\" & MESTATUS(h)(1) & \"00\" & MESTATUS(h)(0);\n MESTATUS(h)(0) <= csr_wdata_i(0);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (13 to 31 => '0') & \"11\" & \"000\" & MESTATUS(h)(2) & \"000\" & MESTATUS(h)(1) & \"00\" & MESTATUS(h)(0);\n if(rs1(instr_word_IE) /= 0) then\n MESTATUS(h)(0) <= (MESTATUS(h)(0) or csr_wdata_i(0));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (13 to 31 => '0') & \"11\" & \"000\" & MESTATUS(h)(2) & \"000\" & MESTATUS(h)(1) & \"00\" & MESTATUS(h)(0);\n if(rs1(instr_word_IE) /= 0) then\n MESTATUS(h)(0) <= (MESTATUS(h)(0) and (not csr_wdata_i(0)));\n end if;\n when others =>\n null;\n end case;\n \n when MCPUID_addr => -- read only\n case csr_op_i is\n when CSRRC|CSRRS|CSRRCI|CSRRSI =>\n if(rs1(instr_word_IE) = 0) then\n csr_rdata_o_replicated(h) <= (9 to 31 => '0') & MCPUID(h);\n else\n csr_access_denied_o_replicated(h) <= '1';\n end if;\n when CSRRW|CSRRWI =>\n csr_access_denied_o_replicated(h) <= '1';\n when others =>\n null;\n end case;\n\n when MIMPID_addr => -- read only\n case csr_op_i is\n when CSRRC|CSRRS|CSRRCI|CSRRSI =>\n if(rs1(instr_word_IE) = 0) then\n csr_rdata_o_replicated(h) <= (16 to 31 => '0') & MIMPID(h);\n else\n csr_access_denied_o_replicated(h) <= '1';\n end if;\n when CSRRW|CSRRWI =>\n csr_access_denied_o_replicated(h) <= '1';\n when others =>\n null;\n end case;\n\n when MHARTID_addr => -- read only\n case csr_op_i is\n when CSRRC|CSRRS|CSRRCI|CSRRSI =>\n if(rs1(instr_word_IE) = 0) then\n csr_rdata_o_replicated(h) <= (10 to 31 => '0') & MHARTID(h);\n else\n csr_access_denied_o_replicated(h) <= '1';\n end if;\n when CSRRW|CSRRWI =>\n csr_access_denied_o_replicated(h) <= '1';\n when others =>\n null;\n end case;\n\n when MIRQ_addr => -- read only\n case csr_op_i is\n when CSRRC|CSRRS|CSRRCI|CSRRSI =>\n if(rs1(instr_word_IE) = 0) then\n csr_rdata_o_replicated(h) <= MIRQ(h);\n else\n csr_access_denied_o_replicated(h) <= '1';\n end if;\n when CSRRW|CSRRWI =>\n csr_access_denied_o_replicated(h) <= '1';\n when others =>\n null;\n end case;\n\n when BADADDR_addr => -- read only\n case csr_op_i is\n when CSRRC|CSRRS|CSRRCI|CSRRSI =>\n if(rs1(instr_word_IE) = 0) then\n csr_rdata_o_replicated(h) <= MBADADDR(h);\n else\n csr_access_denied_o_replicated(h) <= '1';\n end if;\n when CSRRW|CSRRWI =>\n csr_access_denied_o_replicated(h) <= '1';\n when others =>\n null;\n end case;\n\n when MCYCLE_addr =>\n if (MCYCLE_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MCYCLE(h);\n MCYCLE(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MCYCLE(h);\n if(rs1(instr_word_IE) /= 0) then\n MCYCLE(h) <= (MCYCLE(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MCYCLE(h);\n if(rs1(instr_word_IE) /= 0) then\n MCYCLE(h) <= (MCYCLE(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MCYCLEH_addr =>\n if (MCYCLE_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MCYCLEH(h);\n MCYCLEH(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MCYCLEH(h);\n if(rs1(instr_word_IE) /= 0) then\n MCYCLEH(h) <= (MCYCLEH(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MCYCLEH(h);\n if(rs1(instr_word_IE) /= 0) then\n MCYCLEH(h) <= (MCYCLEH(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MINSTRET_addr =>\n if (MINSTRET_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= std_logic_vector(unsigned(MINSTRET(h))-1); --old value in reading\n MINSTRET(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= std_logic_vector(unsigned(MINSTRET(h))-1);\n if(rs1(instr_word_IE) /= 0) then\n MINSTRET(h) <= (MINSTRET(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= std_logic_vector(unsigned(MINSTRET(h))-1);\n if(rs1(instr_word_IE) /= 0) then\n MINSTRET(h) <= (MINSTRET(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MINSTRETH_addr =>\n if (MINSTRET_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n if(MINSTRET(h) = x\"00000000\" and MINSTRETH(h) /= x\"00000000\") then\n csr_rdata_o_replicated(h) <= std_logic_vector(unsigned(MINSTRETH(h))-1);\n else\n csr_rdata_o_replicated(h) <= MINSTRETH(h);\n end if;\n MINSTRETH(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n if(MINSTRET(h) = x\"00000000\" and MINSTRETH(h) /= x\"00000000\") then\n csr_rdata_o_replicated(h) <= std_logic_vector(unsigned(MINSTRETH(h))-1);\n else\n csr_rdata_o_replicated(h) <= MINSTRETH(h);\n end if;\n if(rs1(instr_word_IE) /= 0) then\n MINSTRETH(h) <= (MINSTRETH(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n if(MINSTRET(h) = x\"00000000\" and MINSTRETH(h) /= x\"00000000\") then\n csr_rdata_o_replicated(h) <= std_logic_vector(unsigned(MINSTRETH(h))-1);\n else\n csr_rdata_o_replicated(h) <= MINSTRETH(h);\n end if;\n if(rs1(instr_word_IE) /= 0) then\n MINSTRETH(h) <= (MINSTRETH(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMCOUNTER3_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER3(h);\n MHPMCOUNTER3(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER3(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER3(h) <= (MHPMCOUNTER3(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER3(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER3(h) <= (MHPMCOUNTER3(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n\n when MHPMCOUNTER6_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER6(h);\n MHPMCOUNTER6(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER6(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER6(h) <= (MHPMCOUNTER6(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER6(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER6(h) <= (MHPMCOUNTER6(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMCOUNTER7_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER7(h);\n MHPMCOUNTER7(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER7(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER7(h) <= (MHPMCOUNTER7(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER7(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER7(h) <= (MHPMCOUNTER7(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMCOUNTER8_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER8(h);\n MHPMCOUNTER8(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER8(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER8(h) <= (MHPMCOUNTER8(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER8(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER8(h) <= (MHPMCOUNTER8(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMCOUNTER9_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER9(h);\n MHPMCOUNTER9(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER9(h);\n", "right_context": " null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMCOUNTER10_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER10(h);\n MHPMCOUNTER10(h) <= csr_wdata_i;\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER10(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER10(h) <= (MHPMCOUNTER10(h) or csr_wdata_i);\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= MHPMCOUNTER10(h);\n if(rs1(instr_word_IE) /= 0) then\n MHPMCOUNTER10(h) <= (MHPMCOUNTER10(h) and not(csr_wdata_i));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n\n when PCER_addr =>\n if (MHPMCOUNTER_EN = 1 or MCYCLE_EN = 1 or MINSTRET_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= PCER(h);\n PCER(h) <= csr_wdata_i;\n MHPMEVENT3(h) <= csr_wdata_i(2); \n MHPMEVENT6(h) <= csr_wdata_i(5);\n MHPMEVENT7(h) <= csr_wdata_i(6);\n MHPMEVENT8(h) <= csr_wdata_i(7);\n MHPMEVENT9(h) <= csr_wdata_i(8);\n MHPMEVENT10(h) <= csr_wdata_i(9);\n\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= PCER(h);\n if(rs1(instr_word_IE) /= 0) then\n PCER(h) <= (PCER(h) or csr_wdata_i);\n MHPMEVENT3(h) <= (PCER(h)(2) or csr_wdata_i(2));\n MHPMEVENT6(h) <= (PCER(h)(5) or csr_wdata_i(5));\n MHPMEVENT7(h) <= (PCER(h)(6) or csr_wdata_i(6));\n MHPMEVENT8(h) <= (PCER(h)(7) or csr_wdata_i(7));\n MHPMEVENT9(h) <= (PCER(h)(8) or csr_wdata_i(8));\n MHPMEVENT10(h) <= (PCER(h)(9) or csr_wdata_i(9));\n\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= PCER(h);\n if(rs1(instr_word_IE) /= 0) then\n PCER(h) <= (PCER(h) and not(csr_wdata_i));\n MHPMEVENT3(h) <= (PCER(h)(2) and not (csr_wdata_i(2)));\n MHPMEVENT6(h) <= (PCER(h)(5) and not (csr_wdata_i(5)));\n MHPMEVENT7(h) <= (PCER(h)(6) and not (csr_wdata_i(6)));\n MHPMEVENT8(h) <= (PCER(h)(7) and not (csr_wdata_i(7)));\n MHPMEVENT9(h) <= (PCER(h)(8) and not (csr_wdata_i(8)));\n MHPMEVENT10(h) <= (PCER(h)(9) and not (csr_wdata_i(9)));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMEVENT3_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (2 => MHPMEVENT3(h), others => '0');\n MHPMEVENT3(h) <= csr_wdata_i(2);\n PCER(h)(2) <= csr_wdata_i(2);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (2 => MHPMEVENT3(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT3(h) <= (MHPMEVENT3(h) or csr_wdata_i(2));\n PCER(h)(2) <= (PCER(h)(2) or csr_wdata_i(2));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (2 => MHPMEVENT3(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT3(h) <= (MHPMEVENT3(h) and not(csr_wdata_i(2)));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMEVENT6_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (5 => MHPMEVENT6(h), others => '0');\n MHPMEVENT6(h) <= csr_wdata_i(5);\n PCER(h)(5) <= csr_wdata_i(5);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (5 => MHPMEVENT6(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT6(h) <= (MHPMEVENT6(h) or csr_wdata_i(5));\n PCER(h)(5) <= (PCER(h)(5) or csr_wdata_i(5));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (5 => MHPMEVENT6(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT6(h) <= (MHPMEVENT6(h) and not(csr_wdata_i(5)));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if; \n\n when MHPMEVENT7_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (6 => MHPMEVENT7(h), others => '0');\n MHPMEVENT7(h) <= csr_wdata_i(6);\n PCER(h)(6) <= csr_wdata_i(6);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (6 => MHPMEVENT7(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT7(h) <= (MHPMEVENT7(h) or csr_wdata_i(6));\n PCER(h)(6) <= (PCER(h)(6) or csr_wdata_i(6));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (6 => MHPMEVENT7(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT7(h) <= (MHPMEVENT7(h) and not(csr_wdata_i(6)));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMEVENT8_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (7 => MHPMEVENT8(h), others => '0');\n MHPMEVENT8(h) <= csr_wdata_i(7);\n PCER(h)(7) <= csr_wdata_i(7);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (7 => MHPMEVENT8(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT8(h) <= (MHPMEVENT8(h) or csr_wdata_i(7));\n PCER(h)(7) <= (PCER(h)(7) or csr_wdata_i(7));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (7 => MHPMEVENT8(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT8(h) <= (MHPMEVENT8(h) and not(csr_wdata_i(7)));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMEVENT9_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (8 => MHPMEVENT9(h), others => '0');\n MHPMEVENT9(h) <= csr_wdata_i(8);\n PCER(h)(8) <= csr_wdata_i(8);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (8 => MHPMEVENT9(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT9(h) <= (MHPMEVENT9(h) or csr_wdata_i(8));\n PCER(h)(8) <= (PCER(h)(8) or csr_wdata_i(8));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (8 => MHPMEVENT9(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT9(h) <= (MHPMEVENT9(h) and not(csr_wdata_i(8)));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when MHPMEVENT10_addr =>\n if (MHPMCOUNTER_EN = 1) then\n case csr_op_i is\n when CSRRW|CSRRWI =>\n csr_rdata_o_replicated(h) <= (9 => MHPMEVENT10(h), others => '0');\n MHPMEVENT10(h) <= csr_wdata_i(9);\n PCER(h)(9) <= csr_wdata_i(9);\n when CSRRS|CSRRSI =>\n csr_rdata_o_replicated(h) <= (9 => MHPMEVENT10(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT10(h) <= (MHPMEVENT10(h) or csr_wdata_i(9));\n PCER(h)(9) <= (PCER(h)(9) or csr_wdata_i(9));\n end if;\n when CSRRC|CSRRCI =>\n csr_rdata_o_replicated(h) <= (9 => MHPMEVENT10(h), others => '0');\n if(rs1(instr_word_IE) /= 0) then\n MHPMEVENT10(h) <= (MHPMEVENT10(h) and not(csr_wdata_i(9)));\n end if;\n when others =>\n null;\n end case;\n else\n csr_rdata_o_replicated(h) <= (others => '0');\n end if;\n\n when others => -- invalid CSR address. ignored. May raise exception in future.\n csr_rdata_o_replicated(h) <= (others => '0'); -- unhandled situation\n -- default value\n end case;\n else\n null; -- invalid CSR operation, ignored. May raise exception in future.\n end if; -- csr_op_i\n end if; -- trap conditions, csr_instr_done, csr_instr_req\n\n ------------------------------------------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā• --\n ------------------------------------------------------------------------------------------------------------------------------------------------------ \n\n -- PERFORMANCE COUNTER AUTOMATIC UPDATING --\n\n if dbg_req_o = '0' then\n --THIS BIG CONDITION CHECKS WRITING TO THE CSR. IF A COUNTER IS WRITTEN, YOU DON'T HAVE TO INCREMENT IT.\n --The problems are only during writing on MCYCLE/H and MINSTRET/H or on any other counters that count csr instructions.\n\n if (MCYCLE_EN = 1) then\n if (PCER(h)(0) = '1'\n and not(csr_instr_req = '1'\n and (csr_addr_i = (MCYCLE_addr) or csr_addr_i = MCYCLEH_addr)\n and (csr_op_i = CSRRWI\n or csr_op_i = CSRRW\n or (csr_op_i = CSRRS and rs1(instr_word_IE) /= 0)\n or (csr_op_i = CSRRSI and rs1(instr_word_IE) /= 0)\n or (csr_op_i = CSRRC and rs1(instr_word_IE) /= 0)\n or (csr_op_i = CSRRCI and rs1(instr_word_IE) /= 0)))) then --cycle counter\n if harc_EXEC = h or count_all = 1 then -- count_all is bypass and enables counting regardless of the hart executing\n if(MCYCLE(h) = x\"FFFFFFFF\") then\n MCYCLEH(h) <= std_logic_vector(unsigned(MCYCLEH(h))+1);\n MCYCLE(h) <= x\"00000000\";\n else\n MCYCLE(h) <= std_logic_vector(unsigned(MCYCLE(h))+1);\n end if;\n end if;\n end if;\n end if;\n\n if (MINSTRET_EN = 1) then\n if (PCER(h)(1) = '1'\n and not(csr_instr_req = '1'\n and (csr_addr_i = (MINSTRET_addr) or csr_addr_i = MINSTRETH_addr)\n and (csr_op_i = CSRRWI\n or csr_op_i = CSRRW\n or (csr_op_i = CSRRS and rs1(instr_word_IE) /= 0)\n or (csr_op_i = CSRRSI and rs1(instr_word_IE) /= 0)\n or (csr_op_i = CSRRC and rs1(instr_word_IE) /= 0)\n or (csr_op_i = CSRRCI and rs1(instr_word_IE) /= 0)))) then --instruction counter\n if harc_EXEC = h or count_all = 1 then -- count_all is bypass and enables counting regardless of the hart executing \n if(instr_rvalid_IE = '1' ) then\n if (MINSTRET(h) = x\"FFFFFFFF\") then\n MINSTRETH(h) <= std_logic_vector(unsigned(MINSTRETH(h))+1);\n MINSTRET(h) <= x\"00000000\";\n else\n MINSTRET(h) <= std_logic_vector(unsigned(MINSTRET(h))+1);\n end if;\n end if;\n end if;\n end if;\n end if;\n\n if (PCER(h)(2) = '1') then --load/store access stall\n if (MHPMCOUNTER_EN = 1) then\n if (data_req_o = '1' and data_gnt_i = '0') then\n MHPMCOUNTER3(h) <= std_logic_vector(unsigned(MHPMCOUNTER3(h))+1);\n end if;\n end if;\n end if;\n\n if(PCER(h)(5) = '1') then --load access \n if (MHPMCOUNTER_EN = 1) then\n if harc_EXEC = h or count_all = 1 then -- count_all is bypass and enables counting regardless of the hart executing\n if (data_req_o = '1' and data_gnt_i = '1' and data_we_o = '0') then\n MHPMCOUNTER6(h) <= std_logic_vector(unsigned(MHPMCOUNTER6(h))+1);\n end if;\n end if;\n end if;\n end if;\n\n if(PCER(h)(6) = '1') then --store access \n if (MHPMCOUNTER_EN = 1) then\n if harc_EXEC = h or count_all = 1 then -- count_all is bypass and enables counting regardless of the hart executing\n if (data_req_o = '1' and data_gnt_i = '1' and data_we_o = '1') then\n MHPMCOUNTER7(h) <= std_logic_vector(unsigned(MHPMCOUNTER7(h))+1);\n end if;\n end if;\n end if;\n end if;\n\n if(PCER(h)(7) = '1') then --jump \n if (MHPMCOUNTER_EN = 1) then\n if harc_EXEC = h or count_all = 1 then -- count_all is bypass and enables counting regardless of the hart executing\n if (jump_instr = '1') then\n MHPMCOUNTER8(h) <= std_logic_vector(unsigned(MHPMCOUNTER8(h))+1);\n end if;\n end if;\n end if;\n end if;\n\n if(PCER(h)(8) = '1') then --branch \n if (MHPMCOUNTER_EN = 1) then\n if harc_EXEC = h or count_all = 1 then -- count_all is bypass and enables counting regardless of the hart executing\n if (branch_instr = '1') then\n MHPMCOUNTER9(h) <= std_logic_vector(unsigned(MHPMCOUNTER9(h))+1);\n end if;\n end if;\n end if;\n end if;\n\n if(PCER(h)(9) = '1') then --btaken\n if (MHPMCOUNTER_EN = 1) then\n if harc_EXEC = h or count_all = 1 then -- count_all is bypass and enables counting regardless of the hart executing\n if (branch_instr = '1' and set_branch_condition = '1') then\n MHPMCOUNTER10(h) <= std_logic_vector(unsigned(MHPMCOUNTER10(h))+1);\n end if;\n end if;\n end if;\n end if;\n\n end if; --debug_req_o='0'\n end if; -- reset or clk'event\n end process;\n\n end generate CSR_updating_logic;\n -- end of replicated logic ------------------------------------------------------------\n\n--here we OR the signals coming from different CS logic replicas\n process(all)\n variable wire1, wire2 : std_logic;\n begin\n wire1 := '0'; wire2 := '0';\n for h in harc_range loop\n wire1 := wire1 or csr_instr_done_replicated(h);\n wire2 := wire2 or csr_access_denied_o_replicated(h);\n end loop;\n csr_instr_done <= wire1;\n csr_access_denied_o <= wire2;\n end process;\n\n-- this is a mux choosing the csr data output corresponding to the actual harc executed\n csr_rdata_o <= csr_rdata_o_replicated(harc_EXEC);\n\n\n-- small fsm using the served_irq signals coming from different PC updating logic replicas\n-- to operate on the irq_ack signals \n irq_ack_manager : process(clk_i, rst_ni)\n variable wire1 : std_logic;\n begin\n if rst_ni = '0' then\n irq_ack_o_internal <= '0';\n elsif rising_edge(clk_i) then\n wire1 := '0';\n for h in harc_range loop\n wire1 := wire1 or served_irq(h);\n end loop;\n case irq_ack_o_internal is\n when '0' =>\n if wire1 = '0' then\n irq_ack_o_internal <= '0';\n else\n irq_ack_o_internal <= '1';\n irq_id_o <= irq_id_i;\n end if;\n when '1' =>\n irq_ack_o_internal <= '0';\n when others => null;\n end case;\n end if;\n end process irq_ack_manager;\n\n------------------------------------------------------------------------ end of CSE Unit ---------\n-------------------------------------------------------------------------------------------------- \n\nend CSR;\n--------------------------------------------------------------------------------------------------\n-- END of CSR Unit architecture -----------------------------------------------------------------\n--------------------------------------------------------------------------------------------------\n", "groundtruth": " if(rs1(instr_word_IE) /= 0) then\r\n MHPMCOUNTER9(h) <= (MHPMCOUNTER9(h) or csr_wdata_i);\r\n end if;\r\n when CSRRC|CSRRCI =>\r\n csr_rdata_o_replicated(h) <= MHPMCOUNTER9(h);\r\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-DSP_Unit.vhd", "left_context": "----------------------------------------------------------------------------------------------------------\n-- DSP Unit(s) -- --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 02-04-2020 --\n----------------------------------------------------------------------------------------------------------\n-- The DSP unit executes on vectors fetched from local-low-latency-wide-bus scratchpad memories. --\n-- The DSP has five functional units, adder/subtractor, multiplier, right arith/logic shifter, --\n-- accumulator, and ReLu each of which supports three integer data types (8-bit, 16-bit and 32-bits) --\n-- The data parallelism of the DSP is defined by the SIMD parameter in the PKG file. Increasing the --\n-- data level parallelism increasess the number of banks per SPM as well, as the number of functional --\n-- units. To increase the instruction level parallelism, the replicated_accl_en parameter must be --\n-- set. Setting it will provide a dedicated hardware accelerator for each hart, --\n-- Custom CSRs are implemented for the accelerator unit --\n----------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages -----------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n-- DSP pinout --------------------\nentity DSP_Unit is\n generic(\n THREAD_POOL_SIZE : natural;\n accl_en : natural;\n replicate_accl_en : natural;\n multithreaded_accl_en : natural;\n SPM_NUM : natural; \n Addr_Width : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n FU_NUM : natural;\n TPS_CEIL : natural;\n TPS_BUF_CEIL : natural;\n SPM_ADDR_WID : natural;\n SIMD_BITS : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n port (\n -- Core Signals\n clk_i, rst_ni : in std_logic;\n -- Processing Pipeline Signals\n rs1_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rs2_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rd_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n -- CSR Signals\n MVSIZE : in array_2d(THREAD_POOL_SIZE-1 downto 0)(Addr_Width downto 0);\n MVTYPE : in array_2d(THREAD_POOL_SIZE-1 downto 0)(3 downto 0);\n MPSCLFAC : in array_2d(THREAD_POOL_SIZE-1 downto 0)(4 downto 0);\n dsp_except_data : out array_2d(ACCL_NUM-1 downto 0)(31 downto 0);\n -- Program Counter Signals\n dsp_taken_branch : out std_logic_vector(ACCL_NUM-1 downto 0);\n dsp_except_condition : out std_logic_vector(ACCL_NUM-1 downto 0);\n -- ID_Stage Signals\n decoded_instruction_DSP : in std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0);\n harc_EXEC : in natural range THREAD_POOL_SIZE-1 downto 0;\n pc_IE : in std_logic_vector(31 downto 0);\n RS1_Data_IE : in std_logic_vector(31 downto 0);\n RS2_Data_IE : in std_logic_vector(31 downto 0);\n RD_Data_IE : in std_logic_vector(Addr_Width -1 downto 0);\n dsp_instr_req : in std_logic_vector(ACCL_NUM-1 downto 0);\n spm_rs1 : in std_logic;\n spm_rs2 : in std_logic;\n vec_read_rs1_ID : in std_logic;\n vec_read_rs2_ID : in std_logic;\n vec_write_rd_ID : in std_logic;\n busy_dsp : out std_logic_vector(ACCL_NUM-1 downto 0);\n -- Scratchpad Interface Signals\n dsp_data_gnt_i : in std_logic_vector(ACCL_NUM-1 downto 0);\n dsp_sci_wr_gnt : in std_logic_vector(ACCL_NUM-1 downto 0);\n dsp_sc_data_read : in array_3d(ACCL_NUM-1 downto 0)(1 downto 0)(SIMD_Width-1 downto 0);\n dsp_we_word : out array_2d(ACCL_NUM-1 downto 0)(SIMD-1 downto 0);\n dsp_sc_read_addr : out array_3d(ACCL_NUM-1 downto 0)(1 downto 0)(Addr_Width-1 downto 0);\n dsp_to_sc : out array_3d(ACCL_NUM-1 downto 0)(SPM_NUM-1 downto 0)(1 downto 0);\n dsp_sc_data_write_wire : out array_2d(ACCL_NUM-1 downto 0)(SIMD_Width-1 downto 0);\n dsp_sc_write_addr : out array_2d(ACCL_NUM-1 downto 0)(Addr_Width-1 downto 0);\n dsp_sci_we : out array_2d(ACCL_NUM-1 downto 0)(SPM_NUM-1 downto 0);\n dsp_sci_req : out array_2d(ACCL_NUM-1 downto 0)(SPM_NUM-1 downto 0);\n -- tracer signals\n state_DSP : out array_2d(ACCL_NUM-1 downto 0)(1 downto 0)\n\n );\nend entity; ------------------------------------------\n\n\narchitecture DSP of DSP_Unit is\n\n subtype harc_range is natural range THREAD_POOL_SIZE-1 downto 0;\n subtype accl_range is integer range ACCL_NUM-1 downto 0;\n subtype fu_range is integer range FU_NUM-1 downto 0;\n\n\n signal nextstate_DSP : array_2d(accl_range)(1 downto 0);\n\n -- Virtual Parallelism Signals\n signal cmp_en : std_logic_vector(accl_range); -- enables the use of the shifters\n signal shift_en : std_logic_vector(accl_range); -- enables the use of the shifters\n signal add_en : std_logic_vector(accl_range); -- enables the use of the adders\n signal mul_en : std_logic_vector(accl_range); -- enables the use of the multipliers\n signal accum_en : std_logic_vector(accl_range); -- enables the use of the accumulator\n signal cmp_en_wire : std_logic_vector(accl_range); -- enables the use of the shifters\n signal shift_en_wire : std_logic_vector(accl_range); -- enables the use of the shifters\n signal add_en_wire : std_logic_vector(accl_range); -- enables the use of the adders\n signal mul_en_wire : std_logic_vector(accl_range); -- enables the use of the multipliers\n signal accum_en_wire : std_logic_vector(accl_range); -- enables the use of the accumulatorss\n signal add_en_pending_wire : std_logic_vector(accl_range); -- signal to preserve the request to access the adder \"multhithreaded mode\" only\n signal shift_en_pending_wire : std_logic_vector(accl_range); -- signal to preserve the request to access the shifter \"multhithreaded mode\" only\n signal mul_en_pending_wire : std_logic_vector(accl_range); -- signal to preserve the request to access the multiplier \"multhithreaded mode\" only\n signal accum_en_pending_wire : std_logic_vector(accl_range); -- signal to preserve the request to access the accumulator \"multhithreaded mode\" only\n signal cmp_en_pending_wire : std_logic_vector(accl_range); -- signal to preserve the request to access the ReLU \"multhithreaded mode\" only\n signal add_en_pending : std_logic_vector(accl_range); -- signal to preserve the request to access the adder \"multhithreaded mode\" only\n signal shift_en_pending : std_logic_vector(accl_range); -- signal to preserve the request to access the shifter \"multhithreaded mode\" only\n signal mul_en_pending : std_logic_vector(accl_range); -- signal to preserve the request to access the multiplier \"multhithreaded mode\" only\n signal accum_en_pending : std_logic_vector(accl_range); -- signal to preserve the request to access the accumulator \"multhithreaded mode\" only\n signal cmp_en_pending : std_logic_vector(accl_range); -- signal to preserve the request to access the ReLU \"multhithreaded mode\" only\n signal busy_add : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_mul : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_shf : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_acc : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_cmp : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_add_wire : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_mul_wire : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_shf_wire : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_acc_wire : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal busy_cmp_wire : std_logic; -- busy signal active only when the FU is shared and currently in use \n signal halt_hart : std_logic_vector(accl_range); -- halts the thread when the requested functional unit is in use\n signal fu_req : array_2D(accl_range)(4 downto 0); -- Each threa has request bits equal to the total number of FUs\n signal fu_gnt : array_2D(accl_range)(4 downto 0); -- Each threa has grant bits equal to the total number of FUs\n signal fu_gnt_wire : array_2D(accl_range)(4 downto 0); -- Each threa has grant bits equal to the total number of FUs\n signal fu_gnt_en : array_2D(accl_range)(4 downto 0); -- Enable the giving of the grant to the thread pointed at by the issue buffer\n signal fu_rd_ptr : array_2D(4 downto 0)(TPS_BUF_CEIL-1 downto 0); -- five rd pointers each has a number of bits equal to ceil(log2(THREAD_POOL_SIZE-1))\n signal fu_wr_ptr : array_2D(4 downto 0)(TPS_BUF_CEIL-1 downto 0); -- five rd pointers each has a number of bits equal to ceil(log2(THREAD_POOL_SIZE-1))\n -- five buffers for each FU times the \"TPS-1\" and not \"TPS\" since there is always one thread active, and not needing a buffer. Each buffer hold the thread_ID \"TPS_CEIL\"\n signal fu_issue_buffer : array_3D(4 downto 0)(THREAD_POOL_SIZE-2 downto 0)(TPS_CEIL-1 downto 0);\n\n -- Functional Unit Ports ---\n --signal dsp_in_sign_bits : array_2d(accl_range)(4*SIMD-1 downto 0); -- vivado unsynthesizable, but more efficient alternative\n signal dsp_in_shifter_operand : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_in_shifter_operand_lat : array_2d(fu_range)(SIMD_Width-1 downto 0); -- 15 bits because i only want to latch the signed bits\n signal dsp_in_shifter_operand_lat_wire : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_int_shifter_operand : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_out_shifter_results : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_in_cmp_operands : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_in_mul_operands : array_3d(fu_range)(1 downto 0)(SIMD_Width-1 downto 0);\n signal dsp_out_mul_results : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_out_cmp_results : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_in_accum_operands : array_2d(fu_range)(SIMD_Width-1 downto 0);\n signal dsp_out_accum_results : array_2d(fu_range)(31 downto 0);\n signal dsp_in_adder_operands : array_3d(fu_range)(1 downto 0)(SIMD_Width-1 downto 0);\n signal dsp_in_adder_operands_lat : array_3d(fu_range)(1 downto 0)(SIMD_Width/2 -1 downto 0); -- data_Width devided by the number of pipeline stages\n signal dsp_out_adder_results : array_2d(fu_range)(SIMD_Width-1 downto 0);\n\n signal carry_8_wire : array_2d(fu_range)(SIMD-1 downto 0); -- carry-out bit of the \"dsp_add_8_0\" signal\n signal carry_16_wire : array_2d(fu_range)(SIMD-1 downto 0); -- carry-out bit of the \"dsp_add_16_8\" signal\n signal carry_16 : array_2d(fu_range)(SIMD-1 downto 0); -- carry-out bit of the \"dsp_add_16_8\" signal\n signal carry_24_wire : array_2d(fu_range)(SIMD-1 downto 0); -- carry-out bit of the \"dsp_add_24_16\" signal\n signal dsp_add_8_0 : array_3d(fu_range)(SIMD-1 downto 0)(8 downto 0); -- 9-bits, contains the results of 8-bit adders\n signal dsp_add_16_8 : array_3d(fu_range)(SIMD-1 downto 0)(8 downto 0); -- 9-bits contains the results of 8-bit adders\n signal dsp_add_8_0_wire : array_3d(fu_range)(SIMD-1 downto 0)(8 downto 0); -- 9-bits, contains the results of 8-bit adders\n signal dsp_add_16_8_wire : array_3d(fu_range)(SIMD-1 downto 0)(8 downto 0); -- 9-bits contains the results of 8-bit adders\n signal dsp_add_24_16_wire : array_3d(fu_range)(SIMD-1 downto 0)(8 downto 0); -- 9-bits contains the results of 8-bit adders\n signal dsp_add_32_24_wire : array_3d(fu_range)(SIMD-1 downto 0)(8 downto 0); -- 9-bits, this should be 8 if we choose to discard the overflow of the addition of the upper byte\n signal mul_tmp_a : array_3d(fu_range)(SIMD-1 downto 0)(Data_Width-1 downto 0);\n signal mul_tmp_b : array_3d(fu_range)(SIMD-1 downto 0)(Data_Width-1 downto 0);\n signal mul_tmp_c : array_3d(fu_range)(SIMD-1 downto 0)(Data_Width-1 downto 0);\n signal mul_tmp_d : array_3d(fu_range)(SIMD-1 downto 0)(Data_Width-1 downto 0);\n signal dsp_mul_a : array_2d(fu_range)(SIMD_Width -1 downto 0); -- Contains the results of the 16-bit multipliers\n signal dsp_mul_b : array_2d(fu_range)(SIMD_Width -1 downto 0); -- Contains the results of the 16-bit multipliers\n signal dsp_mul_c : array_2d(fu_range)(SIMD_Width -1 downto 0); -- Contains the results of the 16-bit multipliers\n signal dsp_mul_d : array_2d(fu_range)(SIMD_Width -1 downto 0); -- Contains the results of the 16-bit multipliers\n\n signal carry_pass : array_2d(accl_range)(2 downto 0); -- carry enable signal, depending on it's configuration, we can do KADDV8, KADDV16, KADDV32\n signal FUNCT_SELECT_MASK : array_2d(accl_range)(31 downto 0); -- when the mask is set to \"FFFFFFFF\" we enable KDOTP32 execution using the 16-bit muls\n signal twos_complement : array_2d(accl_range)(31 downto 0);\n signal dsp_shift_enabler : array_2d(accl_range)(15 downto 0);\n signal dsp_in_shift_amount : array_2d(accl_range)(4 downto 0);\n\n signal dsp_sc_data_write_wire_int : array_2d(accl_range)(SIMD_Width-1 downto 0);\n signal dsp_sc_data_write_int : array_2d(accl_range)(SIMD_Width-1 downto 0);\n\n signal MVTYPE_DSP : array_2d(accl_range)(1 downto 0);\n signal vec_write_rd_DSP : std_logic_vector(accl_range); -- Indicates whether the result being written is a vector or a scalar\n signal vec_read_rs1_DSP : std_logic_vector(accl_range); -- Indicates whether the operand being read is a vector or a scalar\n signal vec_read_rs2_DSP : std_logic_vector(accl_range); -- Indicates whether the operand being read is a vector or a scalar\n signal dotp : std_logic_vector(accl_range); -- indicator used in the pipeline handler to switch functional units\n signal dotpps : std_logic_vector(accl_range); -- indicator used in the pipeline handler to switch functional units\n signal slt : std_logic_vector(accl_range); -- indicator used in the pipeline handler to switch functional units\n signal wb_ready : std_logic_vector(accl_range);\n signal halt_dsp : std_logic_vector(accl_range);\n signal halt_dsp_lat : std_logic_vector(accl_range);\n signal recover_state : std_logic_vector(accl_range);\n signal recover_state_wires : std_logic_vector(accl_range);\n signal dsp_data_gnt_i_lat : std_logic_vector(accl_range);\n signal shifter_stage_1_en : std_logic_vector(accl_range);\n signal shifter_stage_2_en : std_logic_vector(accl_range);\n signal shifter_stage_3_en : std_logic_vector(accl_range);\n signal adder_stage_1_en : std_logic_vector(accl_range);\n signal adder_stage_2_en : std_logic_vector(accl_range);\n signal adder_stage_3_en : std_logic_vector(accl_range);\n signal mul_stage_1_en : std_logic_vector(accl_range);\n signal mul_stage_2_en : std_logic_vector(accl_range);\n signal mul_stage_3_en : std_logic_vector(accl_range);\n signal cmp_stage_1_en : std_logic_vector(accl_range);\n signal cmp_stage_2_en : std_logic_vector(accl_range);\n signal accum_stage_1_en : std_logic_vector(accl_range);\n signal accum_stage_2_en : std_logic_vector(accl_range);\n signal accum_stage_3_en : std_logic_vector(accl_range);\n signal dsp_except_data_wire : array_2d(accl_range)(31 downto 0);\n signal MSB_stage_1 : array_3d(accl_range)(1 downto 0)(4*SIMD-1 downto 0);\n signal MSB_stage_2 : array_3d(accl_range)(1 downto 0)(4*SIMD-1 downto 0);\n signal MSB_stage_3 : array_3d(accl_range)(1 downto 0)(4*SIMD-1 downto 0);\n\n signal decoded_instruction_DSP_lat : array_2d(accl_range)(DSP_UNIT_INSTR_SET_SIZE -1 downto 0);\n signal overflow_rs1_sc : array_2d(accl_range)(Addr_Width downto 0);\n signal overflow_rs2_sc : array_2d(accl_range)(Addr_Width downto 0);\n signal overflow_rd_sc : array_2d(accl_range)(Addr_Width downto 0);\n signal dsp_rs1_to_sc : array_2d(accl_range)(SPM_ADDR_WID-1 downto 0);\n signal dsp_rs2_to_sc : array_2d(accl_range)(SPM_ADDR_WID-1 downto 0);\n signal dsp_rd_to_sc : array_2d(accl_range)(SPM_ADDR_WID-1 downto 0);\n signal dsp_sc_data_read_mask : array_2d(accl_range)(SIMD_Width-1 downto 0);\n signal RS1_Data_IE_lat : array_2d(accl_range)(31 downto 0);\n signal RS2_Data_IE_lat : array_2d(accl_range)(31 downto 0);\n signal RD_Data_IE_lat : array_2d(accl_range)(Addr_Width -1 downto 0);\n signal MVSIZE_READ : array_2d(accl_range)(Addr_Width downto 0); -- Bytes remaining to read\n signal MVSIZE_READ_MASK : array_2d(accl_range)(Addr_Width downto 0); -- Bytes remaining to read\n signal MVSIZE_WRITE : array_2d(accl_range)(Addr_Width downto 0); -- Bytes remaining to write\n signal MPSCLFAC_DSP : array_2d(accl_range)(4 downto 0);\n signal busy_dsp_internal : std_logic_vector(accl_range);\n signal busy_DSP_internal_lat : std_logic_vector(accl_range);\n signal rf_rs2 : std_logic_vector(accl_range);\n signal relu_instr : std_logic_vector(accl_range);\n signal SIMD_RD_BYTES_wire : array_2d_int(accl_range);\n signal SIMD_RD_BYTES : array_2d_int(accl_range);\n\n component ACCUMULATOR\n generic(\n multithreaded_accl_en : natural;\n SIMD : natural;\n ---------------------------------------------------------\n ACCL_NUM : natural;\n FU_NUM : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n port(\n clk_i : in std_logic;\n rst_ni : in std_logic;\n MVTYPE_DSP : in array_2d(accl_range)(1 downto 0);\n accum_stage_1_en : in std_logic_vector(accl_range);\n accum_stage_2_en : in std_logic_vector(accl_range);\n recover_state_wires : in std_logic_vector(accl_range);\n halt_dsp_lat : in std_logic_vector(accl_range);\n state_DSP : in array_2d(accl_range)(1 downto 0);\n decoded_instruction_DSP_lat : in array_2d(accl_range)(DSP_UNIT_INSTR_SET_SIZE -1 downto 0);\n dsp_in_accum_operands : in array_2d(fu_range)(SIMD_Width-1 downto 0);\n dsp_out_accum_results : out array_2d(fu_range)(31 downto 0)\n );\n end component;\n\n--------------------------------------------------------------------------------------------------\n-------------------------------- DSP BEGIN -------------------------------------------------------\nbegin\n\n\n busy_dsp <= busy_dsp_internal;\n\n DSP_replicated : for h in accl_range generate\n\n\n ------------ Sequential Stage of DSP Unit -------------------------------------------------------------------------\n DSP_Exec_Unit : process(clk_i, rst_ni) -- single cycle unit, fully synchronous \n begin\n if rst_ni = '0' then\n relu_instr(h) <= '0';\n rf_rs2(h) <= '0';\n dotpps(h) <= '0';\n dotp(h) <= '0';\n slt(h) <= '0';\n recover_state(h) <= '0';\n elsif rising_edge(clk_i) then\n if dsp_instr_req(h) = '1' or busy_DSP_internal_lat(h) = '1' then \n\n case state_DSP(h) is\n\n when dsp_init =>\n\n -------------------------------------------------------------\n -- ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• -- \n -------------------------------------------------------------\n\n FUNCT_SELECT_MASK(h) <= (others => '0');\n twos_complement(h) <= (others => '0');\n relu_instr(h) <= '0';\n rf_rs2(h) <= '0';\n dotpps(h) <= '0';\n dotp(h) <= '0';\n slt(h) <= '0';\n -- Set signals to enable correct virtual parallelism operation\n if (decoded_instruction_DSP(KADDV_bit_position) = '1' or \n decoded_instruction_DSP(KSVADDSC_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n carry_pass(h) <= \"111\"; -- pass all carry_outs\n elsif decoded_instruction_DSP(KSVADDRF_bit_position) = '1' and \n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n carry_pass(h) <= \"111\"; -- pass all carry_outs\n rf_rs2(h) <= '1';\n elsif (decoded_instruction_DSP(KADDV_bit_position) = '1' or\n decoded_instruction_DSP(KSVADDSC_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then\n carry_pass(h) <= \"101\"; -- pass carrries 9, and 25\n elsif decoded_instruction_DSP(KSVADDRF_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then\n carry_pass(h) <= \"101\"; -- pass carrries 9, and 25\n rf_rs2(h) <= '1';\n elsif (decoded_instruction_DSP(KADDV_bit_position) = '1' or\n decoded_instruction_DSP(KSVADDSC_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"00\" then\n carry_pass(h) <= \"000\"; -- don't pass carry_outs and keep addition 8-bit\n elsif decoded_instruction_DSP(KSVADDRF_bit_position) = '1' and \n MVTYPE(harc_EXEC)(3 downto 2) = \"00\" then\n carry_pass(h) <= \"000\"; -- don't pass carry_outs and keep addition 8-bit\n rf_rs2(h) <= '1';\n elsif (decoded_instruction_DSP(KSUBV_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n carry_pass(h) <= \"111\"; -- pass all carry_outs\n twos_complement(h) <= \"00010001000100010001000100010001\";\n elsif (decoded_instruction_DSP(KSUBV_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then\n carry_pass(h) <= \"101\"; -- pass carrries 9, and 25\n twos_complement(h) <= \"01010101010101010101010101010101\";\n elsif (decoded_instruction_DSP(KSUBV_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"00\" then\n carry_pass(h) <= \"000\"; -- don't pass carry_outs and keep addition 8-bit\n twos_complement(h) <= \"11111111111111111111111111111111\";\n elsif (decoded_instruction_DSP(KVSLT_bit_position) = '1' or\n decoded_instruction_DSP(KSVSLT_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n carry_pass(h) <= \"111\"; -- pass all carry_outs\n twos_complement(h) <= \"00010001000100010001000100010001\";\n slt(h) <= '1';\n elsif (decoded_instruction_DSP(KVSLT_bit_position) = '1' or\n decoded_instruction_DSP(KSVSLT_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then\n carry_pass(h) <= \"101\"; -- pass carrries 9, and 25\n twos_complement(h) <= \"01010101010101010101010101010101\";\n slt(h) <= '1';\n elsif (decoded_instruction_DSP(KVSLT_bit_position) = '1' or\n decoded_instruction_DSP(KSVSLT_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"00\" then\n carry_pass(h) <= \"000\"; -- don't pass carry_outs and keep addition 8-bit\n twos_complement(h) <= \"11111111111111111111111111111111\";\n slt(h) <= '1';\n elsif decoded_instruction_DSP(KDOTP_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n -- KDOTP32 does not use the adders of KADDV instructions but rather adds the mul_acc results using it's own adders\n FUNCT_SELECT_MASK(h) <= (others => '1'); -- This enables 32-bit multiplication with the 16-bit multipliers\n dotp(h) <= '1';\n elsif decoded_instruction_DSP(KDOTP_bit_position) = '1' and \n MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then\n dotp(h) <= '1';\n elsif decoded_instruction_DSP(KDOTP_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"00\" then\n dotp(h) <= '1';\n elsif decoded_instruction_DSP(KDOTPPS_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n FUNCT_SELECT_MASK(h) <= (others => '1'); -- This enables 32-bit multiplication with the 16-bit multipliers\n dotpps(h) <= '1';\n elsif decoded_instruction_DSP(KDOTPPS_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then\n dotpps(h) <= '1';\n elsif decoded_instruction_DSP(KDOTPPS_bit_position) = '1' and \n MVTYPE(harc_EXEC)(3 downto 2) = \"00\" then\n dotpps(h) <= '1';\n elsif decoded_instruction_DSP(KSVMULRF_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n FUNCT_SELECT_MASK(h) <= (others => '1');\n rf_rs2(h) <= '1';\n elsif decoded_instruction_DSP(KSVMULRF_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then\n rf_rs2(h) <= '1';\n elsif decoded_instruction_DSP(KSVMULRF_bit_position) = '1' and\n MVTYPE(harc_EXEC)(3 downto 2) = \"00\" then\n rf_rs2(h) <= '1';\n elsif (decoded_instruction_DSP(KVMUL_bit_position) = '1' or\n decoded_instruction_DSP(KSVMULSC_bit_position) = '1') and\n MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then\n FUNCT_SELECT_MASK(h) <= (others => '1');\n elsif decoded_instruction_DSP(KRELU_bit_position) = '1' then\n relu_instr(h) <= '1';\n end if;\n\n -- We backup data from decode stage since they will get updated\n\n MVSIZE_READ_MASK(h) <= MVSIZE(harc_EXEC);\n MVSIZE_WRITE(h) <= MVSIZE(harc_EXEC);\n MPSCLFAC_DSP(h) <= MPSCLFAC(harc_EXEC);\n MVTYPE_DSP(h) <= MVTYPE(harc_EXEC)(3 downto 2);\n decoded_instruction_DSP_lat(h) <= decoded_instruction_DSP;\n vec_write_rd_DSP(h) <= vec_write_rd_ID;\n vec_read_rs1_DSP(h) <= vec_read_rs1_ID;\n vec_read_rs2_DSP(h) <= vec_read_rs2_ID;\n dsp_rs1_to_sc(h) <= rs1_to_sc;\n dsp_rs2_to_sc(h) <= rs2_to_sc;\n dsp_rd_to_sc(h) <= rd_to_sc;\n RD_Data_IE_lat(h) <= RD_Data_IE;\n -- Increment the read addresses\n if dsp_data_gnt_i(h) = '1' then\n if vec_read_rs1_ID = '1' then\n RS1_Data_IE_lat(h) <= std_logic_vector(unsigned(RS1_Data_IE) + SIMD_RD_BYTES_wire(h)); -- source 1 address increment\n else\n RS1_Data_IE_lat(h) <= RS1_Data_IE;\n end if;\n if vec_read_rs2_ID = '1' then\n RS2_Data_IE_lat(h) <= std_logic_vector(unsigned(RS2_Data_IE) + SIMD_RD_BYTES_wire(h)); -- source 2 address increment\n else\n RS2_Data_IE_lat(h) <= RS2_Data_IE;\n end if;\n -- Decrement the vector elements that have already been operated on\n if unsigned(MVSIZE(harc_EXEC)) >= SIMD_RD_BYTES_wire(h) then\n MVSIZE_READ(h) <= std_logic_vector(unsigned(MVSIZE(harc_EXEC)) - SIMD_RD_BYTES_wire(h)); -- decrement by SIMD_BYTE Execution Capability\n else\n MVSIZE_READ(h) <= (others => '0'); -- decrement the remaining bytes\n end if;\n else\n RS1_Data_IE_lat(h) <= RS1_Data_IE;\n RS2_Data_IE_lat(h) <= RS2_Data_IE;\n MVSIZE_READ(h) <= MVSIZE(harc_EXEC);\n end if;\n -------------------------------------------------------------------------------\n\n when dsp_exec =>\n recover_state(h) <= recover_state_wires(h);\n if halt_dsp(h) = '1' and halt_dsp_lat(h) = '0' then\n dsp_sc_data_write_int(h) <= dsp_sc_data_write_wire_int(h);\n end if;\n\n\n --------------------------------------------------------------------------\n -- ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•šā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā• -- \n --------------------------------------------------------------------------\n\n if halt_dsp(h) = '0' then\n -- Increment the write address when we have a result as a vector\n if vec_write_rd_DSP(h) = '1' and wb_ready(h) = '1' then\n RD_Data_IE_lat(h) <= std_logic_vector(unsigned(RD_Data_IE_lat(h)) + SIMD_RD_BYTES_wire(h)); -- destination address increment\n end if;\n if wb_ready(h) = '1' then\n if to_integer(unsigned(MVSIZE_WRITE(h))) >= SIMD_RD_BYTES_wire(h) then\n MVSIZE_WRITE(h) <= std_logic_vector(unsigned(MVSIZE_WRITE(h)) - SIMD_RD_BYTES_wire(h)); -- decrement by SIMD_BYTE Execution Capability \n else\n MVSIZE_WRITE(h) <= (others => '0'); -- decrement the remaining bytes\n end if;\n end if;\n -- Increment the read addresses\n if to_integer(unsigned(MVSIZE_READ(h))) >= SIMD_RD_BYTES_wire(h) and dsp_data_gnt_i(h) = '1' then -- Increment the addresses untill all the vector elements are operated fetched\n if vec_read_rs1_DSP(h) = '1' then\n RS1_Data_IE_lat(h) <= std_logic_vector(unsigned(RS1_Data_IE_lat(h)) + SIMD_RD_BYTES_wire(h)); -- source 1 address increment\n end if;\n if vec_read_rs2_DSP(h) = '1' then\n RS2_Data_IE_lat(h) <= std_logic_vector(unsigned(RS2_Data_IE_lat(h)) + SIMD_RD_BYTES_wire(h)); -- source 2 address increment\n end if;\n end if;\n -- Decrement the vector elements that have already been operated on\n if dsp_data_gnt_i(h) = '1' then\n if to_integer(unsigned(MVSIZE_READ(h))) >= SIMD_RD_BYTES_wire(h) then\n MVSIZE_READ(h) <= std_logic_vector(unsigned(MVSIZE_READ(h)) - SIMD_RD_BYTES_wire(h)); -- decrement by SIMD_BYTE Execution Capability\n else\n MVSIZE_READ(h) <= (others => '0'); -- decrement the remaining bytes\n end if;\n end if;\n dsp_sc_data_read_mask(h) <= (others => '0');\n if dsp_data_gnt_i_lat(h) = '1' then\n if to_integer(unsigned(MVSIZE_READ_MASK(h))) >= SIMD_RD_BYTES_wire(h) then\n dsp_sc_data_read_mask(h) <= (others => '1');\n MVSIZE_READ_MASK(h) <= std_logic_vector(unsigned(MVSIZE_READ_MASK(h)) - SIMD_RD_BYTES_wire(h)); -- decrement by SIMD_BYTE Execution Capability \n else\n MVSIZE_READ_MASK(h) <= (others => '0');\n dsp_sc_data_read_mask(h)(to_integer(unsigned(MVSIZE_READ_MASK(h)))*8 - 1 downto 0) <= (others => '1');\n end if;\n end if;\n end if;\n\n when others =>\n null;\n end case;\n end if;\n end if;\n end process;\n\n ------------ Combinational Stage of DSP Unit ----------------------------------------------------------------------\n DSP_Excpt_Cntrl_Unit_comb : process(all)\n \n variable busy_DSP_internal_wires : std_logic;\n variable dsp_except_condition_wires : std_logic_vector(harc_range);\n variable dsp_taken_branch_wires : std_logic_vector(harc_range); \n \n begin\n\n busy_DSP_internal_wires := '0';\n dsp_except_condition_wires(h) := '0';\n dsp_taken_branch_wires(h) := '0';\n wb_ready(h) <= '0';\n halt_dsp(h) <= '0';\n nextstate_DSP(h) <= dsp_init;\n recover_state_wires(h) <= recover_state(h);\n dsp_except_data_wire(h) <= dsp_except_data(h);\n overflow_rs1_sc(h) <= (others => '0');\n overflow_rs2_sc(h) <= (others => '0');\n overflow_rd_sc(h) <= (others => '0');\n dsp_we_word(h) <= (others => '0');\n dsp_sci_req(h) <= (others => '0');\n dsp_sci_we(h) <= (others => '0');\n dsp_sc_write_addr(h) <= (others => '0');\n dsp_sc_read_addr(h) <= (others => (others => '0'));\n dsp_to_sc(h) <= (others => (others => '0'));\n\n if dsp_instr_req(h) = '1' or busy_DSP_internal_lat(h) = '1' then\n case state_DSP(h) is\n\n when dsp_init =>\n\n ---------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ -- \n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•”ā• ā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• --\n ---------------------------------------------------------------------------------------------------------------------\n\n overflow_rs1_sc(h) <= std_logic_vector('0' & unsigned(RS1_Data_IE(Addr_Width -1 downto 0)) + unsigned(MVSIZE(harc_EXEC)) -1);\n overflow_rs2_sc(h) <= std_logic_vector('0' & unsigned(RS2_Data_IE(Addr_Width -1 downto 0)) + unsigned(MVSIZE(harc_EXEC)) -1);\n overflow_rd_sc(h) <= std_logic_vector('0' & unsigned(RD_Data_IE(Addr_Width -1 downto 0)) + unsigned(MVSIZE(harc_EXEC)) -1);\n if MVSIZE(harc_EXEC) = (0 to Addr_Width => '0') then\n null;\n elsif MVSIZE(harc_EXEC)(1 downto 0) /= \"00\" and MVTYPE(harc_EXEC)(3 downto 2) = \"10\" then -- Set exception if the number of bytes are not divisible by four\n dsp_except_condition_wires(h) := '1';\n dsp_taken_branch_wires(h) := '1'; \n dsp_except_data_wire(h) <= ILLEGAL_VECTOR_SIZE_EXCEPT_CODE;\n elsif MVSIZE(harc_EXEC)(0) /= '0' and MVTYPE(harc_EXEC)(3 downto 2) = \"01\" then -- Set exception if the number of bytes are not divisible by two\n dsp_except_condition_wires(h) := '1';\n dsp_taken_branch_wires(h) := '1';\n dsp_except_data_wire(h) <= ILLEGAL_VECTOR_SIZE_EXCEPT_CODE;\n elsif (rs1_to_sc = \"100\" and vec_read_rs1_ID = '1') or\n (rs2_to_sc = \"100\" and vec_read_rs2_ID = '1') or\n rd_to_sc = \"100\" then -- Set exception for non scratchpad access\n dsp_except_condition_wires(h) := '1';\n dsp_taken_branch_wires(h) := '1'; \n dsp_except_data_wire(h) <= ILLEGAL_ADDRESS_EXCEPT_CODE;\n elsif rs1_to_sc = rs2_to_sc and vec_read_rs1_ID = '1' and vec_read_rs2_ID = '1' then -- Set exception for same read access\n dsp_except_condition_wires(h) := '1';\n dsp_taken_branch_wires(h) := '1'; \n dsp_except_data_wire(h) <= READ_SAME_SCARTCHPAD_EXCEPT_CODE; \n elsif (overflow_rs1_sc(h)(Addr_Width) = '1' and vec_read_rs1_ID = '1') or (overflow_rs2_sc(h)(Addr_Width) = '1' and vec_read_rs2_ID = '1') then -- Set exception if reading overflows the scratchpad's address\n dsp_except_condition_wires(h) := '1';\n dsp_taken_branch_wires(h) := '1'; \n dsp_except_data_wire(h) <= SCRATCHPAD_OVERFLOW_EXCEPT_CODE;\n elsif overflow_rd_sc(h)(Addr_Width) = '1' and vec_write_rd_ID = '1' then -- Set exception if reading overflows the scratchpad's address, scalar writes are excluded\n dsp_except_condition_wires(h) := '1';\n dsp_taken_branch_wires(h) := '1'; \n dsp_except_data_wire(h) <= SCRATCHPAD_OVERFLOW_EXCEPT_CODE;\n else\n if halt_hart(h) = '0' then\n nextstate_DSP(h) <= dsp_exec;\n else\n nextstate_DSP(h) <= dsp_halt_hart;\n end if;\n busy_DSP_internal_wires := '1';\n end if;\n\n if rs1_to_sc /= \"100\" and spm_rs1 = '1' and halt_hart(h) = '0' then\n dsp_sci_req(h)(to_integer(unsigned(rs1_to_sc))) <= '1';\n dsp_to_sc(h)(to_integer(unsigned(rs1_to_sc)))(0) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE(Addr_Width-1 downto 0);\n end if;\n if rs2_to_sc /= \"100\" and spm_rs2 = '1' and rs1_to_Sc /= rs2_to_sc and halt_hart(h) = '0' then -- Do not send a read request if the second operand accesses the same spm as the first, \n dsp_sci_req(h)(to_integer(unsigned(rs2_to_sc))) <= '1';\n dsp_to_sc(h)(to_integer(unsigned(rs2_to_sc)))(1) <= '1';\n dsp_sc_read_addr(h)(1) <= RS2_Data_IE(Addr_Width-1 downto 0);\n end if;\n \n when dsp_halt_hart =>\n\n if halt_hart(h) = '0' then\n nextstate_DSP(h) <= dsp_exec;\n else\n nextstate_DSP(h) <= dsp_halt_hart;\n end if;\n busy_DSP_internal_wires := '1';\n\n when dsp_exec =>\n\n -----------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• --\n -----------------------------------------------------------------------------------------------------------------------\n\n ------ SMP BANK ENABLER --------------------------------------------------------------------------------------------------\n -- the following enables the appropriate banks to write the SIMD output, depending whether the result is a vector or a --\n -- scalar, and adjusts the enabler appropriately based on the SIMD size. If the bytes to write are greater than SIMD*4 --\n -- then all banks are enabaled, else we perform the selective bank enabling as shown below under the 'elsif' clause --\n --------------------------------------------------------------------------------------------------------------------------\n\n if (dsp_sci_wr_gnt(h) = '0' and wb_ready(h) = '1') then\n halt_dsp(h) <= '1';\n recover_state_wires(h) <= '1';\n elsif unsigned(MVSIZE_WRITE(h)) <= SIMD_RD_BYTES(h) then\n recover_state_wires(h) <= '0';\n end if;\n\n if vec_write_rd_DSP(h) = '1' and dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) = '1' then\n if unsigned(MVSIZE_WRITE(h)) >= (SIMD)*4+1 then -- \n dsp_we_word(h) <= (others => '1');\n elsif unsigned(MVSIZE_WRITE(h)) >= 1 then\n for i in 0 to SIMD-1 loop\n if i <= to_integer(unsigned(MVSIZE_WRITE(h))-1)/4 then -- Four because of the number of bytes per word\n if to_integer(unsigned(dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0))/4 + i) < SIMD then\n dsp_we_word(h)(to_integer(unsigned(dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0))/4 + i)) <= '1';\n elsif to_integer(unsigned(dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0))/4 + i) >= SIMD then\n dsp_we_word(h)(to_integer(unsigned(dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0))/4 + i - SIMD)) <= '1';\n end if;\n end if;\n end loop;\n end if;\n elsif vec_write_rd_DSP(h) = '0' and dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) = '1' then\n dsp_we_word(h)(to_integer(unsigned(dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0))/4)) <= '1';\n end if;\n -------------------------------------------------------------------------------------------------------------------------\n\n\n if decoded_instruction_DSP_lat(h)(KBCAST_bit_position) = '1' then\n -- KBCAST signals are handeled here\n if MVSIZE_WRITE(h) > (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n wb_ready(h) <= '1';\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KVCP_bit_position) = '1' then\n -- KVCP signals are handeled here\n if adder_stage_3_en(h) = '1' then\n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1'; \n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n if MVSIZE_WRITE(h) > (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KRELU_bit_position) = '1' then\n -- KRELU signals are handeled here\n if cmp_stage_2_en(h) = '1' then\n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1'; \n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n if MVSIZE_WRITE(h) > (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KVSLT_bit_position) = '1' then\n -- KADDV and KSUBV signals are handeled here\n if cmp_stage_2_en(h) = '1' then\n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1'; \n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs2_to_sc(h))))(1) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs2_to_sc(h)))) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n dsp_sc_read_addr(h)(1) <= RS2_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n if MVSIZE_WRITE(h) > (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVSLT_bit_position) = '1' then\n -- KADDV and KSUBV signals are handeled here\n if cmp_stage_2_en(h) = '1' then\n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1'; \n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n if MVSIZE_WRITE(h) > (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSRAV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSRLV_bit_position) = '1' then\n -- KSRAV signals are handeled here\n if shifter_stage_3_en(h) = '1' then\n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1'; \n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n if MVSIZE_WRITE(h) > (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KADDV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSUBV_bit_position) = '1' then\n -- KADDV and KSUBV signals are handeled here\n if adder_stage_3_en(h) = '1' then\n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1'; \n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs2_to_sc(h))))(1) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs2_to_sc(h)))) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n dsp_sc_read_addr(h)(1) <= RS2_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n if MVSIZE_WRITE(h) > (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n \n if decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' then\n -- KDOTP signals are handeled here\n if accum_stage_3_en(h) = '1' then\n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1'; \n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n if vec_read_rs2_DSP(h) = '1' then\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs2_to_sc(h)))) <= '1';\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs2_to_sc(h))))(1) <= '1';\n dsp_sc_read_addr(h)(1) <= RS2_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n elsif MVSIZE_WRITE(h) = (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_init;\n else\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVADDSC_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVADDRF_bit_position) = '1' then\n -- KMUL signals are handeled here\n if mul_stage_3_en(h) = '1' or adder_stage_3_en(h) = '1' then \n wb_ready(h) <= '1';\n elsif recover_state(h) = '1' then\n wb_ready(h) <= '1';\n end if;\n if MVSIZE_READ(h) > (0 to Addr_Width => '0') then\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs1_to_sc(h)))) <= '1';\n if rf_rs2(h) = '0' then -- if the scalar does not come from the regfile\n dsp_sci_req(h)(to_integer(unsigned(dsp_rs2_to_sc(h)))) <= '1';\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs2_to_sc(h))))(1) <= '1';\n dsp_sc_read_addr(h)(1) <= RS2_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n end if;\n dsp_to_sc(h)(to_integer(unsigned(dsp_rs1_to_sc(h))))(0) <= '1';\n dsp_sc_read_addr(h)(0) <= RS1_Data_IE_lat(h)(Addr_Width - 1 downto 0);\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n elsif MVSIZE_WRITE(h) = (0 to Addr_Width => '0') then\n nextstate_DSP(h) <= dsp_init;\n else\n nextstate_DSP(h) <= dsp_exec;\n busy_DSP_internal_wires := '1';\n end if;\n if wb_ready(h) = '1' then\n dsp_sci_we(h)(to_integer(unsigned(dsp_rd_to_sc(h)))) <= '1';\n dsp_sc_write_addr(h) <= RD_Data_IE_lat(h);\n end if;\n end if;\n\n when others =>\n null;\n end case;\n end if;\n \n busy_DSP_internal(h) <= busy_DSP_internal_wires;\n dsp_except_condition(h) <= dsp_except_condition_wires(h);\n dsp_taken_branch(h) <= dsp_taken_branch_wires(h);\n \n end process;\n\n ---------------------------------------------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n ---------------------------------------------------------------------------------------------------------------------------------------------------------\n\n fsm_DSP_pipeline_controller : process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n dsp_data_gnt_i_lat(h) <= '0';\n adder_stage_1_en(h) <= '0';\n adder_stage_2_en(h) <= '0';\n adder_stage_3_en(h) <= '0';\n shifter_stage_1_en(h) <= '0';\n shifter_stage_2_en(h) <= '0';\n mul_stage_1_en(h) <= '0';\n mul_stage_2_en(h) <= '0';\n mul_stage_3_en(h) <= '0';\n accum_stage_1_en(h) <= '0';\n accum_stage_2_en(h) <= '0';\n accum_stage_3_en(h) <= '0';\n cmp_stage_1_en(h) <= '0';\n cmp_stage_2_en(h) <= '0';\n busy_DSP_internal_lat(h) <= '0';\n state_DSP(h) <= dsp_init;\n elsif rising_edge(clk_i) then\n dsp_data_gnt_i_lat(h) <= dsp_data_gnt_i(h);\n adder_stage_1_en(h) <= dsp_data_gnt_i_lat(h) and add_en(h);\n adder_stage_2_en(h) <= adder_stage_1_en(h);\n adder_stage_3_en(h) <= adder_stage_2_en(h);\n mul_stage_1_en(h) <= dsp_data_gnt_i_lat(h) and mul_en(h);\n mul_stage_2_en(h) <= mul_stage_1_en(h);\n mul_stage_3_en(h) <= mul_stage_2_en(h);\n accum_stage_2_en(h) <= accum_stage_1_en(h);\n accum_stage_3_en(h) <= accum_stage_2_en(h);\n shifter_stage_2_en(h) <= shifter_stage_1_en(h);\n shifter_stage_3_en(h) <= shifter_stage_2_en(h);\n cmp_stage_2_en(h) <= cmp_stage_1_en(h);\n if dotpps(h) = '1' then\n shifter_stage_1_en(h) <= mul_stage_2_en(h);\n accum_stage_1_en(h) <= shifter_stage_2_en(h);\n elsif dotp(h) = '1' then\n accum_stage_1_en(h) <= mul_stage_2_en(h);\n elsif slt(h) = '1' then\n cmp_stage_1_en(h) <= adder_stage_2_en(h);\n else\n shifter_stage_1_en(h) <= dsp_data_gnt_i_lat(h) and shift_en(h);\n accum_stage_1_en(h) <= dsp_data_gnt_i_lat(h) and accum_en(h);\n cmp_stage_1_en(h) <= dsp_data_gnt_i_lat(h) and cmp_en(h);\n end if;\n halt_dsp_lat(h) <= halt_dsp(h);\n state_DSP(h) <= nextstate_DSP(h);\n busy_DSP_internal_lat(h) <= busy_DSP_internal(h);\n SIMD_RD_BYTES(h) <= SIMD_RD_BYTES_wire(h);\n dsp_except_data(h) <= dsp_except_data_wire(h);\n end if;\n end process;\n\n DSP_FU_ENABLER_SYNC : process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n shift_en(h) <= '0'; \n add_en(h) <= '0'; \n cmp_en(h) <= '0';\n accum_en(h) <= '0'; \n mul_en(h) <= '0';\n add_en_pending(h) <= '0';\n shift_en_pending(h) <= '0';\n mul_en_pending(h) <= '0';\n accum_en_pending(h) <= '0';\n cmp_en_pending(h) <= '0';\n elsif rising_edge(clk_i) then\n shift_en(h) <= shift_en_wire(h); \n add_en(h) <= add_en_wire(h); \n cmp_en(h) <= cmp_en_wire(h); \n accum_en(h) <= accum_en_wire(h); \n mul_en(h) <= mul_en_wire(h); \n add_en_pending(h) <= add_en_pending_wire(h);\n shift_en_pending(h) <= shift_en_pending_wire(h);\n mul_en_pending(h) <= mul_en_pending_wire(h);\n accum_en_pending(h) <= accum_en_pending_wire(h);\n cmp_en_pending(h) <= cmp_en_pending_wire(h);\n end if;\n\n end process;\n\nend generate DSP_replicated;\n\n -------------------------------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n -------------------------------------------------------------------------------------------------------------------------------------------\n\nFU_HANDLER_MC : if multithreaded_accl_en = 0 generate\n DSP_FU_ENABLER_comb : process(all)\n begin\n for h in accl_range loop\n shift_en_wire(h) <= shift_en(h); \n add_en_wire(h) <= add_en(h); \n cmp_en_wire(h) <= cmp_en(h); \n accum_en_wire(h) <= accum_en(h); \n mul_en_wire(h) <= mul_en(h); \n halt_hart(h) <= '0';\n\n if add_en(h) = '1' and busy_DSP_internal(h) = '0' then\n add_en_wire(h) <= '0';\n end if;\n if mul_en(h) = '1' and busy_DSP_internal(h) = '0' then\n mul_en_wire(h) <= '0';\n end if;\n if shift_en(h) = '1' and busy_DSP_internal(h) = '0' then\n shift_en_wire(h) <= '0';\n end if;\n if accum_en(h) = '1' and busy_DSP_internal(h) = '0' then\n accum_en_wire(h) <= '0';\n end if;\n if cmp_en(h) = '1' and busy_DSP_internal(h) = '0' then\n cmp_en_wire(h) <= '0';\n end if;\n\n if dsp_instr_req(h) = '1' or busy_DSP_internal_lat(h) = '1' then\n\n case state_DSP(h) is\n\n when dsp_init =>\n\n -- Set signals to enable correct virtual parallelism operation\n if decoded_instruction_DSP(KADDV_bit_position) = '1' or \n decoded_instruction_DSP(KSVADDSC_bit_position) = '1' or\n decoded_instruction_DSP(KSVADDRF_bit_position) = '1' or\n decoded_instruction_DSP(KSUBV_bit_position) = '1' or\n decoded_instruction_DSP(KVCP_bit_position) = '1' then\n add_en_wire(h) <= '1';\n elsif decoded_instruction_DSP(KDOTP_bit_position) = '1' then\n mul_en_wire(h) <= '1';\n accum_en_wire(h) <= '1';\n elsif decoded_instruction_DSP(KDOTPPS_bit_position) = '1' then\n mul_en_wire(h) <= '1';\n shift_en_wire(h) <= '1';\n accum_en_wire(h) <= '1';\n elsif decoded_instruction_DSP(KVSLT_bit_position) = '1' or\n decoded_instruction_DSP(KSVSLT_bit_position) = '1' then\n add_en_wire(h) <= '1';\n cmp_en_wire(h) <= '1';\n elsif decoded_instruction_DSP(KVRED_bit_position) = '1' then\n accum_en_wire(h) <= '1';\n elsif decoded_instruction_DSP(KSVMULRF_bit_position) = '1' or\n decoded_instruction_DSP(KSVMULSC_bit_position) = '1' or\n decoded_instruction_DSP(KVMUL_bit_position) = '1' then\n mul_en_wire(h) <= '1';\n elsif decoded_instruction_DSP(KSRAV_bit_position) = '1' or\n decoded_instruction_DSP(KSRLV_bit_position) = '1' then\n shift_en_wire(h) <= '1';\n elsif decoded_instruction_DSP(KRELU_bit_position) = '1' then\n cmp_en_wire(h) <= '1';\n end if;\n when others =>\n null;\n end case;\n end if;\n end loop;\n end process;\nend generate FU_HANDLER_MC;\n\nFU_HANDLER_MT : if multithreaded_accl_en = 1 generate\n DSP_FU_ENABLER_comb : process(all)\n begin\n\n for h in accl_range loop\n\n shift_en_wire(h) <= shift_en(h); \n add_en_wire(h) <= add_en(h); \n cmp_en_wire(h) <= cmp_en(h); \n accum_en_wire(h) <= accum_en(h); \n mul_en_wire(h) <= mul_en(h); \n add_en_pending_wire(h) <= add_en_pending(h);\n shift_en_pending_wire(h) <= shift_en_pending(h);\n mul_en_pending_wire(h) <= mul_en_pending(h);\n accum_en_pending_wire(h) <= accum_en_pending(h);\n cmp_en_pending_wire(h) <= cmp_en_pending(h);\n fu_req(h) <= (others => '0');\n halt_hart(h) <= '0';\n\n\n if add_en(h) = '1' and busy_DSP_internal(h) = '0' then\n add_en_wire(h) <= '0';\n end if;\n if mul_en(h) = '1' and busy_DSP_internal(h) = '0' then\n mul_en_wire(h) <= '0';\n end if;\n if shift_en(h) = '1' and busy_DSP_internal(h) = '0' then\n shift_en_wire(h) <= '0';\n end if;\n if accum_en(h) = '1' and busy_DSP_internal(h) = '0' then\n accum_en_wire(h) <= '0';\n end if;\n if cmp_en(h) = '1' and busy_DSP_internal(h) = '0' then\n cmp_en_wire(h) <= '0';\n end if;\n\n if dsp_instr_req(h) = '1' or busy_DSP_internal_lat(h) = '1' then\n\n case state_DSP(h) is\n\n when dsp_init =>\n\n -- Set signals to enable correct virtual parallelism operation\n if decoded_instruction_DSP(KADDV_bit_position) = '1' or \n decoded_instruction_DSP(KSVADDSC_bit_position) = '1' or\n decoded_instruction_DSP(KSVADDRF_bit_position) = '1' or\n decoded_instruction_DSP(KSUBV_bit_position) = '1' or\n decoded_instruction_DSP(KVCP_bit_position) = '1' then\n if busy_add = '0' and add_en_pending = (accl_range => '0') then \n add_en_wire(h) <= '1';\n else\n add_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(0) <= '1';\n end if;\n elsif decoded_instruction_DSP(KDOTP_bit_position) = '1' then\n if busy_mul = '0' and busy_acc = '0' and mul_en_pending = (accl_range => '0') and accum_en_pending = (accl_range => '0') then \n mul_en_wire(h) <= '1';\n accum_en_wire(h) <= '1';\n else\n mul_en_pending_wire(h) <= '1';\n accum_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(2) <= '1';\n fu_req(h)(3) <= '1';\n end if;\n elsif decoded_instruction_DSP(KDOTPPS_bit_position) = '1' then\n if busy_mul = '0' and busy_acc = '0' and busy_shf = '0' and mul_en_pending = (accl_range => '0') and accum_en_pending = (accl_range => '0') and shift_en_pending = (accl_range => '0') then \n mul_en_wire(h) <= '1';\n shift_en_wire(h) <= '1';\n accum_en_wire(h) <= '1';\n else\n mul_en_pending_wire(h) <= '1';\n shift_en_pending_wire(h) <= '1';\n accum_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(2) <= '1';\n fu_req(h)(1) <= '1';\n fu_req(h)(3) <= '1';\n end if;\n elsif decoded_instruction_DSP(KVRED_bit_position) = '1' then\n if busy_acc = '0' and accum_en_pending = (accl_range => '0') then \n accum_en_wire(h) <= '1';\n else\n accum_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(3) <= '1';\n end if;\n elsif decoded_instruction_DSP(KSVMULRF_bit_position) = '1' or\n decoded_instruction_DSP(KSVMULSC_bit_position) = '1' or\n decoded_instruction_DSP(KVMUL_bit_position) = '1' then\n if busy_mul = '0' and mul_en_pending = (accl_range => '0') then \n mul_en_wire(h) <= '1';\n else\n mul_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(2) <= '1';\n end if;\n elsif decoded_instruction_DSP(KSRAV_bit_position) = '1' or\n decoded_instruction_DSP(KSRLV_bit_position) = '1' then\n if busy_shf = '0' and shift_en_pending = (accl_range => '0') then \n shift_en_wire(h) <= '1';\n else\n shift_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(1) <= '1';\n end if;\n elsif decoded_instruction_DSP(KRELU_bit_position) = '1' then\n if busy_cmp = '0' and cmp_en_pending = (accl_range => '0') then \n cmp_en_wire(h) <= '1';\n else\n cmp_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(4) <= '1';\n end if;\n elsif decoded_instruction_DSP(KVSLT_bit_position) = '1' or\n decoded_instruction_DSP(KSVSLT_bit_position) = '1' then\n if busy_cmp = '0' and busy_add = '0' and cmp_en_pending = (accl_range => '0') and add_en_pending = (accl_range => '0') then \n add_en_wire(h) <= '1';\n cmp_en_wire(h) <= '1';\n else\n add_en_pending_wire(h) <= '1';\n cmp_en_pending_wire(h) <= '1';\n halt_hart(h) <= '1';\n fu_req(h)(0) <= '1';\n fu_req(h)(4) <= '1';\n end if;\n end if;\n\n when dsp_halt_hart =>\n \n if fu_gnt(h)(0) = '1' then\n add_en_wire(h) <= '1';\n add_en_pending_wire(h) <= '0';\n elsif add_en_pending(h) = '1' and fu_gnt(h)(0) = '0' then\n halt_hart(h) <= '1';\n end if;\n\n if fu_gnt(h)(1) = '1' then\n shift_en_wire(h) <= '1';\n shift_en_pending_wire(h) <= '0';\n elsif shift_en_pending(h) = '1' and fu_gnt(h)(1) = '0' then\n halt_hart(h) <= '1';\n end if;\n\n if fu_gnt(h)(2) = '1' then\n mul_en_wire(h) <= '1';\n mul_en_pending_wire(h) <= '0';\n elsif mul_en_pending(h) = '1' and fu_gnt(h)(2) = '0' then\n halt_hart(h) <= '1';\n end if;\n\n if fu_gnt(h)(3) = '1' then\n accum_en_wire(h) <= '1';\n accum_en_pending_wire(h) <= '0';\n elsif accum_en_pending(h) = '1' and fu_gnt(h)(3) = '0' then\n halt_hart(h) <= '1';\n end if;\n\n if fu_gnt(h)(4) = '1' then\n cmp_en_wire(h) <= '1';\n cmp_en_pending_wire(h) <= '0';\n elsif cmp_en_pending(h) = '1' and fu_gnt(h)(4) = '0' then\n halt_hart(h) <= '1';\n end if;\n\n when others =>\n null;\n end case;\n end if;\n end loop;\n end process;\n\n FU_Issue_Buffer_sync : process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n fu_rd_ptr <= (others => (others => '0'));\n fu_wr_ptr <= (others => (others => '0'));\n fu_gnt <= (others => (others => '0'));\n elsif rising_edge(clk_i) then\n fu_gnt <= fu_gnt_wire;\n for h in accl_range loop\n for i in 0 to 4 loop -- Loop index 'i' is for the total number of different functional units (regardless what SIMD config is set)\n if fu_req(h)(i) = '1' then -- if a reservation was made, to use a functional unit\n --to_integer(unsigned(fu_issue_buffer(i)(to_integer(unsigned(fu_wr_ptr(i)))))) <= h; -- store the thread_ID in its corresponding buffer at the fu_wr_ptr position\n --fu_issue_buffer(to_integer(unsigned(fu_wr_ptr(i))))(i) <= std_logic_vector(unsigned(h)); -- store the thread_ID in its corresponding buffer at the fu_wr_ptr position\n fu_issue_buffer(i)(to_integer(unsigned(fu_wr_ptr(i)))) <= std_logic_vector(to_unsigned(h,TPS_CEIL));\n if unsigned(fu_wr_ptr(i)) = THREAD_POOL_SIZE - 2 then -- increment the pointer wr logic\n fu_wr_ptr(i) <= (others => '0');\n else\n fu_wr_ptr(i) <= std_logic_vector(unsigned(fu_wr_ptr(i)) + 1);\n end if;\n end if;\n case state_DSP(h) is\n when dsp_halt_hart =>\n if fu_gnt_en(h)(i) = '1' then\n if unsigned(fu_rd_ptr(i)) = THREAD_POOL_SIZE - 2 then -- increment the read pointer\n fu_rd_ptr(i) <= (others => '0');\n else\n fu_rd_ptr(i) <= std_logic_vector(unsigned(fu_rd_ptr(i)) + 1);\n end if;\n end if;\n when others =>\n null;\n end case;\n end loop;\n end loop;\n end if;\n end process;\n\n FU_Issue_Buffer_comb : process(all)\n begin\n for h in accl_range loop\n fu_gnt_wire(h) <= (others => '0');\n fu_gnt_en(h) <= (others => '0');\n if add_en_pending_wire(h) = '1' and busy_add_wire = '0' then\n fu_gnt_en(h)(0) <= '1';\n end if;\n if shift_en_pending_wire(h) = '1' and busy_shf_wire = '0' then\n fu_gnt_en(h)(1) <= '1';\n end if;\n if mul_en_pending_wire(h) = '1' and busy_mul_wire = '0' then\n fu_gnt_en(h)(2) <= '1';\n end if;\n if accum_en_pending_wire(h) = '1' and busy_acc_wire = '0' then\n fu_gnt_en(h)(3) <= '1';\n end if;\n if cmp_en_pending_wire(h) = '1' and busy_cmp_wire = '0' then\n fu_gnt_en(h)(4) <= '1';\n end if;\n case state_DSP(h) is\n when dsp_halt_hart =>\n for i in 0 to 4 loop \n if fu_gnt_en(h)(i) = '1' then\n fu_gnt_wire(to_integer(unsigned(fu_issue_buffer(i)(to_integer(unsigned(fu_rd_ptr(i)))))))(i) <= '1'; -- give a grant to fu_gnt(h)(i), such that the 'h' index points to the thread in \"fu_issue_buffer\"\n end if;\n end loop;\n when others =>\n null;\n end case;\n end loop;\n end process;\n\n\n DSP_BUSY_FU_SYNC : process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n busy_add <= busy_add_wire;\n busy_mul <= busy_mul_wire;\n busy_shf <= busy_shf_wire;\n busy_acc <= busy_acc_wire;\n busy_cmp <= busy_cmp_wire;\n end if;\n end process;\n\nend generate FU_HANDLER_MT;\n\nbusy_add_wire <= '1' when multithreaded_accl_en = 1 and add_en_wire /= (accl_range => '0') else '0';\nbusy_mul_wire <= '1' when multithreaded_accl_en = 1 and mul_en_wire /= (accl_range => '0') else '0';\nbusy_shf_wire <= '1' when multithreaded_accl_en = 1 and shift_en_wire /= (accl_range => '0') else '0';\nbusy_acc_wire <= '1' when multithreaded_accl_en = 1 and accum_en_wire /= (accl_range => '0') else '0';\nbusy_cmp_wire <= '1' when multithreaded_accl_en = 1 and cmp_en_wire /= (accl_range => '0') else '0';\n\n\n -----------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• --\n -----------------------------------------------------------------\n\nMULTICORE_OUT_MAPPER : if multithreaded_accl_en = 0 generate\nMAPPER_replicated : for h in fu_range generate\n\n MAPPING_OUT_UNIT_comb : process(all)\n begin\n dsp_sc_data_write_wire_int(h) <= (others => '0');\n dsp_sc_data_write_wire(h) <= dsp_sc_data_write_wire_int(h);\n SIMD_RD_BYTES_wire(h) <= SIMD*(Data_Width/8);\n\n if dsp_instr_req(h) = '1' or busy_DSP_internal_lat(h) = '1' then\n case state_DSP(h) is\n when dsp_init =>\n\n -- Set signals to enable correct virtual parallelism operation\n if (decoded_instruction_DSP(KDOTP_bit_position) = '1' or\n decoded_instruction_DSP(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP(KVRED_bit_position) = '1' or\n decoded_instruction_DSP(KSVMULRF_bit_position) = '1' or\n decoded_instruction_DSP(KVMUL_bit_position) = '1' or\n decoded_instruction_DSP(KSVMULSC_bit_position) = '1') and \n MVTYPE(h)(3 downto 2) = \"00\" then\n SIMD_RD_BYTES_wire(h) <= SIMD*(Data_Width/8)/2;\n end if; \n\n when dsp_exec =>\n\n -- Set signals to enable correct virtual parallelism operation\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"00\") then\n SIMD_RD_BYTES_wire(h) <= SIMD*(Data_Width/8)/2;\n end if; \n\n if decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h)(31 downto 0) <= dsp_out_accum_results(h); -- AAA add a mask in order to store the lower half word when 16-bit or entire word when 32-bit\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 2*SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(7+8*(i) downto 8*(i)) <= dsp_out_mul_results(h)(7+8*(2*i) downto 8*(2*i));\n end loop;\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"10\") then\n dsp_sc_data_write_wire_int(h) <= dsp_out_mul_results(h);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSRAV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSRLV_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h) <= dsp_out_shifter_results(h);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDSC_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVADDRF_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KADDV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSUBV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVCP_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h) <= dsp_out_adder_results(h);\n end if;\n\n\n if decoded_instruction_DSP_lat(h)(KRELU_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVSLT_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVSLT_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h) <= dsp_out_cmp_results(h);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KBCAST_bit_position) = '1' and MVTYPE_DSP(h) = \"10\" then\n for i in 0 to SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(31+32*(i) downto 32*(i)) <= RS1_Data_IE_lat(h);\n end loop;\n elsif decoded_instruction_DSP_lat(h)(KBCAST_bit_position) = '1' and MVTYPE_DSP(h) = \"01\" then\n for i in 0 to 2*SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(15+16*(i) downto 16*(i)) <= RS1_Data_IE_lat(h)(15 downto 0);\n end loop;\n elsif decoded_instruction_DSP_lat(h)(KBCAST_bit_position) = '1' and MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 4*SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(7+8*(i) downto 8*(i)) <= RS1_Data_IE_lat(h)(7 downto 0);\n end loop;\n end if;\n\n if halt_dsp(h) = '0' and halt_dsp_lat(h) = '1' then\n dsp_sc_data_write_wire(h) <= dsp_sc_data_write_int(h);\n end if;\n when others =>\n null;\n end case;\n end if;\n end process;\n\nend generate;\nend generate;\n\nMULTITHREAD_OUT_MAPPER : if multithreaded_accl_en = 1 generate\n MAPPING_OUT_UNIT_comb : process(all)\n begin\n for h in 0 to (ACCL_NUM - FU_NUM) loop\n dsp_sc_data_write_wire_int(h) <= (others => '0');\n dsp_sc_data_write_wire(h) <= dsp_sc_data_write_wire_int(h);\n SIMD_RD_BYTES_wire(h) <= SIMD*(Data_Width/8);\n\n if dsp_instr_req(h) = '1' or busy_DSP_internal_lat(h) = '1' then\n case state_DSP(h) is\n when dsp_init =>\n\n -- Set signals to enable correct virtual parallelism operation\n if (decoded_instruction_DSP(KDOTP_bit_position) = '1' or\n decoded_instruction_DSP(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP(KVRED_bit_position) = '1' or\n decoded_instruction_DSP(KSVMULRF_bit_position) = '1' or\n decoded_instruction_DSP(KVMUL_bit_position) = '1' or\n decoded_instruction_DSP(KSVMULSC_bit_position) = '1') and\n MVTYPE(h)(3 downto 2) = \"00\" then\n SIMD_RD_BYTES_wire(h) <= SIMD*(Data_Width/8)/2;\n end if; \n\n when dsp_exec =>\n\n -- Set signals to enable correct virtual parallelism operation\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n MVTYPE_DSP(h) = \"00\" then\n SIMD_RD_BYTES_wire(h) <= SIMD*(Data_Width/8)/2;\n end if; \n\n if decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h)(31 downto 0) <= dsp_out_accum_results(0); -- AAA add a mask in order to store the lower half word when 16-bit or entire word when 32-bit\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 2*SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(7+8*(i) downto 8*(i)) <= dsp_out_mul_results(0)(7+8*(2*i) downto 8*(2*i));\n end loop;\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"10\") then\n dsp_sc_data_write_wire_int(h) <= dsp_out_mul_results(0);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSRAV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSRLV_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h) <= dsp_out_shifter_results(0);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDSC_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVADDRF_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KADDV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSUBV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVCP_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h) <= dsp_out_adder_results(0);\n end if;\n\n\n if decoded_instruction_DSP_lat(h)(KRELU_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KVSLT_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSVSLT_bit_position) = '1' then\n dsp_sc_data_write_wire_int(h) <= dsp_out_cmp_results(0);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KBCAST_bit_position) = '1' and MVTYPE_DSP(h) = \"10\" then\n for i in 0 to SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(31+32*(i) downto 32*(i)) <= RS1_Data_IE_lat(h);\n end loop;\n elsif decoded_instruction_DSP_lat(h)(KBCAST_bit_position) = '1' and MVTYPE_DSP(h) = \"01\" then\n for i in 0 to 2*SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(15+16*(i) downto 16*(i)) <= RS1_Data_IE_lat(h)(15 downto 0);\n end loop;\n elsif decoded_instruction_DSP_lat(h)(KBCAST_bit_position) = '1' and MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 4*SIMD-1 loop\n dsp_sc_data_write_wire_int(h)(7+8*(i) downto 8*(i)) <= RS1_Data_IE_lat(h)(7 downto 0);\n end loop;\n end if;\n\n if halt_dsp(h) = '0' and halt_dsp_lat(h) = '1' then\n dsp_sc_data_write_wire(h) <= dsp_sc_data_write_int(h);\n end if;\n when others =>\n null;\n end case;\n end if;\n end loop;\n end process;\nend generate;\n\n--FU_IN_MAPPER_replicated : for f in accl_range generate\n--FU_IN_MAPPER : if (multithreaded_accl_en = 0 or (multithreaded_accl_en = 1 and f = 0)) generate\n\nFU_replicated : for f in fu_range generate\n\n DSP_MAPPING_IN_UNIT_comb : process(all)\n variable h : integer;\n begin\n\n MSB_stage_1(f) <= (others => (others => '0')); \n dsp_in_mul_operands(f) <= (others => (others => '0'));\n dsp_in_adder_operands(f) <= (others => (others => '0'));\n dsp_in_shift_amount(f) <= (others => '0');\n dsp_in_shifter_operand(f) <= (others => '0');\n dsp_in_accum_operands(f) <= (others => '0');\n dsp_in_cmp_operands(f) <= (others => '0');\n\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n\n if dsp_instr_req(h) = '1' or busy_DSP_internal_lat(h) = '1' then\n case state_DSP(h) is\n\n when dsp_exec =>\n\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1') and\n MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 2*SIMD-1 loop\n dsp_in_mul_operands(f)(0)(15+16*(i) downto 16*(i)) <= (x\"00\" & (dsp_sc_data_read(h)(0)(7+8*(i) downto 8*(i)) and dsp_sc_data_read_mask(h)(7+8*(i) downto 8*(i))));\n dsp_in_mul_operands(f)(1)(15+16*(i) downto 16*(i)) <= (x\"00\" & (dsp_sc_data_read(h)(1)(7+8*(i) downto 8*(i)) and dsp_sc_data_read_mask(h)(7+8*(i) downto 8*(i))));\n if dotp(h) = '1' then\n dsp_in_accum_operands(f) <= dsp_out_mul_results(f);\n elsif dotpps(h) = '1' then\n dsp_in_shift_amount(f) <= MPSCLFAC_DSP(h);\n dsp_in_shifter_operand(f) <= dsp_out_mul_results(f);\n dsp_in_accum_operands(f) <= dsp_out_shifter_results(f);\n end if;\n end loop;\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KDOTP_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1') and\n (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"10\") then\n dsp_in_mul_operands(f)(0) <= dsp_sc_data_read(h)(0) and dsp_sc_data_read_mask(h);\n dsp_in_mul_operands(f)(1) <= dsp_sc_data_read(h)(1) and dsp_sc_data_read_mask(h);\n if dotp(h) = '1' then\n dsp_in_accum_operands(f) <= dsp_out_mul_results(f);\n elsif dotpps(h) = '1' then\n dsp_in_shift_amount(f) <= MPSCLFAC_DSP(h);\n dsp_in_shifter_operand(f) <= dsp_out_mul_results(f);\n dsp_in_accum_operands(f) <= dsp_out_shifter_results(f);\n end if;\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 2*SIMD-1 loop\n if vec_read_rs2_DSP(h) = '0' then\n if rf_rs2(h) = '1' then\n dsp_in_mul_operands(f)(1)(15+16*(i) downto 16*(i)) <= x\"00\" & RS2_Data_IE_lat(h)(7 downto 0); -- map the scalar value\n elsif rf_rs2(h) = '0' then\n dsp_in_mul_operands(f)(1)(15+16*(i) downto 16*(i)) <= x\"00\" & dsp_sc_data_read(h)(1)(7 downto 0); -- map the scalar value\n end if;\n else\n dsp_in_mul_operands(f)(1)(15+16*(i) downto 16*(i)) <= x\"00\" & dsp_sc_data_read(h)(1)(7+8*(i) downto 8*(i));\n end if;\n dsp_in_mul_operands(f)(0)(15+16*(i) downto 16*(i)) <= x\"00\" & dsp_sc_data_read(h)(0)(7+8*(i) downto 8*(i));\n end loop;\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n MVTYPE_DSP(h) = \"01\" then\n if vec_read_rs2_DSP(h) = '0' then\n if rf_rs2(h) = '1' then\n for i in 0 to 2*SIMD-1 loop\n dsp_in_mul_operands(f)(1)(15+16*(i) downto 16*(i)) <= RS2_Data_IE_lat(h)(15 downto 0); -- map the scalar value\n end loop;\n elsif rf_rs2(h) = '0' then\n for i in 0 to 2*SIMD-1 loop\n dsp_in_mul_operands(f)(1)(15+16*(i) downto 16*(i)) <= dsp_sc_data_read(h)(1)(15 downto 0); -- map the scalar value\n end loop; \n end if;\n else\n dsp_in_mul_operands(f)(1) <= dsp_sc_data_read(h)(1);\n end if;\n dsp_in_mul_operands(f)(0) <= dsp_sc_data_read(h)(0);\n end if;\n\n if (decoded_instruction_DSP_lat(h)(KVMUL_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULRF_bit_position) = '1' or \n decoded_instruction_DSP_lat(h)(KSVMULSC_bit_position) = '1') and\n MVTYPE_DSP(h) = \"10\" then\n if vec_read_rs2_DSP(h) = '0' then\n if rf_rs2(h) = '1' then\n for i in 0 to SIMD-1 loop\n dsp_in_mul_operands(f)(1)(31+32*(i) downto 32*(i)) <= RS2_Data_IE_lat(h)(31 downto 0); -- map the scalar value\n end loop;\n elsif rf_rs2(h) = '0' then\n for i in 0 to SIMD-1 loop\n dsp_in_mul_operands(f)(1)(31+32*(i) downto 32*(i)) <= dsp_sc_data_read(h)(1)(31 downto 0); -- map the scalar value\n end loop;\n end if;\n else\n dsp_in_mul_operands(f)(1) <= dsp_sc_data_read(h)(1);\n end if;\n dsp_in_mul_operands(f)(0) <= dsp_sc_data_read(h)(0);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KADDV_bit_position) = '1' then \n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n dsp_in_adder_operands(f)(1) <= dsp_sc_data_read(h)(1);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSRAV_bit_position) = '1' or\n decoded_instruction_DSP_lat(h)(KSRLV_bit_position) = '1' then \n dsp_in_shifter_operand(f) <= dsp_sc_data_read(h)(0);\n dsp_in_shift_amount(f) <= RS2_Data_IE_lat(h)(4 downto 0); -- map the scalar value (shift amount)\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDSC_bit_position) = '1' and MVTYPE_DSP(h) = \"10\" then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n for i in 0 to SIMD-1 loop\n dsp_in_adder_operands(f)(1)(31+32*(i) downto 32*(i)) <= dsp_sc_data_read(h)(1)(31 downto 0);\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDSC_bit_position) = '1' and MVTYPE_DSP(h) = \"01\" then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n for i in 0 to 2*SIMD-1 loop\n dsp_in_adder_operands(f)(1)(15+16*(i) downto 16*(i)) <= dsp_sc_data_read(h)(1)(15 downto 0);\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDSC_bit_position) = '1' and MVTYPE_DSP(h) = \"00\" then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n for i in 0 to 4*SIMD-1 loop\n dsp_in_adder_operands(f)(1)(7+8*(i) downto 8*(i)) <= dsp_sc_data_read(h)(1)(7 downto 0);\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDRF_bit_position) = '1' and MVTYPE_DSP(h) = \"10\" then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n for i in 0 to SIMD-1 loop\n dsp_in_adder_operands(f)(1)(31+32*(i) downto 32*(i)) <= RS2_Data_IE_lat(h)(31 downto 0);\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDRF_bit_position) = '1' and MVTYPE_DSP(h) = \"01\" then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n for i in 0 to 2*SIMD-1 loop\n dsp_in_adder_operands(f)(1)(15+16*(i) downto 16*(i)) <= RS2_Data_IE_lat(h)(15 downto 0);\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVADDRF_bit_position) = '1' and MVTYPE_DSP(h) = \"00\" then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n for i in 0 to 4*SIMD-1 loop\n dsp_in_adder_operands(f)(1)(7+8*(i) downto 8*(i)) <= RS2_Data_IE_lat(h)(7 downto 0);\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSUBV_bit_position) = '1' then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n dsp_in_adder_operands(f)(1) <= (not dsp_sc_data_read(h)(1));\n end if;\n\n if decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1' and MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 2*SIMD-1 loop\n dsp_in_accum_operands(f)(15+16*(i) downto 16*(i)) <= x\"00\" & (dsp_sc_data_read(h)(0)(7+8*(i) downto 8*(i)) and dsp_sc_data_read_mask(h)(7+8*(i) downto 8*(i)));\n end loop;\n end if;\n if decoded_instruction_DSP_lat(h)(KVRED_bit_position) = '1' and (MVTYPE_DSP(h) = \"01\" or MVTYPE_DSP(h) = \"10\") then\n dsp_in_accum_operands(f) <= dsp_sc_data_read(h)(0) and dsp_sc_data_read_mask(h);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KRELU_bit_position) = '1' then\n dsp_in_cmp_operands(f) <= dsp_sc_data_read(h)(0);\n end if;\n\n if decoded_instruction_DSP_lat(h)(KVSLT_bit_position) = '1' then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n dsp_in_adder_operands(f)(1) <= (not dsp_sc_data_read(h)(1));\n dsp_in_cmp_operands(f) <= dsp_out_adder_results(f);\n for i in 0 to 1 loop -- loops through both read busses for operands rs1, and rs2\n for j in 0 to 4*SIMD-1 loop -- loop transfers all the MSBs from the input to the output\n MSB_stage_1(f)(i)(j) <= dsp_sc_data_read(h)(i)(7+8*(j));\n end loop;\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KSVSLT_bit_position) = '1'then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n dsp_in_cmp_operands(f) <= dsp_out_adder_results(f);\n if MVTYPE_DSP(h) = \"10\" then\n for i in 0 to SIMD-1 loop\n dsp_in_adder_operands(f)(1)(31+32*(i) downto 32*(i)) <= not(RS2_Data_IE_lat(h)(31 downto 0));\n end loop;\n for j in 0 to SIMD-1 loop -- this index loops throughout the SIMD lanes\n MSB_stage_1(f)(1)(4*(j)+3) <= RS2_Data_IE_lat(h)(31); -- Save the MSB in an array to be used for comparator results\n end loop;\n elsif MVTYPE_DSP(h) = \"01\" then\n for i in 0 to 2*SIMD-1 loop\n dsp_in_adder_operands(f)(1)(15+16*(i) downto 16*(i)) <= not(RS2_Data_IE_lat(h)(15 downto 0));\n end loop;\n for i in 0 to 1 loop -- this index loops throughout the MSBs in the 8-bit subwords in the 32-bit word \"RS2_Data_IE_lat\"\n for j in 0 to SIMD-1 loop -- this index loops throughout the SIMD lanes\n MSB_stage_1(f)(1)(4*(j)+1+2*(i)) <= RS2_Data_IE_lat(h)(15); -- Save the MSB in an array to be used for comparator results\n end loop;\n end loop;\n elsif MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 4*SIMD-1 loop\n dsp_in_adder_operands(f)(1)(7+8*(i) downto 8*(i)) <= not(RS2_Data_IE_lat(h)(7 downto 0));\n end loop;\n for i in 0 to 3 loop -- this index loops throughout the MSBs in the 8-bit subwords in the 32-bit word \"RS2_Data_IE_lat\"\n for j in 0 to SIMD-1 loop -- this index loops throughout the SIMD lanes\n MSB_stage_1(f)(1)(4*(j)+i) <= RS2_Data_IE_lat(h)(7); -- Save the MSB in an array to be used for comparator results\n end loop;\n end loop;\n end if;\n for i in 0 to 4*SIMD-1 loop -- loop transfers all the MSBs from the input to the output\n MSB_stage_1(f)(0)(i) <= dsp_sc_data_read(h)(0)(7+8*(i));\n end loop;\n end if;\n\n if decoded_instruction_DSP_lat(h)(KVCP_bit_position) = '1' then\n dsp_in_adder_operands(f)(0) <= dsp_sc_data_read(h)(0);\n end if;\n\n when others =>\n null;\n end case;\n end if;\n end loop;\n end process;\n\n--end generate;\n--end generate;\n\n--FU_IN_MAPPER : if (multithreaded_accl_en = 0 or (multithreaded_accl_en = 1 and f = 0) generate\n\n ------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā• ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ --\n -- -ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• --\n ------------------------------------------------------------------------------------------------\n \n fsm_DSP_adder_stage_1 : process(all)\n variable h : integer;\n begin\n dsp_add_8_0_wire(f) <= dsp_add_8_0(f);\n dsp_add_16_8_wire(f) <= dsp_add_16_8(f);\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n", "right_context": " -- (2) Each addition results in an 8-bit value, and the 9th bit being the carry, depending on the instruction (KADDV32, KADDV16, KADDV8) we either pass the or block the carries.\n -- (3) CARRIES:\n -- (a) If we pass all the carries in the 32-bit word, we will have executed KADDV32 (4*32-bit parallel additions)\n -- (b) If we pass the 9th and 25th carries we would have executed KADDV16 (8*16-bit parallel additions)\n -- (c) If we pass none of the carries then we would have executed KADDV8 (16*8-bit parallel additions)\n dsp_add_8_0_wire(f)(i) <= std_logic_vector('0' & unsigned(dsp_in_adder_operands(f)(0)(7+8*(4*i) downto 8*(4*i))) + unsigned(dsp_in_adder_operands(f)(1)(7+8*(4*i) downto 8*(4*i))) + twos_complement(h)(0+(4*i)));\n dsp_add_16_8_wire(f)(i) <= std_logic_vector('0' & unsigned(dsp_in_adder_operands(f)(0)(15+8*(4*i) downto 8+8*(4*i))) + unsigned(dsp_in_adder_operands(f)(1)(15+8*(4*i) downto 8+8*(4*i))) + carry_8_wire(f)(i) + twos_complement(h)(1+(4*i)));\n -- All the 8-bit adders are lumped into one output write signal that will write to the scratchpads\n -- Carries are either passed or blocked for the 9-th, 17-th, and 25-th bits\n carry_8_wire(f)(i) <= dsp_add_8_0_wire(f)(i)(8) and carry_pass(h)(0);\n carry_16_wire(f)(i) <= dsp_add_16_8_wire(f)(i)(8) and carry_pass(h)(1);\n end if;\n end loop;\n end loop;\n end process;\n\n ---------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- -ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• --\n ---------------------------------------------------------------------------------------------------\n\n fsm_DSP_adder_stage_2 : process(all)\n variable h : integer;\n begin\n carry_24_wire(f) <= (others => '0');\n dsp_add_24_16_wire(f) <= (others => (others => '0'));\n dsp_add_32_24_wire(f) <= (others => (others => '0'));\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n -- Addition is here\n if halt_dsp_lat(h) = '0' then\n -- Addition in SIMD Virtual Parallelism is executed here, if the carries are blocked, we will have a chain of 8-bit or 16-bit adders, else we have 32-bit adders\n for i in 0 to SIMD-1 loop\n if (adder_stage_2_en(h) = '1' or recover_state_wires(h) = '1') then\n dsp_add_24_16_wire(f)(i) <= std_logic_vector('0' & unsigned(dsp_in_adder_operands_lat(f)(0)(7+8*(2*i) downto 8*(2*i))) + \n unsigned(dsp_in_adder_operands_lat(f)(1)(7+8*(2*i) downto 8*(2*i))) + \n carry_16(f)(i) + twos_complement(h)(2+(4*i)));\n dsp_add_32_24_wire(f)(i) <= std_logic_vector('0' & unsigned(dsp_in_adder_operands_lat(f)(0)(15+8*(2*i) downto 8+8*(2*i))) + \n unsigned(dsp_in_adder_operands_lat(f)(1)(15+8*(2*i) downto 8+8*(2*i))) + \n carry_24_wire(f)(i) + twos_complement(h)(3+(4*i)));\n -- All the 8-bit adders are lumped into one output write signal that will write to the scratchpads\n -- Carries are either passed or blocked for the 9-th, 17-th, and 25-th bits\n carry_24_wire(f)(i) <= dsp_add_24_16_wire(f)(i)(8) and carry_pass(h)(2);\n end if;\n end loop;\n end if;\n end loop;\n end process;\n\n fsm_DSP_adder : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n -- Addition is here\n if add_en(h) = '1' and halt_dsp_lat(h) = '0' then\n carry_16(f) <= carry_16_wire(f);\n dsp_add_8_0(f) <= dsp_add_8_0_wire(f);\n dsp_add_16_8(f) <= dsp_add_16_8_wire(f);\n MSB_stage_2(f) <= MSB_stage_1(f);\n -- Addition in SIMD Virtual Parallelism is executed here, if the carries are blocked, we will have a chain of 8-bit or 16-bit adders, else we have normal 32-bit adders\n for i in 0 to SIMD-1 loop\n if (adder_stage_2_en(h) = '1' or recover_state_wires(h) = '1') then\n -- All the 8-bit adders are lumped into one output signal\n dsp_out_adder_results(f)(31+32*(i) downto 32*(i)) <= dsp_add_32_24_wire(f)(i)(7 downto 0) & dsp_add_24_16_wire(f)(i)(7 downto 0) & dsp_add_16_8(f)(i)(7 downto 0) & dsp_add_8_0(f)(i)(7 downto 0);\n end if;\n end loop;\n for i in 0 to SIMD-1 loop\n for j in 0 to 1 loop\n dsp_in_adder_operands_lat(f)(j)(15 +16*(i) downto 16*(i)) <= dsp_in_adder_operands(f)(j)(31+32*(i) downto 16+32*(i));\n end loop;\n end loop;\n end if;\n end loop;\n end if;\n end process;\n\n ------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā• ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• --\n ------------------------------------------------------------------------------------------------------------\n\n fsm_DSP_shifter_stg_1 : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n if shift_en(h) = '1' and (shifter_stage_1_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n for i in 0 to SIMD-1 loop\n dsp_int_shifter_operand(f)(31+32*(i) downto 32*(i)) <= to_stdlogicvector(to_bitvector(dsp_in_shifter_operand(f)(31+32*(i) downto 32*(i))) srl to_integer(unsigned(dsp_in_shift_amount(f))));\n end loop;\n --for i in 0 to 4*SIMD-1 loop -- latch the sign bits\n --dsp_in_sign_bits(f)(i) <= dsp_in_shifter_operand(f)(7+8*(i));\n --end loop;\n if MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 4*SIMD-1 loop -- latch the sign bits\n dsp_in_shifter_operand_lat(f)(7+8*i downto 8*i) <= (others => dsp_in_shifter_operand(f)(7+8*i));\n end loop;\n elsif MVTYPE_DSP(h) = \"01\" then\n for i in 0 to 2*SIMD-1 loop -- latch the sign bits\n dsp_in_shifter_operand_lat(f)(15+16*i downto 16*i) <= (others => dsp_in_shifter_operand(f)(15+16*i));\n end loop;\n elsif MVTYPE_DSP(h) = \"10\" then\n for i in 0 to SIMD-1 loop -- latch the sign bits\n dsp_in_shifter_operand_lat(f)(31+32*i downto 32*i) <= (others => dsp_in_shifter_operand(f)(31+32*i));\n end loop;\n end if;\n end if;\n end loop;\n end if;\n end process;\n\n ----------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• --\n ----------------------------------------------------------------------------------------------------------------\n\n fsm_DSP_shifter_stg_2 : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n if shift_en(h) = '1' and (shifter_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n if MVTYPE_DSP(h) = \"10\" then\n for i in 0 to SIMD-1 loop\n dsp_out_shifter_results(f)(31+32*(i) downto 32*(i)) <= dsp_in_shifter_operand_lat_wire(f)(31 +32*(i) downto 32*(i)) or dsp_int_shifter_operand(f)(31+32*(i) downto 32*(i));\n end loop;\n elsif MVTYPE_DSP(h) = \"01\" or (decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1' and MVTYPE_DSP(h) = \"00\") then -- KDOTPPS8 has been added here because the number of elements loaded for mul operations is equal for 8-bit and 16-bits instr\n for i in 0 to 2*SIMD-1 loop\n dsp_out_shifter_results(f)(15+16*(i) downto 16*(i)) <= dsp_in_shifter_operand_lat_wire(f)(15 +16*(i) downto 16*(i)) or (dsp_int_shifter_operand(f)(15+16*(i) downto 16*(i)) and dsp_shift_enabler(h)(15 downto 0));\n end loop;\n elsif MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 4*SIMD-1 loop\n dsp_out_shifter_results(f)(7+8*(i) downto 8*(i)) <= dsp_in_shifter_operand_lat_wire(f)(7 +8*(i) downto 8*(i)) or (dsp_int_shifter_operand(f)(7+8*(i) downto 8*(i)) and dsp_shift_enabler(h)(7 downto 0));\n end loop;\n end if;\n end if;\n end loop;\n end if;\n end process;\n\n fsm_DSP_shifter_comb : process(all)\n variable h : integer;\n begin\n dsp_in_shifter_operand_lat_wire(f) <= (others => '0');\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n dsp_shift_enabler(h) <= (others => '0');\n if shift_en(h) = '1' and halt_dsp_lat(h) = '0' then\n if MVTYPE_DSP(h) = \"01\" then\n dsp_shift_enabler(h)(15 - to_integer(unsigned(dsp_in_shift_amount(h)(3 downto 0))) downto 0) <= (others => '1');\n elsif MVTYPE_DSP(h) = \"00\" then\n dsp_shift_enabler(h)(7 - to_integer(unsigned(dsp_in_shift_amount(h)(2 downto 0))) downto 0) <= (others => '1');\n end if;\n if (decoded_instruction_DSP_lat(h)(KSRAV_bit_position) = '1' or decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1') and\n MVTYPE_DSP(h) = \"10\" then -- 32-bit sign extension for for srl in stage 1\n for i in 0 to SIMD-1 loop\n --dsp_in_shifter_operand_lat(f)(31+32*(i) downto 31 - to_integer(unsigned(dsp_in_shift_amount(h)(4 downto 0)))+32*(i)) <= (others => dsp_in_sign_bits(h)(3+4*(i)));\n dsp_in_shifter_operand_lat_wire(f)(31+32*(i) downto 31 - to_integer(unsigned(dsp_in_shift_amount(f)(4 downto 0)))+32*(i)) <= \n dsp_in_shifter_operand_lat(f)( 31+32*(i) downto 31 - to_integer(unsigned(dsp_in_shift_amount(f)(4 downto 0)))+32*(i));\n end loop;\n elsif (decoded_instruction_DSP_lat(h)(KSRAV_bit_position) = '1' or decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1') and\n MVTYPE_DSP(h) = \"01\" then -- 16-bit sign extension for for srl in stage 1\n for i in 0 to 2*SIMD-1 loop\n --dsp_in_shifter_operand_lat(f)(15+16*(i) downto 15 - to_integer(unsigned(dsp_in_shift_amount(h)(3 downto 0)))+16*(i)) <= (others => dsp_in_sign_bits(h)(1+2*(i)));\n dsp_in_shifter_operand_lat_wire(f)(15+16*(i) downto 15 - to_integer(unsigned(dsp_in_shift_amount(f)(3 downto 0)))+16*(i)) <= \n dsp_in_shifter_operand_lat(f)( 15+16*(i) downto 15 - to_integer(unsigned(dsp_in_shift_amount(f)(3 downto 0)))+16*(i));\n end loop;\n elsif (decoded_instruction_DSP_lat(h)(KSRAV_bit_position) = '1' or decoded_instruction_DSP_lat(h)(KDOTPPS_bit_position) = '1') and\n MVTYPE_DSP(h) = \"00\" then -- 8-bit sign extension for for srl in stage 1\n for i in 0 to 4*SIMD-1 loop\n --dsp_in_shifter_operand_lat(f)(7+8*(i) downto 7 - to_integer(unsigned(dsp_in_shift_amount(h)(2 downto 0)))+8*(i)) <= (others => dsp_in_sign_bits(h)(i));\n dsp_in_shifter_operand_lat_wire(f)(7+8*(i) downto 7 - to_integer(unsigned(dsp_in_shift_amount(f)(2 downto 0)))+8*(i)) <= \n dsp_in_shifter_operand_lat(f)( 7+8*(i) downto 7 - to_integer(unsigned(dsp_in_shift_amount(f)(2 downto 0)))+8*(i));\n end loop;\n end if;\n end if;\n end loop;\n end process; \n\n --------------------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā• ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• --\n --------------------------------------------------------------------------------------------------------------------------------\n -- STAGE 1 --\n fsm_MUL_STAGE_1 : process(clk_i,rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n if halt_dsp_lat(h) = '0' then\n if mul_en(h) = '1' and (mul_stage_1_en(h) = '1' or recover_state_wires(h) = '1') then\n for i in 0 to SIMD-1 loop\n -- Unwinding the loop: \n -- (1) The impelemtation in the loop does multiplication for KDOTP32, and KDOTP16 using only 16-bit multipliers. \"A*B\" = [Ahigh*(2^16) + Alow]*[Bhigh*(2^16) + Blow]\n -- (2) Expanding this equation \"[Ahigh*(2^16) + Alow]*[Bhigh*(2^16) + Blow]\" gives: \"Ahigh*Bhigh*(2^32) + Ahigh*Blow*(2^16) + Alow*Bhigh*(2^16) + Alow*Blow\" which are the terms being stored in dsp_out_mul_results\n -- (3) Partial Multiplication \n -- (a) \"dsp_mul_a\" <= Ahigh*Bhigh \n -- (b) \"dsp_mul_b\" <= Ahigh*Blow\n -- (c) \"dsp_mul_c\" <= Alow*Bhigh\n -- (d) \"dsp_mul_d\" <= Alow*Blow\n -- (4) \"dsp_mul_a\" is shifted by 32 bits to the left, \"dsp_mul_b\" and \"dsp_mul_c\" are shifted by 16-bits to the left, \"dsp_mul_d\" is not shifted\n -- (5) For 16-bit and 8-bit muls, the FUNCT_SELECT_MASK is set to x\"00000000\" blocking the terms in \"dsp_mul_b\" and \"dsp_mul_c\". For executing 32-bit muls , we set the mask to x\"FFFFFFFF\"\n dsp_mul_a(f)(31+32*(i) downto 32*(i)) <= std_logic_vector(unsigned(dsp_in_mul_operands(f)(0)(15+16*(2*i+1) downto 16*(2*i+1))) * unsigned(dsp_in_mul_operands(f)(1)(15+16*(2*i+1) downto 16*(2*i+1))));\n dsp_mul_b(f)(31+32*(i) downto 32*(i)) <= std_logic_vector((unsigned(dsp_in_mul_operands(f)(0)(16*(2*i+1) - 1 downto 16*(2*i))) * unsigned(dsp_in_mul_operands(f)(1)(15+16*(2*i+1) downto 16*(2*i+1)))) and unsigned(FUNCT_SELECT_MASK(h)));\n dsp_mul_c(f)(31+32*(i) downto 32*(i)) <= std_logic_vector((unsigned(dsp_in_mul_operands(f)(0)(15+16*(2*i+1) downto 16*(2*i+1))) * unsigned(dsp_in_mul_operands(f)(1)(16*(2*i+1) - 1 downto 16*(2*i)))) and unsigned(FUNCT_SELECT_MASK(h)));\n dsp_mul_d(f)(31+32*(i) downto 32*(i)) <= std_logic_vector(unsigned(dsp_in_mul_operands(f)(0)(16*(2*i+1) - 1 downto 16*(2*i))) * unsigned(dsp_in_mul_operands(f)(1)(16*(2*i+1) - 1 downto 16*(2*i))));\n end loop;\n end if;\n end if;\n end loop;\n end if;\n end process;\n\n fsm_MUL_STAGE_1_COMB : process(all)\n variable h : integer;\n begin\n mul_tmp_a(f) <= (others => (others => '0'));\n mul_tmp_b(f) <= (others => (others => '0'));\n mul_tmp_c(f) <= (others => (others => '0'));\n mul_tmp_d(f) <= (others => (others => '0'));\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n -- KDOTP and KSVMUL instructions are handeled here\n -- this part right here shifts the intermidiate resutls appropriately, and then accumulates them in order to get the final mul result\n if mul_en(h) = '1' and (mul_stage_2_en(h) = '1' or recover_state_wires(h) = '1') then\n for i in 0 to SIMD-1 loop\n if MVTYPE_DSP(h) /= \"10\" then\n ------------------------------------------------------------------------------------\n mul_tmp_a(f)(i) <= (dsp_mul_a(f)(15+16*(2*i) downto 16*(2*i)) & x\"0000\");\n mul_tmp_d(f)(i) <= (x\"0000\" & dsp_mul_d(f)(15+16*(2*i) downto 16*(2*i)));\n ------------------------------------------------------------------------------------\n elsif MVTYPE_DSP(h) = \"10\" then\n -- mul_tmp_a(f)(i) <= (dsp_mul_a(f)(31+32*(2*i) downto 31*(2*i)) & x\"0000\"); -- The upper 32-bit results of the multiplication are discarded (Ah*Bh)\n mul_tmp_b(f)(i) <= (dsp_mul_b(f)(15+16*(2*i) downto 16*(2*i)) & x\"0000\"); -- Modified to only add the partial result to the lower 32-bits (Ah*Bl)\n mul_tmp_c(f)(i) <= (dsp_mul_c(f)(15+16*(2*i) downto 16*(2*i)) & x\"0000\"); -- Modified to only add the partial result to the lower 32-bits (Al*Bh)\n mul_tmp_d(f)(i) <= (dsp_mul_d(f)(31+32*(i) downto 32*(i))); -- This is the lower 32-bit result of the partial mmultiplication (Al*Bl)\n end if;\n end loop;\n end if;\n end loop;\n end process;\n\n ------------------------------------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• --\n ------------------------------------------------------------------------------------------------------------------------------------\n\n -- STAGE 2 --\n fsm_MUL_STAGE_2 : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n -- Accumulate the partial multiplications to make up bigger multiplications\n if mul_en(h) = '1' and (mul_stage_2_en(h) = '1' or recover_state_wires(h) = '1') and halt_dsp_lat(h) = '0' then\n for i in 0 to SIMD-1 loop\n dsp_out_mul_results(f)((Data_Width-1)+Data_Width*(i) downto Data_Width*(i)) <= (std_logic_vector(unsigned(mul_tmp_a(f)(i)) + unsigned(mul_tmp_b(f)(i)) + unsigned(mul_tmp_c(f)(i)) + unsigned(mul_tmp_d(f)(i))));\n end loop;\n end if;\n end loop;\n end if;\n end process;\n\n ----------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n --ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n --ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n --ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n --ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n ----------------------------------------------------------------------------------------------------\n\n fsm_RELU : process(clk_i, rst_ni)\n variable h : integer;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n for g in 0 to (ACCL_NUM - FU_NUM) loop\n if multithreaded_accl_en = 1 then\n h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n if cmp_en(h) = '1' and halt_dsp_lat(h) = '0' then\n MSB_stage_3(f) <= MSB_stage_2(f);\n if cmp_stage_1_en(h) = '1' or recover_state_wires(h) = '1' then\n if MVTYPE_DSP(h) = \"10\" then\n for i in 0 to SIMD-1 loop\n if relu_instr(h) = '1' then\n if dsp_in_cmp_operands(f)(31+32*(i)) = '1' then\n dsp_out_cmp_results(f)(31+32*(i) downto 32*(i)) <= (others => '0');\n else\n dsp_out_cmp_results(f)(31+32*(i) downto 32*(i)) <= dsp_in_cmp_operands(f)(31+32*(i) downto 32*(i));\n end if;\n else\n if MSB_stage_3(f)(1)(4*(i)+3) = MSB_stage_3(f)(0)(4*(i)+3) then -- if both signs are equal, than read the MSB from the subtractor\n if dsp_in_cmp_operands(f)(31+32*(i)) = '1' then\n dsp_out_cmp_results(f)(31+32*(i) downto 32*(i)) <= (31+32*(i) downto 32*(i)+1 => '0') & '1';\n else\n dsp_out_cmp_results(f)(31+32*(i) downto 32*(i)) <= (others => '0');\n end if;\n elsif MSB_stage_3(f)(1)(4*(i)+3) /= MSB_stage_3(f)(0)(4*(i)+3) and MSB_stage_3(f)(0)(4*(i)+3) = '1' then\n dsp_out_cmp_results(f)(31+32*(i) downto 32*(i)) <= (31+32*(i) downto 32*(i)+1 => '0') & '1';\n else\n dsp_out_cmp_results(f)(31+32*(i) downto 32*(i)) <= (others => '0');\n end if;\n end if;\n end loop;\n elsif MVTYPE_DSP(h) = \"01\" then\n for i in 0 to 2*SIMD-1 loop\n if relu_instr(h) = '1' then\n if dsp_in_cmp_operands(f)(15+16*(i)) = '1' then\n dsp_out_cmp_results(f)(15+16*(i) downto 16*(i)) <= (others => '0');\n else\n dsp_out_cmp_results(f)(15+16*(i) downto 16*(i)) <= dsp_in_cmp_operands(f)(15+16*(i) downto 16*(i));\n end if;\n else\n if MSB_stage_3(f)(1)(2*(i)+1) = MSB_stage_3(f)(0)(2*(i)+1) then -- if both signs are equal, than read the MSB from the subtractor\n if dsp_in_cmp_operands(f)(15+16*(i)) = '1' then\n dsp_out_cmp_results(f)(15+16*(i) downto 16*(i)) <= (15+16*(i) downto 16*(i)+1 => '0') & '1';\n else\n dsp_out_cmp_results(f)(15+16*(i) downto 16*(i)) <= (others => '0');\n end if;\n elsif MSB_stage_3(f)(1)(2*(i)+1) /= MSB_stage_3(f)(0)(2*(i)+1) and MSB_stage_3(f)(0)(2*(i)+1) = '1' then\n dsp_out_cmp_results(f)(15+16*(i) downto 16*(i)) <= (15+16*(i) downto 16*(i)+1 => '0') & '1';\n else\n dsp_out_cmp_results(f)(15+16*(i) downto 16*(i)) <= (others => '0');\n end if;\n end if;\n end loop;\n elsif MVTYPE_DSP(h) = \"00\" then\n for i in 0 to 4*SIMD-1 loop\n if relu_instr(h) = '1' then\n if dsp_in_cmp_operands(f)(7+8*(i)) = '1' then\n dsp_out_cmp_results(f)(7+8*(i) downto 8*(i)) <= (others => '0');\n else\n dsp_out_cmp_results(f)(7+8*(i) downto 8*(i)) <= dsp_in_cmp_operands(f)(7+8*(i) downto 8*(i));\n end if;\n else\n if MSB_stage_3(f)(1)(i) = MSB_stage_3(f)(0)(i) then -- if both signs are equal, than read the MSB from the subtractor\n if dsp_in_cmp_operands(f)(7+8*(i)) = '1' then\n dsp_out_cmp_results(f)(7+8*(i) downto 8*(i)) <= (7+8*(i) downto 8*(i)+1 => '0') & '1';\n else\n dsp_out_cmp_results(f)(7+8*(i) downto 8*(i)) <= (others => '0');\n end if;\n elsif MSB_stage_3(f)(1)(i) /= MSB_stage_3(f)(0)(i) and MSB_stage_3(f)(0)(i) = '1' then\n dsp_out_cmp_results(f)(7+8*(i) downto 8*(i)) <= (7+8*(i) downto 8*(i)+1 => '0') & '1';\n else\n dsp_out_cmp_results(f)(7+8*(i) downto 8*(i)) <= (others => '0');\n end if;\n end if;\n end loop; -- SIMD LOOP\n end if;\n end if;\n end if;\n end loop; -- ACCL NUM LOOP\n end if;\n end process;\n\nend generate FU_replicated;\n\n ----------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• --\n ----------------------------------------------------\n\n ACCUM_STG : ACCUMULATOR\n generic map(\n multithreaded_accl_en => multithreaded_accl_en, \n SIMD => SIMD, \n -------------------------------------------------\n ACCL_NUM => ACCL_NUM, \n FU_NUM => FU_NUM, \n Data_Width => Data_Width, \n SIMD_Width => SIMD_Width\n )\n port map(\n clk_i => clk_i,\n rst_ni => rst_ni,\n MVTYPE_DSP => MVTYPE_DSP,\n accum_stage_1_en => accum_stage_1_en,\n accum_stage_2_en => accum_stage_2_en,\n recover_state_wires => recover_state_wires,\n halt_dsp_lat => halt_dsp_lat,\n state_DSP => state_DSP,\n decoded_instruction_DSP_lat => decoded_instruction_DSP_lat,\n dsp_in_accum_operands => dsp_in_accum_operands,\n dsp_out_accum_results => dsp_out_accum_results\n );\n\n\n------------------------------------------------------------------------ end of DSP Unit ---------\n-------------------------------------------------------------------------------------------------- \n\nend DSP;\n--------------------------------------------------------------------------------------------------\n-- END of DSP architecture -----------------------------------------------------------------------\n--------------------------------------------------------------------------------------------------\n", "groundtruth": " h := g; -- set the spm rd/wr ports equal to the \"for-loop\"\n elsif multithreaded_accl_en = 0 then\n h := f; -- set the spm rd/wr ports equal to the \"for-generate\" \n end if;\n -- Addition in SIMD Virtual Parallelism is executed here, if the carries are blocked, we will have a chain of 8-bit or 16-bit adders, else we have 32-bit adders\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Debug_Unit.vhd", "left_context": "--------------------------------------------------------------------------------------------------------\n-- Debug Unit -- --\n-- Author(s): Gianmarco Cerutti --\n-- Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 17-11-2019 --\n--------------------------------------------------------------------------------------------------------\n-- Debug Unit halts and sigle steps the core, it can read the current and next program counters, --\n-- The register file can also be accessed by the debug unit. --\n--------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\nentity Debug_UNIT is\n generic(\n THREAD_POOL_SIZE : integer;\n LUTRAM_RF : natural;\n ACCL_NUM : natural;\n RF_SIZE : natural\n );\n port(\n set_branch_condition : in std_logic;\n ie_except_condition : in std_logic;\n ls_except_condition : in std_logic;\n dsp_except_condition : in std_logic_vector(ACCL_NUM-1 downto 0);\n set_except_condition : in std_logic;\n set_mret_condition : in std_logic;\n served_irq : in std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n irq_pending : in std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n taken_branch_pc_lat : in array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n incremented_pc : in array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n MTVEC : in array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n MIP : in array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n MSTATUS : in array_2d(THREAD_POOL_SIZE-1 downto 0)(1 downto 0);\n MCAUSE : in array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n mepc_incremented_pc : in array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0) := (others => (others => '0'));\n mepc_interrupt_pc : in array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0) := (others => (others => '0'));\n regfile : in array_3d(THREAD_POOL_SIZE-1 downto 0)(RF_SIZE-1 downto 0)(31 downto 0);\n pc_IE : in std_logic_vector (31 downto 0);\n pc_ID : in std_logic_vector (31 downto 0);\n harc_ID : in integer range THREAD_POOL_SIZE-1 downto 0;\n ebreak_instr : in std_logic;\n dbg_ack_i : in std_logic;\n taken_branch : in std_logic;\n taken_branch_pending : in std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n dbg_req_o : out std_logic;\n clk_i : in std_logic;\n rst_ni : in std_logic;\n debug_req_i : in std_logic;\n debug_gnt_o : out std_logic;\n debug_rvalid_o : out std_logic;\n debug_addr_i : in std_logic_vector(14 downto 0);\n debug_we_i : in std_logic;\n debug_wdata_i : in std_logic_vector(31 downto 0);\n debug_rdata_o : out std_logic_vector(31 downto 0);\n debug_halted_o : out std_logic;\n debug_halt_i : in std_logic;\n debug_resume_i : in std_logic\n );\nend entity;\n\narchitecture DBG of Debug_Unit is\n\n\n\n type fsm_DBU_states is (RUNNING, HALT_REQ, HALT, SINGLE_STEP_REQ, SINGLE_STEP);\n signal state_DBU : fsm_DBU_states;\n signal nextstate_DBU : fsm_DBU_states;\n signal dbg_halt_req : std_logic;\n signal dbg_resume_core : std_logic;\n signal dbg_ssh : std_logic;\n signal dbg_sse : std_logic;\n\n -- wire only signals (For Synopsis Comaptibility)\n signal dbg_halted_o_wire : std_logic;\n\nbegin\n\n debug_halted_o <= dbg_halted_o_wire;\n\n --DEBUG_UNIT--\n --There are two processes, one handle the minterface between the external and the core, and one memorize the debug state.\n\n DBU_interface_handler : process(clk_i, rst_ni)\n begin\n if(rst_ni = '0') then\n debug_rvalid_o <= '0';\n debug_rdata_o <= (others => '0');\n dbg_halt_req <= '0';\n dbg_sse <= '0';\n dbg_ssh <= '1';\n dbg_resume_core <= '0';\n elsif rising_edge(clk_i) then\n dbg_ssh <= '1';\n if (debug_req_i = '1') then\n debug_rvalid_o <= '1';\n if(debug_we_i = '0') then --read access\n case debug_addr_i(13 downto 8) is\n when \"000000\" => --debug register always accessible\n case debug_addr_i(6 downto 2) is\n when \"00000\" =>\n debug_rdata_o <= (0 => dbg_halted_o_wire,\n 16 => dbg_sse,\n others => '0');\n when \"00001\" =>\n debug_rdata_o <= (0 => dbg_ssh, others => '0');\n when others =>\n null;\n end case;\n when \"100000\" => --debug regster accessible only when core is halted, that's why there is a condition on dbg_halted_o_wire\n if dbg_halted_o_wire = '1' then\n case debug_addr_i(2) is\n when '1' => --previous pc \n debug_rdata_o <= pc_ie;\n when '0' => -- next pc\n debug_rdata_o <= pc_id;\n when others =>\n null;\n end case;\n end if;\n when \"000100\" => --Read the GPR\n if LUTRAM_RF = 0 then\n debug_rdata_o <= regfile(harc_ID)(to_integer(unsigned(debug_addr_i(6 downto 2))));\n end if;\n when others =>\n null;\n end case;\n else -- write access\n debug_rvalid_o <= '0';\n case debug_addr_i(13 downto 8) is\n when \"000000\" => --debug register always accessible\n case debug_addr_i(6 downto 2) is\n when \"00000\" => -- debug control\n if (debug_wdata_i(16) = '1') then\n if dbg_halted_o_wire = '0' then\n dbg_halt_req <= '1';\n else\n dbg_halt_req <= '0';\n end if;\n else\n if dbg_halted_o_wire = '1' then\n dbg_resume_core <= '1';\n dbg_halt_req <= '0';\n end if;\n end if;\n if(debug_wdata_i(0) = '1') then\n dbg_sse <= '1';\n else\n dbg_sse <= '0';\n end if;\n when \"00001\" => -- debug hit\n if (debug_wdata_i(0) = '0') then\n if dbg_sse = '1' and dbg_halted_o_wire = '1' then\n dbg_ssh <= '0';\n end if;\n", "right_context": " null;\n end case;\n end if;\n end if;\n end if;\n end process;\n\n DBU_combination_access : process (all)\n begin\n if (debug_req_i = '1') then\n debug_gnt_o <= '1';\n else\n debug_gnt_o <= '0';\n end if;\n end process;\n\n --DEBUG_UNIT_NEXTSTATE\n fsm_Debug_Unit_nextstate : process(all)\n begin\n dbg_req_o <= '0';\n dbg_halted_o_wire <= '0';\n nextstate_DBU <= RUNNING;\n case state_DBU is\n when RUNNING =>\n if ebreak_instr = '1' then\n if dbg_sse = '1' then\n nextstate_DBU <= SINGLE_STEP;\n else\n nextstate_DBU <= HALT;\n end if;\n elsif dbg_halt_req = '1' then\n dbg_req_o <= '1';\n if dbg_sse = '1' then\n nextstate_DBU <= SINGLE_STEP_REQ;\n else\n nextstate_DBU <= HALT_REQ;\n end if;\n end if;\n when HALT_REQ =>\n dbg_req_o <= '1';\n if dbg_ack_i = '1' then\n nextstate_DBU <= HALT;\n else\n if dbg_resume_core = '0' then\n if dbg_sse = '1' then\n nextstate_DBU <= SINGLE_STEP_REQ;\n else\n nextstate_DBU <= HALT_REQ;\n end if;\n end if;\n end if; --dbg_ack_i \n when HALT =>\n dbg_req_o <= '1';\n dbg_halted_o_wire <= '1';\n if dbg_resume_core = '0' then\n if dbg_sse = '1' then\n nextstate_DBU <= SINGLE_STEP;\n else\n nextstate_DBU <= HALT;\n end if;\n end if;\n when SINGLE_STEP_REQ =>\n dbg_req_o <= '1';\n if dbg_ack_i = '1' then\n nextstate_DBU <= SINGLE_STEP;\n else\n if dbg_sse = '0' then\n nextstate_DBU <= HALT_REQ;\n else\n nextstate_DBU <= SINGLE_STEP_REQ;\n end if;\n end if;\n when SINGLE_STEP =>\n if dbg_sse = '0' then\n if dbg_resume_core = '0' then\n dbg_req_o <= '1';\n dbg_halted_o_wire <= '1';\n nextstate_DBU <= HALT;\n end if;\n elsif dbg_ssh = '0' then -- when a signle step is hit, the debug halt is stopped for one exact cycle\n nextstate_DBU <= SINGLE_STEP_REQ;\n else\n dbg_req_o <= '1';\n dbg_halted_o_wire <= '1';\n nextstate_DBU <= SINGLE_STEP;\n end if;\n when others =>\n null;\n end case;\n end process;\n\n\n fsm_DBU_register_state : process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n state_DBU <= RUNNING;\n elsif rising_edge(clk_i) then\n state_DBU <= nextstate_DBU;\n end if;\n end process;\n\n------------------------------------------------------------------------ end of DBG Unit ---------\n-------------------------------------------------------------------------------------------------- \n\nend DBG;\n--------------------------------------------------------------------------------------------------\n-- END of DBG Unit architecture -----------------------------------------------------------------\n--------------------------------------------------------------------------------------------------\n", "groundtruth": " end if;\r\n when others =>\r\n null;\r\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-ID_STAGE.vhd", "left_context": "----------------------------------------------------------------------------------------------------------------\n-- Stage ID - (Instruction decode and registerfile read) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 07-04-2020 --\n----------------------------------------------------------------------------------------------------------------\n-- Does operation decoding, and issues the result in a one-hot decoding form to the next stage --\n-- In this stage we detect based on the incoming instruction whether superscalar execution can be enabled. --\n-- This pipeline stage always takes one cycle latency --\n----------------------------------------------------------------------------------------------------------------\n\n-- package riscv_kless is new work.riscv_klessydra;\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.riscv_kless.all;\n--use work.klessydra_parameters.all;\n\n-- pipeline pinout --------------------\nentity ID_STAGE is\n generic(\n THREAD_POOL_SIZE : integer;\n RV32M : natural;\n superscalar_exec_en : natural;\n accl_en : natural;\n replicate_accl_en : natural;\n SPM_NUM\t\t : natural; \n Addr_Width : natural;\n SPM_STRT_ADDR : std_logic_vector(31 downto 0);\n ACCL_NUM : natural;\n RF_SIZE : natural;\n RF_CEIL : natural;\n SPM_ADDR_WID : natural\n );\n port (\n\t-- Branch Control Signals\n comparator_en : out std_logic;\n ls_instr_req : out std_logic;\n ie_instr_req : out std_logic;\n dsp_instr_req : out std_logic_vector(ACCL_NUM-1 downto 0);\n decoded_instruction_IE : out std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0);\n decoded_instruction_LS : out std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0);\n decoded_instruction_DSP : out std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0);\n data_be_ID : out std_logic_vector(3 downto 0);\n data_width_ID : out std_logic_vector(1 downto 0);\n amo_store : in std_logic;\n amo_load : out std_logic;\n amo_load_skip : out std_logic;\n load_op : out std_logic;\n store_op : out std_logic;\n instr_word_IE : out std_logic_vector(31 downto 0);\n harc_ID : in integer range THREAD_POOL_SIZE-1 downto 0;\n pc_ID : in std_logic_vector(31 downto 0); -- pc_ID is PC entering ID stage\n core_busy_IE : in std_logic;\n core_busy_LS : in std_logic;\n busy_LS : in std_logic;\n busy_DSP : in std_logic_vector(ACCL_NUM-1 downto 0);\n busy_ID : out std_logic;\n ls_parallel_exec : out std_logic;\n dsp_parallel_exec : out std_logic;\n dsp_to_jump : out std_logic;\n pc_IE : out std_logic_vector(31 downto 0); -- pc_IE is pc entering stage IE ***\n instr_rvalid_ID : in std_logic; \n instr_rvalid_IE : out std_logic; -- validity bit at IE input\n halt_IE : out std_logic;\n halt_LSU : out std_logic;\n instr_word_ID_lat : in std_logic_vector(31 downto 0);\n spm_rs1 : out std_logic;\n spm_rs2 : out std_logic;\n signed_op : out std_logic;\n harc_EXEC : out integer range THREAD_POOL_SIZE-1 downto 0;\n vec_read_rs1_ID : out std_logic;\n vec_read_rs2_ID : out std_logic;\n vec_write_rd_ID : out std_logic;\n vec_width_ID : out std_logic_vector(1 downto 0);\n -- clock, reset active low\n clk_i : in std_logic;\n rst_ni : in std_logic\n );\nend entity; ------------------------------------------\n\n\n-- Klessydra T03x (4 stages) pipeline implementation -----------------------\narchitecture DECODE of ID_STAGE is\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0;\n subtype accl_range is integer range ACCL_NUM - 1 downto 0; \n\n signal harc_ID_to_DSP : accl_range;\n signal dsp_instr_req_wire : std_logic_vector(accl_range);\n -- instruction operands\n signal S_Imm_IE : std_logic_vector(11 downto 0); -- debugging signals\n signal I_Imm_IE : std_logic_vector(11 downto 0); -- debugging signals\n signal B_Imm_IE : std_logic_vector(11 downto 0); -- debugging signals\n signal CSR_ADDR_IE : std_logic_vector(11 downto 0); -- debugging signals\n\n function rs1 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(15+(RF_CEIL-1) downto 15)));\n end;\n\n function rs2 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(20+(RF_CEIL-1) downto 20)));\n end;\n\n function rd (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(7+(RF_CEIL-1) downto 7)));\n end;\n\nbegin\n\n fsm_ID_sync : process(clk_i, rst_ni, instr_word_ID_lat) -- synch single state process\n variable OPCODE_wires : std_logic_vector (6 downto 0);\n variable FUNCT3_wires : std_logic_vector (2 downto 0);\n variable FUNCT7_wires : std_logic_vector (6 downto 0);\n variable FUNCT12_wires : std_logic_vector (11 downto 0);\n begin\n OPCODE_wires := OPCODE(instr_word_ID_lat);\n FUNCT3_wires := FUNCT3(instr_word_ID_lat);\n FUNCT7_wires := FUNCT7(instr_word_ID_lat);\n FUNCT12_wires := FUNCT12(instr_word_ID_lat);\n if rst_ni = '0' then\n pc_IE <= (others => '0');\n harc_EXEC <= 0;\n instr_rvalid_IE <= '0';\n ie_instr_req <= '0';\n ls_instr_req <= '0';\n comparator_en <= '0'; \n elsif rising_edge(clk_i) then\n ls_instr_req <= '0';\n ie_instr_req <= '0';\n if core_busy_IE = '1' or core_busy_LS = '1' or ls_parallel_exec = '0' or dsp_parallel_exec = '0' then -- the instruction pipeline is halted\n halt_IE <= '1';\n halt_LSU <= '1';\n instr_rvalid_IE <= '0';\n elsif instr_rvalid_ID = '0' then -- wait for a valid instruction\n instr_rvalid_IE <= '0';\n halt_IE <= '0';\n halt_LSU <= '0';\n else -- process the incoming instruction \n halt_IE <= '0';\n halt_LSU <= '0';\n instr_rvalid_IE <= '1';\n if dsp_to_jump = '0' then\n instr_word_IE <= instr_word_ID_lat;\n else\n instr_word_IE <= x\"0000_006F\";\n end if;\n -- pc propagation\n pc_IE <= pc_ID;\n -- harc propagation\n harc_EXEC <= harc_ID;\n --S_Imm_IE <= std_logic_vector(to_unsigned(S_immediate(instr_word_ID_lat), 12));\n --I_Imm_IE <= std_logic_vector(to_unsigned(to_integer(unsigned(I_immediate(instr_word_ID_lat))), 12));\n --B_Imm_IE <= std_logic_vector(to_unsigned(to_integer(unsigned(B_immediate(instr_word_ID_lat))), 12));\n --CSR_ADDR_IE <= std_logic_vector(to_unsigned(to_integer(unsigned(CSR_ADDR(instr_word_ID_lat))), 12));\n\n comparator_en <= '0';\n ie_instr_req <= '0';\n amo_load_skip <= '0';\n amo_load <= '0';\n load_op <= '0';\n store_op <= '0';\n signed_op <= '0';\n if accl_en = 1 then\n spm_rs1 <= '0';\n spm_rs2 <= '0';\n vec_write_rd_ID <= '0';\n vec_read_rs1_ID <= '0';\n vec_read_rs2_ID <= '0';\n vec_width_ID <= \"00\";\n end if;\n\n -----------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n -----------------------------------------------------------------------------------------------------------\n\n -- process the instruction\n -- read data from the operand registers\n -- Decode Starts here\n\n case OPCODE_wires is\n\t\t\t\n when OP_IMM =>\n ie_instr_req <= '1';\n if(rd(instr_word_ID_lat) /= 0) then\n case FUNCT3_wires is\n when ADDI => -- ADDI instruction\n decoded_instruction_IE <= ADDI_pattern;\n when SLTI => -- SLTI instruction\n decoded_instruction_IE <= SLTI_pattern;\n when SLTIU => -- SLTIU instruction\n decoded_instruction_IE <= SLTIU_pattern;\n when ANDI => -- ANDI instruction\n decoded_instruction_IE <= ANDI_pattern;\n when ORI => -- ORI instruction\n decoded_instruction_IE <= ORI_pattern;\n when XORI => -- XORI instruction\n decoded_instruction_IE <= XORI_pattern;\n when SLLI => -- SLLI instruction\n decoded_instruction_IE <= SLLI_pattern;\n when SRLI_SRAI =>\n case FUNCT7_wires is\n when SRLI7 => -- SRLI instruction\n decoded_instruction_IE <= SRLI7_pattern;\n when SRAI7 => -- SRAI instruction\n decoded_instruction_IE <= SRAI7_pattern;\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case; -- FUNCT7_wires cases\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case; -- FUNCT3_wires cases \n else -- R0_INSTRUCTION \n decoded_instruction_IE <= NOP_pattern;\n end if; -- if rd(instr_word_ID_lat) /=0\n\t\t\t\t\n when LUI => -- LUI instruction\n ie_instr_req <= '1';\n if (rd(instr_word_ID_lat) /= 0) then\n decoded_instruction_IE <= LUI_pattern;\n else -- R0_INSTRUCTION\n decoded_instruction_IE <= NOP_pattern;\n end if;\n\t\t\t\t\n when AUIPC => -- AUIPC instruction\n ie_instr_req <= '1';\n if (rd(instr_word_ID_lat) /= 0) then\n decoded_instruction_IE <= AUIPC_pattern;\n else -- R0_INSTRUCTION\n decoded_instruction_IE <= NOP_pattern;\n end if;\n\n when OP =>\n ie_instr_req <= '1';\n if (rd(instr_word_ID_lat) /= 0) then\n case FUNCT7_wires is\n when OP_I1 =>\n", "right_context": " decoded_instruction_IE <= SLT_pattern;\n when SLTU => -- SLTU instruction\n comparator_en <= '1';\n decoded_instruction_IE <= SLTU_pattern;\n when ANDD => -- AND instruction\n decoded_instruction_IE <= ANDD_pattern;\n when ORR => -- OR instruction\n decoded_instruction_IE <= ORR_pattern;\n when XORR => -- XOR instruction \n decoded_instruction_IE <= XORR_pattern;\n when SLLL => -- SLL instruction \n decoded_instruction_IE <= SLLL_pattern;\n when SRLL => -- SRL instruction \n decoded_instruction_IE <= SRLL7_pattern;\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case;\n when OP_I2 =>\n case FUNCT3_wires is\n when SUB7 =>\n decoded_instruction_IE <= SUB7_pattern;\n when SRAA =>\n decoded_instruction_IE <= SRAA7_pattern;\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case;\n when OP_M => -- MUL/DIV instructions\n if RV32M = 1 then\n case FUNCT3_wires is\n when MUL =>\n comparator_en <= '1';\n decoded_instruction_IE <= MUL_pattern;\n when MULH =>\n comparator_en <= '1';\n signed_op <= '1';\n decoded_instruction_IE <= MULH_pattern;\n when MULHSU =>\n comparator_en <= '1';\n signed_op <= '1';\n decoded_instruction_IE <= MULHSU_pattern;\n when MULHU =>\n comparator_en <= '1';\n decoded_instruction_IE <= MULHU_pattern;\n when DIV =>\n comparator_en <= '1';\n signed_op <= '1';\n decoded_instruction_IE <= DIV_pattern;\n when DIVU =>\n comparator_en <= '1';\n decoded_instruction_IE <= DIVU_pattern;\n when REMD =>\n comparator_en <= '1';\n signed_op <= '1';\n decoded_instruction_IE <= REM_pattern;\n when REMDU =>\n comparator_en <= '1';\n decoded_instruction_IE <= REMU_pattern;\n when others =>\n decoded_instruction_IE <= ILL_pattern;\n end case;\n else\n decoded_instruction_IE <= ILL_pattern; \n end if;\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case;\n else -- R0_INSTRUCTION\n decoded_instruction_IE <= NOP_pattern;\n end if;\n\n when JAL => -- JAL instruction\n ie_instr_req <= '1';\n decoded_instruction_IE <= JAL_pattern;\n\n when JALR => -- JAL instruction\n ie_instr_req <= '1';\n decoded_instruction_IE <= JALR_pattern;\n\n when BRANCH => -- BRANCH instruction \n ie_instr_req <= '1';\n case FUNCT3_wires is\n when BEQ => -- BEQ instruction \n comparator_en <= '1';\n decoded_instruction_IE <= BEQ_pattern;\n when BNE => -- BNE instruction\n comparator_en <= '1';\n decoded_instruction_IE <= BNE_pattern;\n when BLT => -- BLT instruction \n comparator_en <= '1';\n decoded_instruction_IE <= BLT_pattern;\n when BLTU => -- BLTU instruction\n comparator_en <= '1';\n decoded_instruction_IE <= BLTU_pattern;\n when BGE => -- BGE instruction\n comparator_en <= '1';\n decoded_instruction_IE <= BGE_pattern;\n when BGEU => -- BGEU instruction\n comparator_en <= '1';\n decoded_instruction_IE <= BGEU_pattern;\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case; -- FUNCT3_wires cases\n\n when LOAD => -- LOAD instruction\n load_op <= '1';\n if (rd(instr_word_ID_lat) /= 0) then -- is all in the next_state process\n case FUNCT3_wires is\n when LW =>\n ls_instr_req <= '1';\n data_width_ID <= \"10\";\n data_be_ID <= \"1111\";\n decoded_instruction_LS <= LW_pattern;\n when LH =>\n ls_instr_req <= '1';\n data_width_ID <= \"01\";\n data_be_ID <= \"0011\";\n decoded_instruction_LS <= LH_pattern;\n when LHU =>\n ls_instr_req <= '1';\n data_width_ID <= \"01\";\n data_be_ID <= \"0011\";\n decoded_instruction_LS <= LHU_pattern;\n when LB =>\n ls_instr_req <= '1';\n data_width_ID <= \"00\";\n data_be_ID <= \"0001\";\n decoded_instruction_LS <= LB_pattern;\n when LBU =>\n ls_instr_req <= '1';\n data_width_ID <= \"00\";\n data_be_ID <= \"0001\";\n decoded_instruction_LS <= LBU_pattern;\n when others => -- ILLEGAL_INSTRUCTION\n ie_instr_req <= '1';\n decoded_instruction_IE <= ILL_pattern;\n end case;\n else -- R0_INSTRUCTION\n ie_instr_req <= '1';\n decoded_instruction_IE <= NOP_pattern;\n end if;\n\n when STORE => -- STORE instruction\n store_op <= '1';\n case FUNCT3_wires is\n when SW => -- is all in the next_state process\n ls_instr_req <= '1';\n ie_instr_req <= '1';\n data_width_ID <= \"10\";\n data_be_ID <= \"1111\";\n decoded_instruction_LS <= SW_pattern;\n decoded_instruction_IE <= SW_MIP_pattern;\n when SH =>\n ls_instr_req <= '1';\n data_width_ID <= \"01\";\n data_be_ID <= \"0011\";\n decoded_instruction_LS <= SH_pattern;\n when SB =>\n ls_instr_req <= '1';\n data_width_ID <= \"00\";\n data_be_ID <= \"0001\";\n decoded_instruction_LS <= SB_pattern;\n when others => -- ILLEGAL_INSTRUCTION\n ie_instr_req <= '1';\n decoded_instruction_IE <= ILL_pattern;\n end case;\n\n when MISC_MEM =>\n ie_instr_req <= '1';\n case FUNCT3_wires is\n when FENCE => -- FENCE instruction\n decoded_instruction_IE <= FENCE_pattern;\n when FENCEI => -- FENCEI instruction\n decoded_instruction_IE <= FENCEI_pattern;\n when others => -- ILLEGAL_INSTRUCTION\n decoded_instruction_IE <= ILL_pattern;\n end case; -- FUNCT3_wires cases\n\n when SYSTEM =>\n ie_instr_req <= '1';\n case FUNCT3_wires is\n when PRIV =>\n if (rs1(instr_word_ID_lat) = 0 and rd(instr_word_ID_lat) = 0) then\n case FUNCT12_wires is\n when ECALL => -- ECALL instruction\n decoded_instruction_IE <= ECALL_pattern;\n when EBREAK => -- EBREAK instruction \n decoded_instruction_IE <= EBREAK_pattern;\n when mret => -- mret instruction \n decoded_instruction_IE <= MRET_pattern;\n when WFI => -- WFI instruction \n decoded_instruction_IE <= WFI_pattern;\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case; -- FUNCT12_wires cases\n else -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end if;\n when CSRRW =>\n decoded_instruction_IE <= CSRRW_pattern;\n when CSRRS =>\n if(rd(instr_word_ID_lat) /= 0) then\n decoded_instruction_IE <= CSRRS_pattern;\n else -- R0_INSTRUCTION\n decoded_instruction_IE <= NOP_pattern;\n end if;\n when CSRRC =>\n if(rd(instr_word_ID_lat) /= 0) then\n decoded_instruction_IE <= CSRRC_pattern;\n else -- R0_INSTRUCTION\n decoded_instruction_IE <= NOP_pattern;\n end if;\n when CSRRWI =>\n decoded_instruction_IE <= CSRRWI_pattern;\n when CSRRSI =>\n if(rd(instr_word_ID_lat) /= 0) then\n decoded_instruction_IE <= CSRRSI_pattern;\n else -- R0_INSTRUCTION\n decoded_instruction_IE <= NOP_pattern; -- AAA highly likely not to be a NOP\n end if;\n when CSRRCI =>\n if(rd(instr_word_ID_lat) /= 0) then\n decoded_instruction_IE <= CSRRCI_pattern;\n else -- R0_INSTRUCTION\n decoded_instruction_IE <= NOP_pattern;\n end if;\n when others => -- ILLEGAL_INSTRUCTION \n decoded_instruction_IE <= ILL_pattern;\n end case; -- FUNCT3_wires cases\n\n when AMO =>\n data_width_ID <= \"10\";\n case FUNCT3_wires is\n when SINGLE =>\n ls_instr_req <= '1';\n decoded_instruction_LS <= AMOSWAP_pattern;\n if(rd(instr_word_ID_lat) /= 0) then\n amo_load_skip <= '0';\n if amo_store = '1' then\n amo_load <= '0';\n elsif amo_store = '0' then\n amo_load <= '1';\n end if;\n elsif (rd(instr_word_ID_lat) = 0) then\n amo_load_skip <= '1';\n end if;\n when others => -- ILLEGAL_INSTRUCTION\n ie_instr_req <= '1';\n decoded_instruction_IE <= ILL_pattern;\n end case;\n\n when KMEM =>\n if accl_en = 1 then\n case FUNCT7_wires is\n when KMEMLD => -- KMEMLD_INSTRUCTION\n ls_instr_req <= '1';\n decoded_instruction_LS <= KMEMLD_pattern;\n when KMEMSTR => -- KMEMSTR_INSTRUCTION\n ls_instr_req <= '1';\n decoded_instruction_LS <= KMEMSTR_pattern;\n when KBCASTLD => -- KBCASTLD_INSTRUCTION\n ls_instr_req <= '1';\n decoded_instruction_LS <= KBCASTLD_pattern;\n when others => -- ILLEGAL_INSTRUCTION\n ie_instr_req <= '1';\n decoded_instruction_IE <= ILL_pattern;\n end case;\n end if;\n\n when KDSP =>\n if accl_en = 1 then\n if busy_DSP(harc_ID_to_DSP) = '0' then\n case FUNCT7_wires is\n when KADDV => -- KADDV_INSTRUCTION\n vec_write_rd_ID <= '1';\n vec_read_rs1_ID <= '1';\n vec_read_rs2_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KADDV_pattern;\n when KSUBV => -- KSUBV_INSTRUCTION\n vec_write_rd_ID <= '1';\n vec_read_rs1_ID <= '1';\n vec_read_rs2_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KSUBV_pattern;\n when KVMUL => -- KVMUL_INSTRUCTION\n vec_write_rd_ID <= '1';\n vec_read_rs1_ID <= '1';\n vec_read_rs2_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KVMUL_pattern;\n when KVRED => -- KVRED_INSTRUCTION\n vec_read_rs1_ID <= '1';\n spm_rs1 <= '1';\n decoded_instruction_DSP <= KVRED_pattern;\n when KDOTP => -- KDOTP_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_read_rs2_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KDOTP_pattern;\n when KDOTPPS => -- KDOTPPS_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_read_rs2_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KDOTPPS_pattern;\n when KSVADDSC => -- KSVADDSC_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KSVADDSC_pattern;\n when KSVADDRF => -- KSVADDRF_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n spm_rs1 <= '1';\n decoded_instruction_DSP <= KSVADDRF_pattern;\n when KSVMULSC => -- KSVMULSC_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KSVMULSC_pattern;\n when KSVMULRF => -- KSVMULRF_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n spm_rs1 <= '1';\n decoded_instruction_DSP <= KSVMULRF_pattern;\n when KSRAV => -- KSRAV_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n spm_rs1 <= '1';\n decoded_instruction_DSP <= KSRAV_pattern;\n when KSRLV => -- KSRLV_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n spm_rs1 <= '1';\n decoded_instruction_DSP <= KSRLV_pattern;\n when KRELU => -- KRELU_INSTRUCTION\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n spm_rs1 <= '1';\n decoded_instruction_DSP <= KRELU_pattern;\n when KVSLT =>\n vec_write_rd_ID <= '1';\n vec_read_rs1_ID <= '1';\n vec_read_rs2_ID <= '1';\n spm_rs1 <= '1';\n spm_rs2 <= '1';\n decoded_instruction_DSP <= KVSLT_pattern;\n when KSVSLT =>\n vec_write_rd_ID <= '1';\n vec_read_rs1_ID <= '1';\n spm_rs1 <= '1';\n decoded_instruction_DSP <= KSVSLT_pattern;\n when KBCAST => -- KBCAST_INSTRUCTION\n vec_write_rd_ID <= '1';\n decoded_instruction_DSP <= KBCAST_pattern;\n when KVCP => -- KVCP_INSTRUCTION\n spm_rs1 <= '1';\n vec_read_rs1_ID <= '1';\n vec_write_rd_ID <= '1';\n decoded_instruction_DSP <= KVCP_pattern;\n when others => -- ILLEGAL_INSTRUCTION\n ie_instr_req <= '1';\n decoded_instruction_IE <= ILL_pattern;\n end case;\n else\n ie_instr_req <= '1';\n decoded_instruction_IE <= JAL_pattern;\n end if;\n end if;\n \n when others => -- ILLEGAL_INSTRUCTION\n ie_instr_req <= '1';\n decoded_instruction_IE <= ILL_pattern;\n\n end case; -- OPCODE_wires cases \n -- Decode OF INSTRUCTION (END) --------------------------\n\n end if; -- instr. conditions\n end if; -- clk\n end process;\n\n---------------------------------------------------------------------------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n-- ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n-- ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n---------------------------------------------------------------------------------------------------------------------------------------------------------------\n\n harc_ID_to_DSP <= 0 when replicate_accl_en= 0 else harc_ID;\n\n Superscalar_Enable : if superscalar_exec_en = 1 generate\n fsm_ID_comb : process(all)\n variable OPCODE_wires : std_logic_vector (6 downto 0);\n begin\n OPCODE_wires := OPCODE(instr_word_ID_lat);\t\n -- parallelism enablers, halts the pipeline when it is zero. -------------------\n ls_parallel_exec <= '0' when (OPCODE_wires = LOAD or OPCODE_wires = STORE or OPCODE_wires = AMO or OPCODE_wires = KMEM) and busy_LS = '1' else '1';\n dsp_parallel_exec <= '0' when (OPCODE_wires = KMEM or OPCODE_wires = AMO) and busy_DSP(harc_ID_to_DSP) = '1' else '1';\n dsp_to_jump <= '1' when OPCODE_wires = KDSP and busy_DSP(harc_ID_to_DSP) = '1' else '0';\n if core_busy_IE = '1' or core_busy_LS = '1' or ls_parallel_exec = '0' or dsp_parallel_exec = '0' then\n busy_ID <= '1'; -- wait for the stall to finish, block new instructions \n elsif core_busy_IE = '0' and core_busy_LS = '0' and ls_parallel_exec = '1' and dsp_parallel_exec = '1' then\n busy_ID <= '0'; -- wait for a valid instruction or process the instruction \n end if; \n end process;\n end generate;\n\n Superscalar_Disable: if superscalar_exec_en = 0 generate\n fsm_ID_comb : process(all)\n variable OPCODE_wires : std_logic_vector (6 downto 0);\n begin\n OPCODE_wires := OPCODE(instr_word_ID_lat);\t\n ls_parallel_exec <= '0' when busy_LS = '1' else '1';\n dsp_parallel_exec <= '0' when unsigned(busy_DSP) /= 0 else '1';\n dsp_to_jump <= '1' when OPCODE_wires = KDSP and busy_DSP(harc_ID_to_DSP) = '1' else '0';\n if core_busy_IE = '1' or core_busy_LS = '1' or ls_parallel_exec = '0' or dsp_parallel_exec = '0' then\n busy_ID <= '1'; -- wait for the stall to finish, block new instructions \n elsif core_busy_IE = '0' and core_busy_LS = '0' and ls_parallel_exec = '1' and dsp_parallel_exec = '1' then\n busy_ID <= '0'; -- wait for a valid instruction or process the instruction \n end if; \n end process;\n end generate;\n\n process(all)\n begin\n dsp_instr_req_wire <= (others => '0');\n if core_busy_IE = '0' and core_busy_LS = '0' and ls_parallel_exec = '1' and dsp_parallel_exec = '1' and instr_rvalid_ID = '1' then\n if OPCODE(instr_word_ID_lat) = KDSP then\n dsp_instr_req_wire(harc_ID_to_DSP) <= '1';\n end if;\n end if;\n end process;--------------------------------------------------------------------------------\n\n process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n dsp_instr_req <= dsp_instr_req_wire;\n end if;\n end process;\n\n---------------------------------------------------------------------- end of ID stage -----------\n--------------------------------------------------------------------------------------------------\nend DECODE;\n--------------------------------------------------------------------------------------------------\n-- END of ID architecture ------------------------------------------------------------------------\n--------------------------------------------------------------------------------------------------", "groundtruth": " case FUNCT3_wires is\n when ADD => --ADD instruction\n decoded_instruction_IE <= ADD7_pattern;\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-IE_STAGE.vhd", "left_context": "--------------------------------------------------------------------------------------------------------------\n-- stage IE -- (Instruction Execute) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 01-03-2020 --\n--------------------------------------------------------------------------------------------------------------\n-- This stage is composed of an fsm unit fsm_IE that executes the incoming operations, --\n-- Priveleged and CSR instructions are also executed here, load-store and custom instructions are not --\n-- The multipliers are a up to a three cycle latency instructions, while the dividers are up to 32 cycles --\n-- and drives the control signals for accessing data memory and stalling the pipeline if needed --\n-- fsm_IE may invoke separate units for handling specific instructions (exceptions, csrs) --\n--------------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n-- pipeline pinout --------------------\nentity IE_STAGE is\n generic(\n THREAD_POOL_SIZE : integer;\n RV32M : natural;\n RF_CEIL : natural\n );\n port (\n\t-- clock, and reset active low\n clk_i, rst_ni : in std_logic;\n irq_i : in std_logic;\n RS1_Data_IE : in std_logic_vector(31 downto 0);\n RS2_Data_IE : in std_logic_vector(31 downto 0);\n irq_pending : in std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n fetch_enable_i : in std_logic;\n csr_instr_done : in std_logic;\n csr_access_denied_o : in std_logic;\n csr_rdata_o : in std_logic_vector(31 downto 0);\n pc_IE : in std_logic_vector(31 downto 0);\n instr_word_IE : in std_logic_vector(31 downto 0);\n data_addr_internal_IE : in std_logic_vector(31 downto 0);\n comparator_en : in std_logic;\n signed_op : in std_logic;\n ie_instr_req : in std_logic;\n dbg_req_o : in std_logic;\n MSTATUS : in array_2D(THREAD_POOL_SIZE-1 downto 0)(1 downto 0);\n harc_EXEC : in integer range THREAD_POOL_SIZE-1 downto 0;\n instr_rvalid_IE : in std_logic; -- validity bit at IE input\n taken_branch : in std_logic;\n halt_IE : in std_logic;\n decoded_instruction_IE : in std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0);\n csr_addr_i : out std_logic_vector(11 downto 0);\n ie_except_data : out std_logic_vector(31 downto 0);\n ie_csr_wdata_i : out std_logic_vector(31 downto 0);\n csr_op_i : out std_logic_vector(2 downto 0);\n csr_wdata_en : out std_logic;\n harc_to_csr : out integer range THREAD_POOL_SIZE-1 downto 0;\n csr_instr_req : out std_logic;\n core_busy_IE : out std_logic;\n jump_instr : out std_logic;\n jump_instr_lat : out std_logic;\n WFI_Instr : out std_logic;\n sleep_state : out std_logic;\n reset_state : out std_logic;\n set_branch_condition : out std_logic;\n IE_except_condition : out std_logic;\n set_mret_condition : out std_logic;\n set_wfi_condition : out std_logic;\n ie_taken_branch : out std_logic;\n branch_instr : out std_logic;\n branch_instr_lat : out std_logic;\n PC_offset : out array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n served_irq \t : out std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n dbg_ack_i : out std_logic;\n ebreak_instr : out std_logic;\n absolute_jump : out std_logic;\n instr_rvalid_WB : out std_logic;\n instr_word_IE_WB : out std_logic_vector (31 downto 0);\n IE_WB_EN : out std_logic;\n IE_WB : out std_logic_vector(31 downto 0);\n MUL_WB_EN : out std_logic;\n MUL_WB : out std_logic_vector(31 downto 0);\n harc_IE_WB : out integer range THREAD_POOL_SIZE-1 downto 0;\n pc_WB : out std_logic_vector(31 downto 0);\n state_IE : out fsm_IE_states\n\t );\nend entity; ------------------------------------------\n\n\n-- Klessydra T03x (4 stages) pipeline implementation -----------------------\narchitecture EXECUTE of IE_STAGE is\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0;\n\n signal core_busy_IE_lat : std_logic;\n\n signal zero_rs1 : std_logic;\n signal zero_rs2 : std_logic;\n signal pass_BEQ : std_logic;\n signal pass_BNE : std_logic;\n signal pass_BLT : std_logic;\n signal pass_BLTU : std_logic;\n signal pass_BGE : std_logic;\n signal pass_BGEU : std_logic;\n\n signal state_mulh, nextstate_mulh : mulh_states;\n signal state_mul, nextstate_mul : mul_states;\n signal state_div, nextstate_div : div_states;\n signal nextstate_IE : fsm_IE_states;\n signal partial_mulh_a : std_logic_vector(31 downto 0);\n signal partial_mulh_b : std_logic_vector(31 downto 0);\n signal partial_mulh_c : std_logic_vector(31 downto 0);\n signal partial_mulh_d : std_logic_vector(31 downto 0);\n signal partial_mul_b : std_logic_vector(31 downto 0);\n signal partial_mul_c : std_logic_vector(31 downto 0);\n signal partial_mul_d : std_logic_vector(31 downto 0);\n signal partial_mulh_a_wire : std_logic_vector(31 downto 0);\n signal partial_mulh_b_wire : std_logic_vector(31 downto 0);\n signal partial_mulh_c_wire : std_logic_vector(31 downto 0);\n signal partial_mulh_d_wire : std_logic_vector(31 downto 0);\n signal partial_mul_b_wire : std_logic_vector(31 downto 0);\n signal partial_mul_c_wire : std_logic_vector(31 downto 0);\n signal partial_mul_d_wire : std_logic_vector(31 downto 0);\n signal MUL_int, MUL : std_logic_vector(63 downto 0);\n signal MUL_low : std_logic_vector(31 downto 0);\n signal RS1_Data_IE_int : std_logic_vector(31 downto 0);\n signal RS2_Data_IE_int : std_logic_vector(31 downto 0);\n signal RS1_Data_IE_int_wire : std_logic_vector(31 downto 0);\n signal RS2_Data_IE_int_wire : std_logic_vector(31 downto 0);\n signal div_bypass_en : std_logic;\n signal sub : std_logic_vector(32 downto 0);\n signal res_wire, res : std_logic_vector(63 downto 0);\n signal div_count_wire, div_count : unsigned(5 downto 0);\n\n signal add_op_A : std_logic_vector(31 downto 0);\n signal add_op_B : std_logic_vector(31 downto 0);\n signal sr_op_A : std_logic_vector(31 downto 0); \n signal sr_op_B : std_logic_vector(4 downto 0);\n signal sl_op_A : std_logic_vector(31 downto 0);\n signal sl_op_B : std_logic_vector(4 downto 0);\n signal logic_op_A : std_logic_Vector(31 downto 0);\n signal logic_op_B : std_logic_Vector(31 downto 0);\n\n signal wfi_count : std_logic_vector(31 downto 0);\n\n -- signals for counting intructions\n signal clock_cycle : std_logic_vector(63 downto 0); -- RDCYCLE\n signal external_counter : std_logic_vector(63 downto 0); -- RDTIME\n --signal instruction_counter : std_logic_vector(63 downto 0); -- RDINSTRET\n\n function rs1 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(15+(RF_CEIL-1) downto 15)));\n end;\n\n function rs2 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(20+(RF_CEIL-1) downto 20)));\n end;\n\n function rd (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(7+(RF_CEIL-1) downto 7)));\n end;\n\nbegin\n\n ----------------------------------------------------------\n -- ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• --\n ----------------------------------------------------------\n\n fsm_IE_sync : process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n IE_WB <= std_logic_vector(to_unsigned(0, 32));\n IE_WB_EN <= '0';\n MUL_WB_EN <= '0';\n --instruction_counter <= std_logic_vector(to_unsigned(0, 64));\n csr_instr_req <= '0';\n csr_wdata_en <= '0';\n csr_op_i <= (others => '0');\n ie_except_data <= (others => '0');\n ie_csr_wdata_i <= (others => '0');\n csr_addr_i <= (others => '0');\n wfi_count <= (others => '0');\n core_busy_IE_lat <= '0';\n elsif rising_edge(clk_i) then\n\t\t core_busy_IE_lat <= core_busy_IE;\n csr_instr_req <= '0';\n\n case state_IE is -- stage state\n when sleep =>\n null;\n when reset =>\n null;\n when debug =>\n null;\n when normal =>\n -- check if there is a valid instruction and the thread it belongs to is not in a delay slot: \n if ie_instr_req = '0' and core_busy_IE_lat = '0' then\n IE_WB_EN <= '0';\n MUL_WB_EN <= '0';\n -- in a generic version we would have conditions on busy_WB \n -- in all states of the IE stage, and similarly in the comb process, just\n -- like we did in the ID stage.\n elsif irq_pending(harc_EXEC) = '1' then\n -- manage irq as an absolute branch to MTVEC, also defining mepc value properly in program counter unit\n -- irq is served only if we are not in a delay slot for the interrupted harc\n -- for simplicity presently only harc 0 is interrupted (decided in program counter unit)\n -- the current valid instruction is discarded, only its pc value gets used for mepc\n IE_WB_EN <= '0';\n MUL_WB_EN <= '0';\n else\n --instruction_counter <= std_logic_vector(unsigned(instruction_counter)+1); -- AAA should be updated or removed since the exec stage has been split\n pc_WB <= pc_IE;\n instr_word_IE_WB <= instr_word_IE;\n harc_IE_WB <= harc_EXEC;\n csr_wdata_en <= '0';\n -- misaligned_err <= '0';\n\n -- EXECUTE OF INSTRUCTION -------------------------------------------\n\n IE_WB_EN <= '0';\n MUL_WB_EN <= '0';\n\n -------------------------- ADDER ------------------------------\n if decoded_instruction_IE(ADDI_bit_position) = '1' or\n decoded_instruction_IE(ADD7_bit_position) = '1' or\n decoded_instruction_IE(SUB7_bit_position) = '1' or\n decoded_instruction_IE(AUIPC_bit_position) = '1' or\n decoded_instruction_IE(JAL_bit_position) = '1' or \n decoded_instruction_IE(JALR_bit_position) = '1' then\n if (rd(instr_word_IE) /= 0) then -- this condition is only for JAL and JALR which still execute even when \"rd = x0\"\n IE_WB_EN <= '1';\n end if;\n IE_WB <= std_logic_vector(signed(add_op_A)+signed(add_op_B));\n end if;\n ---------------------------------------------------------------\n\n ----------------------- SHIFTERS -----------------------------\n if decoded_instruction_IE(SLLI_bit_position) = '1' or\n decoded_instruction_IE(SLLL_bit_position) = '1' then\n IE_WB_EN <= '1';\n IE_WB <= to_stdlogicvector(to_bitvector(sl_op_A) sll to_integer(unsigned(sl_op_B)));\n end if;\n if decoded_instruction_IE(SRLI7_bit_position) = '1' or\n decoded_instruction_IE(SRLL7_bit_position) = '1' then\n IE_WB_EN <= '1';\n IE_WB <= to_stdlogicvector(to_bitvector(sr_op_A) srl to_integer(unsigned(sr_op_B)));\n end if;\n if decoded_instruction_IE(SRAI7_bit_position) = '1' or\n decoded_instruction_IE(SRAA7_bit_position) = '1' then\n IE_WB_EN <= '1';\n IE_WB <= to_stdlogicvector(to_bitvector(sr_op_A) sra to_integer(unsigned(sr_op_B)));\n end if;\n --------------------------------------------------------------\n\n -------------------- LOGIC UNITS -----------------------------\n if decoded_instruction_IE(ANDI_bit_position) = '1' or\n decoded_instruction_IE(ANDD_bit_position) = '1' then\n IE_WB_EN <= '1';\n IE_WB <= logic_op_A and logic_op_B;\n end if;\n\n if decoded_instruction_IE(ORI_bit_position) = '1' or\n decoded_instruction_IE(ORR_bit_position) = '1' then\n IE_WB_EN <= '1';\n IE_WB <= logic_op_A or logic_op_B;\n end if;\n\n if decoded_instruction_IE(XORI_bit_position) = '1' or\n decoded_instruction_IE(XORR_bit_position) = '1' then\n IE_WB_EN <= '1';\n IE_WB <= logic_op_A xor logic_op_B;\n end if;\n --------------------------------------------------------------\n\n\n if decoded_instruction_IE(SLTI_bit_position) = '1' then\n if (signed(RS1_Data_IE) < signed (I_immediate(instr_word_IE))) then\n IE_WB_EN <= '1';\n IE_WB <= std_logic_vector(to_unsigned(1, 32));\n else\n IE_WB_EN <= '1';\n IE_WB <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(SLTIU_bit_position) = '1' then\n if (unsigned(RS1_Data_IE) < unsigned (I_immediate(instr_word_IE))) then\n IE_WB_EN <= '1';\n IE_WB <= std_logic_vector(to_unsigned(1, 32));\n else\n IE_WB_EN <= '1';\n IE_WB <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(LUI_bit_position) = '1' then\n IE_WB_EN <= '1';\n IE_WB <= U_immediate(instr_word_IE);\n end if;\n\n if decoded_instruction_IE(SLT_bit_position) = '1' then\n IE_WB_EN <= '1';\n if pass_BLT = '1' then\n IE_WB <= std_logic_vector(to_unsigned(1, 32));\n else\n IE_WB <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(SLTU_bit_position) = '1' then\n IE_WB_EN <= '1';\n if pass_BLTU = '1' then\n IE_WB <= std_logic_vector(to_unsigned(1, 32));\n else\n IE_WB <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(ECALL_bit_position) = '1' then\n ie_except_data <= ECALL_EXCEPT_CODE;\n csr_wdata_en <= '1';\n end if;\n -----------------------------------------------------------\n\n ---------------- SOFTWARE IRQ SEND OP ---------------------\n if decoded_instruction_IE(SW_MIP_bit_position) = '1' then\n if data_addr_internal_IE(31 downto 8) = x\"0000FF\" then\n csr_op_i <= CSRRW;\n if halt_IE = '0' then\n csr_instr_req <= '1';\n end if;\n ie_csr_wdata_i <= RS2_Data_IE;\n csr_wdata_en <= '1';\n csr_addr_i <= MIP_ADDR;\n for i in harc_range loop\n if data_addr_internal_IE(7 downto 0) = std_logic_vector(to_unsigned((4*i),8)) then\n \tharc_to_csr <= i;\n end if;\n end loop;\n end if;\n end if;\n ---------------------------------------------------------\n\n --------------------- CSR OPS ---------------------------\n if decoded_instruction_IE(CSRRC_bit_position) = '1' or \n decoded_instruction_IE(CSRRS_bit_position) = '1' or \n decoded_instruction_IE(CSRRW_bit_position) = '1' then\n csr_op_i <= FUNCT3(instr_word_IE);\n if halt_IE = '0' then\n csr_instr_req <= '1';\n end if;\n ie_csr_wdata_i <= RS1_Data_IE;\n csr_wdata_en <= '1';\n csr_addr_i <= std_logic_vector(to_unsigned(to_integer(unsigned(CSR_ADDR(instr_word_IE))), 12));\n harc_to_csr <= harc_EXEC;\n end if;\n\n if decoded_instruction_IE(CSRRSI_bit_position) = '1' or \n decoded_instruction_IE(CSRRCI_bit_position) = '1' or \n decoded_instruction_IE(CSRRWI_bit_position) = '1' then\n csr_op_i <= FUNCT3(instr_word_IE);\n if halt_IE = '0' then\n csr_instr_req <= '1';\n end if;\n ie_csr_wdata_i <= std_logic_vector(resize(to_unsigned(rs1(instr_word_IE), 5), 32));\n csr_wdata_en <= '1';\n csr_addr_i <= std_logic_vector(to_unsigned(to_integer(unsigned(CSR_ADDR(instr_word_IE))), 12));\n harc_to_csr <= harc_EXEC;\n end if;\n -------------------------------------------------------\n\n if decoded_instruction_IE(ILL_bit_position) = '1' then\n ie_except_data <= ILLEGAL_INSN_EXCEPT_CODE;\n csr_wdata_en <= '1';\n end if;\n\n if decoded_instruction_IE(WFI_bit_position) = '1' then\n wfi_count <= std_logic_vector(unsigned(wfi_count)+1); \n end if;\n\n if RV32M = 1 then\n if decoded_instruction_IE(MUL_bit_position) = '1' then\n --IE_WB_EN <= '1';\n MUL_WB_EN <= '1';\n --IE_WB <= MUL_low(31 downto 0);\n MUL_WB <= MUL_low;\n end if;\n\n if decoded_instruction_IE(MULH_bit_position) = '1' or \n decoded_instruction_IE(MULHU_bit_position) = '1' or\n decoded_instruction_IE(MULHSU_bit_position) = '1' then\n if core_busy_IE = '0' then\n IE_WB_EN <= '1';\n IE_WB <= MUL(63 downto 32);\n end if;\n end if;\n\n if decoded_instruction_IE(DIVU_bit_position) = '1' then\n if div_count(5) = '1' or div_bypass_en = '1' then\n IE_WB_EN <= '1';\n end if;\n if zero_rs2 = '1' then\n IE_WB <= (others => '1');\n elsif zero_rs1 = '1' then\n IE_WB <= (others => '0');\n elsif pass_BEQ then\n IE_WB <= (31 downto 1 => '0') & '1';\n elsif pass_BLTU then\n IE_WB <= (others => '0');\n else\n IE_WB <= res(31 downto 0);\n end if;\n end if;\n\n if decoded_instruction_IE(DIV_bit_position) = '1' then\n if div_count(5) = '1' or div_bypass_en = '1' then\n IE_WB_EN <= '1';\n end if;\n if zero_rs2 = '1' then\n IE_WB <= (others => '1');\n elsif zero_rs1 = '1' then\n IE_WB <= (others => '0');\n -- elsif abs(signed(RS1_DATA_IE)) < abs(signed(RS2_DATA_IE)) then\n -- IE_WB <= (others => '0');\n elsif pass_BEQ then\n if RS2_DATA_IE(31) = RS1_DATA_IE(31) then\n IE_WB <= (31 downto 1 => '0') & '1';\n else\n IE_WB <= (31 downto 0 => '1');\n end if;\n else\n if RS1_DATA_IE(31) = RS2_DATA_IE(31) then\n IE_WB <= res(31 downto 0);\n else\n IE_WB <= std_logic_vector(unsigned(not(res(31 downto 0)))+1);\n end if;\n end if;\n end if;\n\n if decoded_instruction_IE(REMU_bit_position) = '1' then\n if div_count(5) = '1' or div_bypass_en = '1' then\n IE_WB_EN <= '1';\n end if;\n if zero_rs2 = '1' then\n IE_WB <= RS1_Data_IE;\n elsif zero_rs1 = '1' then\n IE_WB <= (others => '0');\n elsif pass_BEQ then\n IE_WB <= (others => '0');\n elsif pass_BLTU then\n IE_WB <= RS1_Data_IE;\n else\n IE_WB <= res(63 downto 32);\n end if;\n end if;\n\n if decoded_instruction_IE(REM_bit_position) = '1' then\n if div_count(5) = '1' or div_bypass_en = '1' then\n IE_WB_EN <= '1';\n end if;\n if zero_rs2 = '1' then\n IE_WB <= RS1_Data_IE;\n elsif zero_rs1 = '1' then\n IE_WB <= (others => '0');\n elsif pass_BEQ then\n IE_WB <= (others => '0');\n -- elsif abs(signed(RS1_DATA_IE)) < abs(signed(RS2_DATA_IE)) then\n -- IE_WB <= RS1_Data_IE;\n -- elsif abs(signed(RS1_DATA_IE)) = abs(signed(RS2_DATA_IE)) then\n -- IE_WB <= (others => '0');\n else\n if RS1_DATA_IE(31) = '1' then\n IE_WB <= std_logic_vector(unsigned(not(res(63 downto 32)))+1);\n else\n IE_WB <= res(63 downto 32);\n end if;\n end if;\n end if;\n end if;\n\n -- EXECUTE OF INSTRUCTION (END) --------------------------\n end if; -- instr_rvalid_IE values\n \n when csr_instr_wait_state =>\n csr_instr_req <= '0';\n if (csr_instr_done = '1' and csr_access_denied_o = '0') then\n if (rd(instr_word_IE) /= 0) then\n IE_WB_EN <= '1';\n IE_WB <= csr_rdata_o;\n else\n IE_WB_EN <= '0';\n end if;\n elsif (csr_instr_done = '1' and csr_access_denied_o = '1') then -- ILLEGAL_INSTRUCTION\n IE_WB_EN <= '0';\n csr_wdata_en <= '1';\n ie_except_data <= ILLEGAL_INSN_EXCEPT_CODE;\n else\n IE_WB_EN <= '0'; -- do nothing and wait\n end if;\n end case; -- fsm_IE state cases\n end if; -- reset, clk_i\n end process;\n\n div_bypass_en_gen : if RV32M = 1 generate\n div_bypass_en <= '1' when zero_rs2 or zero_rs1 or pass_BEQ or (pass_BLTU and not signed_op) else '0';\n end generate;\n\n\n -----------------------------------------------------------\n -- ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• --\n -----------------------------------------------------------\n\n fsm_IE_comb : process(all)\n\n variable PC_offset_wires : array_2D(harc_range)(31 downto 0);\n variable absolute_jump_wires : std_logic;\n variable core_busy_IE_wires : std_logic;\n variable IE_except_condition_wires : std_logic;\n variable set_branch_condition_wires : std_logic;\n variable ie_taken_branch_wires : std_logic;\n variable set_mret_condition_wires : std_logic;\n variable set_wfi_condition_wires : std_logic;\n variable jump_instr_wires : std_logic;\n variable branch_instr_wires : std_logic;\n variable ebreak_instr_wires : std_logic;\n variable dbg_ack_i_wires : std_logic;\n variable WFI_Instr_wires : std_logic;\n variable served_irq_wires : std_logic_vector(harc_range);\n variable nextstate_IE_wires : fsm_IE_states;\n\n begin\n PC_offset_wires := (others => (others => '0'));\n served_irq_wires := (others => '0');\n nextstate_IE_wires := normal;\n absolute_jump_wires := '0';\n core_busy_IE_wires := '0';\n IE_except_condition_wires := '0';\n set_branch_condition_wires := '0';\n set_wfi_condition_wires := '0'; \n ie_taken_branch_wires := '0';\n set_mret_condition_wires := '0';\n jump_instr_wires := '0';\n branch_instr_wires := '0';\n ebreak_instr_wires := '0';\n dbg_ack_i_wires := '0';\n WFI_Instr_wires := '0';\n reset_state <= '0';\n sleep_state <= '0';\n if RV32M = 1 then\n RS1_Data_IE_int_wire <= RS1_Data_IE_int;\n RS2_Data_IE_int_wire <= RS2_Data_IE_int;\n partial_mulh_a_wire <= (others => '0');\n partial_mulh_b_wire <= (others => '0');\n partial_mulh_c_wire <= (others => '0');\n partial_mulh_d_wire <= (others => '0');\n partial_mul_b_wire <= (others => '0');\n partial_mul_c_wire <= (others => '0');\n partial_mul_d_wire <= (others => '0');\n MUL_int <= (others => '0');\n MUL <= (others => '0');\n MUL_low <= (others => '0');\n div_count_wire <= (others => '0');\n res_wire <= (others => '0');\n sub <= (others => '0');\n nextstate_mul <= mult;\n nextstate_mulh <= init;\n nextstate_div <= init;\n end if;\n\n case state_IE is -- stage status\n when sleep =>\n if dbg_req_o = '1' then\n dbg_ack_i_wires := '1';\n core_busy_IE_wires := '1';\n nextstate_IE_wires := sleep;\n sleep_state <= '1';\n elsif irq_i = '1' or fetch_enable_i = '1' then\n nextstate_IE_wires := normal;\n else\n core_busy_IE_wires := '1';\n nextstate_IE_wires := sleep;\n end if;\n\n when reset =>\n reset_state <= '1';\n if dbg_req_o = '1' then\n dbg_ack_i_wires := '1';\n core_busy_IE_wires := '1';\n nextstate_IE_wires := reset;\n elsif fetch_enable_i = '0' then\n nextstate_IE_wires := reset;\n core_busy_IE_wires := '1';\n else\n nextstate_IE_wires := normal;\n end if;\n\n when debug =>\n dbg_ack_i_wires := '1';\n if dbg_req_o = '0' then\n nextstate_IE_wires := normal;\n else\n nextstate_IE_wires := debug;\n core_busy_IE_wires := '1';\n end if;\n\n when normal =>\n\n if ie_instr_req = '0' and core_busy_IE_lat = '0' then\n -- does nothing and wait\n elsif irq_pending(harc_EXEC)= '1' then\n -- manage irq as an absolute branch to MTVEC, also defining mepc value properly in program counter unit\n -- irq is served only if we are not in a delay slot for the interrupted harc\n -- for simplicity presently only harc 0 is interrupted (decided in program counter unit)\n -- the current valid instruction is discarded, only its pc value gets used for mepc\n served_irq_wires(harc_EXEC) := '1';\n ie_taken_branch_wires := '1';\n if decoded_instruction_IE(WFI_bit_position) = '1' then -- Inform the CSR unit that the last instruction before we went to the subroutine was a WFI instruction.\n WFI_Instr_wires := '1';\n end if;\n else -- process the instruction\n \n -- EXECUTE OF INSTRUCTION ---------------------\n\n if decoded_instruction_IE(JAL_bit_position) = '1' then -- JAL instruction\n jump_instr_wires := '1';\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n PC_offset_wires(harc_EXEC) := UJ_immediate(instr_word_IE);\n end if;\n\n if decoded_instruction_IE(JALR_bit_position) = '1' then --JALR instruction\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n PC_offset_wires(harc_EXEC) := std_logic_vector(signed(RS1_Data_IE)\n + signed(I_immediate(instr_word_IE)))\n and X\"FFFFFFFE\"; -- bitwise and to set '0' the LSB -- AAA remove this and put inst_word_IE(31 downto 1) & '0'; instead\n jump_instr_wires := '1';\n absolute_jump_wires := '1';\n end if;\n\n if decoded_instruction_IE(BEQ_bit_position) = '1' then\n branch_instr_wires := '1';\n PC_offset_wires(harc_EXEC) := B_immediate(instr_word_IE);\n if pass_BEQ = '1' then\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(BNE_bit_position) = '1' then\n branch_instr_wires := '1';\n PC_offset_wires(harc_EXEC) := B_immediate(instr_word_IE);\n if pass_BNE = '1' then\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(BLT_bit_position) = '1' then\n branch_instr_wires := '1';\n PC_offset_wires(harc_EXEC) := B_immediate(instr_word_IE);\n if pass_BLT = '1' then\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(BLTU_bit_position) = '1' then\n branch_instr_wires := '1';\n PC_offset_wires(harc_EXEC) := B_immediate(instr_word_IE);\n if pass_BLTU = '1' then\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(BGE_bit_position) = '1' then\n branch_instr_wires := '1';\n PC_offset_wires(harc_EXEC) := B_immediate(instr_word_IE);\n if pass_BGE = '1' then\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(BGEU_bit_position) = '1' then\n branch_instr_wires := '1';\n PC_offset_wires(harc_EXEC) := B_immediate(instr_word_IE);\n if pass_BGEU = '1' then\n set_branch_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(SW_MIP_bit_position) = '1' then\n if data_addr_internal_IE(31 downto 8) = x\"0000FF\" and halt_IE = '0' then\n core_busy_IE_wires := '1';\n nextstate_IE_wires := csr_instr_wait_state;\n end if;\n end if;\n\n if decoded_instruction_IE(CSRRW_bit_position) = '1' or decoded_instruction_IE(CSRRWI_bit_position) = '1' or\n decoded_instruction_IE(CSRRC_bit_position) = '1' or decoded_instruction_IE(CSRRCI_bit_position) = '1' or\n decoded_instruction_IE(CSRRS_bit_position) = '1' or decoded_instruction_IE(CSRRSI_bit_position) = '1' then\n if halt_IE = '0' then\n core_busy_IE_wires := '1';\n nextstate_IE_wires := csr_instr_wait_state;\n end if;\n end if;\n\n if decoded_instruction_IE(ECALL_bit_position) = '1' then\n IE_except_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n\n if decoded_instruction_IE(EBREAK_bit_position) = '1' then\n ebreak_instr_wires := '1';\n end if;\n\n if decoded_instruction_IE(MRET_bit_position) = '1' then\n set_mret_condition_wires := '1';\n ie_taken_branch_wires := '1';\n if fetch_enable_i = '0' then\n nextstate_IE_wires := sleep;\n core_busy_IE_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(WFI_bit_position) = '1' then\n if MSTATUS(harc_EXEC)(0) = '1' then\n set_wfi_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n end if;\n\n if decoded_instruction_IE(ILL_bit_position) = '1' then -- ILLEGAL_INSTRUCTION\n IE_except_condition_wires := '1';\n ie_taken_branch_wires := '1';\n end if;\n\n if RV32M = 1 then\n\n if decoded_instruction_IE(MULH_bit_position) = '1' or\n decoded_instruction_IE(MULHU_bit_position) = '1' or\n decoded_instruction_IE(MULHSU_bit_position) = '1' then\n case state_mulh is\n when init =>\n if RS1_Data_IE(31) = '1' and signed_op = '1' then\n RS1_Data_IE_int_wire <= std_logic_vector(signed(not(RS1_Data_IE))+1);\n else\n RS1_Data_IE_int_wire <= RS1_Data_IE;\n end if;\n if RS2_Data_IE(31) = '1' and signed_op = '1' and decoded_instruction_IE(MULHSU_bit_position) = '0' then\n RS2_Data_IE_int_wire <= std_logic_vector(signed(not(RS2_Data_IE))+1);\n else\n RS2_Data_IE_int_wire <= RS2_Data_IE;\n end if;\n nextstate_mulh <= mult;\n core_busy_IE_wires := '1';\n when mult =>\n partial_mulh_a_wire <= std_logic_vector( unsigned(RS1_Data_IE_int(31 downto 16)) \n * unsigned(RS2_Data_IE_int(31 downto 16)));\n partial_mulh_b_wire <= std_logic_vector( unsigned(RS1_Data_IE_int(15 downto 0)) \n * unsigned(RS2_Data_IE_int(31 downto 16)));\n partial_mulh_c_wire <= std_logic_vector( unsigned(RS1_Data_IE_int(31 downto 16)) \n * unsigned(RS2_Data_IE_int(15 downto 0)));\n partial_mulh_d_wire <= std_logic_vector( unsigned(RS1_Data_IE_int(15 downto 0)) \n * unsigned(RS2_Data_IE_int(15 downto 0)));\n nextstate_mulh <= accum;\n core_busy_IE_wires := '1';\n when accum =>\n MUL_int <= std_logic_vector(( unsigned(partial_mulh_a) & unsigned(partial_mulh_d)) +\n (x\"0000\" & unsigned(partial_mulh_b) & x\"0000\") +\n (x\"0000\" & unsigned(partial_mulh_c) & x\"0000\"));\n if (RS1_Data_IE(31) /= RS2_Data_IE(31) and decoded_instruction_IE(MULH_bit_position) = '1') or\n (RS1_Data_IE(31) = '1' and decoded_instruction_IE(MULHSU_bit_position) = '1') then\n MUL <= std_logic_vector(signed(not(MUL_int))+1);\n else\n MUL <= MUL_int;\n end if;\n end case;\n end if;\n\n if decoded_instruction_IE(MUL_bit_position) = '1' then\n partial_mul_b_wire <= std_logic_vector( unsigned(RS1_Data_IE(15 downto 0)) \n * unsigned(RS2_Data_IE(31 downto 16)));\n partial_mul_c_wire <= std_logic_vector( unsigned(RS1_Data_IE(31 downto 16)) \n * unsigned(RS2_Data_IE(15 downto 0)));\n partial_mul_d_wire <= std_logic_vector( unsigned(RS1_Data_IE(15 downto 0)) \n * unsigned(RS2_Data_IE(15 downto 0)));\n MUL_low <= std_logic_vector((unsigned(partial_mul_d_wire(31 downto 16)) +\n unsigned(partial_mul_b_wire(15 downto 0)) +\n unsigned(partial_mul_c_wire(15 downto 0))) &\n unsigned(partial_mul_d_wire(15 downto 0)));\n end if;\n\n if decoded_instruction_IE(DIV_bit_position) = '1' or \n decoded_instruction_IE(REM_bit_position) = '1' or\n decoded_instruction_IE(DIVU_bit_position) = '1' or \n decoded_instruction_IE(REMU_bit_position) = '1' then\n case state_div is\n when init =>\n if RS1_Data_IE(31) = '0' or signed_op = '0' then\n res_wire <= (31 downto 0 => '0') & RS1_Data_IE;\n else\n RS1_Data_IE_int_wire <= std_logic_vector(signed(not(RS1_Data_IE)) + 1);\n res_wire <= (31 downto 0 => '0') & RS1_Data_IE_int_wire;\n end if;\n if RS2_Data_IE(31) = '0' or signed_op = '0' then\n RS2_Data_IE_int_wire <= RS2_Data_IE;\n else\n RS2_Data_IE_int_wire <= std_logic_vector(signed(not(RS2_Data_IE)) + 1);\n end if;\n nextstate_div <= divide;\n core_busy_IE_wires := '1';\n when divide =>\n if div_count(5) /= '1' then\n div_count_wire <= div_count + 1;\n nextstate_div <= divide;\n core_busy_IE_wires := '1';\n end if;\n if sub(32) = '1' then -- RS2_Data_IE is the divisor\n res_wire <= res(62 downto 0) & '0';\n else\n res_wire <= sub(31 downto 0) & res(30 downto 0) & '1';\n end if;\n sub <= std_logic_vector(('0' & unsigned(res(62 downto 31))) - ('0' & unsigned(RS2_Data_IE_int)));\n end case; \n end if;\n\n end if; -- END RV32M\n\n if dbg_req_o = '1' then\n nextstate_IE_wires := debug;\n dbg_ack_i_wires := '1';\n core_busy_IE_wires := '1';\n end if;\n\n -- EXECUTE OF INSTRUCTION (END)\n end if; -- instr_rvalid_IE values \n\n when csr_instr_wait_state =>\n if csr_instr_done = '0' then\n nextstate_IE_wires := csr_instr_wait_state;\n core_busy_IE_wires := '1';\n elsif (csr_instr_done = '1' and csr_access_denied_o = '1') then -- ILLEGAL_INSTRUCTION\n nextstate_IE_wires := normal;\n IE_except_condition_wires := '1';\n ie_taken_branch_wires := '1';\n else\n nextstate_IE_wires := normal;\n end if;\n\n end case; -- fsm_IE state cases\n\n PC_offset <= PC_offset_wires;\n absolute_jump <= absolute_jump_wires;\n core_busy_IE <= core_busy_IE_wires;\n IE_except_condition <= IE_except_condition_wires;\n set_branch_condition <= set_branch_condition_wires;\n served_irq <= served_irq_wires;\n ie_taken_branch <= ie_taken_branch_wires;\n set_mret_condition <= set_mret_condition_wires; \n set_wfi_condition <= set_wfi_condition_wires;\n jump_instr <= jump_instr_wires;\n branch_instr <= branch_instr_wires;\n ebreak_instr <= ebreak_instr_wires;\n dbg_ack_i <= dbg_ack_i_wires;\n nextstate_IE <= nextstate_IE_wires;\n WFI_Instr\t\t <= WFI_Instr_wires;\n end process;\n\n fsm_IE_state : process(clk_i, rst_ni) -- also implements the delay slot counters and some aux signals\n begin\n \n if rst_ni = '0' then\n branch_instr_lat <= '0'; \n jump_instr_lat <= '0';\n state_IE <= reset;\n if RV32M = 1 then \n state_mulh <= init;\n state_mul <= mult;\n state_div <= init;\n end if;\n elsif rising_edge(clk_i) then\n branch_instr_lat <= branch_instr;\n jump_instr_lat <= jump_instr;\n state_IE <= nextstate_IE;\n if RV32M = 1 then\n state_mulh <= nextstate_mulh;\n state_mul <= nextstate_mul;\n state_div <= nextstate_div;\n div_count <= div_count_wire;\n res <= res_wire;\n RS1_Data_IE_int <= RS1_Data_IE_int_wire; -- used by the divider as well\n RS2_Data_IE_int <= RS2_Data_IE_int_wire; -- used by the divider as well\n --partial_mul_b <= partial_mul_b_wire;\n --partial_mul_c <= partial_mul_c_wire;\n --partial_mul_d <= partial_mul_d_wire;\n partial_mulh_a <= partial_mulh_a_wire;\n partial_mulh_b <= partial_mulh_b_wire;\n partial_mulh_c <= partial_mulh_c_wire;\n partial_mulh_d <= partial_mulh_d_wire;\n end if;\n end if;\n end process;\n\n --------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n --------------------------------------------------------------------------------\n\n IE_Mapper_comb : process(all)\n begin\n add_op_A <= (others => '0');\n add_op_B <= (others => '0');\n sl_op_A <= (others => '0');\n sl_op_B <= (others => '0');\n sr_op_A <= (others => '0');\n sr_op_B <= (others => '0');\n logic_op_A <= (others => '0');\n logic_op_B <= (others => '0');\n\n if decoded_instruction_IE(ADDI_bit_position) = '1' then\n add_op_A <= RS1_data_IE;\n add_op_B <= I_immediate(instr_word_IE);\n end if;\n if decoded_instruction_IE(ADD7_bit_position) = '1' then\n add_op_A <= RS1_data_IE;\n add_op_B <= RS2_data_IE;\n end if;\n if decoded_instruction_IE(SUB7_bit_position) = '1' then\n add_op_A <= RS1_data_IE;\n add_op_B <= std_logic_vector(unsigned(not(RS2_data_IE))+1);\n end if;\n if decoded_instruction_IE(AUIPC_bit_position) = '1' then\n add_op_A <= pc_IE;\n add_op_B <= U_immediate(instr_word_IE);\n end if;\n if decoded_instruction_IE(JAL_bit_position) = '1' or decoded_instruction_IE(JALR_bit_position) = '1' then\n add_op_A <= pc_IE;\n add_op_B <= (3 to 31 => '0') & \"100\";\n end if;\n\n if decoded_instruction_IE(SLLI_bit_position) = '1' then\n sl_op_A <= RS1_Data_IE;\n sl_op_B <= SHAMT(instr_word_IE);\n end if;\n if decoded_instruction_IE(SRLI7_bit_position) = '1' then\n sr_op_A <= RS1_Data_IE;\n sr_op_B <= SHAMT(instr_word_IE);\n end if;\n if decoded_instruction_IE(SRAI7_bit_position) = '1' then\n sr_op_A <= RS1_Data_IE;\n sr_op_B <= SHAMT(instr_word_IE);\n end if;\n if decoded_instruction_IE(SLLL_bit_position) = '1' then\n sl_op_A <= RS1_Data_IE;\n sl_op_B <= RS2_Data_IE(4 downto 0);\n end if;\n if decoded_instruction_IE(SRLL7_bit_position) = '1' then\n sr_op_A <= RS1_Data_IE;\n sr_op_B <= RS2_Data_IE(4 downto 0);\n end if;\n if decoded_instruction_IE(SRAA7_bit_position) = '1' then\n sr_op_A <= RS1_Data_IE;\n sr_op_B <= RS2_Data_IE(4 downto 0);\n end if;\n\n if decoded_instruction_IE(ANDI_bit_position) = '1' or\n decoded_instruction_IE(ORI_bit_position) = '1' or\n decoded_instruction_IE(XORI_bit_position) = '1' then\n logic_op_A <= RS1_Data_IE;\n logic_op_B <= I_immediate(instr_word_IE);\n end if;\n if decoded_instruction_IE(ANDD_bit_position) = '1' or\n decoded_instruction_IE(ORR_bit_position) = '1' or\n decoded_instruction_IE(XORR_bit_position) = '1' then\n logic_op_A <= RS1_Data_IE;\n logic_op_B <= RS2_Data_IE;\n end if;\n end process;\n\n\n ------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ --\n -- ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n ------------------------------------------------------------------------------------------------------\n\n comparator_enable_comb : process(all)\n begin\n pass_BEQ <= '0';\n pass_BNE <= '0';\n pass_BLT <= '0';\n pass_BGE <= '0';\n pass_BLTU <= '0';\n pass_BGEU <= '0';\n zero_rs1 <= '0';\n zero_rs2 <= '0';\n if comparator_en = '1' then\n if unsigned(RS1_Data_IE) = 0 then\n zero_rs1 <= '1';\n end if;\n if unsigned(RS2_Data_IE) = 0 then\n zero_rs2 <= '1';\n end if;\n if (signed(RS1_Data_IE) = signed(RS2_Data_IE)) then\n pass_BEQ <= '1';\n else\n pass_BNE <= '1';\n end if;\n if (signed(RS1_Data_IE) < signed(RS2_Data_IE)) then\n pass_BLT <= '1';\n else\n pass_BGE <= '1';\n end if;\n if (unsigned(RS1_Data_IE) < unsigned(RS2_Data_IE)) then\n", "right_context": "\nend EXECUTE;\n--------------------------------------------------------------------------------------------------\n-- END of IE architecture ------------------------------------------------------------------------\n--------------------------------------------------------------------------------------------------", "groundtruth": " pass_BLTU <= '1';\n else\n pass_BGEU <= '1';\n end if;\n end if;\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-IF_STAGE.vhd", "left_context": "--------------------------------------------------------------------------------------------------------------\n-- stage IF -- (Instruction Fetch) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 17-11-2019 --\n--------------------------------------------------------------------------------------------------------------\n-- The fetch stage requests an instruction from the program memory, and the instruction arrives in the --\n-- next cycle going directly to the decode stage. The fetch stage does not hold any buffers --\n--------------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n-- pipeline pinout --------------------\nentity IF_STAGE is\n generic(\n THREAD_POOL_SIZE : integer\n );\n port(\n pc_IF : in std_logic_vector(31 downto 0);\n harc_IF : in integer range THREAD_POOL_SIZE-1 downto 0;\n\tbusy_ID : in std_logic;\n\tinstr_rvalid_i : in std_logic; \n harc_ID : out integer range THREAD_POOL_SIZE-1 downto 0;\n pc_ID : out std_logic_vector(31 downto 0); -- pc_ID is PC entering ID stage\n instr_rvalid_ID : out std_logic; \n\tinstr_word_ID_lat : out std_logic_vector(31 downto 0);\n -- clock, reset active low\n clk_i : in std_logic;\n rst_ni : in std_logic;\n -- program memory interface\n instr_req_o : out std_logic;\n instr_gnt_i : in std_logic;\n instr_rdata_i : in std_logic_vector(31 downto 0)\n );\nend entity; ------------------------------------------\n\n\n-- Klessydra T03x (4 stages) pipeline implementation -----------------------\narchitecture FETCH of IF_STAGE is\n\n -- state signals\n signal instr_word_ID : std_logic_vector(31 downto 0);\n signal instr_rvalid_state : std_logic;\n\n--------------------------------------------------------------------------------------------------\n----------------------- ARCHITECTURE BEGIN -------------------------------------------------------\nbegin\n\n----------------------------------------------------------------------------------------------------\n-- stage IF -- (instruction fetch)\n----------------------------------------------------------------------------------------------------\n-- This pipeline stage is implicitly present as the program memory is synchronous\n-- with 1 cycle latency.\n-- The fsm_IF manages the interface with program memory. \n-- The PC_IF is updated by a dedicated unit which is transparent to the fsm_IF.\n----------------------------------------------------------------------------------------------------\n\n fsm_IF_nextstate : process(all) -- acts as the control unit of the synchronous program memory\n", "right_context": " begin\n if rising_edge(clk_i) then\n if instr_gnt_i = '1' then\n -- pc propagation\n pc_ID <= pc_IF;\n -- harc propagation\n harc_ID <= harc_IF;\n end if;\n end if;\n end process;\n\n -- instr_rvalid_ID controller, needed to keep instr_valid_ID set during \n -- stalls of the fetch stage. This is a synthesized mealy fsm\n process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n instr_rvalid_state <= '0';\n elsif rising_edge(clk_i) then\n if instr_rvalid_i = '1' then \n instr_word_ID <= instr_rdata_i;\n end if;\n instr_rvalid_state <= busy_ID and (instr_rvalid_i or instr_rvalid_state);\n end if;\n end process;\n instr_rvalid_ID <= (instr_rvalid_i or instr_rvalid_state);\n\n -- latch ir on program memory output, because memory output remains for 1 cycle only\n instr_word_ID_lat <= instr_rdata_i when instr_rvalid_i = '1' else instr_word_ID;\n --instr_word_ID_lat <= instr_rdata_i when instr_rvalid_i = '1' else (others => '0');\n\n--------------------------------------------------------------------- end of IF stage -------------\n---------------------------------------------------------------------------------------------------\n\nend FETCH;\n--------------------------------------------------------------------------------------------------\n-- END of IE architecture ------------------------------------------------------------------------\n--------------------------------------------------------------------------------------------------", "groundtruth": " begin\n if busy_ID = '0' then\n instr_req_o <= '1';\n else\n instr_req_o <= '0';\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Load_Store_Unit.vhd", "left_context": "--------------------------------------------------------------------------------------------------------------\n-- LSU -- (Load-Store Unit) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 8-12-2019 --\n--------------------------------------------------------------------------------------------------------------\n-- The LSU performs all the operations that access the external memories. Including the amoswap, and the --\n-- custom burst load and store instructions. The LSU can allow superscalar execution with other execution --\n-- units if a store operation is executing, Loaded instructions write either to the regfile or the SPMs --\n--------------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n-- LD-STR pinout --------------------\nentity Load_Store_Unit is\n generic(\n THREAD_POOL_SIZE : integer;\n accl_en : natural;\n replicate_accl_en : natural;\n SIMD : natural;\n SPM_NUM\t\t : natural; \n Addr_Width : natural;\n Data_Width : natural;\n SIMD_BITS : natural;\n ACCL_NUM : natural;\n SPM_ADDR_WID : natural\n );\n port (\n -- clock, and reset active low\n clk_i, rst_ni : in std_logic;\n -- Program Counter Signals\n irq_pending : in std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n -- ID_Stage Signals\n RS1_Data_IE : in std_logic_vector(31 downto 0);\n RS2_Data_IE : in std_logic_vector(31 downto 0);\n RD_Data_IE : in std_logic_vector(31 downto 0);\n instr_word_IE : in std_logic_vector(31 downto 0);\n pc_IE : in std_logic_vector(31 downto 0);\n decoded_instruction_LS : in std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0);\n data_be_ID : in std_logic_vector(3 downto 0);\n data_width_ID : in std_logic_vector(1 downto 0);\n harc_EXEC : in integer range THREAD_POOL_SIZE-1 downto 0;\n LS_instr_req : in std_logic;\n load_op : in std_logic;\n store_op : in std_logic;\n --sw_mip : in std_logic;\n core_busy_LS : out std_logic;\n busy_LS : out std_logic;\n -- Processing Pipeline Signals\n rs1_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rs2_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rd_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n halt_LSU : in std_logic;\n data_addr_internal : out std_logic_vector(31 downto 0);\n ls_except_data : out std_logic_vector(31 downto 0);\n ls_except_condition : out std_logic;\n ls_taken_branch : out std_logic;\n amo_load : in std_logic;\n amo_load_skip : in std_logic;\n amo_store : out std_logic;\n -- CSR Signals\n misaligned_err : out std_logic;\n -- Scratchpad Interface Signals\n ls_data_gnt_i : in std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_wr_gnt : in std_logic;\n ls_sc_data_read_wire : in std_logic_vector(Data_Width-1 downto 0);\n state_LS : out fsm_LS_states;\n harc_LS_wire : out integer range ACCL_NUM-1 downto 0;\n sc_word_count_wire : out integer;\n spm_bcast : out std_logic;\n kmemld_inflight : out std_logic_vector(SPM_NUM-1 downto 0);\n kmemstr_inflight : out std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_req : out std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_we : out std_logic_vector(SPM_NUM-1 downto 0);\n ls_sc_read_addr : out std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n ls_sc_write_addr : out std_logic_vector(Addr_Width-(SIMD_BITS+3)downto 0);\n ls_sc_data_write_wire : out std_logic_vector(Data_Width-1 downto 0);\n -- WB_Stage Signals\n LS_WB_EN : out std_logic;\n harc_LS_WB : out integer range THREAD_POOL_SIZE-1 downto 0;\n instr_word_LS_WB : out std_logic_vector(31 downto 0);\n LS_WB : out std_logic_vector(31 downto 0);\n -- Data memory interface\n data_req_o : out std_logic;\n data_gnt_i : in std_logic;\n data_rvalid_i : in std_logic;\n data_we_o : out std_logic;\n data_be_o : out std_logic_vector(3 downto 0);\n data_addr_o : out std_logic_vector(31 downto 0);\n data_wdata_o : out std_logic_vector(31 downto 0);\n data_rdata_i : in std_logic_vector(31 downto 0);\n data_err_i : in std_logic\n\t);\nend entity; ------------------------------------------\n\narchitecture LSU of Load_Store_Unit is\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0;\n subtype accl_range is integer range ACCL_NUM - 1 downto 0; \n\n signal nextstate_LS : fsm_LS_states;\n -- Memory fault signals\n signal data_addr_internal_lat : std_logic_vector(31 downto 0);\n signal load_err : std_logic;\n signal store_err : std_logic;\n signal amo_store_lat : std_logic;\n signal overflow_rs1_sc : std_logic_vector(Addr_Width downto 0);\n signal overflow_rd_sc : std_logic_vector(Addr_Width downto 0);\n signal busy_LS_lat : std_logic;\n signal sc_word_count : integer;\n signal harc_LS : accl_range;\n signal harc_LOAD : harc_range;\n signal ls_rs1_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n signal ls_rd_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n signal ls_sc_data_write : std_logic_vector(Data_Width-1 downto 0);\n signal data_be_internal : std_logic_vector(3 downto 0);\n signal RS1_Data_IE_wire_lat : std_logic_vector(31 downto 0); -- Wire to used to directly send the result of the address increment\n signal RS2_Data_IE_wire_lat : std_logic_vector(31 downto 0); -- Wire to used to directly send the result of the address increment\n signal RD_Data_IE_wire_lat : std_logic_vector(31 downto 0); -- Wire to used to directly send the result of the address increment\n signal RS1_Data_IE_lat : std_logic_vector(31 downto 0); -- Used to preserve the old data in case we start executing in parallel\n signal RS2_Data_IE_lat : std_logic_vector(31 downto 0); -- Used to preserve the old data in case we start executing in parallel\n signal RD_Data_IE_lat : std_logic_vector(31 downto 0); -- Used to preserve the old data in case we start executing in parallel\n\n signal add_op_A : std_logic_vector(31 downto 0);\n signal add_op_B : std_logic_vector(31 downto 0);\n signal add_out : std_logic_vector(31 downto 0);\n\nbegin\n\n -- Memory fault signals\n load_err <= data_gnt_i and data_err_i and not(data_we_o);\n store_err <= data_gnt_i and data_err_i and data_we_o;\n\n -- Memory address signal\n data_addr_o <= data_addr_internal(31 downto 2) & \"00\";\n data_be_o <= to_stdlogicvector(to_bitvector(data_be_internal) sll\n to_integer(unsigned(data_addr_internal(1 downto 0))));\n\n------------------------------------------------------------------------\n-- ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ --\n-- ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• --\n------------------------------------------------------------------------\n\n LSU_sync : process(clk_i, rst_ni)\n begin\n\t \n if rst_ni = '0' then\n\t amo_store <= '0';\n\t amo_store_lat <= '0';\n\t LS_WB_EN <= '0';\n\t busy_LS_lat <= '0';\n\t LS_WB <= (others => '0');\n harc_LS_WB <= THREAD_POOL_SIZE-1;\n misaligned_err <= '0';\n instr_word_LS_WB <= (others => '0');\n if accl_en = 1 then\n ls_rs1_to_sc <= (others => '0');\n ls_rd_to_sc <= (others => '0');\n end if;\n\telsif rising_edge(clk_i) then\n amo_store <= '0';\n misaligned_err <= '0';\n LS_WB <= (others => '0');\n busy_LS_lat <= busy_LS or core_busy_LS;\n if accl_en = 1 then\n RS1_Data_IE_lat <= RS1_Data_IE_wire_lat;\n RS2_Data_IE_lat <= RS2_Data_IE_wire_lat;\n RD_Data_IE_lat <= RD_Data_IE_wire_lat;\n end if;\n if ls_instr_req = '0' and busy_LS_lat = '0' then\n LS_WB_EN <= '0';\n elsif LS_instr_req = '1' or busy_LS_lat = '1' then\n if data_rvalid_i = '1' then\n ls_sc_data_write <= data_rdata_i;\n end if;\n LS_WB_EN <= '0';\n case state_LS is\t\n when normal =>\n\n --------------------------------------------------------------\n -- ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• --\n --------------------------------------------------------------\n\n if load_op = '1' or (amo_load = '1' and halt_LSU = '0')then -- Load Instructions\n if ((data_addr_internal(1 downto 0) = \"00\" and data_width_ID = \"10\") or \n (data_addr_internal(0) = '0' and data_width_ID = \"01\") or\n data_width_ID = \"00\") then\n if load_err = '1' then\n ls_except_data <= LOAD_ERROR_EXCEPT_CODE;\n end if;\n\t\t harc_LS_WB <= harc_EXEC;\n\t\t instr_word_LS_WB <= instr_word_IE;\n else\n ls_except_data <= LOAD_MISALIGNED_EXCEPT_CODE;\n misaligned_err <= '1';\n end if;\n end if;\n\n -----------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• --\n -----------------------------------------------------------------------\n\n if store_op = '1' or amo_store = '1' or (amo_load_skip = '1' and halt_LSU = '0') then\t\n if ((data_addr_internal(1 downto 0) = \"00\" and data_width_ID = \"10\") or \n (data_addr_internal(0) = '0' and data_width_ID = \"01\") or\n data_width_ID = \"00\") then\n\t\t\t\tRS2_Data_IE_lat <= RS2_Data_IE;\t\n if (store_err = '1') then\n ls_except_data <= STORE_ERROR_EXCEPT_CODE;\n end if;\n else\n ls_except_data <= STORE_MISALIGNED_EXCEPT_CODE;\n misaligned_err <= '1';\n end if;\n end if;\n\n if amo_store = '1' or amo_load_skip = '1' then\n amo_store_lat <= amo_store;\n\t\t\t amo_store <= '0';\n end if;\n\n\n ------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• --\n ------------------------------------------------------------------------------------------------------\n\n if accl_en = 1 then\n if decoded_instruction_LS(KMEMLD_bit_position) = '1' or\n decoded_instruction_LS(KBCASTLD_bit_position) = '1' then\n -- Illegal byte transfer handler, and illegal writeback address handler\n if RS2_Data_IE(Addr_Width downto 0) = (0 to Addr_Width => '0') then\n null;\n elsif rd_to_sc = \"100\" then -- AAA change \"100\" to make it parametrizable -- Not a scratchpad destination address\n ls_except_data <= ILLEGAL_ADDRESS_EXCEPT_CODE;\n elsif RS1_Data_IE(1 downto 0) /= \"00\" then\n ls_except_data <= LOAD_MISALIGNED_EXCEPT_CODE;\n", "right_context": " elsif overflow_rd_sc(Addr_Width) = '1' then\n ls_except_data <= SCRATCHPAD_OVERFLOW_EXCEPT_CODE;\n else\n RS1_Data_IE_lat <= RS1_Data_IE;\n RS2_Data_IE_lat <= RS2_Data_IE;\n RD_Data_IE_lat <= RD_Data_IE;\n ls_rd_to_sc <= rd_to_sc;\n end if;\n end if;\n\n if decoded_instruction_LS(KMEMSTR_bit_position) = '1' then\n -- Illegal byte transfer handler, and illegal writeback address handler\n if RS2_Data_IE(Addr_Width downto 0) = (0 to Addr_Width => '0') then\n null;\n\t\t elsif rs1_to_sc = \"100\" then -- Not a scratchpad source address\n ls_except_data <= ILLEGAL_ADDRESS_EXCEPT_CODE;\n\t\t elsif RD_Data_IE(1 downto 0) /= \"00\" then\n ls_except_data <= STORE_MISALIGNED_EXCEPT_CODE;\n misaligned_err <= '1'; \n elsif store_err = '1' then\n ls_except_data <= STORE_ERROR_EXCEPT_CODE;\n elsif overflow_rs1_sc(Addr_Width) = '1' then\n ls_except_data <= SCRATCHPAD_OVERFLOW_EXCEPT_CODE;\t\t\t\t\n else\n RS1_Data_IE_lat <= RS1_Data_IE;\n RS2_Data_IE_lat <= RS2_Data_IE;\n RD_Data_IE_lat <= RD_Data_IE;\n ls_rs1_to_sc <= rs1_to_sc;\n end if;\n end if;\n end if;\n\t\t\t \n when data_valid_waiting =>\n\n ----------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•— --\n -- ā•šā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā•šā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•šā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• --\n ----------------------------------------------------------------------------------------------------\n\n\t\t if amo_store_lat = '1' or amo_load_skip = '1' then\n\t\t\t if data_rvalid_i = '1' then\n\t\t amo_store_lat <= '0';\n end if;\n\t end if;\t\n\n if decoded_instruction_LS(LW_bit_position) = '1' or (decoded_instruction_LS(AMOSWAP_bit_position) = '1' and amo_store_lat = '0' and amo_load_skip = '0') then\n\t\t if data_rvalid_i = '1' then\n\t\t LS_WB <= data_rdata_i;\n\t LS_WB_EN <= '1';\n\t\t\t\tif decoded_instruction_LS(AMOSWAP_bit_position) = '1' then\n\t\t\t amo_store <= '1';\n\t\t\t\tend if;\n\t\t end if;\n\t\t end if;\n\n\t\t if decoded_instruction_LS(LH_bit_position) = '1' or decoded_instruction_LS(LHU_bit_position) = '1' then \n if data_rvalid_i = '1' then\n case data_addr_internal(1) is\n when '0' =>\n LS_WB_EN <= '1';\n\t\t\t\t if decoded_instruction_LS(LH_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(signed(data_rdata_i(15 downto 0)), 32));\n\t\t\t\t elsif decoded_instruction_LS(LHU_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(unsigned(data_rdata_i(15 downto 0)), 32));\n\t\t\t\t end if;\n when '1' =>\n LS_WB_EN <= '1';\n\t\t\t\t if decoded_instruction_LS(LH_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(signed(data_rdata_i(31 downto 16)), 32));\n\t\t\t\t elsif decoded_instruction_LS(LHU_bit_position) = '1' then\n\t\t\t\t LS_WB <= std_logic_vector(resize(unsigned(data_rdata_i(31 downto 16)), 32));\n\t\t\t\t end if;\n when others =>\n null;\n end case;\n\t\t end if;\n end if;\n\n\t\t if decoded_instruction_LS(LB_bit_position) = '1' or decoded_instruction_LS(LBU_bit_position) = '1' then \n if data_rvalid_i = '1' then\t\t\n\t\t\t LS_WB_EN <= '1';\n\t case data_addr_internal(1 downto 0) is\n when \"00\" =>\n\t\t\t\t if decoded_instruction_LS(LB_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(signed(data_rdata_i(7 downto 0)), 32));\n\t\t\t\t elsif decoded_instruction_LS(LBU_bit_position) = '1' then\n\t\t\t\t\t LS_WB <= std_logic_vector(resize(unsigned(data_rdata_i(7 downto 0)), 32));\n\t\t\t\t end if;\n when \"01\" =>\n\t\t\t\t if decoded_instruction_LS(LB_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(signed(data_rdata_i(15 downto 8)), 32));\n\t\t\t\t elsif decoded_instruction_LS(LBU_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(unsigned(data_rdata_i(15 downto 8)), 32));\t\t\t\t\t \n\t\t\t\t end if;\n when \"10\" =>\n\t\t\t\t if decoded_instruction_LS(LB_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(signed(data_rdata_i(23 downto 16)), 32));\n\t\t\t\t elsif decoded_instruction_LS(LBU_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(unsigned(data_rdata_i(23 downto 16)), 32));\n\t\t\t\t end if;\n when \"11\" =>\n\t\t\t\t if decoded_instruction_LS(LB_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(signed(data_rdata_i(31 downto 24)), 32));\n\t\t\t\t elsif decoded_instruction_LS(LBU_bit_position) = '1' then\n LS_WB <= std_logic_vector(resize(unsigned(data_rdata_i(31 downto 24)), 32));\n\t\t\t\t end if;\n when others =>\n null; \n end case;\n\t\t\t end if;\n\t\t end if;\n\t end case;\n end if;\n end if;\n end process;\n\n spm_bcast <= '1' when decoded_instruction_LS(KBCASTLD_bit_position) = '1' else '0';\n\n\n-------------------------------------------------------------------------\n-- ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n-- ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n-- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• --\n-------------------------------------------------------------------------\n\n LSU_comb : process(all)\n\n variable data_addr_internal_wires : std_logic_vector (31 downto 0);\n variable data_wdata_o_wires : std_logic_vector (31 downto 0);\n variable data_be_internal_wires : std_logic_vector (3 downto 0);\n variable data_we_o_wires : std_logic;\n variable data_req_o_wires : std_logic;\n variable ls_except_condition_wires : std_logic;\n variable ls_taken_branch_wires : std_logic;\n variable core_busy_LS_wires : std_logic;\n variable busy_LS_wires : std_logic;\n\n begin\n data_addr_internal_wires := std_logic_vector(signed(RS1_Data_IE)); -- The reset value was non-zero in order to keep the switching activity minimal\n nextstate_LS <= normal;\n data_be_internal_wires := (others => '0');\n data_wdata_o_wires := (others => '0');\n data_we_o_wires := '0';\n data_req_o_wires := '0';\n\tls_except_condition_wires := '0';\n\tls_taken_branch_wires := '0';\n core_busy_LS_wires := '0';\n busy_LS_wires := '0';\n\n if accl_en = 1 then\n overflow_rs1_sc <= (others => '0');\n overflow_rd_sc <= (others => '0');\n ls_sc_data_write_wire <= ls_sc_data_write;\n sc_word_count_wire <= sc_word_count;\n kmemld_inflight <= (others => '0');\n kmemstr_inflight <= (others => '0');\n ls_sc_write_addr <= (others => '0');\n\t ls_sc_read_addr <= (others => '0');\n --halt_lsu <= '0';\n RS1_Data_IE_wire_lat <= RS1_Data_IE_lat;\n RS2_Data_IE_wire_lat <= RS2_Data_IE_lat;\n RD_Data_IE_wire_lat <= RD_Data_IE_lat;\n harc_LS_wire <= harc_LS;\n ls_sci_req <= (others => '0');\n ls_sci_we <= (others => '0');\n end if;\n\n if LS_instr_req = '1' or busy_LS_lat = '1' then\n case state_LS is\n when normal =>\n\n --------------------------------------------------------------\n -- ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• --\n --------------------------------------------------------------\n\n if load_op = '1' or (amo_load = '1' and halt_LSU = '0') then\n if amo_load = '0' then\n data_addr_internal_wires := add_out;\n else\n data_addr_internal_wires := RS1_Data_IE;\n end if;\n if ((data_addr_internal_wires(1 downto 0) = \"00\" and data_width_ID = \"10\") or \n (data_addr_internal_wires(0) = '0' and data_width_ID = \"01\") or\n data_width_ID = \"00\") then\n data_be_internal_wires := data_be_ID;\n data_req_o_wires := '1';\n if load_err = '1' then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n else\n core_busy_LS_wires := '1';\n nextstate_LS <= data_valid_waiting;\n end if;\n else\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n end if;\n end if;\n\n -----------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• --\n -----------------------------------------------------------------------\n\n if store_op = '1' or amo_store = '1' or (amo_load_skip = '1' and halt_LSU = '0') then\n if amo_store = '0' and amo_load_skip = '0' then\n data_addr_internal_wires := add_out;\n elsif amo_store = '1' or amo_load_skip = '1' then\n data_addr_internal_wires := RS1_Data_IE;\n end if;\n data_we_o_wires := '1';\n if ((data_addr_internal_wires(1 downto 0) = \"00\" and data_width_ID = \"10\") or \n (data_addr_internal_wires(0) = '0' and data_width_ID = \"01\") or\n data_width_ID = \"00\") then\n data_req_o_wires := '1';\n data_be_internal_wires := data_be_ID;\n data_wdata_o_wires := RS2_Data_IE;\t\t\n if store_err = '1' then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n else\n nextstate_LS <= data_valid_waiting;\n busy_LS_wires := '1';\n if amo_store = '1' or amo_load_skip = '1' then\n core_busy_LS_wires := '1';\n end if;\n end if;\n else\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n end if;\n if data_width_ID = \"01\" then -- store half word\n case data_addr_internal_wires(1) is\n when '0' =>\n data_wdata_o_wires := RS2_Data_IE(31 downto 0);\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when '1' =>\n data_wdata_o_wires := RS2_Data_IE(15 downto 0) & std_logic_vector(to_unsigned(0, 16));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when others =>\n null;\n end case;\n end if;\n if data_width_ID = \"00\" then -- store byte\n case data_addr_internal_wires(1 downto 0) is\n when \"00\" =>\n data_wdata_o_wires := RS2_Data_IE(31 downto 0);\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when \"01\" =>\n data_wdata_o_wires := RS2_Data_IE(23 downto 0) & std_logic_vector(to_unsigned(0, 8));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when \"10\" =>\n data_wdata_o_wires := RS2_Data_IE(15 downto 0) & std_logic_vector(to_unsigned(0, 16));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when \"11\" =>\n data_wdata_o_wires := RS2_Data_IE(7 downto 0) & std_logic_vector(to_unsigned(0, 24));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when others =>\n null;\n end case;\n end if;\n end if;\n\n ------------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• --\n ------------------------------------------------------------------------------------------------------\n\n if accl_en = 1 then\n if decoded_instruction_LS(KMEMLD_bit_position) = '1' or\n decoded_instruction_LS(KBCASTLD_bit_position) = '1' then\n -- RS2_Data_IE(Addr_Width downto 0) instead of RS2_Data_IE(Addr_Width -1 downto 0) in order to allow reading sizes = MAX_SC_SIZE and not MAX_SC_SIZE - 1 \n overflow_rd_sc <= add_out(Addr_Width downto 0); -- If storing data to SC overflows it's address space\n if RS2_Data_IE(Addr_Width downto 0) = (0 to Addr_Width => '0') then\n null;\n elsif rd_to_sc = \"100\" then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n elsif(RS1_Data_IE(1 downto 0) /= \"00\") then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n elsif load_err = '1' then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n elsif overflow_rd_sc(Addr_Width) = '1' then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n else\n nextstate_LS <= data_valid_waiting;\n busy_LS_wires := '1';\n sc_word_count_wire <= to_integer(unsigned(RD_Data_IE(SIMD_BITS+1 downto 1))/2);\n kmemld_inflight(to_integer(unsigned(rd_to_sc))) <= '1';\n if replicate_accl_en=1 then\n harc_LS_wire <= harc_EXEC;\n elsif replicate_accl_en=0 then\n harc_LS_wire <= 0;\n end if;\n end if;\n end if;\n\n if decoded_instruction_LS(KMEMSTR_bit_position) = '1' then\n -- RS2_Data_IE(Addr_Width downto 0) instead of RS2_Data_IE(Addr_Width -1 downto 0) in order to allow reading sizes = MAX_SC_SIZE and not MAX_SC_SIZE - 1 \n overflow_rs1_sc <= add_out(Addr_Width downto 0); -- If loading data from SC overflows it's address space\n if RS2_Data_IE(Addr_Width downto 0) = (0 to Addr_Width => '0') then\n null;\n elsif rs1_to_sc = \"100\" then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n elsif(RD_Data_IE(1 downto 0) /= \"00\") then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n elsif store_err = '1' then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n elsif overflow_rs1_sc(Addr_Width) = '1' then\n ls_except_condition_wires := '1';\n ls_taken_branch_wires := '1';\n else\n nextstate_LS <= data_valid_waiting;\n busy_LS_wires := '1';\n ls_sci_req(to_integer(unsigned(rs1_to_sc))) <= '1';\n ls_sc_read_addr <= RS1_Data_IE(Addr_Width - 1 downto SIMD_BITS+2);\n sc_word_count_wire <= to_integer(unsigned(RS1_Data_IE(SIMD_BITS+1 downto 1))/2);\n kmemstr_inflight(to_integer(unsigned(rs1_to_sc))) <= '1';\n if replicate_accl_en=1 then\n harc_LS_wire <= harc_EXEC;\n elsif replicate_accl_en=0 then\n harc_LS_wire <= 0;\n end if;\n end if;\n end if;\n end if;\n\n when data_valid_waiting => \n\n\n ----------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•— --\n -- ā•šā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā•šā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā•šā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•šā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• --\n ----------------------------------------------------------------------------------------------------\n\n data_addr_internal_wires := data_addr_internal_lat;\n\n -- if ls_sci_wr_gnt = '0' and ls_sci_we /= (0 to SPM_NUM-1 => '0') then\n -- halt_lsu <= '1';\n -- end if;\n\n if decoded_instruction_LS(KMEMLD_bit_position) = '1' or\n decoded_instruction_LS(KBCASTLD_bit_position) = '1' then\n if accl_en = 1 then\n if data_rvalid_i = '1' then\n RS1_Data_IE_wire_lat <= std_logic_vector(unsigned(RS1_Data_IE_lat) + \"100\");\n RD_Data_IE_wire_lat <= std_logic_vector(unsigned(RD_Data_IE_lat) + \"100\");\n if unsigned(RS2_Data_IE_lat(Addr_Width downto 0)) >= 4 then\n RS2_Data_IE_wire_lat <= std_logic_vector(unsigned(RS2_Data_IE_lat) - \"100\");\n else\n RS2_Data_IE_wire_lat <= (others => '0');\n end if;\n end if;\n if RS2_Data_IE_lat(Addr_Width downto 0) /= (0 to Addr_Width => '0') then\n busy_LS_wires := '1';\n data_be_internal_wires := \"1111\";\n data_req_o_wires := '1';\n data_addr_internal_wires := RS1_Data_IE_wire_lat;\n nextstate_LS <= data_valid_waiting;\n ls_sci_we(to_integer(unsigned(ls_rd_to_sc))) <= '1';\n ls_sc_write_addr <= RD_Data_IE_lat(Addr_Width - 1 downto SIMD_BITS+2);\n kmemld_inflight(to_integer(unsigned(ls_rd_to_sc))) <= '1';\n if data_rvalid_i = '1' then\n if RS2_Data_IE_lat(Addr_Width downto 0) >= (4 to Addr_Width => '0') & x\"4\" then\n ls_sc_data_write_wire <= data_rdata_i;\n elsif RS2_Data_IE_lat(Addr_Width downto 0) < (4 to Addr_Width => '0') & x\"4\" then\n ls_sc_data_write_wire(8*to_integer(unsigned(RS2_Data_IE_lat)) - 1 downto 0) <= data_rdata_i(8*to_integer(unsigned(RS2_Data_IE_lat)) - 1 downto 0);\n end if;\n end if;\n if data_rvalid_i = '1' then\n ls_sci_req(to_integer(unsigned(ls_rd_to_sc))) <= '1';\n if sc_word_count = SIMD-1 then\n sc_word_count_wire <= 0;\n else\n sc_word_count_wire <= sc_word_count + 1;\n end if;\n end if;\n end if;\n end if;\n\n elsif decoded_instruction_LS(KMEMSTR_bit_position) = '1' then\n if accl_en = 1 then\n if data_rvalid_i = '1' then\n RS1_Data_IE_wire_lat <= std_logic_vector(unsigned(RS1_Data_IE_lat) + \"100\");\n RD_Data_IE_wire_lat <= std_logic_vector(unsigned(RD_Data_IE_lat) + \"100\");\n if unsigned(RS2_Data_IE_lat(Addr_Width downto 0)) >= 4 then\n RS2_Data_IE_wire_lat <= std_logic_vector(unsigned(RS2_Data_IE_lat) - \"100\");\n else\n RS2_Data_IE_wire_lat <= (others => '0');\n end if;\n end if;\n if RS2_Data_IE_lat(Addr_Width downto 0) /= (0 to Addr_Width => '0') then\n busy_LS_wires := '1';\n nextstate_LS <= data_valid_waiting;\n ls_sc_read_addr <= RS1_Data_IE_wire_lat(Addr_Width - 1 downto SIMD_BITS+2);\n kmemstr_inflight(to_integer(unsigned(ls_rs1_to_sc))) <= '1';\n if to_integer(unsigned(ls_data_gnt_i)) /= 0 then\n data_be_internal_wires := \"1111\";\n data_req_o_wires := '1';\n data_we_o_wires := '1';\n data_addr_internal_wires := RD_Data_IE_lat;\n data_wdata_o_wires := ls_sc_data_read_wire;\n end if;\n -- Increments the address of the SC memory every four words for KMEMSTR\n if data_rvalid_i = '1' then\n ls_sci_req(to_integer(unsigned(ls_rs1_to_sc))) <= '1';\n if sc_word_count = SIMD-1 then\n sc_word_count_wire <= 0;\n else\n sc_word_count_wire <= sc_word_count + 1;\n end if;\n end if;\n end if;\n end if;\n\t \n elsif data_rvalid_i = '1' then\n if store_op = '1' or amo_store_lat = '1' or amo_load_skip = '1' then -- SW or AMOSWAP data writing\n if decoded_instruction_LS(SW_bit_position) = '1' then -- SW data writing\n data_wdata_o_wires := RS2_Data_IE_lat(31 downto 0);\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n end if;\n if decoded_instruction_LS(SH_bit_position) = '1' then -- SH data writing\n case data_addr_internal_wires(1) is\n when '0' =>\n data_wdata_o_wires := RS2_Data_IE_lat(31 downto 0);\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when '1' =>\n data_wdata_o_wires := RS2_Data_IE_lat(15 downto 0) & std_logic_vector(to_unsigned(0, 16));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when others =>\n null;\n end case;\n end if;\n if decoded_instruction_LS(SB_bit_position) = '1' then -- SB data writng\n case data_addr_internal_wires(1 downto 0) is\n when \"00\" =>\n data_wdata_o_wires := RS2_Data_IE_lat(31 downto 0);\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when \"01\" =>\n data_wdata_o_wires := RS2_Data_IE_lat(23 downto 0) & std_logic_vector(to_unsigned(0, 8));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when \"10\" =>\n data_wdata_o_wires := RS2_Data_IE_lat(15 downto 0) & std_logic_vector(to_unsigned(0, 16));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when \"11\" =>\n data_wdata_o_wires := RS2_Data_IE_lat(7 downto 0) & std_logic_vector(to_unsigned(0, 24));\n data_we_o_wires := '1'; -- is a writing\n data_be_internal_wires := data_be_ID;\n when others =>\n null;\n end case;\n end if;\n end if;\n\t\t\n if load_op = '1' or (decoded_instruction_LS(AMOSWAP_bit_position) = '1' and amo_store_lat = '0' and amo_load_skip = '0') then\n data_be_internal_wires := data_be_ID;\n if decoded_instruction_LS(AMOSWAP_bit_position) = '1' then\n core_busy_LS_wires := '1';\t\t\t\t \n\t\t end if;\n\t end if;\n else\n nextstate_LS <= data_valid_waiting;\n busy_LS_wires := '1';\n -- do not change to \"if store_op = '0'\" since that will disable store superscalar execution, because store_op resets to 0 on the next cycle\n if decoded_instruction_LS(SW_bit_position) = '0' and decoded_instruction_LS(SH_bit_position) = '0' and decoded_instruction_LS(SB_bit_position) = '0' then\n core_busy_LS_wires := '1';\n end if;\n\t\t end if;\n\n end case;\n end if;\n\t\n data_addr_internal <= data_addr_internal_wires;\n data_wdata_o <= data_wdata_o_wires;\n data_be_internal <= data_be_internal_wires;\n data_we_o <= data_we_o_wires;\n data_req_o <= data_req_o_wires;\n ls_except_condition <= ls_except_condition_wires;\n ls_taken_branch \t <= ls_taken_branch_wires;\n core_busy_LS <= core_busy_LS_wires;\n busy_LS <= busy_LS_wires;\n \n end process;\n\n fsm_LS_state : process(clk_i, rst_ni) -- also implements some aux signals\n begin\n if rst_ni = '0' then\n state_LS <= normal; \n if accl_en = 1 then\n sc_word_count <= 0;\n\t harc_LS <= ACCL_NUM-1;\n end if;\n harc_LOAD <= THREAD_POOL_SIZE-1;\n elsif rising_edge(clk_i) then\n state_LS <= nextstate_LS;\n\t data_addr_internal_lat <= data_addr_internal;\n if accl_en = 1 then\n\t --halt_lsu_lat <= halt_lsu;\n sc_word_count <= sc_word_count_wire;\n harc_LS <= harc_LS_wire;\n end if;\n end if;\n end process;\n\n -----------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā•ā•ā• --\n -----------------------------------------------------------------------------------------------\n\n LSU_Mapper_comb : process(all)\n begin\n add_op_A <= (others => '0');\n add_op_B <= (others => '0');\n\n -- Perform the addition ---------------------------------------------------\n add_out <= std_logic_vector(signed(add_op_A) + signed(add_op_B));\n ---------------------------------------------------------------------------\n\n -- MAP input address generator -----------------------------------------------------------------------------------\n if load_op = '1' then -- address building operands\n add_op_A <= RS1_data_IE;\n add_op_B <= I_immediate(instr_word_IE);\n end if;\n if store_op = '1' then -- address building operands\n add_op_A <= RS1_data_IE;\n add_op_B <= S_immediate(instr_word_IE);\n end if;\n if accl_en = 1 then\n if decoded_instruction_LS(KMEMLD_bit_position) = '1' or -- calculates overflow spm write\n decoded_instruction_LS(KBCASTLD_bit_position) = '1' then\n add_op_A <= (Addr_Width to 31 => '0') & RD_data_IE(Addr_Width -1 downto 0);\n add_op_B <= (Addr_Width to 31 => '0') & std_logic_vector(unsigned(RS2_data_IE(Addr_Width -1 downto 0))-1);\n end if;\n if decoded_instruction_LS(KMEMSTR_bit_position) = '1' then -- calculates overflow spm read\n add_op_A <= (Addr_Width to 31 => '0') & RS1_data_IE(Addr_Width -1 downto 0);\n add_op_B <= (Addr_Width to 31 => '0') & std_logic_vector(unsigned(RS2_data_IE(Addr_Width -1 downto 0))-1);\n end if;\n end if;\n ---------------------------------------------------------------------------------------------------------------\n end process;\n\n--------------------------------------------------------------------- end of LSU -----------------\n--------------------------------------------------------------------------------------------------\n\nend LSU;\n--------------------------------------------------------------------------------------------------\n-- END of Load-Store architecture ----------------------------------------------------------------\n--------------------------------------------------------------------------------------------------\n", "groundtruth": " misaligned_err <= '1';\n elsif load_err = '1' then -- AAA move to data_valid_waiting stage\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Processing_Pipeline.vhd", "left_context": "--------------------------------------------------------------------------------------------------------------\n-- Processing Pipeline -- --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 07-04-2020 --\n--------------------------------------------------------------------------------------------------------------\n-- The processing pipeline encapsulates all the componenets containing the datapath of the instruction --\n-- Also in this entity there is a non-synthesizable instruction tracer that displays the trace of all the --\n-- the instructions entering the pipe. --\n--------------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.math_real.all;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n-- pipeline pinout --------------------\nentity Pipeline is\n generic(\n THREAD_POOL_SIZE : integer;\n LUTRAM_RF : natural;\n RV32E : natural;\n RV32M : natural;\n superscalar_exec_en : natural;\n accl_en : natural;\n replicate_accl_en : natural;\n multithreaded_accl_en : natural;\n SPM_NUM\t : natural; \n Addr_Width : natural;\n SPM_STRT_ADDR : std_logic_vector(31 downto 0);\n SIMD : natural;\n MCYCLE_EN : natural;\n MINSTRET_EN : natural;\n MHPMCOUNTER_EN : natural;\n count_all : natural;\n debug_en : natural;\n tracer_en : natural;\n --------------------------------\n ACCL_NUM : natural;\n FU_NUM : natural;\n RF_SIZE : natural;\n RF_CEIL : natural;\n TPS_CEIL : natural;\n TPS_BUF_CEIL : natural;\n SPM_ADDR_WID : natural;\n SIMD_BITS : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n port (\n pc_IF : in std_logic_vector(31 downto 0);\n harc_IF : in integer range THREAD_POOL_SIZE-1 downto 0;\n irq_pending : in std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n csr_instr_done : in std_logic;\n csr_access_denied_o : in std_logic;\n csr_rdata_o : in std_logic_vector (31 downto 0);\n dbg_req_o : in std_logic;\n MVSIZE : in array_2d(THREAD_POOL_SIZE-1 downto 0)(Addr_Width downto 0);\n MVTYPE : in array_2d(THREAD_POOL_SIZE-1 downto 0)(3 downto 0);\n MPSCLFAC : in array_2d(THREAD_POOL_SIZE-1 downto 0)(4 downto 0);\n MSTATUS : in array_2d(THREAD_POOL_SIZE-1 downto 0)(1 downto 0);\n PCER : in array_2d(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n served_irq \t : out std_logic_vector(THREAD_POOL_SIZE-1 downto 0);\n WFI_Instr\t\t : out std_logic;\n reset_state : out std_logic;\n misaligned_err : out std_logic;\n pc_ID : out std_logic_vector(31 downto 0);\n pc_IE : out std_logic_vector(31 downto 0);\n ie_except_data : out std_logic_vector(31 downto 0);\n ls_except_data : out std_logic_vector(31 downto 0);\n dsp_except_data : out array_2d(ACCL_NUM-1 downto 0)(31 downto 0);\n taken_branch : out std_logic;\n ie_taken_branch : out std_logic;\n ls_taken_branch : out std_logic;\n dsp_taken_branch : out std_logic_vector(ACCL_NUM-1 downto 0);\n set_branch_condition : out std_logic;\n ie_except_condition : out std_logic;\n ls_except_condition : out std_logic;\n dsp_except_condition : out std_logic_vector(ACCL_NUM-1 downto 0);\n set_mret_condition : out std_logic;\n set_wfi_condition : out std_logic;\n csr_instr_req : out std_logic;\n instr_rvalid_IE : out std_logic; -- validity bit at IE input\n csr_addr_i : out std_logic_vector (11 downto 0);\n csr_wdata_i : out std_logic_vector (31 downto 0);\n csr_op_i : out std_logic_vector (2 downto 0);\n jump_instr : out std_logic;\n jump_instr_lat : out std_logic;\n branch_instr : out std_logic;\n branch_instr_lat : out std_logic;\n harc_ID : out integer range THREAD_POOL_SIZE-1 downto 0;\n harc_EXEC : out integer range THREAD_POOL_SIZE-1 downto 0;\n harc_to_csr : out integer range THREAD_POOL_SIZE-1 downto 0;\n instr_word_IE : out std_logic_vector(31 downto 0);\n PC_offset : out array_2D(THREAD_POOL_SIZE-1 downto 0)(31 downto 0);\n dbg_ack_i : out std_logic;\n ebreak_instr : out std_logic;\n data_addr_internal : out std_logic_vector(31 downto 0);\n absolute_jump : out std_logic;\n regfile : out array_3d(THREAD_POOL_SIZE-1 downto 0)(RF_SIZE-1 downto 0)(31 downto 0);\n -- clock, reset active low, test enable\n clk_i : in std_logic;\n rst_ni : in std_logic;\n -- program memory interface\n instr_req_o : out std_logic;\n instr_gnt_i : in std_logic;\n instr_rvalid_i : in std_logic;\n instr_rdata_i : in std_logic_vector(31 downto 0);\n -- data memory interface\n data_req_o : out std_logic;\n data_gnt_i : in std_logic;\n data_rvalid_i : in std_logic;\n data_we_o : out std_logic;\n data_be_o : out std_logic_vector(3 downto 0);\n data_addr_o : out std_logic_vector(31 downto 0);\n data_wdata_o : out std_logic_vector(31 downto 0);\n data_rdata_i : in std_logic_vector(31 downto 0);\n data_err_i : in std_logic;\n -- interrupt request interface\n irq_i : in std_logic;\n -- miscellanous control signals\n fetch_enable_i : in std_logic;\n core_busy_o : out std_logic\n );\n end entity; ------------------------------------------\n\n\narchitecture Pipe of Pipeline is\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0;\n subtype accl_range is integer range ACCL_NUM - 1 downto 0; \n subtype fu_range is integer range FU_NUM - 1 downto 0;\n\n signal state_IE : fsm_IE_states;\n signal state_LS : fsm_LS_states;\n signal state_DSP : array_2d(accl_range)(1 downto 0);\n signal instr_rvalid_state : std_logic;\n signal busy_ID : std_logic;\n signal core_busy_IE : std_logic;\n \n signal sleep_state : std_logic;\n signal ls_sci_wr_gnt : std_logic;\n signal dsp_sci_wr_gnt : std_logic_vector(accl_range);\n signal ls_data_gnt_i : std_logic_vector(SPM_NUM-1 downto 0);\n signal dsp_data_gnt_i : std_logic_vector(accl_range);\n signal ls_instr_done : std_logic;\n signal csr_wdata_en : std_logic;\n signal ie_to_csr : std_logic_vector(31 downto 0);\n signal ie_csr_wdata_i : std_logic_vector(31 downto 0);\n signal ie_instr_req : std_logic;\n signal ls_instr_req : std_logic;\n signal core_busy_LS : std_logic;\n signal busy_LS : std_logic;\n signal busy_DSP : std_logic_vector(accl_range);\n signal LS_WB_EN : std_logic;\n signal LS_WB : std_logic_vector(31 downto 0);\n signal data_addr_internal_IE : std_logic_vector(31 downto 0);\n signal data_be_ID : std_logic_vector(3 downto 0);\n signal data_width_ID : std_logic_vector(1 downto 0);\n signal IE_WB_EN : std_logic;\n signal IE_WB : std_logic_vector(31 downto 0);\n signal MUL_WB_EN : std_logic;\n signal MUL_WB : std_logic_vector(31 downto 0);\n\n signal comparator_en : std_logic;\n\n signal halt_IE : std_logic;\n signal halt_LSU : std_logic;\n\n signal kmemld_inflight : std_logic_vector(SPM_NUM-1 downto 0);\n signal kmemstr_inflight : std_logic_vector(SPM_NUM-1 downto 0);\n signal sc_word_count_wire : integer;\n\n signal spm_bcast : std_logic;\n\n -- program counters --\n signal pc_WB : std_logic_vector(31 downto 0); -- pc_WB is pc entering stage WB\n\n -- instruction register and instr. propagation registers --\n signal instr_word_ID_lat : std_logic_vector(31 downto 0); -- latch needed for long-latency program memory\n signal instr_rvalid_ID : std_logic; -- validity bit at ID input\n signal instr_word_LS_WB : std_logic_vector(31 downto 0);\n signal instr_word_IE_WB : std_logic_vector(31 downto 0);\n signal decoded_instruction_DSP : std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0);\n signal decoded_instruction_IE : std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0);\n signal decoded_instruction_LS : std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0);\n\n signal amo_load_skip : std_logic;\n signal amo_load : std_logic;\n signal amo_store : std_logic;\n signal load_op : std_logic;\n signal store_op : std_logic;\n --signal sw_mip : std_logic;\n signal signed_op : std_logic;\n\n -- hardware context id at fetch, and propagated hardware context ids\n signal harc_LS_wire : accl_range;\n signal harc_LS_WB : harc_range;\n signal harc_IE_WB : harc_range;\n\n -- DSP Unit Signals\n signal ls_sc_data_write_wire : std_logic_vector(Data_Width-1 downto 0);\n signal ls_sc_data_read_wire : std_logic_vector(Data_Width-1 downto 0);\n signal dsp_sc_data_read : array_3d(accl_range)(1 downto 0)(SIMD_Width-1 downto 0);\n signal dsp_sc_read_addr : array_3d(accl_range)(1 downto 0)(Addr_Width-1 downto 0);\n signal dsp_to_sc : array_3d(accl_range)(SPM_NUM-1 downto 0)(1 downto 0);\n signal dsp_sc_write_addr : array_2d(accl_range)(Addr_Width-1 downto 0);\n signal dsp_sc_data_write_wire : array_2d(accl_range)(SIMD_Width - 1 downto 0);\n signal rs1_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n signal rs2_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n signal rd_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n signal dsp_instr_req : std_logic_vector(accl_range);\n signal ls_sc_read_addr : std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n signal ls_sc_write_addr : std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n signal ls_sci_req : std_logic_vector(SPM_NUM-1 downto 0);\n signal ls_sci_we : std_logic_vector(SPM_NUM-1 downto 0);\n signal dsp_sci_req : array_2d(accl_range)(SPM_NUM-1 downto 0);\n signal dsp_sci_we : array_2d(accl_range)(SPM_NUM-1 downto 0);\n signal spm_rs1 : std_logic;\n signal spm_rs2 : std_logic;\n signal vec_read_rs1_ID : std_logic;\n signal vec_read_rs2_ID : std_logic;\n signal vec_write_rd_ID : std_logic;\n signal dsp_we_word : array_2d(accl_range)(SIMD-1 downto 0);\n\n -- instruction operands\n signal CSR_ADDR_IE : std_logic_vector(11 downto 0); -- unused\n signal RS1_Addr_IE : std_logic_vector(4 downto 0); -- unused\n signal RS2_Addr_IE : std_logic_vector(4 downto 0); -- unused\n signal RS1_Data_IE : std_logic_vector(31 downto 0);\n signal RS2_Data_IE : std_logic_vector(31 downto 0);\n signal RD_Data_IE : std_logic_vector(31 downto 0); -- unused\n\n signal ls_parallel_exec : std_logic;\n signal dsp_parallel_exec : std_logic;\n signal dsp_to_jump : std_logic;\n\n\n constant buf_size : integer := 10;\n\n signal harc_EXEC_lat : harc_range;\n signal core_busy_IE_lat : std_logic;\n signal rs1_chk_en : std_logic;\n signal rs2_chk_en : std_logic;\n signal rd_read_only_chk_en : std_logic;\n signal IE_instr : std_logic;\n signal LSU_instr : std_logic;\n signal DSP_instr : std_logic;\n signal EXEC_instr : std_logic;\n signal EXEC_Instr_lat : std_logic;\n signal rs1_valid : std_logic;\n signal rs2_valid : std_logic;\n signal rd_read_only_valid : std_logic;\n signal rd_valid : std_logic;\n signal rs1_valid_buf : std_logic_vector(buf_size-1 downto 0);\n signal rs2_valid_buf : std_logic_vector(buf_size-1 downto 0);\n signal rd_read_only_valid_buf : std_logic_vector(buf_size-1 downto 0);\n signal rd_valid_buf : std_logic_vector(buf_size-1 downto 0);\n signal Instr_word_buf : array_2d(buf_size-1 downto 0)(31 downto 0);\n signal pc_buf : array_2d(buf_size-1 downto 0)(31 downto 0);\n signal rs1_valid_buf_wire : std_logic_vector(buf_size-1 downto 0);\n signal rs2_valid_buf_wire : std_logic_vector(buf_size-1 downto 0);\n signal rd_valid_buf_wire : std_logic_vector(buf_size-1 downto 0);\n signal rd_read_only_valid_buf_wire : std_logic_vector(buf_size-1 downto 0);\n signal Instr_word_buf_wire : array_2d(buf_size-1 downto 0)(31 downto 0);\n signal pc_buf_wire : array_2d(buf_size-1 downto 0)(31 downto 0);\n signal buf_wr_ptr : integer := 0;\n signal buf_wr_ptr_lat : integer := 0;\n signal RAW_wire : array_2d_int(buf_size-1 downto 0);\n signal RAW : array_2d_int(buf_size-1 downto 0);\n signal tracer_result : std_logic_vector(31 downto 0);\n signal tracer_mul_result : std_logic_vector(63 downto 0);\n\n function rs1 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(15+(RF_CEIL-1) downto 15)));\n end;\n\n function rs2 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(20+(RF_CEIL-1) downto 20)));\n end;\n\n function rd (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(7+(RF_CEIL-1) downto 7)));\n end;\n\n component IF_STAGE is\n generic(\n THREAD_POOL_SIZE : integer\n );\n port (\n pc_IF : in std_logic_vector(31 downto 0);\n busy_ID : in std_logic; \n instr_rvalid_i : in std_logic;\n harc_IF : in harc_range;\n harc_ID : out harc_range;\n pc_ID : out std_logic_vector(31 downto 0); -- pc_ID is PC entering ID stage\n instr_rvalid_ID : out std_logic;\n instr_word_ID_lat : out std_logic_vector(31 downto 0);\n -- clock, reset active low\n clk_i : in std_logic;\n rst_ni : in std_logic;\n -- program memory interface\n instr_req_o : out std_logic;\n instr_gnt_i : in std_logic;\n instr_rdata_i : in std_logic_vector(31 downto 0)\n );\n end component; --------------------------------------------------\n\n component ID_STAGE is\n generic(\n THREAD_POOL_SIZE : integer;\n RV32M : natural;\n superscalar_exec_en : natural;\n accl_en : natural;\n replicate_accl_en : natural;\n SPM_NUM : natural; \n Addr_Width : natural;\n SPM_STRT_ADDR : std_logic_vector(31 downto 0);\n ACCL_NUM : natural;\n RF_CEIL : natural;\n RF_SIZE : natural;\n SPM_ADDR_WID : natural\n );\n port (\n\t-- Branch Control Signals\n comparator_en : out std_logic;\n ls_instr_req : out std_logic;\n ie_instr_req : out std_logic;\n dsp_instr_req : out std_logic_vector(ACCL_NUM-1 downto 0);\n decoded_instruction_IE : out std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0);\n decoded_instruction_LS : out std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0);\n decoded_instruction_DSP : out std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0);\n data_be_ID : out std_logic_vector(3 downto 0);\n data_width_ID : out std_logic_vector(1 downto 0);\n amo_store : in std_logic;\n amo_load : out std_logic;\n amo_load_skip : out std_logic;\n load_op : out std_logic;\n store_op : out std_logic;\n instr_word_IE : out std_logic_vector(31 downto 0);\n harc_ID : in integer range THREAD_POOL_SIZE-1 downto 0;\n pc_ID : in std_logic_vector(31 downto 0); -- pc_ID is PC entering ID stage\n core_busy_IE : in std_logic;\n core_busy_LS : in std_logic;\n busy_LS : in std_logic;\n busy_DSP : in std_logic_vector(ACCL_NUM-1 downto 0);\n busy_ID : out std_logic;\n ls_parallel_exec : out std_logic;\n dsp_parallel_exec : out std_logic;\n dsp_to_jump : out std_logic;\n pc_IE : out std_logic_vector(31 downto 0); -- pc_IE is pc entering stage IE ***\n instr_rvalid_ID : in std_logic; \n instr_rvalid_IE : out std_logic; -- validity bit at IE input\n halt_IE : out std_logic;\n halt_LSU : out std_logic;\n instr_word_ID_lat : in std_logic_vector(31 downto 0);\n spm_rs1 : out std_logic;\n spm_rs2 : out std_logic;\n --sw_mip : out std_logic;\n signed_op : out std_logic;\n harc_EXEC : out integer range THREAD_POOL_SIZE-1 downto 0;\n vec_read_rs1_ID : out std_logic;\n vec_read_rs2_ID : out std_logic;\n vec_write_rd_ID : out std_logic;\n vec_width_ID : out std_logic_vector(1 downto 0);\n -- clock, reset active low\n clk_i : in std_logic;\n rst_ni : in std_logic\n );\n end component; ------------------------------------------\n\n component Load_Store_Unit is\n generic(\n THREAD_POOL_SIZE : integer;\n accl_en : natural;\n replicate_accl_en : natural;\n SIMD : natural;\n SPM_NUM\t\t : natural; \n Addr_Width : natural;\n Data_Width : natural;\n SIMD_BITS : natural;\n ACCL_NUM : natural;\n SPM_ADDR_WID : natural\n );\n port (\n -- clock, and reset active low\n clk_i, rst_ni : in std_logic;\n -- Program Counter Signals\n irq_pending : in std_logic_vector(harc_range);\n -- ID_Stage Signals\n RS1_Data_IE : in std_logic_vector(31 downto 0);\n RS2_Data_IE : in std_logic_vector(31 downto 0);\n RD_Data_IE : in std_logic_vector(31 downto 0);\n instr_word_IE : in std_logic_vector(31 downto 0);\n pc_IE : in std_logic_vector(31 downto 0);\n decoded_instruction_LS : in std_logic_vector(LS_UNIT_INSTR_SET_SIZE-1 downto 0);\n data_be_ID : in std_logic_vector(3 downto 0);\n data_width_ID : in std_logic_vector(1 downto 0);\n harc_EXEC : in harc_range;\n LS_instr_req : in std_logic;\n load_op : in std_logic;\n store_op : in std_logic;\n --sw_mip : in std_logic;\n core_busy_LS : out std_logic;\n busy_LS : out std_logic;\n -- Processing Pipeline Signals\n rs1_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rs2_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rd_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n halt_LSU : in std_logic;\n data_addr_internal : out std_logic_vector(31 downto 0);\n ls_except_data : out std_logic_vector(31 downto 0);\n ls_except_condition : out std_logic;\n ls_taken_branch : out std_logic;\n amo_load : in std_logic;\n amo_load_skip : in std_logic;\n amo_store : out std_logic;\n -- CSR Signals\n misaligned_err : out std_logic;\n -- Scratchpad Interface Signals\n ls_data_gnt_i : in std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_wr_gnt : in std_logic;\n ls_sc_data_read_wire : in std_logic_vector(Data_Width-1 downto 0);\n state_LS : out fsm_LS_states;\n harc_LS_wire : out accl_range;\n sc_word_count_wire : out integer;\n spm_bcast : out std_logic;\n kmemld_inflight : out std_logic_vector(SPM_NUM-1 downto 0);\n kmemstr_inflight : out std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_req : out std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_we : out std_logic_vector(SPM_NUM-1 downto 0);\n ls_sc_read_addr : out std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n ls_sc_write_addr : out std_logic_vector(Addr_Width-(SIMD_BITS+3)downto 0);\n ls_sc_data_write_wire : out std_logic_vector(Data_Width-1 downto 0);\n -- WB_Stage Signals\n LS_WB_EN : out std_logic;\n harc_LS_WB : out harc_range;\n instr_word_LS_WB : out std_logic_vector(31 downto 0);\n LS_WB : out std_logic_vector(31 downto 0);\n -- Data memory interface\n data_req_o : out std_logic;\n data_gnt_i : in std_logic;\n data_rvalid_i : in std_logic;\n data_we_o : out std_logic;\n data_be_o : out std_logic_vector(3 downto 0);\n data_addr_o : out std_logic_vector(31 downto 0);\n data_wdata_o : out std_logic_vector(31 downto 0);\n data_rdata_i : in std_logic_vector(31 downto 0);\n data_err_i : in std_logic\n\t);\n end component; ------------------------------------------ \n\n component IE_STAGE is\n generic(\n THREAD_POOL_SIZE : integer;\n RV32M : natural;\n RF_CEIL : natural\n );\n port (\n\t -- clock, and reset active low\n clk_i, rst_ni : in std_logic;\n irq_i : in std_logic;\n RS1_Data_IE : in std_logic_vector(31 downto 0);\n RS2_Data_IE : in std_logic_vector(31 downto 0);\n irq_pending : in std_logic_vector(harc_range);\n fetch_enable_i : in std_logic;\n csr_instr_done : in std_logic;\n csr_access_denied_o : in std_logic;\n csr_rdata_o : in std_logic_vector(31 downto 0);\n pc_IE : in std_logic_vector(31 downto 0);\n instr_word_IE : in std_logic_vector(31 downto 0);\n data_addr_internal_IE : in std_logic_vector(31 downto 0);\n comparator_en : in std_logic;\n --sw_mip : in std_logic;\n signed_op : in std_logic;\n ie_instr_req : in std_logic;\n dbg_req_o : in std_logic;\n MSTATUS : in array_2d(harc_range)(1 downto 0);\n harc_EXEC : in harc_range;\n instr_rvalid_IE : in std_logic; -- validity bit at IE input\n taken_branch : in std_logic;\n halt_IE : in std_logic;\n decoded_instruction_IE : in std_logic_vector(EXEC_UNIT_INSTR_SET_SIZE-1 downto 0);\n csr_addr_i : out std_logic_vector(11 downto 0);\n ie_except_data : out std_logic_vector(31 downto 0);\n ie_csr_wdata_i : out std_logic_vector(31 downto 0);\n csr_op_i : out std_logic_vector(2 downto 0);\n csr_wdata_en : out std_logic;\n harc_to_csr : out harc_range;\n csr_instr_req : out std_logic;\n core_busy_IE : out std_logic;\n jump_instr : out std_logic;\n jump_instr_lat : out std_logic;\n WFI_Instr : out std_logic;\n sleep_state : out std_logic;\n reset_state : out std_logic;\n set_branch_condition : out std_logic;\n IE_except_condition : out std_logic;\n set_mret_condition : out std_logic;\n set_wfi_condition : out std_logic;\n ie_taken_branch : out std_logic;\n branch_instr : out std_logic;\n branch_instr_lat : out std_logic;\n PC_offset : out array_2D(harc_range)(31 downto 0);\n served_irq \t : out std_logic_vector(harc_range);\n dbg_ack_i : out std_logic;\n ebreak_instr : out std_logic;\n absolute_jump : out std_logic;\n instr_word_IE_WB : out std_logic_vector (31 downto 0);\n IE_WB_EN : out std_logic;\n IE_WB : out std_logic_vector(31 downto 0);\n MUL_WB_EN : out std_logic;\n MUL_WB : out std_logic_vector(31 downto 0);\n harc_IE_WB : out harc_range;\n pc_WB : out std_logic_vector(31 downto 0);\n state_IE : out fsm_IE_states\n );\n end component; ------------------------------------------\n\n component DSP_Unit is\n generic(\n THREAD_POOL_SIZE : integer;\n accl_en : natural;\n replicate_accl_en : natural;\n multithreaded_accl_en : natural;\n SPM_NUM : natural; \n Addr_Width : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n FU_NUM : natural;\n TPS_CEIL : natural;\n TPS_BUF_CEIL : natural;\n SPM_ADDR_WID : natural;\n SIMD_BITS : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n port (\n\t -- Core Signals\n clk_i, rst_ni : in std_logic;\n -- Processing Pipeline Signals\n rs1_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rs2_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rd_to_sc : in std_logic_vector(SPM_ADDR_WID-1 downto 0);\n\t -- CSR Signals\n MVSIZE : in array_2d(harc_range)(Addr_Width downto 0);\n MVTYPE : in array_2d(harc_range)(3 downto 0);\n MPSCLFAC : in array_2d(harc_range)(4 downto 0);\n dsp_except_data : out array_2d(accl_range)(31 downto 0);\n -- Program Counter Signals\n dsp_taken_branch : out std_logic_vector(accl_range);\n dsp_except_condition : out std_logic_vector(accl_range);\n -- ID_Stage Signals\n decoded_instruction_DSP : in std_logic_vector(DSP_UNIT_INSTR_SET_SIZE-1 downto 0);\n harc_EXEC : in harc_range;\n pc_IE : in std_logic_vector(31 downto 0);\n RS1_Data_IE : in std_logic_vector(31 downto 0);\n RS2_Data_IE : in std_logic_vector(31 downto 0);\n RD_Data_IE : in std_logic_vector(Addr_Width -1 downto 0);\n dsp_instr_req : in std_logic_vector(accl_range);\n spm_rs1 : in std_logic;\n spm_rs2 : in std_logic;\n vec_read_rs1_ID : in std_logic;\n vec_read_rs2_ID : in std_logic;\n vec_write_rd_ID : in std_logic;\n busy_dsp : out std_logic_vector(accl_range);\n\t-- Scratchpad Interface Signals\n dsp_data_gnt_i : in std_logic_vector(accl_range);\n dsp_sci_wr_gnt : in std_logic_vector(accl_range);\n dsp_sc_data_read : in array_3d(accl_range)(1 downto 0)(SIMD_Width-1 downto 0);\n dsp_we_word : out array_2d(accl_range)(SIMD-1 downto 0);\n dsp_sc_read_addr : out array_3d(accl_range)(1 downto 0)(Addr_Width-1 downto 0);\n dsp_to_sc : out array_3d(accl_range)(SPM_NUM-1 downto 0)(1 downto 0);\n dsp_sc_data_write_wire : out array_2d(accl_range)(SIMD_Width-1 downto 0);\n dsp_sc_write_addr : out array_2d(accl_range)(Addr_Width-1 downto 0);\n dsp_sci_we : out array_2d(accl_range)(SPM_NUM-1 downto 0);\n dsp_sci_req : out array_2d(accl_range)(SPM_NUM-1 downto 0);\n -- tracer signals\n state_DSP : out array_2d(accl_range)(1 downto 0)\n\t);\n end component; ------------------------------------------\n\n component Scratchpad_memory_interface is\n generic(\n accl_en : natural;\n SPM_NUM : natural; \n Addr_Width : natural;\n SIMD : natural;\n -------------------------------------\n ACCL_NUM : natural;\n SIMD_BITS : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n port (\n clk_i, rst_ni : in std_logic;\n data_rvalid_i : in std_logic;\n state_LS : in fsm_LS_states;\n sc_word_count_wire : in integer;\n spm_bcast : in std_logic;\n harc_LS_wire : in accl_range;\n dsp_we_word : in array_2d(accl_range)(SIMD-1 downto 0);\n ls_sc_data_write_wire : in std_logic_vector(Data_Width-1 downto 0);\n dsp_sc_data_write_wire : in array_2d(accl_range)(SIMD_Width-1 downto 0);\n ls_sc_read_addr : in std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n ls_sc_write_addr : in std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n dsp_sc_write_addr : in array_2d(accl_range)(Addr_Width-1 downto 0);\n ls_sci_req : in std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_we : in std_logic_vector(SPM_NUM-1 downto 0);\n dsp_sci_req : in array_2d(accl_range)(SPM_NUM-1 downto 0);\n dsp_sci_we : in array_2d(accl_range)(SPM_NUM-1 downto 0);\n kmemld_inflight : in std_logic_vector(SPM_NUM-1 downto 0);\n kmemstr_inflight : in std_logic_vector(SPM_NUM-1 downto 0);\n dsp_to_sc : in array_3d(accl_range)(SPM_NUM-1 downto 0)(1 downto 0);\n dsp_sc_read_addr : in array_3d(accl_range)(1 downto 0)(Addr_Width-1 downto 0);\n dsp_sc_data_read : out array_3d(accl_range)(1 downto 0)(SIMD_Width-1 downto 0);\n ls_sc_data_read_wire : out std_logic_vector(Data_Width-1 downto 0);\n ls_sci_wr_gnt : out std_logic;\n dsp_sci_wr_gnt : out std_logic_vector(accl_range);\n ls_data_gnt_i : out std_logic_vector(SPM_NUM-1 downto 0);\n dsp_data_gnt_i : out std_logic_vector(accl_range)\n\t);\n end component; ------------------------------------------\n\n component REGISTERFILE is\n generic(\n THREAD_POOL_SIZE : integer;\n LUTRAM_RF : natural;\n accl_en : natural;\n SPM_NUM : natural; \n Addr_Width : natural;\n SPM_STRT_ADDR : std_logic_vector(31 downto 0);\n RF_SIZE : natural;\n RF_CEIL : natural;\n SPM_ADDR_WID : natural\n );\n port (\n -- clock, reset active low\n clk_i : in std_logic;\n rst_ni : in std_logic;\n -- Branch Control Signals\n harc_ID : in integer range THREAD_POOL_SIZE-1 downto 0;\n pc_ID : in std_logic_vector(31 downto 0); -- pc_ID is PC entering ID stage\n core_busy_IE : in std_logic;\n core_busy_LS : in std_logic;\n ls_parallel_exec : in std_logic;\n dsp_parallel_exec : in std_logic;\n dsp_to_jump : in std_logic;\n instr_rvalid_ID : in std_logic;\n instr_word_ID_lat : in std_logic_vector(31 downto 0);\n LS_WB_EN : in std_logic;\n IE_WB_EN : in std_logic;\n MUL_WB_EN : in std_logic;\n IE_WB : in std_logic_vector(31 downto 0);\n MUL_WB : in std_logic_vector(31 downto 0);\n LS_WB : in std_logic_vector(31 downto 0);\n instr_word_LS_WB : in std_logic_vector(31 downto 0);\n instr_word_IE_WB : in std_logic_vector(31 downto 0);\n harc_LS_WB : in integer range THREAD_POOL_SIZE-1 downto 0;\n harc_IE_WB : in integer range THREAD_POOL_SIZE-1 downto 0;\n RS1_Data_IE : out std_logic_vector(31 downto 0);\n RS2_Data_IE : out std_logic_vector(31 downto 0);\n RD_Data_IE : out std_logic_vector(31 downto 0);\n rs1_to_sc : out std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rs2_to_sc : out std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rd_to_sc : out std_logic_vector(SPM_ADDR_WID-1 downto 0);\n data_addr_internal_IE : out std_logic_vector(31 downto 0);\n regfile : out array_3d(THREAD_POOL_SIZE-1 downto 0)(RF_SIZE-1 downto 0)(31 downto 0)\n );\n end component;\n\n--------------------------------------------------------------------------------------------------\n----------------------- ARCHITECTURE BEGIN -------------------------------------------------------\nbegin\n\n -- Klessydra T13 (4 stages) pipeline implementation -----------------------\n\n -- check for microarchitecture configuration limit, up to 16 thread support.\n assert THREAD_POOL_SIZE < 2**THREAD_ID_SIZE\n report \"Threading configuration not supported\"\n severity error;\n\n\t \n taken_branch <= '1' when (ie_taken_branch = '1' or ls_taken_branch = '1' or unsigned(dsp_taken_branch) /= 0) else '0';\n\t\t\t\t\t\n csr_wdata_i <= ie_csr_wdata_i;\n\n------------------------------------------------------------------------------------------------------------------------------------\n-- Core_busy_o\n------------------------------------------------------------------------------------------------------------------------------------\n\n core_busy_o <= '1' when (instr_rvalid_i or instr_rvalid_ID or instr_rvalid_IE) = '1' and rst_ni = '1' else '0';\n------------------------------------------------------------------------------------------------------------------------------------\n\n dsp_except_off : if accl_en = 0 generate\n dsp_except_condition <= (others => '0');\n dsp_taken_branch <= (others => '0');\n end generate;\n\n------------------------------------------------------------------------------------------------------------------------------------\n-- Mapping of the pipeline stages\n------------------------------------------------------------------------------------------------------------------------------------\n\n ----------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n ---------------------------------------------------------------- \n\n\n FETCH : IF_STAGE\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE\n )\n port map(\n pc_IF => pc_IF, \n harc_IF => harc_IF, \n busy_ID => busy_ID, \n instr_rvalid_i => instr_rvalid_i, \n harc_ID => harc_ID, \n pc_ID => pc_ID, \n instr_rvalid_ID => instr_rvalid_ID, \n instr_word_ID_lat => instr_word_ID_lat, \n clk_i => clk_i, \n rst_ni => rst_ni, \n instr_req_o => instr_req_o, \n instr_gnt_i => instr_gnt_i,\n instr_rdata_i => instr_rdata_i\n );\n\n DECODE : ID_STAGE\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE,\n RV32M => RV32M,\n superscalar_exec_en => superscalar_exec_en,\n accl_en => accl_en,\n replicate_accl_en => replicate_accl_en,\n SPM_NUM\t\t => SPM_NUM, \n Addr_Width => Addr_Width,\n SPM_STRT_ADDR => SPM_STRT_ADDR,\n ACCL_NUM => ACCL_NUM,\n RF_CEIL => RF_CEIL,\n RF_SIZE => RF_SIZE,\n SPM_ADDR_WID => SPM_ADDR_WID\n )\n port map( \n comparator_en => comparator_en,\n ie_instr_req => ie_instr_req, \n ls_instr_req => ls_instr_req, \n dsp_instr_req => dsp_instr_req, \n decoded_instruction_IE => decoded_instruction_IE, \n decoded_instruction_LS => decoded_instruction_LS, \n decoded_instruction_DSP => decoded_instruction_DSP,\n data_be_ID => data_be_ID,\n data_width_ID => data_width_ID,\n amo_store => amo_store,\n amo_load => amo_load,\n amo_load_skip => amo_load_skip,\n load_op => load_op,\n store_op => store_op, \n instr_word_IE => instr_word_IE,\n harc_ID => harc_ID,\n pc_ID => pc_ID,\n core_busy_IE => core_busy_IE,\n core_busy_LS => core_busy_LS,\n busy_LS => busy_LS,\n busy_DSP => busy_DSP,\n busy_ID => busy_ID,\n ls_parallel_exec => ls_parallel_exec,\n dsp_parallel_exec => dsp_parallel_exec,\n dsp_to_jump => dsp_to_jump,\n pc_IE => pc_IE,\n instr_rvalid_ID => instr_rvalid_ID,\n instr_rvalid_IE => instr_rvalid_IE,\n halt_IE => halt_IE,\n halt_LSU => halt_LSU,\n instr_word_ID_lat => instr_word_ID_lat,\n spm_rs1 => spm_rs1,\n spm_rs2 => spm_rs2,\n --sw_mip => sw_mip,\n signed_op => signed_op,\n harc_EXEC => harc_EXEC,\n vec_read_rs1_ID => vec_read_rs1_ID,\n vec_read_rs2_ID => vec_read_rs2_ID,\n vec_write_rd_ID => vec_write_rd_ID,\n clk_i => clk_i,\n rst_ni => rst_ni \n );\n\n LSU : Load_Store_Unit\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE,\n accl_en => accl_en,\n replicate_accl_en => replicate_accl_en,\n SIMD => SIMD,\n SPM_NUM\t\t => SPM_NUM, \n Addr_Width => Addr_Width,\n Data_Width => Data_Width,\n SIMD_BITS => SIMD_BITS,\n ACCL_NUM => ACCL_NUM,\n SPM_ADDR_WID => SPM_ADDR_WID\n )\n port map(\n clk_i => clk_i,\n rst_ni => rst_ni, \n irq_pending => irq_pending,\n instr_word_IE => instr_word_IE, \n pc_IE => pc_IE, \n RS1_Data_IE => RS1_Data_IE, \n RS2_Data_IE => RS2_Data_IE, \n RD_Data_IE => RD_Data_IE,\n decoded_instruction_LS => decoded_instruction_LS,\n data_be_ID => data_be_ID,\n data_width_ID => data_width_ID,\n harc_EXEC => harc_EXEC,\n LS_instr_req => LS_instr_req,\n load_op => load_op,\n store_op => store_op,\n --sw_mip => sw_mip,\n core_busy_LS => core_busy_LS, \n busy_LS => busy_LS,\n rs1_to_sc => rs1_to_sc,\n rs2_to_sc => rs2_to_sc,\n rd_to_sc => rd_to_sc,\n halt_LSU => halt_LSU,\n data_addr_internal => data_addr_internal, \n ls_except_data => ls_except_data, \n ls_except_condition => ls_except_condition, \n ls_taken_branch => ls_taken_branch,\n amo_load => amo_load, \n amo_load_skip => amo_load_skip, \n amo_store => amo_store, \n misaligned_err => misaligned_err,\n ls_data_gnt_i => ls_data_gnt_i,\n ls_sci_wr_gnt => ls_sci_wr_gnt,\n ls_sc_data_read_wire => ls_sc_data_read_wire,\n state_LS => state_LS,\n harc_LS_wire => harc_LS_wire,\n sc_word_count_wire => sc_word_count_wire,\n spm_bcast => spm_bcast,\n kmemld_inflight => kmemld_inflight,\n kmemstr_inflight => kmemstr_inflight,\n ls_sci_req => ls_sci_req,\n ls_sci_we => ls_sci_we,\n ls_sc_read_addr => ls_sc_read_addr,\n ls_sc_write_addr => ls_sc_write_addr,\n ls_sc_data_write_wire => ls_sc_data_write_wire,\n LS_WB_EN => LS_WB_EN, \n harc_LS_WB => harc_LS_WB,\n instr_word_LS_WB => instr_word_LS_WB,\n LS_WB => LS_WB,\n data_req_o => data_req_o, \n data_gnt_i => data_gnt_i, \n data_rvalid_i => data_rvalid_i, \n data_we_o => data_we_o, \n data_be_o => data_be_o, \n data_addr_o => data_addr_o, \n data_wdata_o => data_wdata_o, \n data_rdata_i => data_rdata_i, \n data_err_i => data_err_i \n );\n\n EXECUTE : IE_STAGE\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE, \n RF_CEIL => RF_CEIL,\n RV32M => RV32M\n )\n port map(\n clk_i => clk_i,\n rst_ni => rst_ni,\n irq_i => irq_i,\n RS1_Data_IE => RS1_Data_IE,\n RS2_Data_IE => RS2_Data_IE,\n irq_pending => irq_pending,\n fetch_enable_i => fetch_enable_i,\n csr_instr_done => csr_instr_done,\n csr_access_denied_o => csr_access_denied_o,\n csr_rdata_o => csr_rdata_o,\n pc_IE => pc_IE,\n instr_word_IE => instr_word_IE,\n data_addr_internal_IE => data_addr_internal_IE,\n comparator_en => comparator_en,\n --sw_mip => sw_mip,\n signed_op => signed_op,\n ie_instr_req => ie_instr_req,\n dbg_req_o => dbg_req_o,\n MSTATUS => MSTATUS,\n harc_EXEC => harc_EXEC,\n instr_rvalid_IE => instr_rvalid_IE,\n taken_branch => taken_branch,\n halt_IE => halt_IE,\n decoded_instruction_IE => decoded_instruction_IE,\n csr_addr_i => csr_addr_i,\n ie_except_data => ie_except_data,\n ie_csr_wdata_i => ie_csr_wdata_i,\n csr_op_i => csr_op_i,\n csr_wdata_en => csr_wdata_en,\n harc_to_csr => harc_to_csr,\n csr_instr_req => csr_instr_req,\n core_busy_IE => core_busy_IE,\n jump_instr => jump_instr,\n jump_instr_lat => jump_instr_lat,\n WFI_Instr => WFI_Instr,\n sleep_state => sleep_state,\n reset_state => reset_state,\n set_branch_condition => set_branch_condition,\n IE_except_condition => IE_except_condition,\n set_mret_condition => set_mret_condition,\n set_wfi_condition => set_wfi_condition,\n ie_taken_branch => ie_taken_branch,\n branch_instr => branch_instr,\n branch_instr_lat => branch_instr_lat,\n PC_offset => PC_offset,\n served_irq \t => served_irq,\n dbg_ack_i => dbg_ack_i,\n ebreak_instr => ebreak_instr,\n absolute_jump => absolute_jump,\n instr_word_IE_WB => instr_word_IE_WB,\n IE_WB_EN => IE_WB_EN,\n IE_WB => IE_WB,\n MUL_WB_EN => MUL_WB_EN,\n MUL_WB => MUL_WB,\n harc_IE_WB => harc_IE_WB,\n pc_WB => pc_WB,\n state_IE => state_IE\n );\n\n ACCL_generate : if accl_en = 1 generate\n\n DSP : DSP_Unit\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE, \n accl_en => accl_en, \n replicate_accl_en => replicate_accl_en, \n multithreaded_accl_en => multithreaded_accl_en, \n SPM_NUM\t\t => SPM_NUM, \n Addr_Width => Addr_Width, \n SIMD => SIMD, \n --------------------------------\n ACCL_NUM => ACCL_NUM, \n FU_NUM => FU_NUM, \n TPS_CEIL => TPS_CEIL, \n TPS_BUF_CEIL => TPS_BUF_CEIL, \n SPM_ADDR_WID => SPM_ADDR_WID, \n SIMD_BITS => SIMD_BITS, \n Data_Width => Data_Width, \n SIMD_Width => SIMD_Width\n )\n port map(\n clk_i => clk_i,\n rst_ni => rst_ni,\n rs1_to_sc => rs1_to_sc,\n rs2_to_sc => rs2_to_sc,\n rd_to_sc => rd_to_sc,\n MVSIZE => MVSIZE,\n MVTYPE => MVTYPE,\n MPSCLFAC => MPSCLFAC,\n dsp_except_data => dsp_except_data,\n dsp_taken_branch => dsp_taken_branch,\n dsp_except_condition => dsp_except_condition,\n decoded_instruction_DSP => decoded_instruction_DSP,\n harc_EXEC => harc_EXEC,\n pc_IE => pc_IE,\n RS1_Data_IE => RS1_Data_IE,\n RS2_Data_IE => RS2_Data_IE,\n RD_Data_IE => RD_Data_IE(Addr_Width -1 downto 0),\n dsp_instr_req => dsp_instr_req,\n spm_rs1 => spm_rs1,\n spm_rs2 => spm_rs2,\n vec_read_rs1_ID => vec_read_rs1_ID,\n vec_read_rs2_ID => vec_read_rs2_ID,\n vec_write_rd_ID => vec_write_rd_ID,\n busy_DSP => busy_DSP,\n dsp_data_gnt_i => dsp_data_gnt_i,\n dsp_sci_wr_gnt => dsp_sci_wr_gnt,\n dsp_sc_data_read => dsp_sc_data_read,\n dsp_sc_read_addr => dsp_sc_read_addr,\n dsp_to_sc => dsp_to_sc,\n dsp_sc_data_write_wire => dsp_sc_data_write_wire,\n dsp_we_word => dsp_we_word,\n dsp_sc_write_addr => dsp_sc_write_addr,\n dsp_sci_we => dsp_sci_we,\n dsp_sci_req => dsp_sci_req\n\t);\n\n SCI : Scratchpad_memory_interface\n generic map(\n accl_en => accl_en, \n SPM_NUM => SPM_NUM, \n Addr_Width => Addr_Width, \n SIMD => SIMD, \n ----------------------------------------------\n ACCL_NUM => ACCL_NUM, \n SIMD_BITS => SIMD_BITS, \n Data_Width => Data_Width, \n SIMD_Width => SIMD_Width\n )\n port map( \n clk_i => clk_i,\n rst_ni => rst_ni,\n data_rvalid_i => data_rvalid_i,\n state_LS => state_LS,\n sc_word_count_wire => sc_word_count_wire,\n spm_bcast => spm_bcast,\n harc_LS_wire => harc_LS_wire,\n dsp_we_word => dsp_we_word,\n ls_sc_data_write_wire => ls_sc_data_write_wire,\n dsp_sc_data_write_wire => dsp_sc_data_write_wire,\n ls_sc_read_addr => ls_sc_read_addr,\n ls_sc_write_addr => ls_sc_write_addr,\n dsp_sc_write_addr => dsp_sc_write_addr,\n ls_sci_req => ls_sci_req,\n ls_sci_we => ls_sci_we,\n dsp_sci_req => dsp_sci_req,\n dsp_sci_we => dsp_sci_we,\n kmemld_inflight => kmemld_inflight,\n kmemstr_inflight => kmemstr_inflight,\n dsp_to_sc => dsp_to_sc,\n dsp_sc_read_addr => dsp_sc_read_addr,\t \n dsp_sc_data_read => dsp_sc_data_read,\n ls_sc_data_read_wire => ls_sc_data_read_wire,\n ls_sci_wr_gnt => ls_sci_wr_gnt,\n dsp_sci_wr_gnt => dsp_sci_wr_gnt,\n ls_data_gnt_i => ls_data_gnt_i,\n dsp_data_gnt_i => dsp_data_gnt_i\n\t);\n\n end generate;\n\n RF : REGISTERFILE\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE,\n LUTRAM_RF => LUTRAM_RF,\n accl_en => accl_en,\n SPM_NUM => SPM_NUM,\n Addr_Width => Addr_Width,\n SPM_STRT_ADDR => SPM_STRT_ADDR,\n RF_SIZE => RF_SIZE,\n RF_CEIL => RF_CEIL,\n SPM_ADDR_WID => SPM_ADDR_WID\n )\n port map(\n -- clock, reset active low\n clk_i => clk_i,\n rst_ni => rst_ni,\n -- Branch Control Signals\n harc_ID => harc_ID,\n pc_ID => pc_ID,\n core_busy_IE => core_busy_IE,\n core_busy_LS => core_busy_LS,\n ls_parallel_exec => ls_parallel_exec,\n dsp_parallel_exec => dsp_parallel_exec,\n dsp_to_jump => dsp_to_jump,\n instr_rvalid_ID => instr_rvalid_ID,\n instr_word_ID_lat => instr_word_ID_lat,\n LS_WB_EN => LS_WB_EN,\n IE_WB_EN => IE_WB_EN,\n MUL_WB_EN => MUL_WB_EN,\n IE_WB => IE_WB,\n MUL_WB => MUL_WB,\n LS_WB => LS_WB,\n instr_word_LS_WB => instr_word_LS_WB,\n instr_word_IE_WB => instr_word_IE_WB,\n harc_LS_WB => harc_LS_WB,\n harc_IE_WB => harc_IE_WB,\n RS1_Data_IE => RS1_Data_IE,\n RS2_Data_IE => RS2_Data_IE,\n RD_Data_IE => RD_Data_IE,\n rs1_to_sc => rs1_to_sc,\n rs2_to_sc => rs2_to_sc,\n rd_to_sc => rd_to_sc,\n data_addr_internal_IE => data_addr_internal_IE,\n regfile => regfile\n );\n \n ---------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n ---------------------------------------------------------\n\n -- pragma translate_off\n\n Tracer_generate : if tracer_en = 1 generate\n Tracer_sync : process(clk_i, rst_ni) -- also implements the delay slot counters and some aux signals\n variable row : line;\n variable row0 : line;\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n\n\n ----------------------------------------------------------------\n -- ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n ----------------------------------------------------------------\n\n case state_IE is -- stage state\n when normal =>\n if ie_instr_req = '0' and core_busy_IE_lat = '0' then\n elsif irq_pending(harc_EXEC) = '1' then\n else\n -- EXECUTE OF INSTRUCTION -------------------------------------------\n if (decoded_instruction_IE(SW_MIP_bit_position) = '1') then\n if (data_addr_internal_IE(31 downto 8) = x\"0000FF\") then -- checks that the instruction is not a store\n write(row0, \" \" & to_string(now, ns) & \" \"); --Add a timestamp to line\n write(row0, ht);\n hwrite(row0, pc_IE);\n write(row0, string'(\"_\"));\n hwrite(row0, instr_word_IE); \n end if;\n else\n write(row0, \" \" & to_string(now, ns) & \" \"); --Add a timestamp to line\n write(row0, ht);\n hwrite(row0, pc_IE);\n write(row0, string'(\"_\"));\n hwrite(row0, instr_word_IE); \n end if;\n\n if decoded_instruction_IE(ADDI_bit_position) = '1' then\n write(row0, string'(\" addi x\"));\n end if;\n\n if decoded_instruction_IE(SLTI_bit_position) = '1' then\n write(row0, string'(\" slti x\"));\n end if;\n\n if decoded_instruction_IE(SLTIU_bit_position) = '1' then\n write(row0, string'(\" sltiu x\"));\n end if;\n\n if decoded_instruction_IE(ANDI_bit_position) = '1' then\n write(row0, string'(\" andi x\"));\n end if;\n\n if decoded_instruction_IE(ORI_bit_position) = '1' then\n write(row0, string'(\" ori x\"));\n end if;\n\n if decoded_instruction_IE(XORI_bit_position) = '1' then\n write(row0, string'(\" xori x\"));\n end if;\n\n if decoded_instruction_IE(SLLI_bit_position) = '1' then\n write(row0, string'(\" slli x\"));\n end if;\n\n if decoded_instruction_IE(SRLI7_bit_position) = '1' then\n write(row0, string'(\" srli x\"));\n end if;\n\n if decoded_instruction_IE(SRAI7_bit_position) = '1' then\n write(row0, string'(\" srai x\"));\n end if;\n\n if decoded_instruction_IE(ADDI_bit_position) = '1' or decoded_instruction_IE(SLTI_bit_position) = '1'\n or decoded_instruction_IE(SLTIU_bit_position) = '1' or decoded_instruction_IE(ANDI_bit_position) = '1'\n or decoded_instruction_IE(ORI_bit_position) = '1' or decoded_instruction_IE(XORI_bit_position) = '1'\n or decoded_instruction_IE(SLLI_bit_position) = '1' or decoded_instruction_IE(SRLI7_bit_position) = '1'\n or decoded_instruction_IE(SRAI7_bit_position) = '1' then\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\",0x\"));\n hwrite(row0, I_imm(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n --if accl_en = 1 then\n -- write(row0, string'(\" old_rd=0x\"));\n -- hwrite(row0, RD_Data_IE);\n --end if;\n write(row0, string'(\" new_rd=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_IE(LUI_bit_position) = '1' then\n write(row0, string'(\" lui x\"));\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",0x\"));\n hwrite(row0, U_imm(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n --if accl_en = 1 then\n -- write(row0, string'(\"old_rd=0x\"));\n -- hwrite(row0, RD_Data_IE);\n --end if;\n write(row0, string'(\" new_rd=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_IE(AUIPC_bit_position) = '1' then\n write(row0, string'(\" auipc x\"));\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",0x\"));\n hwrite(row0, U_imm(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n --if accl_en = 1 then\n -- write(row0, string'(\"old_rd=0x\"));\n -- hwrite(row0, RD_Data_IE);\n --end if;\n write(row0, string'(\" new_rd=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_IE(ADD7_bit_position) = '1' then\n write(row0, string'(\" add x\"));\n end if;\n\n if decoded_instruction_IE(SUB7_bit_position) = '1' then\n write(row0, string'(\" sub x\"));\n end if;\n\n if decoded_instruction_IE(SLT_bit_position) = '1' then\n write(row0, string'(\" slt x\"));\n end if;\n\n if decoded_instruction_IE(SLTU_bit_position) = '1' then\n write(row0, string'(\" sltu x\"));\n end if;\n\n if decoded_instruction_IE(ANDD_bit_position) = '1' then\n write(row0, string'(\" and x\"));\n end if;\n\n if decoded_instruction_IE(ORR_bit_position) = '1' then\n write(row0, string'(\" or x\"));\n end if;\n\n if decoded_instruction_IE(XORR_bit_position) = '1' then\n write(row0, string'(\" xor x\"));\n end if;\n\n if decoded_instruction_IE(SLLL_bit_position) = '1' then\n write(row0, string'(\" sll x\"));\n end if;\n\n if decoded_instruction_IE(SRLL7_bit_position) = '1' then\n write(row0, string'(\" srl x\"));\n end if;\n\n if decoded_instruction_IE(SRAA7_bit_position) = '1' then\n write(row0, string'(\" sra x\"));\n end if;\n\n if decoded_instruction_IE(ADD7_bit_position) = '1' or decoded_instruction_IE(SUB7_bit_position) = '1'\n or decoded_instruction_IE(SLT_bit_position) = '1' or decoded_instruction_IE(SLTU_bit_position) = '1'\n or decoded_instruction_IE(ANDD_bit_position) = '1' or decoded_instruction_IE(ORR_bit_position) = '1'\n or decoded_instruction_IE(XORR_bit_position) = '1' or decoded_instruction_IE(SLLL_bit_position) = '1'\n or decoded_instruction_IE(SRLL7_bit_position) = '1' or decoded_instruction_IE(SRAA7_bit_position) = '1' then\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs2(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n write(row0, string'(\" rs2=0x\"));\n hwrite(row0, RS2_Data_IE);\n --if accl_en = 1 then\n -- write(row0, string'(\" old_rd=0x\"));\n -- hwrite(row0, RD_Data_IE);\n --end if;\n write(row0, string'(\" new_rd=0x\"));\n hwrite(row0, tracer_result); end if;\n\n if decoded_instruction_IE(JAL_bit_position) = '1' then\n write(row0, string'(\" jal x\"));\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",0x\"));\n hwrite(row0, UJ_imm(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"next_pc=\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_IE(JALR_bit_position) = '1' then\n write(row0, string'(\" jalr x\"));\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\",0x\"));\n hwrite(row0, I_imm(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"next_pc=\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_IE(BEQ_bit_position) = '1' then\n write(row0, string'(\" beq x\"));\n end if;\n\n if decoded_instruction_IE(BNE_bit_position) = '1' then\n write(row0, string'(\" bne x\"));\n end if;\n\n if decoded_instruction_IE(BLT_bit_position) = '1' then\n write(row0, string'(\" blt x\"));\n end if;\n\n if decoded_instruction_IE(BLTU_bit_position) = '1' then\n write(row0, string'(\" bltu x\"));\n end if;\n\n if decoded_instruction_IE(BGE_bit_position) = '1' then\n write(row0, string'(\" bge x\"));\n end if;\n\n if decoded_instruction_IE(BGEU_bit_position) = '1' then\n write(row0, string'(\" bgeu x\"));\n end if;\n\n if decoded_instruction_IE(BEQ_bit_position) = '1' or\n decoded_instruction_IE(BNE_bit_position) = '1' or\n decoded_instruction_IE(BLT_bit_position) = '1' or\n decoded_instruction_IE(BLTU_bit_position) = '1' or\n decoded_instruction_IE(BGE_bit_position) = '1' or\n decoded_instruction_IE(BGEU_bit_position) = '1' then\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs2(instr_word_IE));\n write(row0, string'(\",0x\"));\n hwrite(row0, B_imm(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n write(row0, string'(\" rs2=0x\"));\n hwrite(row0, RS2_Data_IE);\n write(row0, string'(\" next_pc=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_IE(SW_MIP_bit_position) = '1' then\n end if;\n\n if decoded_instruction_IE(FENCE_bit_position) = '1' then\n write(row0, string'(\" fence\"));\n end if;\n\n if decoded_instruction_IE(FENCEI_bit_position) = '1' then\n write(row0, string'(\" fencei\"));\n end if;\n\n if decoded_instruction_IE(ECALL_bit_position) = '1' then\n write(row0, string'(\" ecall\"));\n end if;\n\n if decoded_instruction_IE(EBREAK_bit_position) = '1' then\n write(row0, string'(\" ebreak\"));\n end if;\n\n if decoded_instruction_IE(MRET_bit_position) = '1' then\n write(row0, string'(\" mret\"));\n end if;\n\n if decoded_instruction_IE(WFI_bit_position) = '1' then\n write(row0, string'(\" wfi\"));\n end if;\n\n if decoded_instruction_IE(CSRRW_bit_position) = '1' then\n write(row0, string'(\" csrw x\"));\n end if;\n\n if decoded_instruction_IE(CSRRC_bit_position) = '1' then\n write(row0, string'(\" csrc x\"));\n end if;\n\n if decoded_instruction_IE(CSRRS_bit_position) = '1' then\n write(row0, string'(\" csrs x\"));\n end if;\n\n if decoded_instruction_IE(CSRRWI_bit_position) = '1' then\n write(row0, string'(\" csrwi x\"));\n end if;\n\n if decoded_instruction_IE(CSRRSI_bit_position) = '1' then\n write(row0, string'(\" csrsi x\"));\n end if;\n\n if decoded_instruction_IE(CSRRCI_bit_position) = '1' then\n write(row0, string'(\" csrci x\"));\n end if;\n\n if decoded_instruction_IE(CSRRW_bit_position) = '1' or\n decoded_instruction_IE(CSRRC_bit_position) = '1' or \n decoded_instruction_IE(CSRRS_bit_position) = '1' or\n decoded_instruction_IE(CSRRWI_bit_position) = '1' or\n decoded_instruction_IE(CSRRSI_bit_position) = '1' or\n decoded_instruction_IE(CSRRCI_bit_position) = '1' then\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n case CSR_ADDR(instr_word_IE) is\n when MVSIZE_addr =>\n write(row0, string'(\",mvsize\"));\n when MPSCLFAC_addr =>\n write(row0, string'(\",mpsclfac\"));\n when MSTATUS_addr =>\n write(row0, string'(\",mstatus\"));\n when MIP_addr =>\n write(row0, string'(\",mip\"));\n when MEPC_addr =>\n write(row0, string'(\",mepc\"));\n when MTVEC_addr =>\n write(row0, string'(\",mtvec\"));\n when MCAUSE_addr =>\n write(row0, string'(\",mcause\"));\n when MESTATUS_addr =>\n write(row0, string'(\",mestatus\"));\n when MCPUID_addr =>\n write(row0, string'(\",mcpuid\"));\n when MIMPID_addr =>\n write(row0, string'(\",mimpid\"));\n when MHARTID_addr =>\n write(row0, string'(\",mhartid\"));\n when MIRQ_addr =>\n write(row0, string'(\",mirq\"));\n when BADADDR_addr =>\n write(row0, string'(\",badaddr\"));\n when MCYCLE_addr =>\n write(row0, string'(\",mcycle\"));\n when MCYCLEH_addr =>\n write(row0, string'(\",mcycleh\"));\n when MINSTRET_addr =>\n write(row0, string'(\",minstret\"));\n when MINSTRETH_addr =>\n write(row0, string'(\",minstreth\"));\n when MHPMCOUNTER3_addr =>\n write(row0, string'(\",mhpcounter3\"));\n when MHPMCOUNTER6_addr =>\n write(row0, string'(\",mhpcounter6\"));\n when MHPMCOUNTER7_addr =>\n write(row0, string'(\",mhpcounter7\"));\n when MHPMCOUNTER8_addr =>\n write(row0, string'(\",mhpcounter8\"));\n when MHPMCOUNTER9_addr =>\n write(row0, string'(\",mhpcounter10\"));\n when MHPMCOUNTER10_addr =>\n write(row0, string'(\",mhpcounter10\"));\n when PCER_addr =>\n write(row0, string'(\",pcer\"));\n when MHPMEVENT3_addr =>\n write(row0, string'(\",mhpevent3\"));\n when MHPMEVENT6_addr =>\n write(row0, string'(\",mhpevent6\"));\n when MHPMEVENT7_addr =>\n write(row0, string'(\",mhpevent7\"));\n when MHPMEVENT8_addr =>\n write(row0, string'(\",mhpevent8\"));\n when MHPMEVENT9_addr =>\n write(row0, string'(\",mhpevent9\"));\n when MHPMEVENT10_addr =>\n write(row0, string'(\",mhpevent10\"));\n when others =>\n write(row0, string'(\",0x\"));\n hwrite(row0, instr_word_IE(31 downto 20));\n end case;\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n --if accl_en = 1 then\n -- write(row0, string'(\" old_rd=0x\"));\n -- hwrite(row0, RD_Data_IE);\n --end if;\n end if;\n\n if decoded_instruction_IE(ILL_bit_position) = '1' then\n write(row0, string'(\" ill\"));\n end if;\n\n if decoded_instruction_IE(NOP_bit_position) = '1' then\n write(row0, string'(\" nop\"));\n end if;\n\n if decoded_instruction_IE(MUL_bit_position) = '1' then\n write(row0, string'(\" mul x\"));\n end if;\n\n if decoded_instruction_IE(MULH_bit_position) = '1' then\n write(row0, string'(\" mulh x\"));\n end if;\n\n if decoded_instruction_IE(MULHU_bit_position) = '1' then\n write(row0, string'(\" mulhu x\"));\n end if;\n\n if decoded_instruction_IE(MULHSU_bit_position) = '1' then\n write(row0, string'(\" mulhsu x\"));\n end if;\n\n if decoded_instruction_IE(DIVU_bit_position) = '1' then\n write(row0, string'(\" divu x\"));\n end if;\n\n if decoded_instruction_IE(DIV_bit_position) = '1' then\n write(row0, string'(\" div x\"));\n end if;\n\n if decoded_instruction_IE(REMU_bit_position) = '1' then\n write(row0, string'(\" remu x\"));\n end if;\n\n if decoded_instruction_IE(REM_bit_position) = '1' then\n write(row0, string'(\" rem x\"));\n end if;\n\n if decoded_instruction_IE(MUL_bit_position) = '1' or\n decoded_instruction_IE(MULH_bit_position) = '1' or\n decoded_instruction_IE(MULHU_bit_position) = '1' or\n decoded_instruction_IE(MULHSU_bit_position) = '1' or\n decoded_instruction_IE(DIV_bit_position) = '1' or\n decoded_instruction_IE(DIVU_bit_position) = '1' or\n decoded_instruction_IE(REMU_bit_position) = '1' or\n decoded_instruction_IE(REM_bit_position) = '1' then\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs2(instr_word_IE));\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n write(row0, string'(\" rs2=0x\"));\n hwrite(row0, RS2_Data_IE);\n --if accl_en = 1 then\n -- write(row0, string'(\" old_rd=0x\"));\n -- hwrite(row0, RD_Data_IE);\n --end if;\n write(row0, string'(\" new_rd=0x\"));\n if decoded_instruction_IE(MUL_bit_position) = '1' then\n hwrite(row0, tracer_mul_result(31 downto 0));\n elsif decoded_instruction_IE(MULH_bit_position) = '1' or\n decoded_instruction_IE(MULHU_bit_position) = '1' or\n decoded_instruction_IE(MULHSU_bit_position) = '1' then\n hwrite(row0, tracer_mul_result(63 downto 32));\n end if;\n end if;\n\n\n -- EXECUTE OF INSTRUCTION (END) --------------------------\n end if; -- instr_rvalid_IE values\n when others =>\n end case; -- fsm_IE state cases\n\n\n ----------------------------------------------------------------------------\n -- ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n ----------------------------------------------------------------------------\n\n if LS_instr_req = '1' and halt_LSU = '0' then\n case state_LS is\t\n when normal =>\n\n if not(decoded_instruction_IE(SW_MIP_bit_position) = '1' and data_addr_internal_IE(31 downto 8) = x\"0000FF\") then -- checks that the instruction is not a sw_mip\n write(row0, \" \" & to_string(now, ns) & \" \"); --Add a timestamp to line\n write(row0, ht);\n hwrite(row0, pc_IE);\n write(row0, '_');\n hwrite(row0, instr_word_IE); \n end if;\n\n if decoded_instruction_LS(LW_bit_position) = '1' then\n write(row0, string'(\" lw x\"));\n end if;\n\n if decoded_instruction_LS(LH_bit_position) = '1' then\n write(row0, string'(\" lh x\"));\n end if;\n\n if decoded_instruction_LS(LHU_bit_position) = '1' then\n write(row0, string'(\" lhu x\"));\n end if;\n\n if decoded_instruction_LS(LB_bit_position) = '1' then\n write(row0, string'(\" lb x\"));\n end if;\n\n if decoded_instruction_LS(LBU_bit_position) = '1' then\n write(row0, string'(\" lbu x\"));\n end if;\n\n if decoded_instruction_LS(LW_bit_position) = '1' or\n decoded_instruction_LS(LH_bit_position) = '1' or decoded_instruction_LS(LHU_bit_position) = '1' or \n decoded_instruction_LS(LB_bit_position) = '1' or decoded_instruction_LS(LBU_bit_position) = '1' then\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",\"));\n write(row0, string'(\",0x\"));\n hwrite(row0, I_imm(instr_word_IE));\n write(row0, string'(\"(x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\")\"));\n write(row0, ht);\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n --write(row0, string'(\" rd=0x\"));\n --hwrite(row0, RD_Data_IE);\n write(row0, string'(\" addr=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_LS(SW_bit_position) = '1' then\n write(row0, string'(\" sw x\"));\n end if;\n\n if decoded_instruction_LS(SH_bit_position) = '1' then\n write(row0, string'(\" sh x\"));\n end if;\n\n if decoded_instruction_LS(SB_bit_position) = '1' then\n write(row0, string'(\" sb x\"));\n end if;\n\n if decoded_instruction_LS(SW_bit_position) = '1' or\n decoded_instruction_LS(SH_bit_position) = '1' or\n decoded_instruction_LS(SB_bit_position) = '1' then\n write(row0, rs2(instr_word_IE));\n write(row0, string'(\",\"));\n write(row0, string'(\",0x\"));\n hwrite(row0, S_imm(instr_word_IE));\n write(row0, string'(\"(x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\")\"));\n write(row0, ht);\n write(row0, ht);\n write(row0, ht);\n write(row0, string'(\"rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n write(row0, string'(\" rs2=0x\"));\n hwrite(row0, RS2_Data_IE);\n write(row0, string'(\" addr=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n if decoded_instruction_LS(AMOSWAP_bit_position) = '1' then\n write(row0, string'(\" amoswap x\"));\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs2(instr_word_IE));\n write(row0, string'(\",(x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\")\"));\n write(row0, string'(\" rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n write(row0, string'(\" rs2=0x\"));\n hwrite(row0, RS2_Data_IE);\n write(row0, string'(\" rd=0x\"));\n hwrite(row0, RD_Data_IE);\n write(row0, string'(\" addr=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n", "right_context": "\n if decoded_instruction_LS(KMEMSTR_bit_position) = '1' then\n write(row0, string'(\" kmemstr x\"));\n end if;\n\n if decoded_instruction_LS(KMEMLD_bit_position) = '1' or\n decoded_instruction_LS(KBCASTLD_bit_position) = '1' or \n decoded_instruction_LS(KMEMSTR_bit_position) = '1' then\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs2(instr_word_IE));\n write(row0, string'(\" rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n write(row0, string'(\" rs2=0x\"));\n hwrite(row0, RS2_Data_IE);\n write(row0, string'(\" rd=0x\"));\n hwrite(row0, RD_Data_IE);\n write(row0, string'(\" addr=0x\"));\n hwrite(row0, tracer_result);\n end if;\n\n when data_valid_waiting =>\n end case;\n end if;\n\n\n -----------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n -----------------------------------------------------------------------------\n if accl_en = 1 then\n for h in accl_range loop\n if dsp_instr_req(h) = '1' and instr_word_IE /= x\"0000_006F\" then -- checks that the valid dsp instruction did not to execute as an infinite jump\n write(row0, \" \" & to_string(now, ns) & \" \"); --Add a timestamp to line\n write(row0, ht);\n hwrite(row0, pc_IE);\n write(row0, '_');\n hwrite(row0, instr_word_IE);\n -- Set signals to enable correct virtual parallelism operation\n if decoded_instruction_DSP(KADDV_bit_position) = '1' then\n write(row0, string'(\" kaddv x\"));\n elsif decoded_instruction_DSP(KSVADDRF_bit_position) = '1' then\n write(row0, string'(\" ksvaddrf x\"));\n elsif decoded_instruction_DSP(KSVADDSC_bit_position) = '1' then\n write(row0, string'(\" ksvaddsc x\"));\n elsif decoded_instruction_DSP(KSUBV_bit_position) = '1' then\n write(row0, string'(\" ksubv x\"));\n elsif decoded_instruction_DSP(KVMUL_bit_position) = '1' then\n write(row0, string'(\" kvmul x\"));\n elsif decoded_instruction_DSP(KSVMULRF_bit_position) = '1' then\n write(row0, string'(\" ksvmulrf x\"));\n elsif decoded_instruction_DSP(KSVMULSC_bit_position) = '1' then\n write(row0, string'(\" ksvmulsc x\"));\n elsif decoded_instruction_DSP(KSRLV_bit_position) = '1' then\n write(row0, string'(\" ksrlv x\"));\n elsif decoded_instruction_DSP(KSRAV_bit_position) = '1' then\n write(row0, string'(\" ksrav x\"));\n elsif decoded_instruction_DSP(KVRED_bit_position) = '1' then\n write(row0, string'(\" kvred x\"));\n elsif decoded_instruction_DSP(KDOTP_bit_position) = '1' then\n write(row0, string'(\" kdotp x\"));\n elsif decoded_instruction_DSP(KDOTPPS_bit_position) = '1' then\n write(row0, string'(\" kdotpps x\"));\n elsif decoded_instruction_DSP(KRELU_bit_position) = '1' then\n write(row0, string'(\" krelu x\"));\n elsif decoded_instruction_DSP(KVSLT_bit_position) = '1' then\n write(row0, string'(\" kvslt x\"));\n elsif decoded_instruction_DSP(KSVSLT_bit_position) = '1' then\n write(row0, string'(\" ksvslt x\"));\n elsif decoded_instruction_DSP(KBCAST_bit_position) = '1' then\n write(row0, string'(\" kbcast x\"));\n elsif decoded_instruction_DSP(KVCP_bit_position) = '1' then\n write(row0, string'(\" kvcp x\"));\n end if;\n\n if decoded_instruction_DSP(KVRED_bit_position) = '1' or\n decoded_instruction_DSP(KRELU_bit_position) = '1' or\n decoded_instruction_DSP(KBCAST_bit_position) = '1' or\n decoded_instruction_DSP(KVCP_bit_position) = '1' or\n FUNCT7(instr_word_IE) = KBCAST then\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n else\n write(row0, rd(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs1(instr_word_IE));\n write(row0, string'(\",x\"));\n write(row0, rs2(instr_word_IE));\n end if;\n write(row0, string'(\" SPM_rd(\"));\n write(row0, to_integer(unsigned(rd_to_sc)));\n write(row0, string'(\")=0x\"));\n hwrite(row0, RD_Data_IE);\n if spm_rs1 = '1' then\n write(row0, string'(\" SPM_rs1(\"));\n write(row0, to_integer(unsigned(rs1_to_sc)));\n write(row0, string'(\")=0x\"));\n hwrite(row0, RS1_Data_IE);\n else\n write(row0, string'(\" RF_rs1=0x\"));\n hwrite(row0, RS1_Data_IE);\n end if;\n if spm_rs2 = '1' then\n write(row0, string'(\" SPM_rs2(\"));\n write(row0, to_integer(unsigned(rs2_to_sc)));\n write(row0, string'(\")=0x\"));\n hwrite(row0, RS2_Data_IE);\n else\n write(row0, string'(\" RF_rs2=0x\"));\n hwrite(row0, RS2_Data_IE);\n end if;\n write(row0, string'(\" MVSIZE=0x\"));\n hwrite(row0, MVSIZE(h));\n write(row0, string'(\"(0d'\"));\n write(row0, to_integer(unsigned(MVSIZE(h))));\n write(row0, string'(\")\"));\n end if;\n end loop;\n end if;\n ----------------------------------------------------------------------- Write Line -------------------------------------------------------------\n for i in 0 to THREAD_POOL_SIZE-1 loop\n if harc_EXEC=i then\t\n if (instr_rvalid_IE = '1') then\n if i = 0 then\n writeline(file_handler0, row0); -- Writes line to instr. trace file\n elsif i = 1 then\n writeline(file_handler1, row0); -- Writes line to instr. trace file\n elsif i = 2 then\n writeline(file_handler2, row0); -- Writes line to instr. trace file\n end if;\n end if;\n end if;\n end loop;\n ------------------------------------------------------------------------------------------------------------------------------------------------\n\n end if; -- reset, clk_i\n end process;\n \n\n ----------------------------------------------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ --\n -- ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• --\n ----------------------------------------------------------------------------------------------------\n\n\n Tracer_Comb : process(all) -- also implements the delay slot counters and some aux signals\n begin\n\n IE_instr <= '0';\n LSU_instr <= '0';\n DSP_instr <= '0';\n rs1_valid <= '0';\n rs2_valid <= '0';\n rd_read_only_valid <= '0';\n rd_valid <= '0';\n\n case state_IE is -- stage status\n when normal =>\n if ie_instr_req = '0' and core_busy_IE_lat = '0' then\n elsif irq_pending(harc_EXEC) = '1' then\n else-- process the instruction\n IE_instr <= '1';\n -- TRACE IF EXECUTE INSTRUCTIONS ---------------------\n\n if decoded_instruction_IE(ADDI_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(signed(RS1_Data_IE)+signed(I_immediate(instr_word_IE)));\n end if;\n\n if decoded_instruction_IE(SLTI_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n if (signed(RS1_Data_IE) < signed (I_immediate(instr_word_IE))) then\n tracer_result <= std_logic_vector(to_unsigned(1, 32));\n else\n tracer_result <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(SLTIU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n if (unsigned(RS1_Data_IE) < unsigned (I_immediate(instr_word_IE))) then\n tracer_result <= std_logic_vector(to_unsigned(1, 32));\n else\n tracer_result <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(ANDI_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE and I_immediate(instr_word_IE);\n end if;\n\n if decoded_instruction_IE(ORI_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE or I_immediate(instr_word_IE);\n end if;\n\n if decoded_instruction_IE(XORI_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE xor I_immediate(instr_word_IE);\n end if;\n\n if decoded_instruction_IE(SLLI_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= to_stdlogicvector(to_bitvector(RS1_Data_IE) sll to_integer(unsigned(SHAMT(instr_word_IE))));\n end if;\n\n if decoded_instruction_IE(SRLI7_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= to_stdlogicvector(to_bitvector(RS1_Data_IE) srl to_integer(unsigned(SHAMT(instr_word_IE))));\n end if;\n\n if decoded_instruction_IE(SRAI7_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= to_stdlogicvector(to_bitvector(RS1_Data_IE) sra to_integer(unsigned(SHAMT(instr_word_IE))));\n end if;\n\n if decoded_instruction_IE(LUI_bit_position) = '1' then\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(unsigned(U_immediate(instr_word_IE)));\n end if;\n\n if decoded_instruction_IE(AUIPC_bit_position) = '1' then\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(unsigned(U_immediate(instr_word_IE))+unsigned(pc_IE));\n end if;\n\n if decoded_instruction_IE(ADD7_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(signed(RS1_Data_IE)+signed(RS2_Data_IE));\n end if;\n\n if decoded_instruction_IE(SUB7_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(signed(RS1_Data_IE)-signed(RS2_Data_IE));\n end if;\n\n if decoded_instruction_IE(SLT_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n if (signed(RS1_Data_IE) < signed(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(to_unsigned(1, 32));\n else\n tracer_result <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(SLTU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n if (unsigned(RS1_Data_IE) < unsigned(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(to_unsigned(1, 32));\n else\n tracer_result <= std_logic_vector(to_unsigned(0, 32));\n end if;\n end if;\n\n if decoded_instruction_IE(ANDD_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE and RS2_Data_IE;\n end if;\n\n if decoded_instruction_IE(ORR_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE or RS2_Data_IE;\n end if;\n\n if decoded_instruction_IE(XORR_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE xor RS2_Data_IE;\n end if;\n\n if decoded_instruction_IE(SLLL_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= to_stdlogicvector(to_bitvector(RS1_Data_IE) sll to_integer(unsigned(RS2_Data_IE(4 downto 0))));\n end if;\n\n if decoded_instruction_IE(SRLL7_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= to_stdlogicvector(to_bitvector(RS1_Data_IE) srl to_integer(unsigned(RS2_Data_IE(4 downto 0))));\n end if;\n\n if decoded_instruction_IE(SRAA7_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= to_stdlogicvector(to_bitvector(RS1_Data_IE) sra to_integer(unsigned(RS2_Data_IE(4 downto 0))));\n end if;\n\n if decoded_instruction_IE(FENCE_bit_position) = '1' or decoded_instruction_IE(FENCEI_bit_position) = '1' then\n end if;\n\n if decoded_instruction_IE(JAL_bit_position) = '1' then -- JAL instruction\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(signed(pc_IE)+signed(UJ_immediate(instr_word_IE)));\n end if;\n\n if decoded_instruction_IE(JALR_bit_position) = '1' then --JALR instruction\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(signed(RS1_Data_IE)+signed(I_immediate(instr_word_IE)));\n end if;\n\n if decoded_instruction_IE(BEQ_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n if (signed(RS1_Data_IE) = signed(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(signed(pc_IE)+signed(B_immediate(instr_word_IE)));\n else\n tracer_result <= std_logic_vector(signed(pc_IE)+4); \n end if;\n end if;\n\n if decoded_instruction_IE(BNE_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n if (signed(RS1_Data_IE) /= signed(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(signed(pc_IE)+signed(B_immediate(instr_word_IE)));\n else\n tracer_result <= std_logic_vector(signed(pc_IE)+4); \n end if;\n end if;\n\n if decoded_instruction_IE(BLT_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n if (signed(RS1_Data_IE) < signed(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(signed(pc_IE)+signed(B_immediate(instr_word_IE)));\n else\n tracer_result <= std_logic_vector(signed(pc_IE)+4); \n end if;\n end if;\n\n if decoded_instruction_IE(BLTU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n if (unsigned(RS1_Data_IE) < unsigned(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(signed(pc_IE)+signed(B_immediate(instr_word_IE)));\n else\n tracer_result <= std_logic_vector(signed(pc_IE)+4); \n end if;\n end if;\n\n if decoded_instruction_IE(BGE_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n if (signed(RS1_Data_IE) >= signed(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(signed(pc_IE)+signed(B_immediate(instr_word_IE)));\n else\n tracer_result <= std_logic_vector(signed(pc_IE)+4); \n end if;\n end if;\n\n if decoded_instruction_IE(BGEU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n if (signed(RS1_Data_IE) >= signed(RS2_Data_IE)) then\n tracer_result <= std_logic_vector(signed(pc_IE)+signed(B_immediate(instr_word_IE)));\n else\n tracer_result <= std_logic_vector(signed(pc_IE)+4); \n end if;\n end if;\n\n if decoded_instruction_IE(SW_MIP_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n end if;\n\n if decoded_instruction_IE(CSRRW_bit_position) = '1' or decoded_instruction_IE(CSRRWI_bit_position) = '1' or\n decoded_instruction_IE(CSRRC_bit_position) = '1' or decoded_instruction_IE(CSRRCI_bit_position) = '1' or\n decoded_instruction_IE(CSRRS_bit_position) = '1' or decoded_instruction_IE(CSRRSI_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n end if;\n\n if decoded_instruction_IE(ECALL_bit_position) = '1' then\n end if;\n\n if decoded_instruction_IE(EBREAK_bit_position) = '1' then\n end if;\n\n if decoded_instruction_IE(MRET_bit_position) = '1' then\n end if;\n\n if decoded_instruction_IE(WFI_bit_position) = '1' then\n end if;\n\n if decoded_instruction_IE(ILL_bit_position) = '1' then -- ILLEGAL_INSTRUCTION\n end if;\n\n if decoded_instruction_IE(NOP_bit_position) = '1' then\n end if;\n\n if decoded_instruction_IE(MUL_bit_position) = '1' or \n decoded_instruction_IE(MULH_bit_position) = '1' or\n decoded_instruction_IE(MULHU_bit_position) = '1' or\n decoded_instruction_IE(MULHSU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n end if;\n\n if decoded_instruction_IE(MUL_bit_position) = '1' or \n decoded_instruction_IE(MULH_bit_position) = '1' then\n tracer_mul_result <= std_logic_vector(signed(RS1_Data_IE)*signed(RS2_Data_IE));\n end if;\n\n if decoded_instruction_IE(MULHU_bit_position) = '1' then\n tracer_mul_result <= std_logic_vector(unsigned(RS1_Data_IE)*unsigned(RS2_Data_IE));\n end if;\n\n if decoded_instruction_IE(MULHSU_bit_position) = '1' then\n tracer_mul_result <= x\"FFFFFFFF_00000000\";\n end if;\n\n if decoded_instruction_IE(DIV_bit_position) = '1' or \n decoded_instruction_IE(REM_bit_position) = '1' or\n decoded_instruction_IE(DIVU_bit_position) = '1' or \n decoded_instruction_IE(REMU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n end if;\n\n -- EXECUTE OF INSTRUCTION (END)\n end if; -- instr_rvalid_IE values \n\n when others =>\n\n end case; -- fsm_IE state cases\n\n if LS_instr_req = '1' then\n LSU_instr <= '1';\n case state_LS is\t\n when normal =>\n if decoded_instruction_LS(LW_bit_position) = '1' or\n decoded_instruction_LS(LH_bit_position) = '1' or decoded_instruction_LS(LHU_bit_position) = '1' or \n decoded_instruction_LS(LB_bit_position) = '1' or decoded_instruction_LS(LBU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(signed(RS1_Data_IE)+signed(I_immediate(instr_word_IE)));\n end if;\n\n if decoded_instruction_LS(SW_bit_position) = '1' or\n decoded_instruction_LS(SH_bit_position) = '1' or \n decoded_instruction_LS(SB_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n tracer_result <= std_logic_vector(signed(RS1_Data_IE)+signed(S_immediate(instr_word_IE)));\n end if;\n\n if decoded_instruction_LS(AMOSWAP_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE;\n end if;\n\n if decoded_instruction_LS(KMEMLD_bit_position) = '1' or\n decoded_instruction_LS(KBCASTLD_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RS1_Data_IE;\n end if;\n\n if decoded_instruction_LS(KMEMSTR_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n tracer_result <= RD_Data_IE;\n end if;\n\n when data_valid_waiting =>\n end case;\n end if;\n\n for h in accl_range loop\n if dsp_instr_req(h) = '1' then \n DSP_instr <= '1';\n case state_DSP(h) is\n when dsp_init =>\n if decoded_instruction_DSP(KADDV_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSVADDSC_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSVADDRF_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSUBV_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KVMUL_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSVMULSC_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSVMULRF_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSRAV_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSRLV_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KVRED_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KVSLT_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KSVSLT_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KRELU_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KDOTP_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KDOTPPS_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rs2_valid <= '1' when rs2(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KBCAST_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n elsif decoded_instruction_DSP(KVCP_bit_position) = '1' then\n rs1_valid <= '1' when rs1(instr_word_IE) /= 0;\n rd_read_only_valid <= '1' when rd(instr_word_IE) /= 0;\n end if;\n when others =>\n end case;\n end if;\n end loop;\n end process;\n end generate Tracer_generate;\n\n EXEC_instr <= IE_instr or LSU_instr or DSP_instr;\n\n Dependency_checker : process(all) -- also implements the delay slot counters and some aux signals\n begin\n rs1_chk_en <= '0';\n rs2_chk_en <= '0';\n rd_read_only_chk_en <= '0';\n RAW_wire <= RAW;\n Instr_word_buf_wire <= Instr_word_buf; \n pc_buf_wire <= pc_buf; \n rs1_valid_buf_wire <= rs1_valid_buf; \n rs2_valid_buf_wire <= rs2_valid_buf; \n rd_read_only_valid_buf_wire <= rd_read_only_valid_buf;\n rd_valid_buf_wire <= rd_valid_buf;\n if unsigned(Instr_word_buf(buf_wr_ptr_lat)) /= 0 then -- check if there is a valid instruction (after first instruction this is always valid)\n if unsigned(PCER(0)) /= 0 then -- PCER when a perf counter is enabled the RAW dependency checker os also enabled.\n if harc_EXEC_lat = 0 and EXEC_Instr_lat = '1' then -- the checking only happens for harc_EXEC_lat = 0\n -----------------------------------------------------------------------------------------------\n if rs1_valid_buf(buf_wr_ptr_lat) = '1' then -- if rs1 is valid, then enable rs1_chk\n rs1_chk_en <= '1'; -- enable rs1_chk\n end if;\n -----------------------------------------------------------------------------------------------\n if rs2_valid_buf(buf_wr_ptr_lat) = '1' then -- if rs2(current_instr) is valid\n if rs1_valid_buf(buf_wr_ptr_lat) = '1' then -- if rs2(current_instr) is valid\n if Instr_word_buf(buf_wr_ptr_lat)(24 downto 20) /= Instr_word_buf(buf_wr_ptr_lat)(19 downto 15) then -- rs2 and rs1 operands are different\n rs2_chk_en <= '1'; -- enable if rs1 is valid and not equal to rs2\n end if;\n else -- if rs2 is valid, and rs1 is not then enable rs2\n rs2_chk_en <= '1'; -- enable rs2_chk if rs1 is not valid\n end if;\n end if;\n -----------------------------------------------------------------------------------------------\n if rd_read_only_valid_buf(buf_wr_ptr_lat) = '1' then -- if rd_read_only(current_instr) is valid\n if rs1_valid_buf(buf_wr_ptr_lat) = '1' then -- if rs2(current_instr) is valid\n if Instr_word_buf(buf_wr_ptr_lat)(11 downto 7) /= Instr_word_buf(buf_wr_ptr_lat)(19 downto 15) then -- rd and rs1 operands are different\n if rs2_valid_buf(buf_wr_ptr_lat) = '1' then\n if Instr_word_buf(buf_wr_ptr_lat)(11 downto 7) /= Instr_word_buf(buf_wr_ptr_lat)(24 downto 20) then -- rd and rs2 operands are different\n rd_read_only_chk_en <= '1'; -- enable if rs1, rs2 are valid and they are not equal to rd_read_only\n end if;\n else\n rd_read_only_chk_en <= '1'; -- enable if rs1 is valid and it is not equal to rd_read_only\n end if;\n end if;\n elsif rs2_valid_buf(buf_wr_ptr_lat) = '1' then -- if rs2 is valid, and rs1 is not then enable rs2\n if Instr_word_buf(buf_wr_ptr_lat)(11 downto 7) /= Instr_word_buf(buf_wr_ptr_lat)(24 downto 20) then -- rd and rs2 operands are different\n rd_read_only_chk_en <= '1'; -- enable if rs2 is valid and it is not equal to rd_read_only\n end if;\n else\n rd_read_only_chk_en <= '1'; -- enable rd_read_only_chk if rs1 and rs2 are npt valid\n end if;\n end if;\n -----------------------------------------------------------------------------------------------\n end if;\n end if;\n -----------------------------------------------------------------------------------------------\n if rs1_chk_en = '1' then -- check if the current instruction has rs1 as a valid read operand\n for i in 1 to buf_size-1 loop -- loop through the buffer (starts from i=1, since i=0 is the position of the current instruction)\n if buf_wr_ptr_lat-i >= 0 then -- buffer loop underflow enters here\n if unsigned(Instr_word_buf(buf_wr_ptr_lat-i)) /= 0 then -- if the previous instruction is valid\n if rd_valid_buf(buf_wr_ptr_lat-i) = '1' then -- if the previous instruction has a valid destination rd\n if (Instr_word_buf(buf_wr_ptr_lat)(19 downto 15) = Instr_word_buf(buf_wr_ptr_lat-i)(11 downto 7)) then -- if there is a RAW dependency between rs1(current_instr) and rd(previous_instr)\n Instr_word_buf_wire(buf_wr_ptr_lat-i) <= (others => '0');\n pc_buf_wire(buf_wr_ptr_lat-i) <= (others => '0');\n rs1_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rs2_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rd_read_only_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rd_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n RAW_wire(i) <= RAW(i)+1;\n exit;\n end if;\n end if;\n end if;\n else -- buffer loop overflow are here\n if unsigned(Instr_word_buf(buf_wr_ptr_lat-i+buf_size)) /= 0 then -- if the previous instruction is valid\n if rd_valid_buf(buf_wr_ptr_lat-i+buf_size) = '1' then -- if the previous instruction has a valid destination register\n if (Instr_word_buf(buf_wr_ptr_lat)(19 downto 15) = Instr_word_buf(buf_wr_ptr_lat-i+buf_size)(11 downto 7)) then -- if there is a RAW dependency between rs1(current_instr) and rd(previous_instr)\n Instr_word_buf_wire(buf_wr_ptr_lat-i+buf_size) <= (others => '0');\n pc_buf_wire(buf_wr_ptr_lat-i+buf_size) <= (others => '0');\n rs1_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rs2_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rd_read_only_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rd_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n RAW_wire(i) <= RAW(i)+1;\n exit;\n end if;\n end if;\n end if;\n end if;\n end loop;\n end if;\n if rs2_chk_en = '1' then -- check if the current instruction has rs2 as a valid read operand\n for i in 1 to buf_size-1 loop -- loop through the buffer (starts from i=1, since i=0 is the position of the current instruction)\n if buf_wr_ptr_lat-i >= 0 then -- buffer loop underflow enters here\n if unsigned(Instr_word_buf(buf_wr_ptr_lat-i)) /= 0 then -- if the previous instruction is valid\n if rd_valid_buf(buf_wr_ptr_lat-i) = '1' then -- if the previous instruction has a valid destination rd\n if (Instr_word_buf(buf_wr_ptr_lat)(24 downto 20) = Instr_word_buf(buf_wr_ptr_lat-i)(11 downto 7)) then -- if there is a RAW dependency between rs2(current_instr) and rd(previous_instr)\n Instr_word_buf_wire(buf_wr_ptr_lat-i) <= (others => '0');\n pc_buf_wire(buf_wr_ptr_lat-i) <= (others => '0');\n rs1_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rs2_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rd_read_only_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rd_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n RAW_wire(i) <= RAW(i)+1;\n exit;\n end if;\n end if;\n end if;\n else -- buffer loop overflow are here\n if unsigned(Instr_word_buf(buf_wr_ptr_lat-i+buf_size)) /= 0 then -- if the previous instruction is valid\n if rd_valid_buf(buf_wr_ptr_lat-i+buf_size) = '1' then -- if the previous instruction has a valid destination register\n if (Instr_word_buf(buf_wr_ptr_lat)(24 downto 20) = Instr_word_buf(buf_wr_ptr_lat-i+buf_size)(11 downto 7)) then -- if there is a RAW dependency between rs2(current_instr) and rd(previous_instr)\n Instr_word_buf_wire(buf_wr_ptr_lat-i+buf_size) <= (others => '0');\n pc_buf_wire(buf_wr_ptr_lat-i+buf_size) <= (others => '0');\n rs1_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rs2_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rd_read_only_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rd_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n RAW_wire(i) <= RAW(i)+1;\n exit;\n end if;\n end if;\n end if;\n end if;\n end loop;\n end if;\n if rd_read_only_chk_en = '1' then -- check if the current instruction has rs1 as a valid read operand\n for i in 1 to buf_size-1 loop -- loop through the buffer (starts from i=1, since i=0 is the position of the current instruction)\n if buf_wr_ptr_lat-i >= 0 then -- buffer loop underflow enters here\n if unsigned(Instr_word_buf(buf_wr_ptr_lat-i)) /= 0 then -- if the previous instruction is valid\n if rd_valid_buf(buf_wr_ptr_lat-i) = '1' then -- if the previous instruction has a valid destination rd\n if (Instr_word_buf(buf_wr_ptr_lat)(11 downto 7) = Instr_word_buf(buf_wr_ptr_lat-i)(11 downto 7)) then -- if there is a RAW dependency between rd_read_only(current_instr) and rd(previous_instr)\n Instr_word_buf_wire(buf_wr_ptr_lat-i) <= (others => '0');\n pc_buf_wire(buf_wr_ptr_lat-i) <= (others => '0');\n rs1_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rs2_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rd_read_only_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n rd_valid_buf_wire(buf_wr_ptr_lat-i) <= '0';\n RAW_wire(i) <= RAW(i)+1;\n exit;\n end if;\n end if;\n end if;\n else -- buffer loop overflow are here\n if unsigned(Instr_word_buf(buf_wr_ptr_lat-i+buf_size)) /= 0 then -- if the previous instruction is valid\n if rd_valid_buf(buf_wr_ptr_lat-i+buf_size) = '1' then -- if the previous instruction has a valid destination register\n if (Instr_word_buf(buf_wr_ptr_lat)(11 downto 7) = Instr_word_buf(buf_wr_ptr_lat-i+buf_size)(11 downto 7)) then -- if there is a RAW dependency between rd_read_only(current_instr) and rd(previous_instr)\n Instr_word_buf_wire(buf_wr_ptr_lat-i+buf_size) <= (others => '0');\n pc_buf_wire(buf_wr_ptr_lat-i+buf_size) <= (others => '0');\n rs1_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rs2_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rd_read_only_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n rd_valid_buf_wire(buf_wr_ptr_lat-i+buf_size) <= '0';\n RAW_wire(i) <= RAW(i)+1;\n exit;\n end if;\n end if;\n end if;\n end if;\n end loop;\n end if;\n -----------------------------------------------------------------------------------------------\n end if;\n end process;\n\n Dependency_buffer : process(clk_i, rst_ni) -- also implements the delay slot counters and some aux signals\n begin\n if rst_ni = '0' then\n Instr_word_buf <= (others => (others => '0'));\n pc_buf <= (others => (others => '0'));\n rs1_valid_buf <= (others => '0');\n rs2_valid_buf <= (others => '0');\n rd_read_only_valid_buf <= (others => '0');\n rd_valid_buf <= (others => '0');\n RAW <= (others => 0);\n core_busy_IE_lat <= '0';\n EXEC_Instr_lat <= '0';\n buf_wr_ptr <= 0;\n buf_wr_ptr_lat <= 0;\n harc_EXEC_lat <= 0;\n elsif rising_edge(clk_i) then\n core_busy_IE_lat <= core_busy_IE;\n Instr_word_buf <= Instr_word_buf_wire;\n pc_buf <= pc_buf_wire;\n rs1_valid_buf <= rs1_valid_buf_wire;\n rs2_valid_buf <= rs2_valid_buf_wire;\n rd_read_only_valid_buf <= rd_read_only_valid_buf_wire;\n rd_valid_buf <= rd_valid_buf_wire;\n RAW <= RAW_wire;\n buf_wr_ptr_lat <= buf_wr_ptr;\n EXEC_Instr_lat <= EXEC_Instr;\n harc_EXEC_lat <= harc_EXEC;\n if EXEC_instr = '1' then\n if harc_EXEC = 0 then\n rs1_valid_buf(buf_wr_ptr) <= rs1_valid;\n rs2_valid_buf(buf_wr_ptr) <= rs2_valid;\n rd_read_only_valid_buf(buf_wr_ptr) <= rd_read_only_valid;\n rd_valid_buf(buf_wr_ptr) <= rd_valid;\n Instr_word_buf(buf_wr_ptr) <= Instr_word_IE;\n pc_buf(buf_wr_ptr) <= pc_IE;\n if buf_wr_ptr < buf_size -1 then\n buf_wr_ptr <= buf_wr_ptr+1;\n else\n buf_wr_ptr <= 0;\n end if; \n end if;\n end if;\n end if;\n end process;\n -- pragma translate_on\n\n--------------------------------------------------------------------- end of PIPE -----------------\n---------------------------------------------------------------------------------------------------\n\nend Pipe;\n--------------------------------------------------------------------------------------------------\n-- END of Processing-Pipeline architecture -------------------------------------------------------\n--------------------------------------------------------------------------------------------------", "groundtruth": " if decoded_instruction_LS(KMEMLD_bit_position) = '1' then\r\n write(row0, string'(\" kmemld x\"));\r\n end if;\r\n\r\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Program_Counter_unit.vhd", "left_context": "--------------------------------------------------------------------------------------------------------------\n-- PC -- (Program Counters and hart interleavers) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 17-11-2019 --\n--------------------------------------------------------------------------------------------------------------\n-- Program Counter Managing Units -- synchronous process, sinle cycle. --\n-- Note: in the present version, gives priority to branching over trapping, except LSU and DSP traps -- \n-- i.e. branch instructions are not interruptible. This can be changed but may be unsafe. --\n-- Implements as many PC units as the number of harts supported --\n-- This entity also implements the hardware context counters that interleve the harts in the core. --\n--------------------------------------------------------------------------------------------------------------\n\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n\nentity Program_Counter is\n generic (\n THREAD_POOL_SIZE : integer;\n ACCL_NUM : natural\n );\n port (\n absolute_jump : in std_logic;\n data_we_o_lat : in std_logic;\n PC_offset : in array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\n taken_branch : in std_logic;\n ie_taken_branch : in std_logic;\n ls_taken_branch : in std_logic;\n dsp_taken_branch : in std_logic_vector(ACCL_NUM - 1 downto 0);\n set_branch_condition : in std_logic;\n ie_except_condition : in std_logic;\n ls_except_condition : in std_logic;\n dsp_except_condition : in std_logic_vector(ACCL_NUM - 1 downto 0);\n set_except_condition : in std_logic;\n set_mret_condition : in std_logic;\n set_wfi_condition : in std_logic;\n harc_ID : in integer range THREAD_POOL_SIZE - 1 downto 0;\n harc_EXEC : in integer range THREAD_POOL_SIZE - 1 downto 0;\n instr_rvalid_IE : in std_logic;\n pc_IE : in std_logic_vector(31 downto 0);\n MSTATUS : in array_2d(THREAD_POOL_SIZE - 1 downto 0)(1 downto 0);\n MIP, MEPC, MCAUSE, MTVEC : in array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\n instr_word_IE : in std_logic_vector(31 downto 0);\n reset_state : in std_logic;\n pc_IF : out std_logic_vector(31 downto 0);\n harc_IF : out integer range THREAD_POOL_SIZE - 1 downto 0;\n served_ie_except_condition : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\n served_ls_except_condition : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\n served_dsp_except_condition : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\n served_except_condition : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\n served_mret_condition : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\n served_irq : in std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\n taken_branch_pending : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\n taken_branch_pc_lat : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\n incremented_pc : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\n", "right_context": " boot_addr_i : in std_logic_vector(31 downto 0);\n instr_gnt_i : in std_logic\n );\nend entity;\n\n\narchitecture PC of Program_counter is\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0;\n subtype accl_range is integer range ACCL_NUM - 1 downto 0;\n\n -- pc updater signals\n signal pc_update_enable : std_logic_vector(harc_range);\n signal taken_branch_replicated : std_logic_vector(harc_range);\n signal set_branch_condition_replicated : std_logic_vector(harc_range);\n signal set_wfi_condition_replicated : std_logic_vector(harc_range);\n signal ls_except_condition_replicated : std_logic_vector(harc_range);\n signal ie_except_condition_replicated : std_logic_vector(harc_range);\n signal dsp_except_condition_replicated : std_logic_vector(harc_range);\n signal set_except_condition_replicated : std_logic_vector(harc_range);\n signal set_mret_condition_replicated : std_logic_vector(harc_range);\n signal relative_to_PC : array_2D(harc_range)(31 downto 0);\n signal pc : array_2D(harc_range)(31 downto 0);\n signal boot_pc : std_logic_vector(31 downto 0);\n signal harc_IF_internal : harc_range;\n signal mret_condition_pending_internal : std_logic_vector(harc_range);\n signal mepc_incremented_pc_internal : array_2D(harc_range)(31 downto 0);\n signal incremented_pc_internal : array_2D(harc_range)(31 downto 0);\n signal mepc_interrupt_pc_internal : array_2D(harc_range)(31 downto 0);\n signal taken_branch_pc_lat_internal : array_2D(harc_range)(31 downto 0);\n signal taken_branch_pc_pending_internal : array_2D(harc_range)(31 downto 0);\n signal taken_branch_pending_internal : std_logic_vector(harc_range);\n signal irq_pending_internal : std_logic_vector(harc_range);\n\n ------------------------------------------------------------------------------------------------------------\n -- Subroutine implementing pc updating combinational logic, that is replicated for the threads supported --\n ------------------------------------------------------------------------------------------------------------\n procedure pc_update(\n signal MTVEC : in std_logic_vector(31 downto 0);\n signal instr_gnt_i, taken_branch : in std_logic;\n signal set_wfi_condition : in std_logic;\n signal taken_branch_pending : inout std_logic;\n signal irq_pending : in std_logic;\n signal ie_except_condition : in std_logic;\n signal ls_except_condition : in std_logic;\n signal dsp_except_condition : in std_logic;\n signal set_except_condition : in std_logic;\n signal set_mret_condition : in std_logic;\n signal pc : inout std_logic_vector(31 downto 0);\n signal taken_branch_pc_lat : in std_logic_vector(31 downto 0);\n signal taken_branch_pc_pending : in std_logic_vector(31 downto 0);\n signal incremented_pc : in std_logic_vector(31 downto 0);\n signal boot_pc : in std_logic_vector(31 downto 0);\n signal pc_update_enable : in std_logic;\n signal served_ie_except_condition : out std_logic;\n signal served_ls_except_condition : out std_logic;\n signal served_dsp_except_condition : out std_logic;\n signal served_except_condition : out std_logic;\n signal served_mret_condition : out std_logic) is\n begin\n if pc_update_enable = '1' then\n\n -- interrupt service launched in the previous instr. cycle\n -- this is done for a second instr. cycle for proper synchronization of flushing\n -- nothing pending \n if not taken_branch = '1' and not taken_branch_pending = '1' then\n pc <= incremented_pc;\n served_except_condition <= '0';\n served_ie_except_condition <= '0';\n served_ls_except_condition <= '0';\n served_dsp_except_condition <= '0';\n served_mret_condition <= '0';\n -- taken_branch pending \n elsif taken_branch = '1' then\n pc <= taken_branch_pc_lat;\n taken_branch_pending <= '0';\n served_ie_except_condition <= '1' when ie_except_condition = '1' else '0'; -- for CS units;\n served_ls_except_condition <= '1' when ls_except_condition = '1' else '0'; -- for CS units;\n served_dsp_except_condition <= '1' when dsp_except_condition = '1' else '0'; -- for CS units;\n served_except_condition <= '1' when set_except_condition = '1' else '0'; -- for CS units;\n served_mret_condition <= '1' when set_mret_condition = '1' else '0'; -- for CS units;\n elsif taken_branch_pending = '1' then\n pc <= taken_branch_pc_pending;\n taken_branch_pending <= '0';\n served_ie_except_condition <= '1' when ie_except_condition = '1' else '0'; -- for CS units;\n served_ls_except_condition <= '1' when ls_except_condition = '1' else '0'; -- for CS units;\n served_dsp_except_condition <= '1' when dsp_except_condition = '1' else '0'; -- for CS units;\n served_except_condition <= '1' when set_except_condition = '1' else '0'; -- for CS units;\n served_mret_condition <= '1' when set_mret_condition = '1' else '0'; -- for CS units;\n else\n pc <= boot_pc; -- default, should never occur\n end if;\n -- end of pc value update --- \n else -- sets registers to record pending requests\n served_except_condition <= '0';\n served_mret_condition <= '0';\n if taken_branch = '1' then\n taken_branch_pending <= '1';\n end if;\n if set_except_condition = '1' then\n served_except_condition <= '1';\n end if;\n if dsp_except_condition = '1' then\n served_dsp_except_condition <= '1';\n elsif ls_except_condition = '1' then\n served_ls_except_condition <= '1';\n elsif ie_except_condition = '1' then\n served_ie_except_condition <= '1';\n end if;\n if set_mret_condition = '1' then\n served_mret_condition <= '1';\n end if;\n end if;\n end pc_update;\n --------------------------------------------------------------------------------------\n\nbegin\n\n harc_IF <= harc_IF_internal;\n mepc_incremented_pc <= mepc_incremented_pc_internal;\n mepc_interrupt_pc <= mepc_interrupt_pc_internal;\n taken_branch_pc_lat <= taken_branch_pc_lat_internal;\n incremented_pc <= incremented_pc_internal;\n taken_branch_pending <= taken_branch_pending_internal;\n irq_pending <= irq_pending_internal;\n\n hardware_context_counter : process(all)\n begin\n if rst_ni = '0' then\n harc_IF_internal <= THREAD_POOL_SIZE -1;\n elsif rising_edge(clk_i) then\n if instr_gnt_i = '1' then\n harc_IF_internal <= harc_IF_internal - 1 when harc_IF_internal > 0 else THREAD_POOL_SIZE -1;\n end if;\n end if;\n end process hardware_context_counter;\n\n -- this is the multiplexer on the PC_IF\n pc_IF <= pc(harc_IF_internal);\n\n -- fixed connections, not replicated \n boot_pc <= boot_addr_i(31 downto 8) & std_logic_vector(to_unsigned(128, 8));\n ----------------------------------------------------------------------------------------------\n -- this part of logic and registers is replicated as many times as the supported threads: --\n pc_update_logic : for h in harc_range generate\n\n mepc_incremented_pc_internal(h) <= MEPC(h);\n mepc_interrupt_pc_internal(h) <= MEPC(h) when MCAUSE(h)(30) = '0' else std_logic_vector(unsigned(MEPC(h)) + 4); -- MCAUSE(30) = '0' indicates that we weren't executing a WFI instruction\n\n relative_to_PC(h) <= std_logic_vector(to_unsigned(0, 32)) when (absolute_jump = '1')\n else pc_IE;\n incremented_pc_internal(h) <= std_logic_vector(unsigned(pc(h))+4);\n irq_pending_internal(h) <= ((MIP(h)(11) or MIP(h)(7) or MIP(h)(3)) and MSTATUS(h)(0));\n\n set_wfi_condition_replicated(h) <= '1' when set_wfi_condition = '1' and (harc_EXEC = h)\n else '0';\n taken_branch_replicated(h) <= '1' when dsp_taken_branch /= (accl_range => '0') and (harc_EXEC = h)\n\t else '1' when ls_taken_branch = '1' and (harc_EXEC = h)\n\t else '1' when ie_taken_branch = '1' and (harc_EXEC = h)\n else '0';\n set_branch_condition_replicated(h) <= '1' when set_branch_condition = '1' and (harc_EXEC = h)\n else '0';\n dsp_except_condition_replicated(h) <= '1' when dsp_except_condition /= (accl_range => '0') and (harc_EXEC = h)\n else '0';\n ls_except_condition_replicated(h) <= '1' when ls_except_condition = '1' and (harc_EXEC = h)\n else '0';\n ie_except_condition_replicated(h) <= '1' when ie_except_condition = '1' and (harc_EXEC = h)\n else '0';\n set_except_condition_replicated(h) <= '1' when dsp_except_condition_replicated(h) = '1' or ls_except_condition_replicated(h) = '1' or ie_except_condition_replicated(h) = '1'\n else '0';\n set_mret_condition_replicated(h) <= '1' when set_mret_condition = '1' and (harc_EXEC = h)\n else '0';\n\n -- latch on the branch address, possibly useless but may be needed in future situations, served_irq has the highest priority, interrupt request are checked before executing any instructions in the IE_Stage\n\n taken_branch_pc_lat_internal(h) <=\n MTVEC(h) when dsp_except_condition_replicated(h) = '1' else -- sets MTVEC address for exception trap\n MTVEC(h) when ls_except_condition_replicated(h) = '1' else -- sets MTVEC address for exception trap\n std_logic_vector(signed(relative_to_PC(h))+signed(PC_offset(h))) when set_branch_condition_replicated(h) = '1' else -- sets a jump or a branch address\n std_logic_vector(signed(relative_to_PC(h))) when set_wfi_condition_replicated(h) = '1' else -- sets a wfi address (spin lock)\n MTVEC(h) when ie_except_condition_replicated(h) = '1' else -- sets MTVEC address for exception trap\n mepc_incremented_pc_internal(h) when set_mret_condition_replicated(h) = '1' and MCAUSE(h)(31) = '0' else -- sets return address from exception subroutine\n mepc_interrupt_pc_internal(h) when set_mret_condition_replicated(h) = '1' and MCAUSE(h)(31) = '1' else -- sets return address from interrupt subroutine\n MTVEC(h) when served_irq(h) else -- sets MTVEC address for exception trap, \n (others => '0');\n\n\n pc_update_enable(h) <= '1' when instr_gnt_i = '1'\n and (harc_IF_internal = h\n or taken_branch_replicated(h) = '1'\n or set_wfi_condition_replicated(h) = '1'\n or taken_branch_pending_internal(h) = '1')\n else '0';\n\n pc_updater : process(clk_i, rst_ni, boot_pc)\n begin\n if rst_ni = '0' then\n pc(h) <= (others => '0'); -- better to put 0 to ensure clear synthesis\n taken_branch_pc_pending_internal(h) <= (others => '0');\n taken_branch_pending_internal(h) <= '0';\n served_ie_except_condition(h) <= '0';\n served_ls_except_condition(h) <= '0';\n served_dsp_except_condition(h) <= '0';\n served_except_condition(h) <= '0';\n served_mret_condition(h) <= '0';\n elsif rising_edge(clk_i) then\n -- synch.ly updates pc with new value depending on conditions pending \n -- synch.ly raises \"served\" signal for the condition that is being served \n -- synch.ly lowers \"served\" signal for other conditions\n if taken_branch_replicated(h) = '1' then \n taken_branch_pc_pending_internal(h) <= taken_branch_pc_lat_internal(h);\n end if;\n if reset_state = '1' then\n pc(h) <= boot_pc;\n else\n pc_update(MTVEC(h), instr_gnt_i, taken_branch_replicated(h), set_wfi_condition_replicated(h), taken_branch_pending_internal(h),\n irq_pending_internal(h),ie_except_condition_replicated(h), ls_except_condition_replicated(h), dsp_except_condition_replicated(h),\n\t\t\t\t\tset_except_condition_replicated(h), set_mret_condition_replicated(h), pc(h), taken_branch_pc_lat_internal(h), taken_branch_pc_pending_internal(h),\n\t\t\t\t\tincremented_pc_internal(h), boot_pc, pc_update_enable(h), served_ie_except_condition(h), served_ls_except_condition(h),\n\t\t\t\t\tserved_dsp_except_condition(h), served_except_condition(h),\n served_mret_condition(h));\n end if;\n end if; --rst , clk\n end process;\n\n\n end generate pc_update_logic;\n -- end of replicated logic -- \n\n\n\n--------------------------------------------------------------------- end of PC Managing Units ---\n-------------------------------------------------------------------------------------------------- \n\nend PC;\n--------------------------------------------------------------------------------------------------\n-- END of Program Counter architecture -----------------------------------------------------------\n--------------------------------------------------------------------------------------------------", "groundtruth": " mepc_incremented_pc : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\r\n mepc_interrupt_pc : out array_2D(THREAD_POOL_SIZE - 1 downto 0)(31 downto 0);\r\n irq_pending : out std_logic_vector(THREAD_POOL_SIZE - 1 downto 0);\r\n clk_i : in std_logic;\r\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Registerfile.vhd", "left_context": "----------------------------------------------------------------------------------------------------------------\n-- Stage ID - (Instruction decode and registerfile read) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 07-04-2020 --\n----------------------------------------------------------------------------------------------------------------\n-- Registerfiles of the incoming hart are read in this stage in parallel with the decoding --\n-- Two types of registerfiles can be generaated for XILINX FPGAs LUTAM based or FF based dpeneding on the --\n-- setting of the generic variaabble chosen --\n-- The scratchpad memory mapper also exists in this stage, which maps the address to the corresponding SPM --\n-- This pipeline stage always takes one cycle latency --\n----------------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.math_real.all;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n-- pipeline pinout --------------------\nentity REGISTERFILE is\n generic(\n THREAD_POOL_SIZE : integer;\n LUTRAM_RF : natural;\n accl_en : natural;\n SPM_NUM\t\t : natural; \n Addr_Width : natural;\n SPM_STRT_ADDR : std_logic_vector(31 downto 0);\n RF_SIZE : natural;\n RF_CEIL : natural;\n SPM_ADDR_WID : natural\n );\n port (\n -- clock, reset active low\n clk_i : in std_logic;\n rst_ni : in std_logic;\n\t-- Branch Control Signals\n\tharc_ID : in integer range THREAD_POOL_SIZE-1 downto 0;\n pc_ID : in std_logic_vector(31 downto 0); -- pc_ID is PC entering ID stage\n\tcore_busy_IE : in std_logic;\n\tcore_busy_LS : in std_logic;\n ls_parallel_exec : in std_logic;\n dsp_parallel_exec : in std_logic;\n dsp_to_jump : in std_logic;\n instr_rvalid_ID : in std_logic;\n\tinstr_word_ID_lat : in std_logic_vector(31 downto 0);\n\tLS_WB_EN : in std_logic;\n\tIE_WB_EN : in std_logic;\n\tMUL_WB_EN : in std_logic;\n\tIE_WB : in std_logic_vector(31 downto 0);\n", "right_context": " rs1_to_sc : out std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rs2_to_sc : out std_logic_vector(SPM_ADDR_WID-1 downto 0);\n rd_to_sc : out std_logic_vector(SPM_ADDR_WID-1 downto 0);\n data_addr_internal_IE : out std_logic_vector(31 downto 0);\n\tregfile : out array_3d(THREAD_POOL_SIZE-1 downto 0)(RF_SIZE-1 downto 0)(31 downto 0)\n );\nend entity; ------------------------------------------\n\n\n-- Klessydra T03x (4 stages) pipeline implementation -----------------------\narchitecture RF of REGISTERFILE is\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0;\n\n signal regfile_lutram_rs1 : array_2d((THREAD_POOL_SIZE*RF_SIZE)-1 downto 0)(31 downto 0);\n signal regfile_lutram_rs2 : array_2d((THREAD_POOL_SIZE*RF_SIZE)-1 downto 0)(31 downto 0);\n signal regfile_lutram_rd : array_2d((THREAD_POOL_SIZE*RF_SIZE)-1 downto 0)(31 downto 0);\n\n attribute ram_style : string;\n attribute ram_style of RS1_Data_IE : signal is \"reg\";\n attribute ram_style of RS2_Data_IE : signal is \"reg\";\n attribute ram_style of RD_Data_IE : signal is \"reg\";\n attribute ram_style of regfile_lutram_rs1 : signal is \"distributed\";\n attribute ram_style of regfile_lutram_rs2 : signal is \"distributed\";\n attribute ram_style of regfile_lutram_rd : signal is \"distributed\";\n\n signal ID_rs1_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n signal ID_rs2_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n signal ID_rd_to_sc : std_logic_vector(SPM_ADDR_WID-1 downto 0);\n\n -- instruction operands\n signal RS1_Addr_IE : std_logic_vector(4 downto 0); -- debugging signals\n signal RS2_Addr_IE : std_logic_vector(4 downto 0); -- debugging signals\n signal RD_Addr_IE : std_logic_vector(4 downto 0); -- debugging signals\n signal RD_EN : std_logic;\n signal WB_RD : std_logic_vector(31 downto 0);\n signal WB_EN : std_logic;\n signal harc_WB : harc_range;\n signal instr_word_WB : std_logic_vector(31 downto 0);\n\n function rs1 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(15+(RF_CEIL-1) downto 15)));\n end;\n\n function rs2 (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(20+(RF_CEIL-1) downto 20)));\n end;\n\n function rd (signal instr : in std_logic_vector(31 downto 0)) return integer is\n begin\n return to_integer(unsigned(instr(7+(RF_CEIL-1) downto 7)));\n end;\n\nbegin\n\n RF_FF : if LUTRAM_RF = 0 generate\n\n RF_ACCESS : process(clk_i, rst_ni, instr_word_ID_lat) -- synch single state process\n begin\n if rst_ni = '0' then\n for h in harc_range loop\n regfile(h)(0) <= (others => '0');\n end loop;\n elsif rising_edge(clk_i) then\n if core_busy_IE = '1' or core_busy_LS = '1' or ls_parallel_exec = '0' or dsp_parallel_exec = '0' then -- the instruction pipeline is halted\n elsif instr_rvalid_ID = '0' then -- wait for a valid instruction\n else -- process the incoming instruction \n\n data_addr_internal_IE <= std_logic_vector(signed(regfile(harc_ID)(rs1(instr_word_ID_lat))) + signed(S_immediate(instr_word_ID_lat)));\n\n ------------------------------------------------------------\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n -- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• --\n -- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n -- ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• --\n ------------------------------------------------------------\n\n ----- REGISTERFILE READ IS DONE HERE --------------------------------------------------------------------------------------------------------------\n RS1_Data_IE <= regfile(harc_ID)(rs1(instr_word_ID_lat));\n RS2_Data_IE <= regfile(harc_ID)(rs2(instr_word_ID_lat));\n if accl_en = 1 then\n if dsp_to_jump = '0' then\n RD_Data_IE <= regfile(harc_ID)(rd(instr_word_ID_lat)); -- only the DSP unit reads the accelerator\n else\n RD_Data_IE <= regfile(harc_ID)(0);\n end if;\n end if;\n -- pragma translate_off\n RD_Data_IE <= regfile(harc_ID)(rd(instr_word_ID_lat)); -- reading the 'rd' data here is only for debugging purposes if the acclerator is disabled\n RS1_Addr_IE <= std_logic_vector(to_unsigned(rs1(instr_word_ID_lat), 5)); -- debugging signals\n RS2_Addr_IE <= std_logic_vector(to_unsigned(rs2(instr_word_ID_lat), 5)); -- debugging signals\n RD_Addr_IE <= std_logic_vector(to_unsigned(rd(instr_word_ID_lat), 5)); -- debugging signals\n -- pragma translate_on\n ----------------------------------------------------------------------------------------------------------------------------------------------------\n end if; -- instr. conditions\n\n if WB_EN = '1' then\n regfile(harc_WB)(rd(instr_word_WB)) <= WB_RD;\n end if;\n end if; -- clk\n end process;\n\n end generate;\n\n RF_LUTRAM : if LUTRAM_RF = 1 generate\n\n RF_RD_EN : process(all) -- synch single state process\n begin\n RD_EN <= '0';\n if core_busy_IE = '1' or core_busy_LS = '1' or ls_parallel_exec = '0' or dsp_parallel_exec = '0' then -- the instruction pipeline is halted\n elsif instr_rvalid_ID = '0' then -- wait for a valid instruction\n else -- process the incoming instruction \n RD_EN <= '1';\n end if; -- instr. conditions\n end process;\n\n RS1_ACCESS : process(clk_i) -- synch single state process\n begin\n if rising_edge(clk_i) then\n if RD_EN = '1' then \n data_addr_internal_IE <= std_logic_vector(signed(regfile_lutram_rs1(32*harc_ID+rs1(instr_word_ID_lat))) + signed(S_immediate(instr_word_ID_lat)));\n if rs1(instr_word_ID_lat) /= 0 then\n RS1_Data_IE <= regfile_lutram_rs1(32*harc_ID+rs1(instr_word_ID_lat));\n else\n RS1_Data_IE <= (others => '0');\n end if;\n -- pragma translate_off\n RD_Data_IE <= regfile_lutram_rs1(32*harc_ID+rd(instr_word_ID_lat)); -- reading the 'rd' data here is only for debugging purposes when the acclerator is disabled\n RS1_Addr_IE <= std_logic_vector(to_unsigned(rs1(instr_word_ID_lat), 5)); -- debugging signals\n RS2_Addr_IE <= std_logic_vector(to_unsigned(rs2(instr_word_ID_lat), 5)); -- debugging signals\n RD_Addr_IE <= std_logic_vector(to_unsigned(rd(instr_word_ID_lat), 5)); -- debugging signals\n -- pragma translate_on\n end if; -- instr. conditions\n if WB_EN = '1' then\n regfile_lutram_rs1(32*harc_WB+rd(instr_word_WB)) <= WB_RD;\n end if;\n end if; -- clk\n end process;\n\n RS2_ACCESS : process(clk_i) -- synch single state process\n begin\n if rising_edge(clk_i) then\n if RD_EN = '1' then \n if rs2(instr_word_ID_lat) /= 0 then\n RS2_Data_IE <= regfile_lutram_rs2(32*harc_ID+rs2(instr_word_ID_lat));\n else\n RS2_Data_IE <= (others => '0');\n end if;\n end if; -- instr. conditions\n if WB_EN = '1' then\n regfile_lutram_rs2(32*harc_WB+rd(instr_word_WB)) <= WB_RD;\n end if;\n end if; -- clk\n end process;\n\n RD_LUTRAM : if accl_en = 1 generate\n RD_ACCESS : process(clk_i) -- synch single state process\n begin\n if rising_edge(clk_i) then\n if accl_en = 1 then\n if RD_EN = '1' then\n RD_Data_IE <= regfile_lutram_rd(32*harc_ID+rd(instr_word_ID_lat)); -- only the DSP unit reads the accelerator\n end if; -- instr. conditions\n end if;\n if WB_EN = '1' then\n regfile_lutram_rd(32*harc_WB+rd(instr_word_WB)) <= WB_RD;\n end if;\n end if; -- clk\n end process;\n\n end generate;\n end generate;\n-----------------------------------------------------------------------------------------------------\n-- Stage WB - (WRITEBACK)\n-----------------------------------------------------------------------------------------------------\n\n harc_WB <= harc_LS_WB when LS_WB_EN = '1' else harc_IE_WB;\n instr_word_WB <= instr_word_LS_WB when LS_WB_EN = '1' else instr_word_IE_WB when (IE_WB_EN = '1' or MUL_WB_EN = '1') else (others => '0');\n WB_EN <= '1' when (LS_WB_EN = '1' or IE_WB_EN = '1' or MUL_WB_EN = '1') else '0';\n WB_RD <= IE_WB when IE_WB_EN = '1' else LS_WB when LS_WB_EN = '1' else MUL_WB when MUL_WB_EN = '1' else (others => '0'); \n\n--------------------------------------------------------------------- end of WB Stage ----------------\n------------------------------------------------------------------------------------------------------\n\n\n------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā–ˆā–ˆā–ˆā–ˆā•”ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n-- ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā• ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā•ā• ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ --\n-- ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā• ā•šā•ā• --\n------------------------------------------------------------------------------------------ \n\n spm_mapper : if accl_en = 1 generate \n RF_FF : if LUTRAM_RF = 0 generate\n Spm_Addr_Mapping : process(all)\n begin\n ID_rs1_to_sc <= std_logic_vector(to_unsigned(SPM_NUM, SPM_ADDR_WID)); -- we assign SPM_NUM to rs1_to_sc as a default case which is out of range (0 to SPM_NUM-1)\n ID_rs2_to_sc <= std_logic_vector(to_unsigned(SPM_NUM, SPM_ADDR_WID)); -- we assign SPM_NUM to rs2_to_sc as a default case which is out of range (0 to SPM_NUM-1)\n ID_rd_to_sc <= std_logic_vector(to_unsigned(SPM_NUM, SPM_ADDR_WID)); -- we assign SPM_NUM to rd_to_sc as a default case which is out of range (0 to SPM_NUM-1)\n for i in 0 to SPM_NUM-1 loop -- Decode the address and assign and set the scratchpad number (0 to SPM_NUM-1) to the operand\n if regfile(harc_ID)(rs1(instr_word_ID_lat))(31 downto Addr_Width) >= std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i)) and\n regfile(harc_ID)(rs1(instr_word_ID_lat))(31 downto Addr_Width) < std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i+1)) then\n ID_rs1_to_sc <= std_logic_vector(to_unsigned(i, SPM_ADDR_WID));\n end if;\n if regfile(harc_ID)(rs2(instr_word_ID_lat))(31 downto Addr_Width) >= std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i)) and\n regfile(harc_ID)(rs2(instr_word_ID_lat))(31 downto Addr_Width) < std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i+1)) then\n ID_rs2_to_sc <= std_logic_vector(to_unsigned(i, SPM_ADDR_WID));\n end if;\n if regfile(harc_ID)(rd(instr_word_ID_lat))(31 downto Addr_Width) >= std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i)) and\n regfile(harc_ID)(rd(instr_word_ID_lat))(31 downto Addr_Width) < std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i+1)) then\n ID_rd_to_sc <= std_logic_vector(to_unsigned(i, SPM_ADDR_WID));\n end if;\n end loop;\n end process;\n end generate;\n \n RF_LUTRAM : if LUTRAM_RF = 1 generate\n Spm_Addr_Mapping : process(all)\n begin\n ID_rs1_to_sc <= std_logic_vector(to_unsigned(SPM_NUM, SPM_ADDR_WID)); -- we assign SPM_NUM to rs1_to_sc as a default case which is out of range (0 to SPM_NUM-1)\n ID_rs2_to_sc <= std_logic_vector(to_unsigned(SPM_NUM, SPM_ADDR_WID)); -- we assign SPM_NUM to rs2_to_sc as a default case which is out of range (0 to SPM_NUM-1)\n ID_rd_to_sc <= std_logic_vector(to_unsigned(SPM_NUM, SPM_ADDR_WID)); -- we assign SPM_NUM to rd_to_sc as a default case which is out of range (0 to SPM_NUM-1)\n for i in 0 to SPM_NUM-1 loop -- Decode the address and assign and set the scratchpad number (0 to SPM_NUM-1) to the operand\n if regfile_lutram_rs1(32*harc_ID+rs1(instr_word_ID_lat))(31 downto Addr_Width) >= std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i)) and\n regfile_lutram_rs1(32*harc_ID+rs1(instr_word_ID_lat))(31 downto Addr_Width) < std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i+1)) then\n ID_rs1_to_sc <= std_logic_vector(to_unsigned(i, SPM_ADDR_WID));\n end if;\n if regfile_lutram_rs2(32*harc_ID+rs2(instr_word_ID_lat))(31 downto Addr_Width) >= std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i)) and\n regfile_lutram_rs2(32*harc_ID+rs2(instr_word_ID_lat))(31 downto Addr_Width) < std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i+1)) then\n ID_rs2_to_sc <= std_logic_vector(to_unsigned(i, SPM_ADDR_WID));\n end if;\n if regfile_lutram_rd(32*harc_ID+rd(instr_word_ID_lat))(31 downto Addr_Width) >= std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i)) and\n regfile_lutram_rd(32*harc_ID+rd(instr_word_ID_lat))(31 downto Addr_Width) < std_logic_vector(unsigned(SPM_STRT_ADDR(31 downto Addr_Width)) + (i+1)) then\n ID_rd_to_sc <= std_logic_vector(to_unsigned(i, SPM_ADDR_WID));\n end if;\n end loop;\n end process;\n end generate;\n\n Spm_Addr_Mapping_Synch : process(clk_i, rst_ni)\n begin\n if rst_ni = '0' then\n elsif rising_edge(clk_i) then\n rs1_to_sc <= ID_rs1_to_sc;\n rs2_to_sc <= ID_rs2_to_sc;\n rd_to_sc <= ID_rd_to_sc;\n end if;\n end process;\n \n end generate;\n\n---------------------------------------------------------------------- end of ID stage -----------\n--------------------------------------------------------------------------------------------------\nend RF;\n--------------------------------------------------------------------------------------------------\n-- END of ID architecture ------------------------------------------------------------------------\n-----------", "groundtruth": "\tMUL_WB : in std_logic_vector(31 downto 0);\n\tLS_WB : in std_logic_vector(31 downto 0);\n\tinstr_word_LS_WB : in std_logic_vector(31 downto 0);\n\tinstr_word_IE_WB : in std_logic_vector(31 downto 0);\n\tharc_LS_WB : in integer range THREAD_POOL_SIZE-1 downto 0;\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Scratchpad_Memory.vhd", "left_context": "-----------------------------------------------------------------------------------------------------------------\n-- SPM -- (Scratchpad Memories) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 17-11-2019 --\n-----------------------------------------------------------------------------------------------------------------\n-- The SPMs are implemented as low latency single cycle read memories. The number of memory banks in this --\n-- entity is decided by many factors. The first being the SIMD size whcih decides the number of banks per -- \n-- SPM. The second being whether the hardware accelerator is replicated, whuch will replicate the SPM --\n-- for all the harts in the core. And the last is the number of SPMs configured by the parameter \"SPM_NUM\". --\n-- Each SPM bank has a read and write port which is 32-bits wide, and the mems are implemented in BRAMs --\n-----------------------------------------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n\n---------------------------------------------------------------------------------------------------\nentity Scratchpad_memory is\n generic(\n SPM_NUM : natural; \n", "right_context": " port(\n clk_i : in std_logic;\n sc_we : in array_2d(ACCL_NUM - 1 downto 0)(SIMD*SPM_NUM-1 downto 0);\n sc_addr_wr : in array_3d(ACCL_NUM - 1 downto 0)(SIMD*SPM_NUM-1 downto 0)(Addr_Width-(SIMD_BITS+3) downto 0);\n sc_addr_rd : in array_3d(ACCL_NUM - 1 downto 0)(SIMD*SPM_NUM-1 downto 0)(Addr_Width-(SIMD_BITS+3) downto 0);\n sc_data_wr : in array_3d(ACCL_NUM - 1 downto 0)(SIMD*SPM_NUM-1 downto 0)(Data_Width-1 downto 0);\n sc_data_rd : out array_3d(ACCL_NUM - 1 downto 0)(SIMD*SPM_NUM-1 downto 0)(Data_Width-1 downto 0)\n );\nend Scratchpad_memory;\n\n---------------------------------------------------------------------------------------------------\narchitecture SC of Scratchpad_memory is\n\nsubtype accl_range is integer range ACCL_NUM - 1 downto 0; \n\nsignal mem : array_3d(ACCL_NUM*SIMD*SPM_NUM-1 downto 0)(2**(Addr_Width-(SIMD_BITS+2))-1 downto 0)(Data_Width-1 downto 0);\nsignal h : std_logic_vector(ACCL_NUM*SIMD*SPM_NUM downto 0);\nattribute ram_style : string;\nattribute ram_style of mem : signal is \"block\";\n\nbegin\n\n --------- replicate logic three times --------------------------------\n spm_replicas : for g in accl_range generate \n spm_banks : for h in 0 to SIMD*SPM_NUM -1 generate \n \n write_logic: process(clk_i) -- \n begin\n if (clk_i'event and clk_i='1') then\n sc_data_rd(g)(h) <= mem(g*SIMD*SPM_NUM + h)(to_integer(unsigned(sc_addr_rd(g)(h))));\n if sc_we(g)(h) = '1' then --write mode\n mem(g*SIMD*SPM_NUM + h)(to_integer(unsigned(sc_addr_wr(g)(h)))) <= sc_data_wr(g)(h);\n end if; -- we\n end if; -- clk\n end process;\n\n end generate spm_banks;\n end generate spm_replicas;\n -- end of replicated logic --------------------------------------------\n\n--------------------------------------------------------------------- end of SPM Logic -----------\n-------------------------------------------------------------------------------------------------- \n\nend SC;\n--------------------------------------------------------------------------------------------------\n-- END of Scratchpad Memory architecture ---------------------------------------------------------\n--------------------------------------------------------------------------------------------------\n", "groundtruth": " Addr_Width : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/RTL-Scratchpad_Memory_Interface.vhd", "left_context": "-----------------------------------------------------------------------------------------------------------------\n-- SPI -- (Scratchpad Memory Interface) --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 02-04-2019 --\n-----------------------------------------------------------------------------------------------------------------\n-- The SPI connects the SPM to the LSU and DSP units. The LSU reads and wirtes one word (32-bits) at a time --\n-- and a bank interleaver switches between the internal banks of the SPM. The DSP reads and writes one SPM -- \n-- line which is \"32*SIMD\" bits wide. Hence there is no need for the bank interleaver. However, the DSP --\n-- can perform misaligned reads and writes. So it needs read and write data rotators to allign the source --\n-- operands to the appropriate functional units, and memory banks. The SPI provides 2 rd and 1 wr port to --\n-- the DSP with a two cycle read latency (one for reading the banks, the other is for rotating) --\n-----------------------------------------------------------------------------------------------------------------\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n--use work.klessydra_parameters.all;\n\n-- SCI pinout --------------------\nentity Scratchpad_memory_interface is\n generic(\n accl_en : natural;\n SPM_NUM\t\t : natural; \n Addr_Width : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n SIMD_BITS : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n port (\n clk_i, rst_ni : in std_logic;\n data_rvalid_i : in std_logic;\n state_LS : in fsm_LS_states;\n sc_word_count_wire : in integer;\n spm_bcast : in std_logic;\n harc_LS_wire : in integer range ACCL_NUM-1 downto 0;\n dsp_we_word : in array_2d(ACCL_NUM-1 downto 0)(SIMD-1 downto 0);\n ls_sc_data_write_wire : in std_logic_vector(Data_Width-1 downto 0);\n dsp_sc_data_write_wire : in array_2d(ACCL_NUM-1 downto 0)(SIMD_Width-1 downto 0);\n ls_sc_read_addr : in std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n ls_sc_write_addr : in std_logic_vector(Addr_Width-(SIMD_BITS+3) downto 0);\n dsp_sc_write_addr : in array_2d(ACCL_NUM-1 downto 0)(Addr_Width-1 downto 0);\n ls_sci_req : in std_logic_vector(SPM_NUM-1 downto 0);\n ls_sci_we : in std_logic_vector(SPM_NUM-1 downto 0);\n dsp_sci_req : in array_2d(ACCL_NUM-1 downto 0)(SPM_NUM-1 downto 0);\n dsp_sci_we : in array_2d(ACCL_NUM-1 downto 0)(SPM_NUM-1 downto 0);\n kmemld_inflight : in std_logic_vector(SPM_NUM-1 downto 0);\n kmemstr_inflight : in std_logic_vector(SPM_NUM-1 downto 0);\n dsp_to_sc : in array_3d(ACCL_NUM-1 downto 0)(SPM_NUM-1 downto 0)(1 downto 0);\n dsp_sc_read_addr : in array_3d(ACCL_NUM-1 downto 0)(1 downto 0)(Addr_Width-1 downto 0);\n dsp_sc_data_read : out array_3d(ACCL_NUM-1 downto 0)(1 downto 0)(SIMD_Width-1 downto 0);\n ls_sc_data_read_wire : out std_logic_vector(Data_Width-1 downto 0);\n ls_sci_wr_gnt : out std_logic;\n dsp_sci_wr_gnt : out std_logic_vector(ACCL_NUM-1 downto 0);\n ls_data_gnt_i : out std_logic_vector(SPM_NUM-1 downto 0);\n dsp_data_gnt_i : out std_logic_vector(ACCL_NUM-1 downto 0)\n\t);\nend entity; ------------------------------------------\n\n\narchitecture SCI of Scratchpad_memory_interface is\n\nsubtype accl_range is integer range ACCL_NUM - 1 downto 0; \n\nsignal dsp_sc_data_write_int_wire : array_2d(accl_range)(SIMD_Width-1 downto 0);\nsignal ls_sc_data_read_int_wire : array_2d(accl_range)(Data_Width-1 downto 0);\nsignal ls_data_gnt_internal : array_2d(accl_range)(SPM_NUM-1 downto 0);\nsignal rd_offset : array_3d(accl_range)(1 downto 0)(SIMD-1 downto 0);\nsignal wr_offset : array_2d(accl_range)(SIMD-1 downto 0);\nsignal dsp_sc_data_read_int_wire : array_3d(accl_range)(1 downto 0)(SIMD_Width-1 downto 0);\nsignal dsp_sc_read_addr_lat : array_3d(accl_range)(1 downto 0)(SIMD_BITS+1 downto 0); -- Only need the lower part to check for the word access\nsignal dsp_sci_req_lat : array_2d(accl_range)(SPM_NUM-1 downto 0);\nsignal dsp_to_sc_lat : array_3d(accl_range)(SPM_NUM-1 downto 0)(1 downto 0);\nsignal dsp_sc_data_read_wire : array_3d(accl_range)(1 downto 0)(SIMD_Width-1 downto 0);\nsignal ls_sc_data_read_replicated : array_2d(accl_range)(Data_Width-1 downto 0);\nsignal ls_sc_data_read_wire_replicated : array_2d(accl_range)(Data_Width-1 downto 0);\nsignal dsp_sci_wr_gnt_lat : std_logic_vector(accl_range);\nsignal ls_sci_wr_gnt_replicated : std_logic_vector(accl_range);\nsignal ls_sci_wr_gnt_lat_replicated : std_logic_vector(accl_range);\nsignal halt_dsp : std_logic_vector(accl_range);\nsignal block_dsp_rd : std_logic_vector(accl_range);\nsignal sc_word_count : array_2d_int(accl_range);\nsignal sc_we : array_2d(accl_range)(SIMD*SPM_NUM-1 downto 0);\nsignal sc_addr_wr : array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Addr_Width-(SIMD_BITS+3) downto 0);\nsignal sc_addr_rd : array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Addr_Width-(SIMD_BITS+3) downto 0);\nsignal sc_data_wr : array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Data_Width-1 downto 0);\nsignal sc_data_rd : array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Data_Width-1 downto 0);\n\ncomponent Scratchpad_memory\n generic(\n SPM_NUM : natural; \n Addr_Width : natural;\n SIMD : natural;\n --------------------------------\n ACCL_NUM : natural;\n SIMD_BITS : natural;\n Data_Width : natural\n );\n port(\n clk_i : in std_logic;\n sc_we : in array_2d(accl_range)(SIMD*SPM_NUM-1 downto 0);\n sc_addr_wr : in array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Addr_Width-(SIMD_BITS+3) downto 0);\n sc_addr_rd : in array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Addr_Width-(SIMD_BITS+3) downto 0);\n sc_data_wr : in array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Data_Width-1 downto 0);\n sc_data_rd : out array_3d(accl_range)(SIMD*SPM_NUM-1 downto 0)(Data_Width-1 downto 0)\n );\nend component;\n--------------------------------------------------------------------------------------------------\n-------------------------------- SCI BEGIN -------------------------------------------------------\nbegin\n\n\n SC : Scratchpad_memory\n generic map(\n SPM_NUM\t\t => SPM_NUM, \n Addr_Width => Addr_Width,\n SIMD => SIMD,\n --------------------------------\n ACCL_NUM => ACCL_NUM,\n SIMD_BITS => SIMD_BITS,\n Data_Width => Data_Width\n )\n port map(\n sc_we => sc_we,\n clk_i => clk_i,\n sc_addr_rd => sc_addr_rd,\n sc_addr_wr => sc_addr_wr,\n sc_data_wr => sc_data_wr,\n sc_data_rd => sc_data_rd\n );\n\n\n process(all)\n begin\n for h in accl_range loop\n for i in 0 to SPM_NUM-1 loop\n ls_data_gnt_i(i) <= ls_data_gnt_internal(h)(0) or ls_data_gnt_internal(h)(i);\n end loop;\n end loop;\n end process;\n\n SPM_replicated : for h in accl_range generate\n \n SCI_Exec_Unit : process(clk_i, rst_ni) -- single cycle unit, fully synchronous \n begin\n if rst_ni = '0' then\n dsp_sc_read_addr_lat(h) <= (others => (others => '0'));\n dsp_to_sc_lat(h) <= (others => (others => '0'));\n dsp_sci_req_lat(h) <= (others => '0');\n ls_data_gnt_internal(h) <= (others => '0');\n halt_dsp(h) <= '0';\n sc_word_count(h) <= 0;\n elsif rising_edge(clk_i) then\n halt_dsp(h) <= '0';\n dsp_sci_wr_gnt_lat(h) <= dsp_sci_wr_gnt(h);\n ls_sci_wr_gnt_lat_replicated(h) <= ls_sci_wr_gnt_replicated(h);\n dsp_sci_req_lat(h) <= dsp_sci_req(h);\n dsp_to_sc_lat(h) <= dsp_to_sc(h);\n if harc_LS_wire = h or spm_bcast = '1' then\n sc_word_count(h) <= sc_word_count_wire;\n end if;\n if unsigned(ls_data_gnt_internal(h)) /= 0 then\n ls_sc_data_read_replicated(h) <= ls_sc_data_read_wire_replicated(h);\n end if;\n if (dsp_sci_wr_gnt(h) = '0' and dsp_sci_we(h) /= (0 to SPM_NUM-1 => '0')) then\n halt_dsp(h) <= '1';\n end if;\n if halt_dsp(h) = '0' then\n dsp_sc_data_read(h) <= dsp_sc_data_read_wire(h);\n end if;\n\n for i in 0 to SPM_NUM-1 loop\n if ls_sci_req(i) = '1' then -- AAA most probably useless\n ls_data_gnt_internal(h)(i) <= '1';\n elsif ls_sci_req(i) = '0' then\n ls_data_gnt_internal(h)(i) <= '0';\n end if;\n if dsp_sci_req(h)(i) = '1' then \n for k in 0 to 1 loop\n dsp_sc_read_addr_lat(h)(k) <= dsp_sc_read_addr(h)(k)(SIMD_BITS+1 downto 0);\n end loop;\n end if;\n end loop;\n end if;\n end process;\n\n ls_sc_data_read_wire <= ls_sc_data_read_wire_replicated(harc_LS_wire);\n ls_sci_wr_gnt <= ls_sci_wr_gnt_replicated(harc_LS_wire);\n\n SCI_Exec_Unit_comb : process(all)\n begin\n dsp_data_gnt_i(h) <= '0';\n block_dsp_rd(h) <= '0';\n for l in 0 to (SIMD*SPM_NUM)-1 loop\n sc_we(h)(l) <= '0';\n sc_addr_rd(h)(l) <= (others => '0');\n", "right_context": " dsp_sci_wr_gnt(h) <= dsp_sci_wr_gnt_lat(h);\n ls_sc_data_read_wire_replicated(h) <= ls_sc_data_read_replicated(h);\n dsp_sc_data_write_int_wire(h) <= (others => '0');\n dsp_sc_data_read_wire(h) <= dsp_sc_data_read(h);\n for i in 0 to SPM_NUM-1 loop\t-- Loop through scratchpads A,B,C,D\n\n if data_rvalid_i = '1' then -- LS write port\n if ls_sci_req(i) = '1' and ls_sci_we(i) = '1' and ls_sci_wr_gnt = '1' then\n if harc_LS_wire = h or spm_bcast = '1' then\n sc_we(h)((SIMD)*i + sc_word_count(h)) <= '1';\n sc_data_wr(h)(sc_word_count(h) + (SIMD)*i) <= ls_sc_data_write_wire(31 downto 0);\n sc_addr_wr(h)(sc_word_count(h) + (SIMD)*i) <= ls_sc_write_addr;\n end if;\n end if; \n end if;\n\n if ls_data_gnt_internal(h)(i) = '1' then\n if harc_LS_wire = h then\n ls_sc_data_read_wire_replicated(h) <= sc_data_rd(h)((SIMD)*i + sc_word_count(h)); -- sc_word_count because data being read is delayed one cycle after the request\n end if;\n end if;\n\n if ls_sci_req(i) = '1' then -- LS read port\n if harc_LS_wire = h then\n sc_addr_rd(h)(sc_word_count_wire + (SIMD)*i) <= ls_sc_read_addr;\n end if;\n end if;\n\n if dsp_sci_we(h)(i) = '1' and dsp_sci_wr_gnt(h) = '1' then -- DSP write port;\n for j in 0 to SIMD-1 loop -- Loop through the sub-scratchpad banks\n sc_we(h)((SIMD)*i+j) <= dsp_we_word(h)(j);\n sc_addr_wr(h)((SIMD)*i+j) <= std_logic_vector(unsigned(dsp_sc_write_addr(h)(Addr_Width-1 downto SIMD_BITS+2)) + wr_offset(h)(j));\n sc_data_wr(h)((SIMD)*i+j) <= dsp_sc_data_write_int_wire(h)(31+32*j downto 32*j);\n end loop;\n end if; \n\n if dsp_sci_req(h)(i) = '1' and dsp_to_sc(h)(i)(0) = '1' and dsp_data_gnt_i(h) = '1' then -- DSP read port 1\n for j in 0 to SIMD-1 loop -- Loop through the sub-scratchpad banks\n sc_addr_rd(h)((SIMD)*i+j) <= std_logic_vector(unsigned(dsp_sc_read_addr(h)(0)(Addr_Width-1 downto SIMD_BITS+2)) + rd_offset(h)(0)(j));\n end loop;\n end if;\n for j in 0 to SIMD-1 loop -- Loop through the sub-scratchpad banks\n if dsp_sci_req_lat(h)(i) = '1' and dsp_to_sc_lat(h)(i)(0) = '1' then -- DSP read port 1\n dsp_sc_data_read_int_wire(h)(0)(31+32*j downto 32*j) <= sc_data_rd(h)((SIMD)*i+j);\n end if;\n end loop;\n\t\t\n if dsp_sci_req(h)(i) = '1' and dsp_to_sc(h)(i)(1) = '1' and dsp_data_gnt_i(h) = '1' then -- DSP read port 2\n for j in 0 to SIMD-1 loop -- Loop through the sub-scratchpads\n sc_addr_rd(h)((SIMD)*i+j) <= std_logic_vector(unsigned(dsp_sc_read_addr(h)(1)(Addr_Width-1 downto SIMD_BITS+2)) + rd_offset(h)(1)(j));\n end loop;\n end if;\n for j in 0 to SIMD-1 loop -- Loop through the sub-scratchpads\n if dsp_sci_req_lat(h)(i) = '1' and dsp_to_sc_lat(h)(i)(1) = '1' then -- DSP read port 2\n dsp_sc_data_read_int_wire(h)(1)(31+32*j downto 32*j) <= sc_data_rd(h)((SIMD)*i+j);\n end if;\n end loop;\n\n if (kmemld_inflight(i) = '1' or kmemstr_inflight(i) = '1') and dsp_sci_req(h)(i) = '1' then\n block_dsp_rd(h) <= '1';\n end if;\n\n -- Allow a DSP read only if the SPM(i) being loaded belongs to another thread and the instruction is not a broadcast load (data hazard)\n if kmemld_inflight(i) = '1' and dsp_sci_req(h)(i) = '1' and h /= harc_LS_wire and spm_bcast = '0' then\n dsp_data_gnt_i(h) <= '1';\n -- Allow a dsp read only when it is not currently being read by a kmemstr becuase we only have one read port (structural hazard)\n elsif kmemstr_inflight(i) = '1' and dsp_sci_req(h)(i) = '1' and h /= harc_LS_wire then\n dsp_data_gnt_i(h) <= '1';\n -- Allow a DSP read if there are no current LSU accesses to SPM(i)\n elsif kmemld_inflight(i) = '0' and kmemstr_inflight(i) = '0' and dsp_sci_req(h)(i) = '1' and block_dsp_rd(h) = '0' then\n dsp_data_gnt_i(h) <= '1';\n end if;\n\n if dsp_sci_we(h) = (0 to SPM_NUM-1 => '0') then\n dsp_sci_wr_gnt(h) <= '0';\n -- Allow the DSP to write only if the kmemld is filling the SPM(i) of another thread\n elsif kmemld_inflight(i) = '1' and dsp_sci_we(h)(i) = '1' and h /= harc_LS_wire and spm_bcast = '0' then\n dsp_sci_wr_gnt(h) <= '1';\n -- Allow the DSP to write only when the kmemstr is reading SPM(i) of another thread\n elsif kmemstr_inflight(i) = '1' and dsp_sci_we(h)(i) = '1' and h /= harc_LS_wire then\n dsp_sci_wr_gnt(h) <= '1';\n -- Allow the DSP to write if there are no current LSU accesses to SPM(i)\n elsif kmemld_inflight(i) = '0' and kmemstr_inflight(i) = '0' and dsp_sci_we(h)(i) = '1' then\n dsp_sci_wr_gnt(h) <= '1';\n end if;\n\n if kmemld_inflight(i) = '1' and dsp_sci_we(h)(i) = '0' then -- One LSU write enable request will put the ls_sci_wr_gnt to '1' if there are no ongoing DSP writes to the same scratchpad\n ls_sci_wr_gnt_replicated(h) <= '1';\n elsif kmemld_inflight(i) = '1' and dsp_sci_we(h)(i) = '1' and (h /= harc_LS_wire) and spm_bcast = '0' then\n ls_sci_wr_gnt_replicated(h) <= '1';\n --elsif unsigned(kmemld_inflight) = 0 then -- All the ls_sci_we must be zero in-order to switch the ls_sci_wr_gnt back to '0'\n elsif kmemld_inflight = (SPM_NUM-1 downto 0 => '0') then\n ls_sci_wr_gnt_replicated(h) <= '0';\n end if;\n end loop;\n\n -----------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā• --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā•šā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā•ā• --\n------------------------------------------------------------------------------------------------ \n\n for i in 0 to SIMD-1 loop\n --if (to_integer(unsigned(dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0))) = 4*i) and (i /= 0) then\n if (dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0) = std_logic_vector(to_unsigned(4*i, SIMD_BITS+2))) and (i /= 0) then\n wr_offset(h)(i-1 downto 0) <= (others => '1');\n end if;\n end loop;\n for i in 0 to SIMD-1 loop\t\t \n --if (to_integer(unsigned(dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0))) = 4*i) then\n if dsp_sc_write_addr(h)(SIMD_BITS+1 downto 0) = std_logic_vector(to_unsigned(4*i, SIMD_BITS+2)) then\n for j in 0 to SIMD-1 loop\n if j <= (SIMD-1)-i then\n dsp_sc_data_write_int_wire(h)(31+32*(j+i) downto 32*(j+i)) <= dsp_sc_data_write_wire(h)(31+32*j downto 32*j);\n elsif j > (SIMD-1)-i then\n dsp_sc_data_write_int_wire(h)(31+32*(j-(SIMD-1)+(i-1)) downto 32*(j-(SIMD-1)+(i-1))) <= dsp_sc_data_write_wire(h)(31+32*j downto 32*j);\n end if;\n end loop;\n end if;\n end loop;\n --for i in 0 to 4*SIMD-1 loop \n -- for j in 0 to 4*SIMD-1 loop\n -- if j <= (4*SIMD-1)-i then\n -- dsp_sc_data_write_int_wire(h)(7+8*(j+i) downto 8*(j+i)) <= dsp_sc_data_write_wire(h)(7+8*j downto 8*j);\n -- elsif j > (4*SIMD-1)-i then\n -- dsp_sc_data_write_int_wire(h)(7+8*(j-(SIMD-1)+(i-1)) downto 8*(j-(SIMD-1)+(i-1))) <= dsp_sc_data_write_wire(h)(7+8*j downto 8*j);\n -- end if;\n -- end loop;\n --end loop;\n\t \n for k in 0 to 1 loop -- index for the rs1 and rs2 read addresses\n for i in 0 to SIMD-1 loop -- index points to the \n --if (to_integer(unsigned(dsp_sc_read_addr(h)(k)(SIMD_BITS+1 downto 0))) = 4*i) and (i /= 0) then -- 4*i instead of i is because the address is word aligned and not byte aligned\n if (dsp_sc_read_addr(h)(k)(SIMD_BITS+1 downto 0) = std_logic_vector(to_unsigned(4*i, SIMD_BITS+2))) and (i /= 0) then\n rd_offset(h)(k)(i-1 downto 0) <= (others => '1'); -- sets the bank offset withing the scratchpad that will be used for the correct bank access\n end if;\n end loop;\n for i in 0 to SIMD-1 loop\n --if (to_integer(unsigned(dsp_sc_read_addr_lat(h)(k))) = 4*i) then\n if dsp_sc_read_addr_lat(h)(k) = std_logic_vector(to_unsigned(4*i, SIMD_BITS+2)) then\n for j in 0 to SIMD-1 loop\n if j >= i then\n dsp_sc_data_read_wire(h)(k)(31+32*(j-i) downto 32*(j-i)) <= dsp_sc_data_read_int_wire(h)(k)(31+32*j downto 32*j);\n elsif j < i then\n dsp_sc_data_read_wire(h)(k)(31+32*((SIMD-1)-i+(j+1)) downto 32*((SIMD-1)-i+(j+1))) <= dsp_sc_data_read_int_wire(h)(k)(31+32*j downto 32*j);\n end if;\n end loop;\n end if;\n end loop;\n --for i in 0 to 4*SIMD-1 loop\n -- for j in 0 to 4*SIMD-1 loop\n -- if j >= i then\n -- dsp_sc_data_read_wire(h)(k)(7+8*(j-i) downto 8*(j-i)) <= dsp_sc_data_read_int_wire(h)(k)(7+8*j downto 8*j);\n -- elsif j < i then\n -- dsp_sc_data_read_wire(h)(k)(7+8*((SIMD-1)-i+(j+1)) downto 8*((SIMD-1)-i+(j+1))) <= dsp_sc_data_read_int_wire(h)(k)(7+8*j downto 8*j);\n -- end if;\n -- end loop;\n --end loop;\n end loop;\n end process;\n\n end generate SPM_replicated;\n\n--------------------------------------------------------------------- end of SCI Logic -----------\n-------------------------------------------------------------------------------------------------- \n\nend SCI;\n--------------------------------------------------------------------------------------------------\n-- END of SCI architecture -----------------------------------------------------------------------\n--------------------------------------------------------------------------------------------------", "groundtruth": " sc_addr_wr(h)(l) <= (others => '0');\n sc_data_wr(h)(l) <= (others => '0');\n end loop;\n rd_offset(h) <= (others => (others => '0'));\n", "crossfile_context": ""} {"task_id": "T13x", "path": "T13x/klessydra-t1-3th/STR-Klessydra_top.vhd", "left_context": "---------------------------------------------------------------------------------------------------------------------\n-- --\n-- Author(s): Abdallah Cheikh abdallah.cheikh@uniroma1.it (abdallah93.as@gmail.com) --\n-- --\n-- Date Modified: 07-04-2020 --\n---------------------------------------------------------------------------------------------------------------------\n---------------------------------------------------------------------------------------------------------------------\n-- Klessydra-T13 core v.5.0: --\n-- RISCY core pinout, RISC-V core, RV32IMA support plus the RISC-VEmbedded E-extension and custom --\n-- K-extension. T13 has 4 pipeline stages F/RD/E/W, in order execution. With the execute stage being superscalar --\n-- Supports interleaved multithreading (IMT), with maximum configurable thread pool size = 16 threads. --\n-- Pure RISCV exception and interrupt handling. Only thread 0 can be interrupted extenranlly. inter-thread ints --\n-- are allowed, and used for thread synchronization. Pulpino irq/exception table fully supported by SW --\n-- runtime system. --\n-- Contributors to the Klessydra Project: Abdallah Cheikh, Francesco Vigli, Luigi Blasi, --\n-- Stefano Sordillo, Gianmarco Cerutti, Simone Ponzio, Ivan Matraxia, Mauro Olivieri. --\n-- last update: 17-11-2019 --\n---------------------------------------------------------------------------------------------------------------------\n\n--package riscv_kless is new work.riscv_klessydra\n-- generic map (RV32E => 0);\n\n-- ieee packages ------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_misc.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\nuse std.textio.all;\n\n-- local packages ------------\nuse work.riscv_klessydra.all;\n-- use work.riscv_kless.all;\n\n-------------------------------------------------------------------------------------------------------------\n-- ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā•ā•ā•šā–ˆā–ˆā•— ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•— ā•šā•ā•ā–ˆā–ˆā•”ā•ā•ā•ā–ˆā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā•šā–ˆā–ˆā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n-- ā–ˆā–ˆā•”ā•ā–ˆā–ˆā•— ā–ˆā–ˆā•‘ ā–ˆā–ˆā•”ā•ā•ā• ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ā•šā•ā•ā•ā•ā–ˆā–ˆā•‘ ā•šā–ˆā–ˆā•”ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•—ā–ˆā–ˆā•”ā•ā•ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā•ā• ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā•šā•ā•ā•ā–ˆā–ˆā•— --\n-- ā–ˆā–ˆā•‘ ā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•—ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā•ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ ā–ˆā–ˆā•‘ā–ˆā–ˆā–ˆā–ˆā–ˆā–ˆā•”ā• --\n-- ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā•ā•šā•ā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•ā•ā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā• ā•šā•ā• ā•šā•ā• ā•šā•ā•ā•šā•ā•ā•ā•ā•ā• --\n-------------------------------------------------------------------------------------------------------------\n\n-- core entity declaration --\nentity klessydra_t1_3th_core is\n generic (\n THREAD_POOL_SIZE : integer := 3; -- Changing the TPS to less than \"number of pipeline stages-1\" is not allowed. And making it bigger than \"pipeline stages-1\" is okay but not recommended\n LUTRAM_RF : natural := 1; -- Changes the regfile from flip-flop type into BRAM type\n RV32E : natural := 0; -- Regfile size, Can be set to 32 for RV32E being 0 else 16 for RV32E being set to 1\n RV32M : natural := 1; -- Enable the M-extension of the risc-v instruction set\n superscalar_exec_en : natural := 1; -- Enables superscalar execution when set to 1, else the stall of the pipeline will depend on tha latency of the instruction\n accl_en : natural := 1; -- Enable the generation of the special purpose accelerator\n replicate_accl_en : natural := 0; -- Set to 1 to replicate the accelerator for every thread\n multithreaded_accl_en : natural := 0; -- Set to 1 to let the replicated accelerator share the functional units (note: replicate_accl_en must be set to '1')\n SPM_NUM : natural := 4; -- The number of scratchpads available \"Minimum allowed is two\"\n Addr_Width : natural := 14; -- This address is for scratchpads. Setting this will make the size of the spm to be: \"2^Addr_Width -1\"\n SPM_STRT_ADDR : std_logic_vector(31 downto 0) := x\"1000_0000\"; -- This is starting address of the spms, it shouldn't overlap any sections in the memory map\n SIMD : natural := 1; -- Changing the SIMD, would change the number of the functional units in the dsp, and the number of banks in the spms (can be power of 2 only e.g. 1,2,4,8)\n MCYCLE_EN : natural := 0; -- Can be set to 1 or 0 only. Setting to zero will disable MCYCLE and MCYCLEH\n MINSTRET_EN : natural := 0; -- Can be set to 1 or 0 only. Setting to zero will disable MINSTRET and MINSTRETH\n MHPMCOUNTER_EN : natural := 0; -- Can be set to 1 or 0 only. Setting to zero will disable all performance counters except \"MCYCLE/H\" and \"MINSTRET/H\"\n count_all : natural := 1; -- Perfomance counters count for all the harts instead of there own hart\n debug_en : natural := 0; -- Generates the debug unit\n tracer_en : natural := 0; -- Enables the generation of the instruction tracer disable in extremely long simulations in order to save storage space\n ----------------------------------------------------------------------------------------\n N_EXT_PERF_COUNTERS : integer := 0; -- ignored in Klessydra\n INSTR_RDATA_WIDTH : integer := 32; -- ignored in Klessydra\n N_HWLP : integer := 2; -- ignored in Klessydra\n N_HWLP_BITS : integer := 4 -- ignored in Klessydra\n );\n port (\n -- clock, reset active low, test enable\n clk_i : in std_logic;\n clock_en_i : in std_logic;\n rst_ni : in std_logic;\n test_en_i : in std_logic;\n -- initialization signals \n boot_addr_i : in std_logic_vector(31 downto 0);\n core_id_i : in std_logic_vector(3 downto 0);\n cluster_id_i : in std_logic_vector(5 downto 0);\n -- program memory interface\n instr_req_o : out std_logic;\n instr_gnt_i : in std_logic;\n instr_rvalid_i : in std_logic;\n instr_addr_o : out std_logic_vector(31 downto 0);\n instr_rdata_i : in std_logic_vector(31 downto 0);\n -- data memory interface\n data_req_o : out std_logic;\n data_gnt_i : in std_logic;\n data_rvalid_i : in std_logic;\n data_we_o : out std_logic;\n data_be_o : out std_logic_vector(3 downto 0);\n data_addr_o : out std_logic_vector(31 downto 0);\n data_wdata_o : out std_logic_vector(31 downto 0);\n data_rdata_i : in std_logic_vector(31 downto 0);\n data_err_i : in std_logic;\n -- interrupt request interface\n irq_i : in std_logic;\n irq_id_i : in std_logic_vector(4 downto 0);\n irq_ack_o : out std_logic;\n irq_id_o : out std_logic_vector(4 downto 0);\n irq_sec_i : in std_logic; -- unused in Pulpino\n sec_lvl_o : out std_logic; -- unused in Pulpino\n -- debug interface\n debug_req_i : in std_logic;\n debug_gnt_o : out std_logic;\n debug_rvalid_o : out std_logic;\n debug_addr_i : in std_logic_vector(14 downto 0);\n debug_we_i : in std_logic;\n debug_wdata_i : in std_logic_vector(31 downto 0);\n debug_rdata_o : out std_logic_vector(31 downto 0);\n debug_halted_o : out std_logic;\n debug_halt_i : in std_logic;\n debug_resume_i : in std_logic;\n -- miscellanous control signals\n fetch_enable_i : in std_logic;\n core_busy_o : out std_logic;\n ext_perf_counters_i : in std_logic_vector(N_EXT_PERF_COUNTERS to 1)\n );\n\nend entity klessydra_t1_3th_core;\n\narchitecture Klessydra_T1 of klessydra_t1_3th_core is\n\n constant RF_SIZE : natural := 32-16*RV32E;\n constant RF_CEIL : natural := integer(ceil(log2(real(RF_SIZE))));\n constant TPS_CEIL : natural := integer(ceil(log2(real(THREAD_POOL_SIZE))));\n constant TPS_BUF_CEIL : natural := integer(ceil(log2(real(THREAD_POOL_SIZE-1))));\n constant SPM_ADDR_WID : natural := integer(ceil(log2(real(SPM_NUM+1)))); \n constant SIMD_BITS : natural := integer(ceil(log2(real(SIMD))));\n constant Data_Width : natural := 32;\n constant SIMD_Width : natural := SIMD*Data_Width;\n\n subtype harc_range is integer range THREAD_POOL_SIZE - 1 downto 0; -- will be used replicated units in the core\n\n constant ACCL_NUM : natural := (THREAD_POOL_SIZE - (THREAD_POOL_SIZE-1)*(1-replicate_accl_en));\n constant FU_NUM : natural := (ACCL_NUM - (ACCL_NUM-1)*(multithreaded_accl_en));\n\n subtype accl_range is integer range ACCL_NUM - 1 downto 0; -- will be used replicated accelerators in the core \n subtype fu_range is integer range FU_NUM - 1 downto 0; -- will be used replicated accelerators in the core \n\n signal reset_state : std_logic;\n\n -- Control Status Register (CSR) signals\n signal MVSIZE : array_2d(harc_range)(Addr_Width downto 0);\n signal MVTYPE : array_2d(harc_range)(3 downto 0);\n signal MPSCLFAC : array_2d(harc_range)(4 downto 0);\n signal MSTATUS : array_2d(harc_range)(1 downto 0);\n signal MEPC : array_2d(harc_range)(31 downto 0);\n signal MCAUSE : array_2d(harc_range)(31 downto 0);\n signal MIP : array_2d(harc_range)(31 downto 0);\n signal MTVEC : array_2d(harc_range)(31 downto 0);\n signal PCER : array_2d(harc_range)(31 downto 0);\n\n signal irq_pending : std_logic_vector(harc_range);\n signal WFI_Instr : std_logic;\n signal except_pc_vec_o : std_logic_vector(31 downto 0);\n\n -- Memory fault signals\n signal load_err, store_err : std_logic;\n\n -- Interface signals from EXEC unit to CSR management unit\n signal csr_instr_req : std_logic;\n signal csr_instr_done : std_logic;\n signal csr_access_denied_o : std_logic;\n signal csr_wdata_i : std_logic_vector(31 downto 0);\n signal csr_op_i : std_logic_vector(2 downto 0);\n signal csr_rdata_o : std_logic_vector(31 downto 0);\n signal csr_addr_i : std_logic_vector (11 downto 0);\n\n -- CSR management unit internal signal\n signal csr_instr_req_replicated : std_logic_vector(harc_range);\n signal csr_instr_done_replicated : std_logic_vector(harc_range);\n signal csr_access_denied_o_replicated : std_logic_vector(harc_range);\n signal csr_rdata_o_replicated : array_2d(harc_range)(31 downto 0);\n\n -- program counters --\n signal pc : array_2d(harc_range)(31 downto 0);\n signal pc_IF : std_logic_vector(31 downto 0); -- pc_IF is the actual pc\n signal pc_ID : std_logic_vector(31 downto 0); -- pc_ID is the orogram counter of the Decode stage\n signal pc_IE : std_logic_vector(31 downto 0); -- pc_IE is pc entering stage IE\n\n -- instruction register and instr. propagation registers --\n signal instr_word_IE : std_logic_vector(31 downto 0);\n signal instr_rvalid_IE : std_logic; -- validity bit at IE input\n\n -- pc updater signals\n signal pc_update_enable : std_logic_vector(harc_range);\n signal wfi_condition_pending : std_logic_vector(harc_range);\n signal served_ie_except_condition : std_logic_vector(harc_range);\n signal served_ls_except_condition : std_logic_vector(harc_range);\n signal served_dsp_except_condition : std_logic_vector(harc_range);\n signal served_except_condition : std_logic_vector(harc_range);\n signal served_mret_condition : std_logic_vector(harc_range);\n signal served_irq : std_logic_vector(harc_range);\n signal taken_branch_pending : std_logic_vector(harc_range);\n signal ie_except_data : std_logic_vector(31 downto 0);\n signal ls_except_data : std_logic_vector(31 downto 0);\n signal dsp_except_data : array_2d(accl_range)(31 downto 0);\n signal taken_branch : std_logic;\n signal ie_taken_branch : std_logic;\n signal ls_taken_branch : std_logic;\n signal dsp_taken_branch : std_logic_vector(accl_range);\n signal set_branch_condition : std_logic;\n signal ie_except_condition : std_logic;\n signal ls_except_condition : std_logic;\n signal dsp_except_condition : std_logic_vector(accl_range);\n signal set_except_condition : std_logic;\n signal set_mret_condition : std_logic;\n signal PC_offset : array_2d(harc_range)(31 downto 0);\n signal pc_except_value : array_2d(harc_range)(31 downto 0);\n signal pc_except_value_wire : array_2d(harc_range)(31 downto 0);\n signal taken_branch_pc_lat : array_2d(harc_range)(31 downto 0);\n signal incremented_pc : array_2d(harc_range)(31 downto 0);\n signal mepc_incremented_pc : array_2d(harc_range)(31 downto 0) := (others => (others => '0'));\n signal mepc_interrupt_pc : array_2d(harc_range)(31 downto 0) := (others => (others => '0'));\n signal relative_to_PC : array_2d(harc_range)(31 downto 0);\n signal absolute_jump : std_logic;\n signal data_we_o_lat : std_logic;\n signal misaligned_err : std_logic;\n\n --//parte probabilmente da eliminare\n -- signals for counting intructions\n --signal clock_cycle : std_logic_vector(63 downto 0); -- RDCYCLE\n --signal external_counter : std_logic_vector(63 downto 0); -- RDTIME\n --signal instruction_counter : std_logic_vector(63 downto 0); -- RDINSTRET\n\n -- regfile replicated array\n signal regfile : array_3d(harc_range)(RF_SIZE-1 downto 0)(31 downto 0);\n\n --signal used by counters\n signal set_wfi_condition : std_logic;\n signal harc_to_csr : harc_range;\n signal jump_instr : std_logic;\n signal jump_instr_lat : std_logic;\n signal branch_instr : std_logic;\n signal branch_instr_lat : std_logic;\n\n -- auxiliary data memory interface signals\n signal data_addr_internal : std_logic_vector(31 downto 0);\n signal data_be_internal : std_logic_vector(3 downto 0);\n\n --DeBug Unit signal and state\n signal dbg_req_o : std_logic;\n signal dbg_ack_i : std_logic;\n signal ebreak_instr : std_logic;\n\n -- hardware context id at fetch, and propagated hardware context ids\n --signal harc_count : harc_min_range;\n signal harc_IF : harc_range;\n signal harc_ID : harc_range;\n signal harc_EXEC : harc_range;\n\n component Program_Counter\n generic (\n THREAD_POOL_SIZE : integer;\n ACCL_NUM : natural\n );\n port (\n absolute_jump : in std_logic;\n data_we_o_lat : in std_logic;\n PC_offset : in array_2d(harc_range)(31 downto 0);\n taken_branch : in std_logic;\n ie_taken_branch : in std_logic;\n ls_taken_branch : in std_logic;\n dsp_taken_branch : in std_logic_vector(accl_range);\n set_branch_condition : in std_logic;\n ie_except_condition : in std_logic;\n ls_except_condition : in std_logic;\n dsp_except_condition : in std_logic_vector(accl_range);\n set_except_condition : in std_logic;\n set_mret_condition : in std_logic;\n set_wfi_condition : in std_logic;\n harc_ID : in harc_range;\n harc_EXEC : in harc_range;\n instr_rvalid_IE : in std_logic;\n pc_IE : in std_logic_vector(31 downto 0);\n MSTATUS : in array_2d(harc_range)(1 downto 0);\n MIP, MEPC, MCAUSE, MTVEC : in array_2d(harc_range)(31 downto 0);\n instr_word_IE : in std_logic_vector(31 downto 0);\n reset_state : in std_logic;\n pc_IF : out std_logic_vector(31 downto 0);\n harc_IF : out harc_range;\n served_ie_except_condition : out std_logic_vector(harc_range);\n served_ls_except_condition : out std_logic_vector(harc_range);\n served_dsp_except_condition : out std_logic_vector(harc_range);\n served_except_condition : out std_logic_vector(harc_range);\n served_mret_condition : out std_logic_vector(harc_range);\n served_irq : in std_logic_vector(harc_range);\n taken_branch_pending : out std_logic_vector(harc_range);\n taken_branch_pc_lat : out array_2d(harc_range)(31 downto 0);\n incremented_pc : out array_2d(harc_range)(31 downto 0);\n mepc_incremented_pc : out array_2d(harc_range)(31 downto 0);\n mepc_interrupt_pc : out array_2d(harc_range)(31 downto 0);\n irq_pending : out std_logic_vector(harc_range);\n clk_i : in std_logic;\n rst_ni : in std_logic;\n irq_i : in std_logic;\n fetch_enable_i : in std_logic;\n boot_addr_i : in std_logic_vector(31 downto 0);\n instr_gnt_i : in std_logic\n );\n end component;\n\n component CSR_Unit\n generic (\n THREAD_POOL_SIZE : integer;\n ACCL_NUM : natural;\n Addr_Width : natural;\n replicate_accl_en : natural;\n accl_en : natural;\n MCYCLE_EN : natural;\n MINSTRET_EN : natural;\n MHPMCOUNTER_EN : natural;\n RF_CEIL : natural;\n count_all : natural\n );\n port (\n pc_IE : in std_logic_vector(31 downto 0);\n ie_except_data : in std_logic_vector(31 downto 0);\n ls_except_data : in std_logic_vector(31 downto 0);\n dsp_except_data : in array_2d(accl_range)(31 downto 0);\n served_ie_except_condition : in std_logic_vector(harc_range);\n served_ls_except_condition : in std_logic_vector(harc_range);\n served_dsp_except_condition : in std_logic_vector(harc_range);\n harc_EXEC : in harc_range;\n harc_to_csr : in harc_range;\n instr_word_IE : in std_logic_vector(31 downto 0);\n served_except_condition : in std_logic_vector(harc_range);\n served_mret_condition : in std_logic_vector(harc_range);\n served_irq : in std_logic_vector(harc_range);\n pc_except_value_wire : in array_2d(harc_range)(31 downto 0);\n dbg_req_o : in std_logic;\n data_addr_internal : in std_logic_vector(31 downto 0);\n jump_instr : in std_logic;\n branch_instr : in std_logic;\n set_branch_condition : in std_logic;\n csr_instr_req : in std_logic;\n misaligned_err : in std_logic;\n WFI_Instr : in std_logic;\n csr_wdata_i : in std_logic_vector(31 downto 0);\n csr_op_i : in std_logic_vector(2 downto 0);\n csr_addr_i : in std_logic_vector(11 downto 0);\n csr_instr_done : out std_logic;\n csr_access_denied_o : out std_logic;\n csr_rdata_o : out std_logic_vector (31 downto 0);\n MVSIZE : out array_2d(harc_range)(Addr_Width downto 0);\n MVTYPE : out array_2d(harc_range)(3 downto 0);\n MPSCLFAC : out array_2d(harc_range)(4 downto 0);\n MSTATUS : out array_2d(harc_range)(1 downto 0);\n MEPC : out array_2d(harc_range)(31 downto 0);\n MCAUSE : out array_2d(harc_range)(31 downto 0);\n MIP : out array_2d(harc_range)(31 downto 0);\n MTVEC : out array_2d(harc_range)(31 downto 0);\n PCER : out array_2d(harc_range)(31 downto 0);\n fetch_enable_i : in std_logic;\n clk_i : in std_logic;\n rst_ni : in std_logic;\n cluster_id_i : in std_logic_vector(5 downto 0);\n instr_rvalid_i : in std_logic;\n instr_rvalid_IE : in std_logic;\n data_we_o : in std_logic;\n data_req_o : in std_logic;\n data_gnt_i : in std_logic;\n irq_i : in std_logic;\n irq_id_i : in std_logic_vector(4 downto 0);\n irq_id_o : out std_logic_vector(4 downto 0);\n irq_ack_o : out std_logic\n );\n end component;\n\n component Debug_Unit\n generic(\n THREAD_POOL_SIZE : integer;\n LUTRAM_RF : natural;\n ACCL_NUM : natural;\n RF_SIZE : natural\n );\n port(\n set_branch_condition : in std_logic;\n ie_except_condition : in std_logic;\n ls_except_condition : in std_logic;\n dsp_except_condition : in std_logic_vector(accl_range);\n set_except_condition : in std_logic;\n set_mret_condition : in std_logic;\n served_irq : in std_logic_vector(harc_range);\n irq_pending : in std_logic_vector(harc_range);\n taken_branch_pc_lat : in array_2d(harc_range)(31 downto 0);\n incremented_pc : in array_2d(harc_range)(31 downto 0);\n MTVEC : in array_2d(harc_range)(31 downto 0);\n MIP : in array_2d(harc_range)(31 downto 0);\n MSTATUS : in array_2d(harc_range)(1 downto 0);\n MCAUSE : in array_2d(harc_range)(31 downto 0);\n mepc_incremented_pc : in array_2d(harc_range)(31 downto 0) := (others => (others => '0'));\n mepc_interrupt_pc : in array_2d(harc_range)(31 downto 0) := (others => (others => '0'));\n regfile : in array_3d(harc_range)(RF_SIZE-1 downto 0)(31 downto 0);\n pc_ID : in std_logic_vector (31 downto 0);\n pc_IE : in std_logic_vector (31 downto 0);\n harc_ID : in harc_range;\n ebreak_instr : in std_logic;\n dbg_ack_i : in std_logic;\n taken_branch : in std_logic;\n taken_branch_pending : in std_logic_vector(harc_range);\n dbg_req_o : out std_logic;\n clk_i : in std_logic;\n rst_ni : in std_logic;\n debug_req_i : in std_logic;\n debug_gnt_o : out std_logic;\n debug_rvalid_o : out std_logic;\n debug_addr_i : in std_logic_vector(14 downto 0);\n debug_we_i : in std_logic;\n debug_wdata_i : in std_logic_vector(31 downto 0);\n debug_rdata_o : out std_logic_vector(31 downto 0);\n debug_halted_o : out std_logic;\n debug_halt_i : in std_logic;\n debug_resume_i : in std_logic\n );\n end component;\n\n component Pipeline\n generic(\n THREAD_POOL_SIZE : integer;\n LUTRAM_RF : natural;\n RV32E : natural;\n RV32M : natural;\n superscalar_exec_en : natural;\n accl_en : natural;\n replicate_accl_en : natural;\n multithreaded_accl_en : natural;\n SPM_NUM : natural; \n Addr_Width : natural;\n SPM_STRT_ADDR : std_logic_vector(31 downto 0);\n SIMD : natural;\n MCYCLE_EN : natural;\n MINSTRET_EN : natural;\n MHPMCOUNTER_EN : natural;\n count_all : natural;\n debug_en : natural;\n tracer_en : natural;\n -------------------------------------\n ACCL_NUM : natural;\n FU_NUM : natural;\n RF_SIZE : natural;\n RF_CEIL : natural;\n TPS_CEIL : natural;\n TPS_BUF_CEIL : natural;\n SPM_ADDR_WID : natural;\n SIMD_BITS : natural;\n Data_Width : natural;\n SIMD_Width : natural\n );\n port (\n pc_IF : in std_logic_vector(31 downto 0);\n harc_IF : in harc_range;\n irq_pending : in std_logic_vector(harc_range);\n csr_instr_done : in std_logic;\n csr_access_denied_o : in std_logic;\n csr_rdata_o : in std_logic_vector (31 downto 0);\n dbg_req_o : in std_logic;\n MVSIZE : in array_2d(harc_range)(Addr_Width downto 0);\n MVTYPE : in array_2d(harc_range)(3 downto 0);\n MPSCLFAC : in array_2d(harc_range)(4 downto 0);\n MSTATUS : in array_2d(harc_range)(1 downto 0);\n PCER : in array_2d(harc_range)(31 downto 0);\n served_irq \t : out std_logic_vector(harc_range);\n WFI_Instr : out std_logic;\n reset_state : out std_logic;\n misaligned_err : out std_logic;\n pc_ID : out std_logic_vector(31 downto 0);\n pc_IE : out std_logic_vector(31 downto 0);\n ie_except_data : out std_logic_vector(31 downto 0);\n ls_except_data : out std_logic_vector(31 downto 0);\n dsp_except_data : out array_2d(accl_range)(31 downto 0);\n taken_branch : out std_logic;\n ie_taken_branch : out std_logic;\n ls_taken_branch : out std_logic;\n dsp_taken_branch : out std_logic_vector(accl_range);\n set_branch_condition : out std_logic;\n ie_except_condition : out std_logic;\n ls_except_condition : out std_logic;\n dsp_except_condition : out std_logic_vector(accl_range);\n set_mret_condition : out std_logic;\n set_wfi_condition : out std_logic;\n csr_instr_req : out std_logic;\n instr_rvalid_IE : out std_logic; -- validity bit at IE input\n csr_addr_i : out std_logic_vector (11 downto 0);\n csr_wdata_i : out std_logic_vector (31 downto 0);\n csr_op_i : out std_logic_vector (2 downto 0);\n jump_instr : out std_logic;\n jump_instr_lat : out std_logic;\n branch_instr : out std_logic;\n branch_instr_lat : out std_logic;\n harc_ID : out harc_range;\n harc_EXEC : out harc_range;\n harc_to_csr : out harc_range;\n instr_word_IE : out std_logic_vector(31 downto 0);\n PC_offset : out array_2d(harc_range)(31 downto 0);\n dbg_ack_i : out std_logic;\n ebreak_instr : out std_logic;\n data_addr_internal : out std_logic_vector(31 downto 0);\n absolute_jump : out std_logic;\n regfile : out array_3d(harc_range)(RF_SIZE-1 downto 0)(31 downto 0);\n -- clock, reset active low, test enable\n clk_i : in std_logic;\n rst_ni : in std_logic;\n -- program memory interface\n instr_req_o : out std_logic;\n instr_gnt_i : in std_logic;\n instr_rvalid_i : in std_logic;\n instr_rdata_i : in std_logic_vector(31 downto 0);\n -- data memory interface\n data_req_o : out std_logic;\n data_gnt_i : in std_logic;\n data_rvalid_i : in std_logic;\n data_we_o : out std_logic;\n data_be_o : out std_logic_vector(3 downto 0);\n data_addr_o : out std_logic_vector(31 downto 0);\n data_wdata_o : out std_logic_vector(31 downto 0);\n data_rdata_i : in std_logic_vector(31 downto 0);\n data_err_i : in std_logic;\n -- interrupt request interface\n\tirq_i \t : in std_logic;\n -- miscellanous control signals\n fetch_enable_i : in std_logic;\n core_busy_o : out std_logic\n );\n end component;\n\n--------------------------------------------------------------------------------------------------\n----------------------- ARCHITECTURE BEGIN ------------------------------------------------------- \nbegin\n\n assert (LUTRAM_RF /= debug_en and LUTRAM_RF /= 1) report \"Debug-Unit cannot read from a LUTRAM regfile.\" severity WARNING;\n\n instr_addr_o <= pc_IF;\n\n set_except_condition <= '1' when (IE_except_condition = '1' or LS_except_condition = '1' or DSP_except_condition /= (accl_range => '0')) else '0';\n\n process(all)\n begin\n pc_except_value_wire <= pc_except_value;\n if set_except_condition = '1' then\n pc_except_value_wire(harc_EXEC) <= pc_IE; \n end if;\n end process;\n\n process(clk_i, rst_ni)\n", "right_context": " Prg_Ctr : Program_Counter\n generic map (\n THREAD_POOL_SIZE => THREAD_POOL_SIZE,\n ACCL_NUM => ACCL_NUM\n )\n port map(\n absolute_jump => absolute_jump,\n data_we_o_lat => data_we_o_lat,\n PC_offset => PC_offset,\n taken_branch => taken_branch,\n ie_taken_branch => ie_taken_branch,\n ls_taken_branch => ls_taken_branch,\n dsp_taken_branch => dsp_taken_branch,\n set_branch_condition => set_branch_condition,\n ie_except_condition => ie_except_condition,\n ls_except_condition => ls_except_condition,\n dsp_except_condition => dsp_except_condition, \n set_except_condition => set_except_condition,\n set_mret_condition => set_mret_condition,\n set_wfi_condition => set_wfi_condition,\n harc_ID => harc_ID,\n harc_EXEC => harc_EXEC,\n instr_rvalid_IE => instr_rvalid_IE,\n pc_IE => pc_IE,\n MIP => MIP,\n MEPC => MEPC,\n MSTATUS => MSTATUS,\n MCAUSE => MCAUSE,\n MTVEC => MTVEC,\n instr_word_IE => instr_word_IE,\n reset_state => reset_state,\n pc_IF => pc_IF,\n harc_IF => harc_IF,\n served_ie_except_condition => served_ie_except_condition,\n served_ls_except_condition => served_ls_except_condition,\n served_dsp_except_condition => served_dsp_except_condition,\n served_except_condition => served_except_condition,\n served_mret_condition => served_mret_condition,\n served_irq => served_irq,\n taken_branch_pending => taken_branch_pending,\n taken_branch_pc_lat => taken_branch_pc_lat,\n incremented_pc => incremented_pc,\n mepc_incremented_pc => mepc_incremented_pc,\n mepc_interrupt_pc => mepc_interrupt_pc,\n irq_pending => irq_pending,\n clk_i => clk_i,\n rst_ni => rst_ni,\n irq_i => irq_i,\n fetch_enable_i => fetch_enable_i,\n boot_addr_i => boot_addr_i,\n instr_gnt_i => instr_gnt_i\n );\n\n CSR : CSR_Unit\n generic map (\n THREAD_POOL_SIZE => THREAD_POOL_SIZE,\n ACCL_NUM => ACCL_NUM,\n Addr_Width => Addr_Width,\n replicate_accl_en => replicate_accl_en,\n accl_en => accl_en,\n MCYCLE_EN => MCYCLE_EN,\n MINSTRET_EN => MINSTRET_EN,\n MHPMCOUNTER_EN => MHPMCOUNTER_EN,\n RF_CEIL => RF_CEIL,\n count_all => count_all\n )\n port map(\n pc_IE => pc_IE,\n ie_except_data => ie_except_data,\n ls_except_data => ls_except_data,\n dsp_except_data => dsp_except_data,\n served_ie_except_condition => served_ie_except_condition,\n served_ls_except_condition => served_ls_except_condition,\n served_dsp_except_condition => served_dsp_except_condition,\n harc_EXEC => harc_EXEC,\n harc_to_csr => harc_to_csr,\n instr_word_IE => instr_word_IE,\n served_except_condition => served_except_condition,\n served_mret_condition => served_mret_condition,\n served_irq => served_irq,\n pc_except_value_wire => pc_except_value_wire,\n dbg_req_o => dbg_req_o,\n data_addr_internal => data_addr_internal,\n jump_instr => jump_instr,\n branch_instr => branch_instr,\n set_branch_condition => set_branch_condition,\n csr_instr_req => csr_instr_req,\n misaligned_err => misaligned_err,\n WFI_Instr => WFI_Instr,\n csr_wdata_i => csr_wdata_i,\n csr_op_i => csr_op_i,\n csr_addr_i => csr_addr_i,\n csr_instr_done => csr_instr_done,\n csr_access_denied_o => csr_access_denied_o,\n csr_rdata_o => csr_rdata_o,\n MVSIZE => MVSIZE,\n MVTYPE => MVTYPE,\n MPSCLFAC => MPSCLFAC,\n MSTATUS => MSTATUS,\n MEPC => MEPC,\n MCAUSE => MCAUSE,\n MIP => MIP,\n MTVEC => MTVEC,\n PCER => PCER,\n fetch_enable_i => fetch_enable_i,\n clk_i => clk_i,\n rst_ni => rst_ni,\n cluster_id_i => cluster_id_i,\n instr_rvalid_i => instr_rvalid_i,\n instr_rvalid_IE => instr_rvalid_IE,\n data_we_o => data_we_o,\n data_req_o => data_req_o,\n data_gnt_i => data_gnt_i,\n irq_i => irq_i,\n irq_id_i => irq_id_i,\n irq_id_o => irq_id_o,\n irq_ack_o => irq_ack_o\n );\n\n DEBUG_generate : if debug_en = 1 generate\n\n DBG : Debug_Unit\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE,\n LUTRAM_RF => LUTRAM_RF,\n ACCL_NUM => ACCL_NUM,\n RF_SIZE => RF_SIZE\n )\n port map(\n set_branch_condition => set_branch_condition,\n ie_except_condition => ie_except_condition,\n ls_except_condition => ls_except_condition,\n dsp_except_condition => dsp_except_condition,\n set_except_condition => set_except_condition,\n set_mret_condition => set_mret_condition,\n served_irq => served_irq,\n irq_pending => irq_pending,\n taken_branch_pc_lat => taken_branch_pc_lat,\n incremented_pc => incremented_pc,\n MTVEC => MTVEC,\n MIP => MIP,\n MSTATUS => MSTATUS,\n MCAUSE => MCAUSE,\n mepc_incremented_pc => mepc_incremented_pc,\n mepc_interrupt_pc => mepc_interrupt_pc,\n regfile => regfile,\n pc_ID => pc_ID,\n pc_IE => pc_IE,\n harc_ID => harc_ID,\n ebreak_instr => ebreak_instr,\n dbg_ack_i => dbg_ack_i,\n taken_branch\t => taken_branch,\n taken_branch_pending => taken_branch_pending,\n dbg_req_o => dbg_req_o,\n clk_i => clk_i,\n rst_ni => rst_ni,\n debug_req_i => debug_req_i,\n debug_gnt_o => debug_gnt_o,\n debug_rvalid_o => debug_rvalid_o,\n debug_addr_i => debug_addr_i,\n debug_we_i => debug_we_i,\n debug_wdata_i => debug_wdata_i,\n debug_rdata_o => debug_rdata_o,\n debug_halted_o => debug_halted_o,\n debug_halt_i => debug_halt_i,\n debug_resume_i => debug_resume_i\n );\n\n end generate;\n\n Pipe : Pipeline\n generic map(\n THREAD_POOL_SIZE => THREAD_POOL_SIZE,\n LUTRAM_RF => LUTRAM_RF,\n RV32E => RV32E,\n RV32M => RV32M,\n superscalar_exec_en => superscalar_exec_en,\n accl_en => accl_en,\n replicate_accl_en => replicate_accl_en,\n multithreaded_accl_en => multithreaded_accl_en,\n SPM_NUM => SPM_NUM, \n Addr_Width => Addr_Width,\n SPM_STRT_ADDR => SPM_STRT_ADDR,\n SIMD => SIMD,\n MCYCLE_EN => MCYCLE_EN,\n MINSTRET_EN => MINSTRET_EN,\n MHPMCOUNTER_EN => MHPMCOUNTER_EN,\n count_all => count_all,\n debug_en => debug_en,\n tracer_en => tracer_en,\n -----------------------------------\n ACCL_NUM => ACCL_NUM,\n FU_NUM => FU_NUM,\n RF_SIZE => RF_SIZE,\n RF_CEIL => RF_CEIL,\n TPS_CEIL => TPS_CEIL,\n TPS_BUF_CEIL => TPS_BUF_CEIL,\n SPM_ADDR_WID => SPM_ADDR_WID,\n SIMD_BITS => SIMD_BITS,\n Data_Width => Data_Width,\n SIMD_Width => SIMD_Width\n )\n port map(\n pc_IF => pc_IF,\n harc_IF => harc_IF,\n irq_pending => irq_pending,\n csr_instr_done => csr_instr_done,\n csr_access_denied_o => csr_access_denied_o,\n csr_rdata_o => csr_rdata_o,\n dbg_req_o => dbg_req_o,\n pc_ID => pc_ID,\n pc_IE => pc_IE,\n ie_except_data => ie_except_data,\n ls_except_data => ls_except_data,\n dsp_except_data => dsp_except_data,\n MVSIZE => MVSIZE,\n MVTYPE => MVTYPE,\n MPSCLFAC => MPSCLFAC,\n MSTATUS => MSTATUS,\n PCER => PCER,\n served_irq => served_irq,\n WFI_Instr => WFI_Instr,\n reset_state => reset_state,\n misaligned_err => misaligned_err,\n taken_branch => taken_branch,\n ie_taken_branch => ie_taken_branch,\n ls_taken_branch => ls_taken_branch,\n dsp_taken_branch => dsp_taken_branch,\n set_branch_condition => set_branch_condition,\n ie_except_condition => ie_except_condition,\n ls_except_condition => ls_except_condition,\n dsp_except_condition => dsp_except_condition,\n set_mret_condition => set_mret_condition,\n set_wfi_condition => set_wfi_condition,\n csr_instr_req => csr_instr_req,\n instr_rvalid_IE => instr_rvalid_IE,\n csr_addr_i => csr_addr_i,\n csr_wdata_i => csr_wdata_i,\n csr_op_i => csr_op_i,\n jump_instr => jump_instr,\n jump_instr_lat => jump_instr_lat,\n branch_instr => branch_instr,\n branch_instr_lat => branch_instr_lat,\n harc_ID => harc_ID,\n harc_EXEC => harc_EXEC,\n harc_to_csr => harc_to_csr,\n instr_word_IE => instr_word_IE,\n PC_offset => PC_offset,\n dbg_ack_i => dbg_ack_i,\n ebreak_instr => ebreak_instr,\n data_addr_internal => data_addr_internal,\n absolute_jump => absolute_jump,\n regfile => regfile,\n clk_i => clk_i,\n rst_ni => rst_ni,\n instr_req_o => instr_req_o,\n instr_gnt_i => instr_gnt_i,\n instr_rvalid_i => instr_rvalid_i,\n instr_rdata_i => instr_rdata_i,\n data_req_o => data_req_o,\n data_gnt_i => data_gnt_i,\n data_rvalid_i => data_rvalid_i,\n data_we_o => data_we_o,\n data_be_o => data_be_o,\n data_addr_o => data_addr_o,\n data_wdata_o => data_wdata_o,\n data_rdata_i => data_rdata_i,\n data_err_i => data_err_i,\n irq_i => irq_i,\n fetch_enable_i => fetch_enable_i,\n core_busy_o => core_busy_o\n );\n\nend Klessydra_T1;\n--------------------------------------------------------------------------------------------------\n-- END of Klessydra T13 core architecture --------------------------------------------------------\n--------------------------------------------------------------------------------------------------", "groundtruth": " begin\r\n if rst_ni = '0' then\r\n elsif rising_edge(clk_i) then\r\n pc_except_value <= pc_except_value_wire; -- AAA verify if it is working for DSP and LSU (not verified yet)\r\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/denise.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse work.ocs.all;\nuse work.priv.all;\n\nentity denise is\n generic (\n CFG_STRDEBUG : boolean := false;\n CFG_BLANK_DURING_VBLANK : boolean := true\n );\n port (\n deni : in denise_in_t;\n deno : out denise_out_t\n );\nend;\n\narchitecture rtl of denise is\n -- In the NTSC television standard, horizontal blanking occupies\n -- 10.9 Ī¼s (17.2%) out of every 63.6 Ī¼s scan line. In PAL, it\n -- occupies 12 Ī¼s (18.8%) out of every 64 Ī¼s scan line.\n -- NTSC: main clock 28.63636 MHz\n -- PAL: main clock 28.37516 MHz, hblank is 85.12548 clk (7 MHz)\n constant HBLANK_START_PAL : natural range 0 to 511 := 3;\n constant HBLANK_NCLK_PAL : natural range 0 to 511 := 85;\n constant NBURST_START_PAL : natural range 0 to 511 := 41;\n constant NBURST_NCLK_PAL : natural range 0 to 511 := 18;\n\n subtype color_index_t is std_ulogic_vector(4 downto 0);\n type color_index_array_t is array (integer range <>) of color_index_t;\n\n type sprite_shift_t is record\n a : word_t;\n b : word_t;\n end record;\n\n type sprite_shift_array_t is array (integer range <>) of sprite_shift_t;\n type shreg_t is record\n bpl : word_array_t(0 to 5);\n bpld : word_array_t(0 to 5);\n spr : sprite_shift_array_t(0 to 7);\n end record;\n\n type state_a is record\n sel : sel_t;\n cck : std_ulogic;\n rga : rga_t;\n end record;\n\n type state_b is record\n sel : sel_t;\n drdx : word_t;\n colori : color_index_t;\n end record;\n\n type bplcon_t is record\n hires : std_ulogic;\n bpu : std_ulogic_vector(2 downto 0);\n homod : std_ulogic;\n dblpf : std_ulogic;\n color : std_ulogic;\n gaud : std_ulogic;\n pf1h : std_ulogic_vector(3 downto 0);\n pf2h : std_ulogic_vector(3 downto 0);\n pf1p : std_ulogic_vector(2 downto 0);\n pf2p : std_ulogic_vector(2 downto 0);\n pf2pri : std_ulogic;\n end record;\n\n type state_c is record\n -- horizontal video beam position, lores\n h : unsigned(8 downto 0);\n hblank : std_ulogic;\n vblank : std_ulogic;\n -- Indicates that beam is currently in the horizontal display window.\n diw : std_ulogic;\n diwstrth : std_ulogic_vector(8 downto 0);\n diwstoph : std_ulogic_vector(8 downto 0);\n bplcon : bplcon_t;\n clxcon : std_ulogic_vector(15 downto 0);\n clxdat : std_ulogic_vector(14 downto 0);\n bpldat : word_array_t(0 to 5);\n spr : sprite_reg_array_t(0 to 7);\n color : rgb4_array_t(0 to 31);\n bpltrig : std_ulogic;\n end record;\n\n type state_d is record\n bplen : std_ulogic_vector(5 downto 0);\n shreg : shreg_t;\n end record;\n\n type bplbus_array_t is array (integer range <>)\n of std_ulogic_vector(5 downto 0);\n\n type state_e is record\n bplbus : bplbus_array_t(0 to 1);\n -- 8 sprites * 2 lines\n sprbus : std_ulogic_vector(15 downto 0);\n end record;\n\n type pfp_array_t is array (integer range <>) of std_ulogic_vector(2 downto 0);\n\n type state_f is record\n bplcolor : color_index_array_t(0 to 1);\n hamop : std_ulogic_vector(1 downto 0);\n sprcolor : std_ulogic_vector(3 downto 0);\n -- playfield X priority code (with respect to sprites)\n pfp : pfp_array_t(0 to 1);\n -- sprite group number\n spp : std_ulogic_vector(2 downto 0);\n end record;\n\n type state_g is record\n color : color_index_array_t(0 to 1);\n issprite : std_ulogic;\n hamop : std_ulogic_vector(1 downto 0);\n end record;\n\n type state_h is record\n rgb : rgb4_array_t(0 to 1);\n nzd : std_ulogic_vector(0 to 1);\n end record;\n\n type state_t is record\n a : state_a;\n b : state_b;\n c : state_c;\n d : state_d;\n e : state_e;\n f : state_f;\n g : state_g;\n h : state_h;\n nburst : std_ulogic;\n drd : word_t;\n drd_oe : std_ulogic;\n drd_ext_noe : std_ulogic;\n drd_ext_to_denice : std_ulogic;\n end record;\n function STATE_SIMINIT return state_t is\n variable v : state_t;\n begin\n v.c.h := (others => '0');\n v.c.bplcon.pf1h := (others => '0');\n v.c.bplcon.pf2h := (others => '0');\n v.c.bplcon.pf1p := (others => '0');\n v.c.bplcon.pf2p := (others => '0');\n v.f.pfp := (others => (others => '0'));\n v.f.spp := (others => '0');\n return v;\n end;\n\n -- joystick inputs are asynchronous to clk7\n signal m0v_sync : std_ulogic;\n signal m0h_sync : std_ulogic;\n signal m1v_sync : std_ulogic;\n signal m1h_sync : std_ulogic;\n signal joy0daty : std_ulogic_vector(7 downto 0);\n signal joy0datx : std_ulogic_vector(7 downto 0);\n signal joy1daty : std_ulogic_vector(7 downto 0);\n signal joy1datx : std_ulogic_vector(7 downto 0);\n\n -- Current pipeline state is in \"r\". Next state is in \"rin\".\n signal r : state_t\n-- pragma translate_off\n := STATE_SIMINIT\n-- pragma translate_on\n ;\n signal rin : state_t;\n\nbegin\n\n -- Main pipeline with flow from stage \"a\" \"h\".\n -- * Stage \"a\" and \"b\" is for RGA bus and register decoding.\n -- * Stage \"c\" does register writes.\n -- * Stage \"d\" and forward is where sprite and bitplane data is shifted out,\n -- including bitplane/sprite priority logic, collision detection, color\n -- lookup, HAM, and more.\n --\n -- Note that the \"hires pixel clock\" is double the frequency of clk7. Some\n -- logic from stage \"e\" and forward is \"replicated\" to handle the \"double\n -- bandwidth\" while staying in the clk7 domain. The effective hires pixel\n -- clock is achieved at the output stage with DDR registers. Thus, we trade\n -- logic resources to avoid introducing another clock. This may change in the\n -- future. (Super-hires clock is 4x clk7.)\n\n process (r, deni, joy0daty, joy0datx, joy1daty, joy1datx)\n variable v : state_t;\n variable readreg : boolean;\n begin\n v := r;\n\n v.a.cck := deni.cck;\n v.a.rga := deni.rga;\n v.a.sel := SEL_NONE;\n readreg := false;\n if deni.cck = '1' then\n v.a.sel := gen_sel(deni.rga);\n if\n v.a.sel.joy0dat = '1' or\n v.a.sel.joy1dat = '1' or\n v.a.sel.clxdat = '1'\n then\n readreg := true;\n end if;\n end if;\n\n v.drd_ext_noe := '1';\n v.drd_ext_to_denice := '1';\n if deni.cck = '1' then\n v.drd_ext_noe := '0';\n end if;\n\n if readreg then\n v.drd_ext_noe := '1';\n v.drd_ext_to_denice := '0';\n end if;\n\n -- read\n v.drd_oe := '0';\n if\n r.a.sel.joy0dat = '1' or\n r.a.sel.joy1dat = '1' or\n r.a.sel.clxdat = '1'\n then\n v.drd_oe := '1';\n v.drd_ext_noe := '0';\n v.drd_ext_to_denice := '0';\n end if;\n v.drd := (others => '-');\n if r.a.sel.joy0dat = '1' then\n v.drd := joy0daty & joy0datx;\n end if;\n if r.a.sel.joy1dat = '1' then\n v.drd := joy1daty & joy1datx;\n end if;\n if r.a.sel.clxdat = '1' then\n v.drd(r.c.clxdat'range) := r.c.clxdat;\n end if;\n\n -- register address decoder\n v.b.sel := SEL_NONE;\n if r.a.cck = '1' then\n v.b.sel := gen_sel(r.a.rga);\n end if;\n v.b.drdx := deni.drd;\n v.b.colori := r.a.rga(5 downto 1);\n\n\n -- Advance beam counter every clk7 cycle.\n v.c.h := r.c.h + 1;\n -- Horizontal counter is reset when Agnus writes a sync strobe.\n if r.b.sel.strhor = '1' or r.b.sel.strvbl = '1' or r.b.sel.strequ = '1' then\n v.c.h := \"111111110\";\n end if;\n\n -- Match display window horizontal start and stop position.\n if std_ulogic_vector(r.c.h) = r.c.diwstrth then\n v.c.diw := '1';\n end if;\n if std_ulogic_vector(r.c.h) = r.c.diwstoph then\n v.c.diw := '0';\n end if;\n\n if r.c.h = to_unsigned(HBLANK_START_PAL, r.c.h'length) then\n v.c.hblank := '1';\n end if;\n if r.c.h = to_unsigned(HBLANK_NCLK_PAL, r.c.h'length) then\n v.c.hblank := '0';\n end if;\n if r.b.sel.strvbl = '1' or r.b.sel.strequ = '1' then\n v.c.vblank := '1';\n elsif r.b.sel.strhor = '1' then\n v.c.vblank := '0';\n end if;\n\n -- ref: http://eab.abime.net/showthread.php?p=1304764\n -- ref: Motorola MC1377\n -- NOTE: The width of these comparators can likely be reduced.\n if\n r.c.bplcon.color = '1' and\n r.c.h = to_unsigned(HBLANK_START_PAL, r.c.h'length)\n then\n v.nburst := '0';\n elsif\n r.c.h = to_unsigned(NBURST_START_PAL+NBURST_NCLK_PAL, r.c.h'length)\n then\n v.nburst := '1';\n end if;\n\n\n -- user writes display window start or stop\n if r.b.sel.diwstrt = '1' then\n v.c.diwstrth := '0' & r.b.drdx(7 downto 0);\n end if;\n if r.b.sel.diwstop = '1' then\n v.c.diwstoph := '1' & r.b.drdx(7 downto 0);\n end if;\n\n -- write color table register\n if false then\n for i in r.c.color'range loop\n if r.b.sel.color(i) = '1' then\n v.c.color(i) := r.b.drdx(r.c.color(i)'range);\n end if;\n end loop;\n else\n if r.b.sel.colorx = '1' then\n v.c.color(to_integer(unsigned(r.b.colori))) :=\n r.b.drdx(r.c.color(0)'range);\n end if;\n end if;\n\n for i in r.c.bpldat'range loop\n if r.b.sel.bpldat(i) = '1' then\n v.c.bpldat(i) := r.b.drdx;\n end if;\n end loop;\n -- A Write to \"bpl1dat\" triggers load of all bitplane shift registers.\n v.c.bpltrig := r.b.sel.bpldat(0);\n\n -- write sprite registers\n for i in r.c.spr'range loop\n if r.b.sel.spr(i).pos = '1' then\n v.c.spr(i).sh(8 downto 1) := r.b.drdx(7 downto 0);\n end if;\n if r.b.sel.spr(i).ctl = '1' then\n v.c.spr(i).sh(0) := r.b.drdx(0);\n -- NOTE: Sprite attach control bit (odd sprites)\n v.c.spr(i).att := r.b.drdx(7);\n v.c.spr(i).en := '0';\n end if;\n if r.b.sel.spr(i).data = '1' then\n v.c.spr(i).data := r.b.drdx;\n v.c.spr(i).en := '1';\n end if;\n if r.b.sel.spr(i).datb = '1' then\n v.c.spr(i).datb := r.b.drdx;\n end if;\n end loop;\n\n -- Bitplane and collision control registers\n if r.b.sel.bplcon0 = '1' then\n v.c.bplcon.hires := r.b.drdx(15);\n v.c.bplcon.bpu := r.b.drdx(14 downto 12);\n v.c.bplcon.homod := r.b.drdx(11);\n v.c.bplcon.dblpf := r.b.drdx(10);\n v.c.bplcon.color := r.b.drdx( 9);\n v.c.bplcon.gaud := r.b.drdx( 8);\n end if;\n if r.b.sel.bplcon1 = '1' then\n v.c.bplcon.pf2h := r.b.drdx( 7 downto 4);\n v.c.bplcon.pf1h := r.b.drdx( 3 downto 0);\n end if;\n if r.b.sel.bplcon2 = '1' then\n v.c.bplcon.pf2pri := r.b.drdx( 6);\n v.c.bplcon.pf2p := r.b.drdx( 5 downto 3);\n v.c.bplcon.pf1p := r.b.drdx( 2 downto 0);\n end if;\n\n if r.b.sel.clxcon = '1' then\n v.c.clxcon := r.b.drdx;\n end if;\n\n v.c.clxdat := (\n collision_detection_logic(r.e.sprbus, r.e.bplbus(0), r.c.clxcon) or\n collision_detection_logic(r.e.sprbus, r.e.bplbus(1), r.c.clxcon)\n );\n -- The collision data register is automatically cleared after it is read.\n if r.a.sel.clxdat = '1' then\n v.c.clxdat := (others => '0');\n end if;\n\n\n -- parallel to serial converters\n\n case r.c.bplcon.bpu is\n", "right_context": " when \"011\" => v.d.bplen := \"000111\";\n when \"100\" => v.d.bplen := \"001111\";\n when \"101\" => v.d.bplen := \"011111\";\n when \"110\" => v.d.bplen := \"111111\";\n when others => null;\n end case;\n\n -- Shift or load the bitplane registers.\n -- The \"bpld\" is for the 16-bit horizontal scroll buffer.\n for i in r.c.bpldat'range loop\n v.d.shreg.bpld(i) := (\n r.d.shreg.bpld(i)(r.d.shreg.bpld(i)'high - 1 downto 0) &\n r.d.shreg.bpl (i)(r.d.shreg.bpl (i)'high)\n );\n if r.c.bpltrig = '1' then\n v.d.shreg.bpl (i) := r.c.bpldat(i);\n else\n v.d.shreg.bpl(i) :=\n r.d.shreg.bpl (i)(r.d.shreg.bpl (i)'high - 1 downto 0) & '0';\n end if;\n end loop;\n\n if r.c.bplcon.hires = '1' then\n for i in 0 to 3 loop\n v.d.shreg.bpld(i) := (\n r.d.shreg.bpld(i)(15-2 downto 0) &\n r.d.shreg.bpl (i)(15 downto 14)\n );\n if r.c.bpltrig = '1' then\n v.d.shreg.bpl(i) := r.c.bpldat(i);\n else\n v.d.shreg.bpl(i) := r.d.shreg.bpl (i)(15-2 downto 0) & \"00\";\n end if;\n end loop;\n end if;\n\n -- Shift out sprite pixels.\n for i in r.c.spr'range loop\n v.d.shreg.spr(i).a :=\n r.d.shreg.spr(i).a(r.d.shreg.spr(i).a'high - 1 downto 0) & '0';\n v.d.shreg.spr(i).b :=\n r.d.shreg.spr(i).b(r.d.shreg.spr(i).b'high - 1 downto 0) & '0';\n if\n (r.c.spr(i).en = '1') and\n (std_ulogic_vector(r.c.h) = r.c.spr(i).sh)\n then\n v.d.shreg.spr(i).a := r.c.spr(i).data;\n v.d.shreg.spr(i).b := r.c.spr(i).datb;\n end if;\n end loop;\n\n\n -- Generate pixel bus\n\n for i in 0 to 1 loop\n if r.c.bplcon.hires = '1' then\n v.e.bplbus(1-i)(0) := (\n r.d.bplen(0) and\n r.d.shreg.bpld(0)(to_integer(unsigned(r.c.bplcon.pf1h and \"1110\"))+i)\n );\n v.e.bplbus(1-i)(2) := (\n r.d.bplen(2) and\n r.d.shreg.bpld(2)(to_integer(unsigned(r.c.bplcon.pf1h and \"1110\"))+i)\n );\n v.e.bplbus(1-i)(4) := '0';\n v.e.bplbus(1-i)(1) := (\n r.d.bplen(1) and\n r.d.shreg.bpld(1)(to_integer(unsigned(r.c.bplcon.pf2h and \"1110\"))+i)\n );\n v.e.bplbus(1-i)(3) := (\n r.d.bplen(3) and\n r.d.shreg.bpld(3)(to_integer(unsigned(r.c.bplcon.pf2h and \"1110\"))+i)\n );\n v.e.bplbus(1-i)(5) := '0';\n else\n v.e.bplbus(i)(0) := (\n r.d.bplen(0) and\n r.d.shreg.bpld(0)(to_integer(unsigned(r.c.bplcon.pf1h)))\n );\n v.e.bplbus(i)(2) := (\n r.d.bplen(2) and\n r.d.shreg.bpld(2)(to_integer(unsigned(r.c.bplcon.pf1h)))\n );\n v.e.bplbus(i)(4) := (\n r.d.bplen(4) and\n r.d.shreg.bpld(4)(to_integer(unsigned(r.c.bplcon.pf1h)))\n );\n v.e.bplbus(i)(1) := (\n r.d.bplen(1) and\n r.d.shreg.bpld(1)(to_integer(unsigned(r.c.bplcon.pf2h)))\n );\n v.e.bplbus(i)(3) := (\n r.d.bplen(3) and\n r.d.shreg.bpld(3)(to_integer(unsigned(r.c.bplcon.pf2h)))\n );\n v.e.bplbus(i)(5) := (\n r.d.bplen(5) and\n r.d.shreg.bpld(5)(to_integer(unsigned(r.c.bplcon.pf2h)))\n );\n end if;\n end loop;\n\n -- Transform 8 individual 2-line sprites into 4 groups of 4-line sprites.\n -- Each group has the same color registers.\n for i in 0 to 3 loop\n v.e.sprbus(4*i+3) := r.d.shreg.spr(2*i+1).b(15);\n v.e.sprbus(4*i+2) := r.d.shreg.spr(2*i+1).a(15);\n v.e.sprbus(4*i+1) := r.d.shreg.spr(2*i+0).b(15);\n v.e.sprbus(4*i+0) := r.d.shreg.spr(2*i+0).a(15);\n if r.c.spr(2*i+1).att = '0' then\n -- Offset into color register space of this sprite,\n -- but only if there is a pixel.\n v.e.sprbus(4*i+3 downto 4*i+2) := std_ulogic_vector(to_unsigned(i, 2));\n if\n (r.d.shreg.spr(2*i+1).b(15) = '0') and\n (r.d.shreg.spr(2*i+1).a(15) = '0') and\n (r.d.shreg.spr(2*i+0).b(15) = '0') and\n (r.d.shreg.spr(2*i+0).a(15) = '0')\n then\n v.e.sprbus(4*i+3 downto 4*i+2) := \"00\";\n end if;\n if\n (r.d.shreg.spr(2*i).b(15) = '0') and\n (r.d.shreg.spr(2*i).a(15) = '0')\n then\n -- High priority sprite is not visible so low priority sprite wins.\n v.e.sprbus(4*i+1) := r.d.shreg.spr(2*i+1).b(15);\n v.e.sprbus(4*i+0) := r.d.shreg.spr(2*i+1).a(15);\n end if;\n end if;\n end loop;\n\n\n -- Display priority control: select between playfields 1, 2.\n -- The \"pfp\" is the selected playfield placement with respect to sprites.\n -- This thing is a bit tricky. Please see the HRM\n\n for i in 0 to 1 loop\n -- select color and priority for bitplanes\n if r.c.bplcon.pf2pri = '1' then\n -- Playfield 2 shall have priority according to BPLCON.\n -- It means our odd numbered planes have priority over our even planes.\n v.f.bplcolor(i) :=\n \"01\" & r.e.bplbus(i)(5) & r.e.bplbus(i)(3) & r.e.bplbus(i)(1);\n v.f.pfp(i) := r.c.bplcon.pf2p;\n if v.f.bplcolor(i) = \"01000\" then\n -- Playfield 2 says color index 0 so playfield 1 wins.\n v.f.bplcolor(i) :=\n \"00\" & r.e.bplbus(i)(4) & r.e.bplbus(i)(2) & r.e.bplbus(i)(0);\n v.f.pfp(i) := r.c.bplcon.pf1p;\n end if;\n else\n -- Playfield 1 shall have priority according to BPLCON.\n v.f.bplcolor(i) :=\n \"00\" & r.e.bplbus(i)(4) & r.e.bplbus(i)(2) & r.e.bplbus(i)(0);\n v.f.pfp(i) := r.c.bplcon.pf1p;\n if\n (v.f.bplcolor(i) = \"00000\") and\n ((r.e.bplbus(i)(5) or r.e.bplbus(i)(3) or r.e.bplbus(i)(1)) /= '0')\n then\n -- Playfield 1 says color index 0 so playfield 2 wins. However, if\n -- playfield 2 also selected its color index 0, then it is\n -- transparent in both playfields. In that case, either the\n -- background color or a sprite shall be visible.\n v.f.bplcolor(i) :=\n \"01\" & r.e.bplbus(i)(5) & r.e.bplbus(i)(3) & r.e.bplbus(i)(1);\n v.f.pfp(i) := r.c.bplcon.pf2p;\n end if;\n end if;\n\n if r.c.bplcon.dblpf = '0' then\n -- Dual-playfield not enabled so bypass the priority logic above.\n -- TODO: Remember bplbus(5 downto 0) and get rid of r.f.hamop?\n v.f.bplcolor(i) := r.e.bplbus(i)(4 downto 0);\n -- HRM says:\n -- \"Be careful: PF2P2 - PF2P0, bits 5-3, are priority bits for\n -- normal (non-dual) playfields.\"\n v.f.pfp(i) := r.c.bplcon.pf2p;\n end if;\n end loop;\n\n v.f.hamop := r.e.bplbus(0)(5 downto 4);\n if r.c.bplcon.dblpf = '0' then\n if r.c.bplcon.homod = '1' then\n v.f.bplcolor(0)(4) := '0';\n end if;\n end if;\n\n -- Select color and priority for sprites.\n v.f.spp := \"111\";\n v.f.sprcolor := \"0000\";\n for i in 3 downto 0 loop\n if r.e.sprbus(4*i+3 downto 4*i) /= \"0000\" then\n v.f.sprcolor := r.e.sprbus(4*i+3 downto 4*i);\n v.f.spp := std_ulogic_vector(to_unsigned(i, 3));\n end if;\n end loop;\n\n\n -- Prio between any playfield and any sprite.\n v.g.issprite := '0';\n for i in 0 to 1 loop\n if unsigned(r.f.pfp(i)) <= unsigned(r.f.spp) then\n if r.f.bplcolor(i) = \"00000\" and r.f.sprcolor /= \"0000\" then\n v.g.color(i) := '1' & r.f.sprcolor;\n if i = 0 then\n v.g.issprite := '1';\n end if;\n else\n v.g.color(i) := r.f.bplcolor(i);\n end if;\n else\n if r.f.sprcolor = \"0000\" then\n v.g.color(i) := r.f.bplcolor(i);\n else\n v.g.color(i) := '1' & r.f.sprcolor;\n if i = 0 then\n v.g.issprite := '1';\n end if;\n end if;\n end if;\n\n -- Color 0 to left and right of display window.\n if r.c.diw = '0' then\n v.g.color(i) := (others => '0');\n end if;\n end loop;\n v.g.hamop := r.f.hamop;\n\n\n -- Color lookup\n for i in 0 to 1 loop\n if isx(r.g.color(i)) then\n v.h.rgb(i) := (others => 'X');\n else\n v.h.rgb(i) := r.c.color(to_integer(unsigned(r.g.color(i))));\n end if;\n end loop;\n\n if r.g.issprite = '0' and (true or r.c.bplcon.hires = '0') then\n if r.c.bplcon.dblpf = '0' then\n if r.c.bplcon.homod = '1' then\n -- Feedback previous RGB output and use current HAM opcode.\n v.h.rgb(0) := hold_and_modify(\n v.h.rgb(0),\n r.h.rgb(0),\n r.g.hamop,\n r.g.color(0)(3 downto 0)\n );\n v.h.rgb(1) := v.h.rgb(0);\n else\n -- EHB is a right-shift of looked-up color and no RGB feedback\n if r.g.hamop(1) = '1' then\n v.h.rgb(0)(11 downto 8) := '0' & v.h.rgb(0)(11 downto 9);\n v.h.rgb(0)( 7 downto 4) := '0' & v.h.rgb(0)( 7 downto 5);\n v.h.rgb(0)( 3 downto 0) := '0' & v.h.rgb(0)( 3 downto 1);\n v.h.rgb(1) := v.h.rgb(0);\n end if;\n end if;\n end if;\n end if;\n\n for i in 0 to 1 loop\n if r.c.hblank = '1' then\n v.h.rgb(i) := (others => '0');\n end if;\n if r.c.vblank = '1' and CFG_BLANK_DURING_VBLANK then\n v.h.rgb(i) := (others => '0');\n end if;\n end loop;\n\n for i in 0 to 1 loop\n v.h.nzd(i) := '1';\n if r.g.color(i) = \"00000\" then\n v.h.nzd(i) := '0';\n end if;\n if r.c.vblank = '1' then\n v.h.nzd(i) := r.c.bplcon.gaud;\n end if;\n end loop;\n\n if CFG_STRDEBUG then\n -- debug output for various Agnus sync strobes\n if r.b.sel.strhor = '1' then v.h.rgb(0) := x\"0f0\"; end if;\n if r.b.sel.strvbl = '1' then v.h.rgb(0) := x\"f00\"; end if;\n if r.b.sel.strequ = '1' then v.h.rgb(0) := x\"00f\"; end if;\n if r.b.sel.strlong = '1' then v.h.rgb(0) := x\"f0f\"; end if;\n end if;\n\n rin <= v;\n end process;\n\n -- Update all clk7 registers for the pipeline.\n r <= rin when rising_edge(deni.clk7);\n\n -- Drive the outputs, registered.\n deno.drd <= r.drd;\n deno.drd_oe <= r.drd_oe;\n deno.rgb <= r.h.rgb;\n deno.nburst <= r.nburst;\n deno.nzd <= r.h.nzd;\n deno.drd_ext_noe <= r.drd_ext_noe;\n deno.drd_ext_to_denice <= r.drd_ext_to_denice;\n\n\n -- The mouse counter logic is independent from the pixel pipeline.\n\n joy0 : block\n begin\n -- Synchronize to clk7 domain.\n m0vs : entity work.syncer\n generic map (width => 2)\n port map (clk => deni.clk7, d => deni.m0v, q => m0v_sync);\n\n m0hs : entity work.syncer\n generic map (width => 2)\n port map (clk => deni.clk7, d => deni.m0h, q => m0h_sync);\n\n -- Decode quadrature inputs.\n q0v : entity work.joyquad\n port map (\n clk7 => deni.clk7,\n cck => deni.cck,\n mv => m0v_sync,\n wen => r.b.sel.joytest,\n wdata => r.b.drdx(15 downto 10),\n rdata => joy0daty\n );\n\n q0h : entity work.joyquad\n port map (\n clk7 => deni.clk7,\n cck => deni.cck,\n mv => m0h_sync,\n wen => r.b.sel.joytest,\n wdata => r.b.drdx( 7 downto 2),\n rdata => joy0datx\n );\n end block;\n\n joy1 : block\n begin\n m1vs : entity work.syncer\n generic map (width => 2)\n port map (clk => deni.clk7, d => deni.m1v, q => m1v_sync);\n\n m1hs : entity work.syncer\n generic map (width => 2)\n port map (clk => deni.clk7, d => deni.m1h, q => m1h_sync);\n\n q1v : entity work.joyquad\n port map (\n clk7 => deni.clk7,\n cck => deni.cck,\n mv => m1v_sync,\n wen => r.b.sel.joytest,\n wdata => r.b.drdx(15 downto 10),\n rdata => joy1daty\n );\n\n q1h : entity work.joyquad\n port map (\n clk7 => deni.clk7,\n cck => deni.cck,\n mv => m1h_sync,\n wen => r.b.sel.joytest,\n wdata => r.b.drdx( 7 downto 2),\n rdata => joy1datx\n );\n end block;\n\nend;\n\n", "groundtruth": " when \"000\" => v.d.bplen := \"000000\";\n when \"001\" => v.d.bplen := \"000001\";\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/joyquad.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse work.priv.all;\n\n-- \"mv\" is a time multiplexed input signal which carries both phases. Current\n-- phase is indicated by \"cck\".\nentity joyquad is\n port (\n clk7 : in std_ulogic;\n cck : in std_ulogic;\n mv : in std_ulogic;\n wen : in std_ulogic;\n wdata : in std_ulogic_vector(7 downto 2);\n rdata : out std_ulogic_vector(7 downto 0)\n );\nend;\n\n", "right_context": "begin\n\n process (r, cck, mv, wen, wdata)\n variable v : reg_t;\n begin\n v := r;\n -- demux the two phases\n if cck = '1' then\n v.v := mv;\n else\n v.vq := mv;\n end if;\n -- (r.vq, r.v) cycles through states \"00\", \"01\", \"11\", \"10\", or reverse\n -- (r.d1, r.d0) cycles through states \"10\", \"11\", \"00\", \"01\", or reverse\n v.d(0) := r.v xor r.vq;\n v.d(1) := not r.vq;\n if isx(std_ulogic_vector(r.d)) or isx(std_ulogic_vector(v.d)) then\n null;\n else\n -- Detect increment and decrement conditions.\n if r.d(1 downto 0) = \"11\" and v.d(1 downto 0) = \"00\" then\n v.d(7 downto 2) := r.d(7 downto 2) + 1;\n end if;\n if r.d(1 downto 0) = \"00\" and v.d(1 downto 0) = \"11\" then\n v.d(7 downto 2) := r.d(7 downto 2) - 1;\n end if;\n end if;\n\n if wen = '1' then\n -- Parallel load has been requested by user.\n v.d(wdata'range) := unsigned(wdata);\n end if;\n rdata <= std_ulogic_vector(r.d);\n\n rin <= v;\n end process;\n\n r <= rin when rising_edge(clk7);\nend;\n\n", "groundtruth": "architecture rtl of joyquad is\n type reg_t is record\n d : unsigned(7 downto 0);\n v : std_ulogic;\n vq : std_ulogic;\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/ocs.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\n-- Definitions for Amiga custom chipset.\npackage ocs is\n subtype addr_t is std_ulogic_vector(11 downto 0);\n subtype word_t is std_ulogic_vector(15 downto 0);\n subtype rgb4_t is std_ulogic_vector(11 downto 0);\n subtype byte_t is std_ulogic_vector( 7 downto 0);\n subtype rga_t is std_ulogic_vector( 8 downto 1);\n type rgb4_array_t is array (integer range <>) of rgb4_t;\n type word_array_t is array (integer range <>) of word_t;\n type byte_array_t is array (integer range <>) of byte_t;\n\n constant RGA_STRHOR : addr_t := x\"03C\";\n", "right_context": " constant RGA_DIWSTOP : addr_t := x\"090\";\n constant RGA_JOY0DAT : addr_t := x\"00A\";\n constant RGA_JOY1DAT : addr_t := x\"00C\";\n constant RGA_JOYTEST : addr_t := x\"036\";\n constant RGA_BPLCON0 : addr_t := x\"100\";\n constant RGA_BPLCON1 : addr_t := x\"102\";\n constant RGA_BPLCON2 : addr_t := x\"104\";\n\n constant RGA_BPL1DAT : addr_t := x\"110\";\n constant RGA_BPL2DAT : addr_t := x\"112\";\n constant RGA_BPL3DAT : addr_t := x\"114\";\n constant RGA_BPL4DAT : addr_t := x\"116\";\n constant RGA_BPL5DAT : addr_t := x\"118\";\n constant RGA_BPL6DAT : addr_t := x\"11A\";\n\n constant RGA_COLOR00 : addr_t := x\"180\";\n constant RGA_COLOR01 : addr_t := x\"182\";\n constant RGA_COLOR02 : addr_t := x\"184\";\n constant RGA_COLOR03 : addr_t := x\"186\";\n constant RGA_COLOR04 : addr_t := x\"188\";\n constant RGA_COLOR05 : addr_t := x\"18A\";\n constant RGA_COLOR06 : addr_t := x\"18C\";\n constant RGA_COLOR07 : addr_t := x\"18E\";\n\n type denise_in_t is record\n clk7 : std_ulogic;\n cck : std_ulogic;\n rga : std_ulogic_vector( 8 downto 1);\n drd : std_ulogic_vector(15 downto 0);\n m0v : std_ulogic;\n m0h : std_ulogic;\n m1v : std_ulogic;\n m1h : std_ulogic;\n ncsync : std_ulogic;\n ncdac : std_ulogic;\n end record;\n\n type denise_out_t is record\n drd : std_ulogic_vector(15 downto 0);\n drd_oe : std_ulogic;\n rgb : rgb4_array_t(0 to 1);\n nzd : std_ulogic_vector(0 to 1);\n nburst : std_ulogic;\n\n -- external bus driver control\n drd_ext_noe : std_ulogic;\n drd_ext_to_denice : std_ulogic;\n end record;\nend;\n\n", "groundtruth": " constant RGA_DIWSTRT : addr_t := x\"08E\";\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/portable/inferred/oddr.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\n", "right_context": " d0 : in std_ulogic;\n d1 : in std_ulogic;\n q : out std_ulogic\n );\nend;\n\n-- FPGA-TN-02065-1-0, Figure 2.1\narchitecture rtl of oddr is\n signal q0 : std_ulogic;\n signal q1 : std_ulogic;\n signal d1s : std_ulogic;\nbegin\n q0 <= d0 when rising_edge(clk);\n d1s <= d1 when rising_edge(clk);\n q1 <= d1s when falling_edge(clk);\n\n q <= q0 when clk = '0' else q1;\nend;\n\n", "groundtruth": "entity oddr is\n port (\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/portable/machxo3d/oddr.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nlibrary machxo3d;\nuse machxo3d.components;\n\nentity oddr is\n port (\n clk : in std_ulogic;\n d0 : in std_ulogic;\n", "right_context": " r : component components.oddrxe\n port map (\n d0 => d0,\n d1 => d1,\n sclk => clk,\n rst => '0',\n q => q\n );\nend;\n\n", "groundtruth": " d1 : in std_ulogic;\n q : out std_ulogic\n );\nend;\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/priv.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse work.ocs.all;\n\n-- Definitions for Denise implementation\npackage priv is\n\n -- Represent one hardware sprite\n type sprite_reg_t is record\n en : std_ulogic;\n att : std_ulogic;\n sh : std_ulogic_vector(8 downto 0);\n data : word_t;\n datb : word_t;\n end record;\n type sprite_reg_array_t is array (integer range <>) of sprite_reg_t;\n\n type sel_sprite_t is record\n pos : std_ulogic; -- --2 W\n ctl : std_ulogic; -- --4 W\n data : std_ulogic; -- --6 W\n datb : std_ulogic; -- --8 W\n end record;\n constant SEL_SPRITE_NONE : sel_sprite_t := (\n pos => '0',\n ctl => '0',\n data => '0',\n datb => '0'\n );\n type sel_sprite_array_t is array (natural range <>) of sel_sprite_t;\n\n -- All register select targets\n type sel_t is record\n joy0dat : std_ulogic; -- 00A R\n joy1dat : std_ulogic; -- 00C R\n clxdat : std_ulogic; -- 00E R\n joytest : std_ulogic; -- 036 W\n strequ : std_ulogic; -- 038 S\n strvbl : std_ulogic; -- 03A S\n strhor : std_ulogic; -- 03C S\n strlong : std_ulogic; -- 03E S\n diwstrt : std_ulogic; -- 08E S\n diwstop : std_ulogic; -- 090 S\n clxcon : std_ulogic; -- 098 W\n bplcon0 : std_ulogic; -- 100 W\n bplcon1 : std_ulogic; -- 102 W\n bplcon2 : std_ulogic; -- 104 W\n bpldat : std_ulogic_vector(0 to 5); -- 110..11A W\n spr : sel_sprite_array_t(0 to 7); -- 140..17E W\n colorx : std_ulogic;\n color : std_ulogic_vector(0 to 31); -- 180..1BE W\n end record;\n constant SEL_NONE : sel_t := (\n joy0dat => '0',\n joy1dat => '0',\n clxdat => '0',\n joytest => '0',\n strequ => '0',\n strvbl => '0',\n strhor => '0',\n strlong => '0',\n diwstrt => '0',\n diwstop => '0',\n clxcon => '0',\n bplcon0 => '0',\n bplcon1 => '0',\n bplcon2 => '0',\n bpldat => (others => '0'),\n spr => (others => SEL_SPRITE_NONE),\n colorx => '0',\n color => (others => '0')\n );\n\n -- register address decoder\n function gen_sel(\n rga : rga_t\n ) return sel_t;\n\n -- return: clxdat\n function collision_detection_logic(\n sprbus : std_ulogic_vector(15 downto 0);\n bplbus : std_ulogic_vector( 5 downto 0);\n clxcon : std_ulogic_vector(15 downto 0)\n ) return std_ulogic_vector;\n\n -- Either normal color selection procedure, or replace R/G/B bits.\n -- return: new rgb\n function hold_and_modify(\n normal : rgb4_t;\n left : rgb4_t;\n op : std_ulogic_vector(1 downto 0);\n replace : std_ulogic_vector(3 downto 0)\n ) return rgb4_t;\n\n function isx(\n v : std_ulogic_vector\n ) return boolean;\n\nend;\n\npackage body priv is\n function gen_sel(\n rga : rga_t\n ) return sel_t\n is\n variable a : std_ulogic_vector(11 downto 0) := \"000\" & rga & \"0\";\n variable s : sel_t := SEL_NONE;\n begin\n if isx(a) then\n return s;\n end if;\n case a is\n when x\"00A\" => s.joy0dat := '1';\n when x\"00C\" => s.joy1dat := '1';\n when x\"036\" => s.joytest := '1';\n when x\"00E\" => s.clxdat := '1';\n when x\"098\" => s.clxcon := '1';\n when x\"038\" => s.strequ := '1';\n when x\"03A\" => s.strvbl := '1';\n when x\"03C\" => s.strhor := '1';\n when x\"03E\" => s.strlong := '1';\n when x\"08E\" => s.diwstrt := '1';\n when x\"090\" => s.diwstop := '1';\n when x\"100\" => s.bplcon0 := '1';\n when x\"102\" => s.bplcon1 := '1';\n when x\"104\" => s.bplcon2 := '1';\n when x\"110\" => s.bpldat(0) := '1';\n when x\"112\" => s.bpldat(1) := '1';\n when x\"114\" => s.bpldat(2) := '1';\n when x\"116\" => s.bpldat(3) := '1';\n when x\"118\" => s.bpldat(4) := '1';\n when x\"11A\" => s.bpldat(5) := '1';\n\n when x\"140\" => s.spr(0).pos := '1';\n when x\"142\" => s.spr(0).ctl := '1';\n when x\"144\" => s.spr(0).data:= '1';\n when x\"146\" => s.spr(0).datb:= '1';\n when x\"148\" => s.spr(1).pos := '1';\n when x\"14A\" => s.spr(1).ctl := '1';\n when x\"14C\" => s.spr(1).data:= '1';\n when x\"14E\" => s.spr(1).datb:= '1';\n\n when x\"150\" => s.spr(2).pos := '1';\n when x\"152\" => s.spr(2).ctl := '1';\n when x\"154\" => s.spr(2).data:= '1';\n", "right_context": " when x\"158\" => s.spr(3).pos := '1';\n when x\"15A\" => s.spr(3).ctl := '1';\n when x\"15C\" => s.spr(3).data:= '1';\n when x\"15E\" => s.spr(3).datb:= '1';\n\n when x\"160\" => s.spr(4).pos := '1';\n when x\"162\" => s.spr(4).ctl := '1';\n when x\"164\" => s.spr(4).data:= '1';\n when x\"166\" => s.spr(4).datb:= '1';\n when x\"168\" => s.spr(5).pos := '1';\n when x\"16A\" => s.spr(5).ctl := '1';\n when x\"16C\" => s.spr(5).data:= '1';\n when x\"16E\" => s.spr(5).datb:= '1';\n\n when x\"170\" => s.spr(6).pos := '1';\n when x\"172\" => s.spr(6).ctl := '1';\n when x\"174\" => s.spr(6).data:= '1';\n when x\"176\" => s.spr(6).datb:= '1';\n when x\"178\" => s.spr(7).pos := '1';\n when x\"17A\" => s.spr(7).ctl := '1';\n when x\"17C\" => s.spr(7).data:= '1';\n when x\"17E\" => s.spr(7).datb:= '1';\n\n when x\"180\" => s.color( 0) := '1';\n when x\"182\" => s.color( 1) := '1';\n when x\"184\" => s.color( 2) := '1';\n when x\"186\" => s.color( 3) := '1';\n when x\"188\" => s.color( 4) := '1';\n when x\"18A\" => s.color( 5) := '1';\n when x\"18C\" => s.color( 6) := '1';\n when x\"18E\" => s.color( 7) := '1';\n when x\"190\" => s.color( 8) := '1';\n when x\"192\" => s.color( 9) := '1';\n when x\"194\" => s.color(10) := '1';\n when x\"196\" => s.color(11) := '1';\n when x\"198\" => s.color(12) := '1';\n when x\"19A\" => s.color(13) := '1';\n when x\"19C\" => s.color(14) := '1';\n when x\"19E\" => s.color(15) := '1';\n when x\"1A0\" => s.color(16) := '1';\n when x\"1A2\" => s.color(17) := '1';\n when x\"1A4\" => s.color(18) := '1';\n when x\"1A6\" => s.color(19) := '1';\n when x\"1A8\" => s.color(20) := '1';\n when x\"1AA\" => s.color(21) := '1';\n when x\"1AC\" => s.color(22) := '1';\n when x\"1AE\" => s.color(23) := '1';\n when x\"1B0\" => s.color(24) := '1';\n when x\"1B2\" => s.color(25) := '1';\n when x\"1B4\" => s.color(26) := '1';\n when x\"1B6\" => s.color(27) := '1';\n when x\"1B8\" => s.color(28) := '1';\n when x\"1BA\" => s.color(29) := '1';\n when x\"1BC\" => s.color(30) := '1';\n when x\"1BE\" => s.color(31) := '1';\n when others =>\n null;\n end case;\n if (a and \"0001\" & \"1100\" & \"0000\") = \"0001\" & \"1000\" & \"0000\" then\n s.colorx := '1';\n end if;\n return s;\n end;\n\n\n -- BIT# COLLISIONS REGISTERED\n -- ----- --------------------------\n -- 15 not used\n -- 14 Sprite 4 (or 5) to sprite 6 (or 7)\n -- 13 Sprite 2 (or 3) to sprite 6 (or 7)\n -- 12 Sprite 2 (or 3) to sprite 4 (or 5)\n -- 11 Sprite 0 (or 1) to sprite 6 (or 7)\n -- 10 Sprite 0 (or 1) to sprite 4 (or 5)\n -- 09 Sprite 0 (or 1) to sprite 2 (or 3)\n -- 08 Playfield 2 to sprite 6 (or 7)\n -- 07 Playfield 2 to sprite 4 (or 5)\n -- 06 Playfield 2 to sprite 2 (or 3)\n -- 05 Playfield 2 to sprite 0 (or 1)\n -- 04 Playfield 1 to sprite 6 (or 7)\n -- 03 Playfield 1 to sprite 4 (or 5)\n -- 02 Playfield 1 to sprite 2 (or 3)\n -- 01 Playfield 1 to sprite 0 (or 1)\n -- 00 Playfield 1 to playfield 2\n\n -- return: false iff sprite pixel is transparent\n function spren(\n sprbus : std_ulogic_vector(15 downto 0);\n i : natural range 0 to 7\n ) return boolean is\n begin\n return sprbus(2*i + 1 downto 2*i) /= \"00\";\n end;\n\n function collision_detection_logic(\n sprbus : std_ulogic_vector(15 downto 0);\n bplbus : std_ulogic_vector( 5 downto 0);\n clxcon : std_ulogic_vector(15 downto 0)\n ) return std_ulogic_vector is\n variable ret : std_ulogic_vector(14 downto 0) := (others => '0');\n variable spr01 : boolean;\n variable spr23 : boolean;\n variable spr45 : boolean;\n variable spr67 : boolean;\n variable even_bpls : boolean;\n variable odd_bpls : boolean;\n begin\n spr01 := spren(sprbus, 0) or (spren(sprbus, 1) and clxcon(12) = '1');\n spr23 := spren(sprbus, 2) or (spren(sprbus, 3) and clxcon(13) = '1');\n spr45 := spren(sprbus, 4) or (spren(sprbus, 5) and clxcon(14) = '1');\n spr67 := spren(sprbus, 6) or (spren(sprbus, 7) and clxcon(15) = '1');\n -- \"even\" in documentation is with 1-based indexing. We use 0-based.\n even_bpls := (\n (clxcon(6+1) = '0' or (bplbus(1) = clxcon(1))) and\n (clxcon(6+3) = '0' or (bplbus(3) = clxcon(3))) and\n (clxcon(6+5) = '0' or (bplbus(5) = clxcon(5)))\n );\n odd_bpls := (\n (clxcon(6+0) = '0' or (bplbus(0) = clxcon(0))) and\n (clxcon(6+2) = '0' or (bplbus(2) = clxcon(2))) and\n (clxcon(6+4) = '0' or (bplbus(4) = clxcon(4)))\n );\n if spr45 and spr67 then ret(14) := '1'; end if;\n if spr23 and spr67 then ret(13) := '1'; end if;\n if spr23 and spr45 then ret(12) := '1'; end if;\n if spr01 and spr67 then ret(11) := '1'; end if;\n if spr01 and spr45 then ret(10) := '1'; end if;\n if spr01 and spr23 then ret( 9) := '1'; end if;\n if even_bpls and spr67 then ret( 8) := '1'; end if;\n if even_bpls and spr45 then ret( 7) := '1'; end if;\n if even_bpls and spr23 then ret( 6) := '1'; end if;\n if even_bpls and spr01 then ret( 5) := '1'; end if;\n if odd_bpls and spr67 then ret( 4) := '1'; end if;\n if odd_bpls and spr45 then ret( 3) := '1'; end if;\n if odd_bpls and spr23 then ret( 2) := '1'; end if;\n if odd_bpls and spr01 then ret( 1) := '1'; end if;\n if even_bpls and odd_bpls then ret( 0) := '1'; end if;\n return ret;\n end;\n\n -- return: rgb\n function hold_and_modify(\n normal : rgb4_t;\n left : rgb4_t;\n op : std_ulogic_vector(1 downto 0);\n replace : std_ulogic_vector(3 downto 0)\n ) return rgb4_t is\n variable ret : rgb4_t;\n begin\n ret := left;\n case op is\n when \"00\" => ret := normal; -- normal color selection procedure\n when \"01\" => ret( 3 downto 0) := replace; -- blue bits\n when \"10\" => ret( 7 downto 4) := replace; -- green bits\n when others => ret(11 downto 8) := replace; -- red bits\n end case;\n return ret;\n end;\n\n function isx(\n v : std_ulogic_vector\n ) return boolean is\n begin\n if\n-- pragma translate_off\n is_x(v) or\n-- pragma translate_on\n false\n then\n return true;\n end if;\n return false;\n end;\n\nend;\n\n", "groundtruth": " when x\"156\" => s.spr(2).datb:= '1';\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/sim/rga_bfm.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\n-- Bus Functional Model for RGA bus\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse work.ocs.all;\nuse work.text.all;\n\npackage rga_bfm is\n type rga_op is (\n IDLE,\n READ,\n WRITE\n );\n\n type rga_log is (LOG_FAIL, LOG_ERROR, LOG_INFO, LOG_DEBUG);\n type rga_cmd is record\n op : rga_op;\n addr : std_logic_vector(11 downto 0);\n wdata : std_logic_vector(15 downto 0);\n rdata : std_logic_vector(15 downto 0);\n req : std_logic;\n ack : std_logic;\n log : rga_log;\n end record;\n\n signal rgacmd : rga_cmd := (\n op => IDLE,\n addr => (others => 'X'),\n wdata => (others => 'X'),\n rdata => (others => 'Z'),\n req => '0',\n ack => 'Z',\n log => LOG_INFO\n );\n\n procedure rga_loglevel (\n signal cmd : inout rga_cmd;\n constant level : rga_log\n );\n\n procedure dbg (constant cmd : rga_cmd; str : string);\n procedure info(constant cmd : rga_cmd; str : string);\n procedure fail(constant cmd : rga_cmd; str : string);\n\n procedure rga_write (\n signal cmd : inout rga_cmd;\n constant addr : in addr_t;\n constant data : in word_t\n );\n\n procedure rga_read (\n signal cmd : inout rga_cmd;\n constant addr : in addr_t;\n variable data : out word_t\n );\n\nend;\n\npackage body rga_bfm is\n\n procedure dbg(constant cmd : rga_cmd; str : string) is\n begin\n", "right_context": " puts(\"DEBUG RGA: \" & str);\n end;\n\n procedure info(constant cmd : rga_cmd; str : string) is\n begin\n if cmd.log < LOG_INFO then return; end if;\n puts(\"INFO RGA: \" & str);\n end;\n\n procedure fail(constant cmd : rga_cmd; str : string) is\n begin\n report \"FAIL RGA: \" & str severity failure;\n end;\n\n procedure rga_loglevel (\n signal cmd : inout rga_cmd;\n constant level : rga_log\n ) is\n begin\n cmd.log <= level;\n end;\n\n procedure rga_begin (\n signal cmd : inout rga_cmd\n ) is\n begin\n cmd.req <= '1';\n wait for 0 ns;\n if cmd.ack /= '1' then\n wait until cmd.ack = '1';\n end if;\n end;\n\n procedure rga_end (\n signal cmd : inout rga_cmd\n ) is\n begin\n cmd.req <= '0';\n wait for 0 ns;\n if cmd.ack /= '0' then\n wait until cmd.ack = '0';\n end if;\n end;\n\n procedure rga_write (\n signal cmd : inout rga_cmd;\n constant addr : in addr_t;\n constant data : in word_t\n ) is\n begin\n cmd.addr <= addr;\n cmd.wdata <= data;\n cmd.op <= WRITE;\n\n rga_begin(cmd);\n rga_end(cmd);\n dbg(cmd, \"write $\" & to_hstring(addr) & \" <- $\" & to_hstring(data));\n end;\n\n procedure rga_read (\n signal cmd : inout rga_cmd;\n constant addr : in addr_t;\n variable data : out word_t\n ) is\n begin\n cmd.addr <= addr;\n cmd.op <= READ;\n\n rga_begin(cmd);\n rga_end(cmd);\n data := cmd.rdata;\n\n dbg(cmd, \"read $\" & to_hstring(addr) & \" -> $\" & to_hstring(data));\n end;\n\nend;\n\n", "groundtruth": " if cmd.log < LOG_DEBUG then return; end if;\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/sim/rga_bfm_impl.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse work.rga_bfm.all;\nuse work.ocs.all;\nuse work.text.all;\n\nentity rga_bfm_impl is\n port (\n clk7 : in std_ulogic;\n cck : in std_ulogic;\n deni : out denise_in_t;\n deno : in denise_out_t\n );\nend;\n\narchitecture beh of rga_bfm_impl is\nbegin\n process\n begin\n info(rgacmd, \"power-on\");\n deni.drd <= (others => 'Z');\n deni.rga <= (others => '1');\n wait until rising_edge(cck);\n wait until rising_edge(cck);\n\n for i in 2 to 9 loop\n wait until rising_edge(cck);\n end loop;\n\n info(rgacmd, \"power-up reset done\");\n\n -- Main loop Ready to take BFM commands\n loop\n if rgacmd.req /= '1' then\n wait until rgacmd.req = '1';\n end if;\n rgacmd.ack <= '1';\n wait for 0 ns;\n\n case rgacmd.op is\n when WRITE|READ =>\n wait until rising_edge(cck);\n wait for 110 ns - 70 ns;\n deni.rga <= rgacmd.addr(8 downto 1);\n wait until falling_edge(cck);\n wait for 10 ns;\n deni.rga <= (others => '1');\n\n wait for 40 ns;\n if rgacmd.op = WRITE then\n deni.drd <= rgacmd.wdata;\n end if;\n wait until rising_edge(cck);\n if rgacmd.op = WRITE then\n", "right_context": " when others =>\n fail(rgacmd, \"Unimplemented operation: \" & rga_op'image(rgacmd.op));\n\n end case;\n rgacmd.ack <= '0';\n wait for 0 ns;\n while rgacmd.req = '1' loop\n end loop;\n end loop;\n end process;\n\n deni.clk7 <= clk7;\n deni.cck <= cck;\n deni.m0v <= '0';\n deni.m0h <= '0';\n deni.m1v <= '0';\n deni.m1h <= '0';\n deni.ncsync <= 'X';\n deni.ncdac <= 'X';\nend;\n\n", "groundtruth": " deni.drd <= (others => 'Z') after 20 ns;\n else\n rgacmd.rdata <= deno.drd;\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/sim/tb.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse work.tbtest.all;\nlibrary ocs;\nuse ocs.ocs.all;\nuse ocs.text.all;\n\n", "right_context": "architecture beh of tb is\n constant CCK_PERIOD : time := 280 ns;\n signal clk7 : std_ulogic := '0';\n signal cck : std_ulogic := '0';\n signal deni : denise_in_t;\n signal deno : denise_out_t;\n\n signal drd : std_logic_vector (15 downto 0);\nbegin\n\n rga_bfm0 : entity ocs.rga_bfm_impl\n port map (\n -- clocks are driven out on deni\n clk7 => clk7,\n cck => cck,\n deni => deni,\n deno => deno\n );\n\n deno.drd <= drd;\n drd <= deni.drd;\n\n dut : entity ocs.top\n port map (\n clk7 => clk7,\n cck => cck,\n rga => deni.rga,\n drd => drd,\n m0v => deni.m0v,\n m0h => deni.m0h,\n m1v => deni.m1v,\n m1h => deni.m1h,\n ncsync => 'X',\n ncdac => 'X'\n );\n\n stim_cck : process\n begin\n if end_of_simulation then\n -- may have PLL or similar running so force stop\n -- std.env.stop(0);\n wait;\n else\n cck <= '0';\n wait for CCK_PERIOD / 2;\n cck <= '1';\n wait for CCK_PERIOD / 2;\n end if;\n end process;\n\n stim_7m : process\n begin\n wait for 15 ns;\n loop\n if end_of_simulation then\n wait;\n else\n clk7 <= '0';\n wait for CCK_PERIOD / 4;\n clk7 <= '1';\n wait for CCK_PERIOD / 4;\n end if;\n end loop;\n end process;\n\n tc: component testcode;\n\n confinfo : process\n begin\n ocs.text.puts(\"sysfreq: \" & integer'image((1000.0 us) / CCK_PERIOD) & \" KHz\");\n ocs.text.puts(\"period: \" & time'image(CCK_PERIOD));\n ocs.text.puts(\"--- simulation begin\");\n wait until end_of_simulation;\n wait for 0 ns;\n ocs.text.puts(\"--- simulation end\");\n wait;\n end process;\nend;\n\n", "groundtruth": "entity tb is\nend;\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/sim/tbtest.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\npackage tbtest is\n component testcode\n end component;\n\n signal end_of_simulation : boolean := false;\nend;\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nlibrary ocs;\nuse ocs.ocs.all;\nuse ocs.rga_bfm.all;\nuse work.tbtest.all;\n\n", "right_context": "", "groundtruth": "entity test is\nend;\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/sim/text.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse std.textio.all;\n\npackage text is\n procedure puts(constant s : in string);\nend;\n\npackage body text is\n procedure puts(constant s : in string) is\n", "right_context": " begin\n write(l, s);\n writeline(output, l);\n end;\nend;\n\n", "groundtruth": " variable l : line;\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/syncer.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity syncer is\n generic (\n width : positive := 2\n );\n port (\n clk : in std_ulogic;\n d : in std_ulogic;\n", "right_context": " );\nend;\n\narchitecture rtl of syncer is\n signal rlev0_async, rlev1_async : std_ulogic;\n signal r : std_ulogic_vector(width-1 downto 0);\n\nbegin\n r0 : process(clk)\n begin\n if rising_edge(clk) then\n rlev0_async <= d;\n rlev1_async <= rlev0_async;\n end if;\n end process;\n\n many : if 2 < width generate\n r1 : process(clk)\n begin\n if rising_edge(clk) then\n r <= r(r'high-1 downto 0) & rlev1_async;\n end if;\n end process;\n end generate;\n\n q <= rlev1_async when width <= 2 else r(r'high);\nend;\n\n", "groundtruth": " q : out std_ulogic\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/test/joy0.vhdl", "left_context": "architecture joy0 of test is\nbegin\n process\n variable data0 : word_t;\n begin\n rga_loglevel(rgacmd, LOG_DEBUG);\n wait for 1 us;\n rga_write(rgacmd, RGA_STRHOR, x\"cafe\");\n", "right_context": " rga_write(rgacmd, RGA_DIWSTOP, x\"f4c1\");\n rga_write(rgacmd, RGA_BPLCON0, x\"2000\");\n rga_write(rgacmd, RGA_BPLCON1, x\"0022\");\n wait for 8 us;\n\n rga_read (rgacmd, RGA_JOY0DAT, data0);\n rga_write(rgacmd, RGA_JOYTEST, x\"55aa\");\n rga_read (rgacmd, RGA_JOY0DAT, data0);\n assert data0(15 downto 10) = \"010101\";\n assert data0( 7 downto 2) = \"101010\";\n\n wait for 3 us;\n end_of_simulation <= true;\n wait;\n end process;\nend;\n\nconfiguration joy0 of tb is\n for beh for tc: testcode\n use entity work.test(joy0);\n end for; end for;\nend;\n\n", "groundtruth": " rga_write(rgacmd, RGA_DIWSTRT, x\"2c81\");\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/test/wb0.vhdl", "left_context": "architecture wb0 of test is\nbegin\n process\n begin\n rga_loglevel(rgacmd, LOG_DEBUG);\n wait for 1 us;\n rga_write(rgacmd, RGA_STRHOR, x\"cafe\");\n rga_write(rgacmd, RGA_DIWSTRT, x\"2c81\");\n rga_write(rgacmd, RGA_DIWSTOP, x\"f4c1\");\n rga_write(rgacmd, RGA_BPLCON0, x\"2000\");\n rga_write(rgacmd, RGA_BPLCON1, x\"0022\");\n wait for 8 us;\n", "right_context": " rga_write(rgacmd, RGA_COLOR06, x\"0666\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n rga_write(rgacmd, RGA_BPL2DAT, x\"3c33\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n rga_write(rgacmd, RGA_BPL1DAT, x\"5555\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n rga_write(rgacmd, RGA_BPL2DAT, x\"0f30\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n rga_write(rgacmd, RGA_BPL1DAT, x\"0f50\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n wait for 1 us;\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n rga_write(rgacmd, RGA_BPL2DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n rga_write(rgacmd, RGA_BPL1DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n rga_write(rgacmd, RGA_BPL2DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n rga_write(rgacmd, RGA_BPL1DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n rga_write(rgacmd, RGA_BPL2DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n rga_write(rgacmd, RGA_BPL1DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n rga_write(rgacmd, RGA_BPL2DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n rga_write(rgacmd, RGA_BPL1DAT, x\"aaaa\");\n rga_write(rgacmd, RGA_COLOR07, x\"0777\");\n\n wait for 8*10 us;\n\n wait for 3 us;\n end_of_simulation <= true;\n wait;\n end process;\nend;\n\nconfiguration wb0 of tb is\n for beh for tc: testcode\n use entity work.test(wb0);\n end for; end for;\nend;\n\n", "groundtruth": "\n rga_write(rgacmd, RGA_COLOR00, x\"0000\");\n rga_write(rgacmd, RGA_COLOR01, x\"0111\");\n rga_write(rgacmd, RGA_COLOR02, x\"0222\");\n", "crossfile_context": ""} {"task_id": "deniser", "path": "deniser/hdl/top.vhdl", "left_context": "-- Copyright (C) 2020-2021 Martin ƅberg\n--\n-- This program is free software; you can redistribute it and/or modify\n-- it under the terms of the GNU General Public License as published by\n-- the Free Software Foundation; either version 2 of the License, or\n-- (at your option) any later version.\n--\n-- This program is distributed in the hope that it will be useful,\n-- but WITHOUT ANY WARRANTY; without even the implied warranty of\n-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n-- GNU General Public License for more details.\n--\n-- You should have received a copy of the GNU General Public License along\n-- with this program; if not, write to the Free Software Foundation, Inc.,\n-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n--\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nlibrary ocs;\n\n-- Technology-independent top level\nentity top is\n port (\n -- 7.15909 MHz\n clk7 : in std_ulogic;\n -- Color clock\n cck : in std_ulogic;\n rga : in std_ulogic_vector( 8 downto 1);\n drd : inout std_ulogic_vector(15 downto 0);\n video_r : out std_ulogic_vector( 3 downto 0);\n video_b : out std_ulogic_vector( 3 downto 0);\n video_g : out std_ulogic_vector( 3 downto 0);\n", "right_context": " m1h : in std_ulogic;\n\n -- Color burst, only for color composite\n nburst : out std_ulogic;\n -- \"PIXELSW\", \"Background indicator\", \"zero detect\", to RGB port\n nzd : out std_ulogic;\n\n -- Composite sync (ECS)\n ncsync : in std_ulogic;\n -- CDAC (ECS)\n ncdac : in std_ulogic;\n\n -- external bus driver control\n drd_noe : out std_ulogic;\n drd_rl_to_fpga : out std_ulogic;\n\n user0 : inout std_ulogic;\n user1 : inout std_ulogic;\n led0 : out std_ulogic\n );\nend;\n\narchitecture rtl of top is\n signal deni : work.ocs.denise_in_t;\n signal deno : work.ocs.denise_out_t;\n\nbegin\n den0 : entity ocs.denise\n port map (\n deni => deni,\n deno => deno\n );\n\n\n -- Connect the inputs\n\n deni.clk7 <= clk7;\n deni.cck <= cck;\n deni.rga <= rga;\n deni.drd <= drd;\n deni.m0v <= m0v;\n deni.m0h <= m0h;\n deni.m1v <= m1v;\n deni.m1h <= m1h;\n deni.ncsync <= ncsync;\n deni.ncdac <= ncdac;\n\n\n -- Drive the outputs\n\n drd <= deno.drd when deno.drd_oe = '1' else \"ZZZZZZZZZZZZZZZZ\";\n drd_noe <= deno.drd_ext_noe;\n drd_rl_to_fpga <= deno.drd_ext_to_denice;\n nburst <= deno.nburst;\n\n -- All logic is clocked in the clk7 domain which corresponds to lores pixel\n -- resolution. DDR output registers are used to emit hires RGB pixels.\n vidx : for i in 0 to 3 generate\n r : entity ocs.oddr\n port map (\n d0 => deno.rgb(0)(8+i),\n d1 => deno.rgb(1)(8+i),\n clk => clk7,\n q => video_r(i)\n );\n\n g : entity ocs.oddr\n port map (\n d0 => deno.rgb(0)(4+i),\n d1 => deno.rgb(1)(4+i),\n clk => clk7,\n q => video_g(i)\n );\n\n b : entity ocs.oddr\n port map (\n d0 => deno.rgb(0)(0+i),\n d1 => deno.rgb(1)(0+i),\n clk => clk7,\n q => video_b(i)\n );\n end generate;\n\n vidnzd : entity ocs.oddr\n port map (\n d0 => deno.nzd(0),\n d1 => deno.nzd(1),\n clk => clk7,\n q => nzd\n );\n\n\n -- Set low brightness on user LED when clk7 is available.\n\n blinkz : block\n signal cnt : unsigned(15 downto 0) := (others => '0');\n begin\n cnt <= cnt + 1 when rising_edge(clk7);\n led0 <= '0' when cnt(cnt'high downto cnt'high-4) = \"1111\" else '1';\n end block;\n\nend;\n\n", "groundtruth": " m0v : in std_ulogic;\n m0h : in std_ulogic;\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/env_c.vhdl", "left_context": "package ENV is\n\n procedure STOP (STATUS : INTEGER);\n procedure FINISH (STATUS : INTEGER);\n\n function RESOLUTION_LIMIT return DELAY_LENGTH;\n\nend package ENV;\nlibrary ieee_proposed;\nuse ieee_proposed.standard_additions.all;\npackage body ENV is\n\n procedure STOP (STATUS : INTEGER) is\n", "right_context": " begin\n report \"Procedure FINISH called with status: \" & INTEGER'image(STATUS)\n severity failure;\n end procedure FINISH;\n\n constant BASE_TIME_ARRAY : time_vector :=\n (\n 1 fs, 10 fs, 100 fs,\n 1 ps, 10 ps, 100 ps,\n 1 ns, 10 ns, 100 ns,\n 1 us, 10 us, 100 us,\n 1 ms, 10 ms, 100 ms,\n 1 sec, 10 sec, 100 sec,\n 1 min, 10 min, 100 min,\n 1 hr, 10 hr, 100 hr\n ) ;\n\n function RESOLUTION_LIMIT return DELAY_LENGTH is\n begin\n for i in BASE_TIME_ARRAY'range loop\n if BASE_TIME_ARRAY(i) > 0 hr then\n return BASE_TIME_ARRAY(i);\n end if;\n end loop;\n report \"STANDATD.RESOLUTION_LIMIT: Simulator resolution not less than 100 hr\"\n severity failure;\n return 1 ns;\n end function RESOLUTION_LIMIT;\n\nend package body ENV;\n", "groundtruth": " begin\n report \"Procedure STOP called with status: \" & INTEGER'image(STATUS)\n severity failure;\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/fixed_float_types_c.vhdl", "left_context": "-- --------------------------------------------------------------------\n-- \"fixed_float_types\" package contains types used in the fixed and floating\n-- point packages..\n-- Please see the documentation for the floating point package.\n-- This package should be compiled into \"ieee_proposed\" and used as follows:\n--\n-- This verison is designed to work with the VHDL-93 compilers. Please\n-- note the \"%%%\" comments. These are where we diverge from the\n-- VHDL-200X LRM.\n--\n-- --------------------------------------------------------------------\n-- Version : $Revision: 1.21 $\n-- Date : $Date: 2007-09-11 14:52:13-04 $\n-- --------------------------------------------------------------------\n\npackage fixed_float_types is\n\n -- Types used for generics of fixed_generic_pkg\n \n type fixed_round_style_type is (fixed_round, fixed_truncate);\n \n type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);\n\n -- Type used for generics of float_generic_pkg\n\n -- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,\n -- and FE_TOWARDZERO floating point rounding macros.\n\n", "right_context": " round_inf, -- Round toward positive infinity\n round_neginf, -- Round toward negative infinity\n round_zero); -- Round toward zero (truncate)\n\nend package fixed_float_types;\n", "groundtruth": " type round_type is (round_nearest, -- Default, nearest LSB '0'\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/fixed_noresize.vhdl", "left_context": "-------------------------------------------------------------------------------\n--* Filename & Ext : fixed_noresize.vhdl\n--* Author : \n--* Created : 2006-08-29\n--* Last modified : $Date: 2006-08-31 09:20:58-04 $\n--* Description : fixed noresize package. This package uses the same\n--* : logic as the \"fixed_pkg\", however it uses the sizing\n--* : rules of numeric_std.\n--* Known Bugs :\n--*\n--* RCS Summary : $Id: fixed_noresize.vhdl,v 1.2 2006-08-31 09:20:58-04 l435385 Exp l435385 $\n--* :\n--* Mod History : $Log: fixed_noresize.vhdl,v $\n--* Mod History : Revision 1.2 2006-08-31 09:20:58-04 l435385\n--* Mod History : Added several comments\n--* Mod History :\n--* Mod History : Revision 1.1 2006-08-30 15:36:15-04 l435385\n--* Mod History : Initial revision\n--* Mod History :\n--* :\n-------------------------------------------------------------------------------\n-- In this package the sizing rules are very different from those in\n-- \"fixed_generic_pkg\" or fixed_pkg. In this package the follow more closely\n-- the sizing rules from numeric_std. See the functions for the range of what\n-- they return.\n-------------------------------------------------------------------------------\n\n\nuse std.textio.all;\nlibrary ieee, ieee_proposed;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee_proposed.fixed_float_types.all;\nuse ieee_proposed.fixed_pkg.all;\n\npackage fixed_noresize is\n\n type fixedu is array (INTEGER range <>) of STD_ULOGIC; -- fixedu\n type fixeds is array (INTEGER range <>) of STD_ULOGIC; -- fixeds\n\n -- ===========================================================================\n -- Arithmetic Operators:\n -- ===========================================================================\n\n -- Absolute value, 2's complement\n -- abs fixeds(a downto b) = fixeds(a downto b)\n function \"abs\" (arg : fixeds) return fixeds;\n\n -- Negation, 2's complement\n -- - fixeds(a downto b) = fixeds(a downto b)\n function \"-\" (arg : fixeds)return fixeds;\n\n -- Addition\n -- fixedu(a downto b) + fixedu(c downto d)\n -- = fixedu(maximum(a,c) downto minimum(b,d))\n function \"+\" (l, r : fixedu) return fixedu;\n function \"+\" (l, r : fixeds) return fixeds;\n\n -- Subtraction\n -- fixedu(a downto b) - fixedu(c downto d)\n -- = fixedu(maximum(a,c) downto minimum(b,d))\n function \"-\" (l, r : fixedu) return fixedu;\n function \"-\" (l, r : fixeds) return fixeds;\n\n -- Multiplication\n -- fixedu(a downto b) * fixedu(c downto d) = fixedu(a+c+1 downto b+d)\n function \"*\" (l, r : fixedu) return fixedu;\n function \"*\" (l, r : fixeds) return fixeds;\n\n -- Division\n -- fixedu(a downto b) / fixedu(c downto d) = fixedu(a downto b)\n function \"/\" (l, r : fixedu) return fixedu;\n function \"/\" (l, r : fixeds) return fixeds;\n\n -- Remainder\n -- fixedu(a downto b) rem fixedu(c downto d) = fixedu(c downto d)\n function \"rem\" (l, r : fixedu) return fixedu;\n function \"rem\" (l, r : fixeds) return fixeds;\n\n -- Modulo\n -- fixedu(a downto b) mod fixedu(c downto d) = fixedu(c downto d)\n function \"mod\" (l, r : fixedu) return fixedu;\n function \"mod\" (l, r : fixeds) return fixeds;\n\n function \"+\" (l : fixedu; r : REAL) return fixedu;\n function \"+\" (l : REAL; r : fixedu) return fixedu;\n function \"+\" (l : fixedu; r : NATURAL) return fixedu;\n function \"+\" (l : NATURAL; r : fixedu) return fixedu;\n function \"-\" (l : fixedu; r : REAL) return fixedu;\n function \"-\" (l : REAL; r : fixedu) return fixedu;\n function \"-\" (l : fixedu; r : NATURAL) return fixedu;\n function \"-\" (l : NATURAL; r : fixedu) return fixedu;\n function \"*\" (l : fixedu; r : REAL) return fixedu;\n function \"*\" (l : REAL; r : fixedu) return fixedu;\n function \"*\" (l : fixedu; r : NATURAL) return fixedu;\n function \"*\" (l : NATURAL; r : fixedu) return fixedu;\n function \"/\" (l : fixedu; r : REAL) return fixedu;\n function \"/\" (l : REAL; r : fixedu) return fixedu;\n function \"/\" (l : fixedu; r : NATURAL) return fixedu;\n function \"/\" (l : NATURAL; r : fixedu) return fixedu;\n function \"rem\" (l : fixedu; r : REAL) return fixedu;\n function \"rem\" (l : REAL; r : fixedu) return fixedu;\n function \"rem\" (l : fixedu; r : NATURAL) return fixedu;\n function \"rem\" (l : NATURAL; r : fixedu) return fixedu;\n function \"mod\" (l : fixedu; r : REAL) return fixedu;\n function \"mod\" (l : REAL; r : fixedu) return fixedu;\n function \"mod\" (l : fixedu; r : NATURAL) return fixedu;\n function \"mod\" (l : NATURAL; r : fixedu) return fixedu;\n\n function \"+\" (l : fixeds; r : REAL) return fixeds;\n function \"+\" (l : REAL; r : fixeds) return fixeds;\n function \"+\" (l : fixeds; r : INTEGER) return fixeds;\n function \"+\" (l : INTEGER; r : fixeds) return fixeds;\n function \"-\" (l : fixeds; r : REAL) return fixeds;\n function \"-\" (l : REAL; r : fixeds) return fixeds;\n function \"-\" (l : fixeds; r : INTEGER) return fixeds;\n function \"-\" (l : INTEGER; r : fixeds) return fixeds;\n function \"*\" (l : fixeds; r : REAL) return fixeds;\n function \"*\" (l : REAL; r : fixeds) return fixeds;\n function \"*\" (l : fixeds; r : INTEGER) return fixeds;\n function \"*\" (l : INTEGER; r : fixeds) return fixeds;\n function \"/\" (l : fixeds; r : REAL) return fixeds;\n function \"/\" (l : REAL; r : fixeds) return fixeds;\n function \"/\" (l : fixeds; r : INTEGER) return fixeds;\n function \"/\" (l : INTEGER; r : fixeds) return fixeds;\n function \"rem\" (l : fixeds; r : REAL) return fixeds;\n function \"rem\" (l : REAL; r : fixeds) return fixeds;\n function \"rem\" (l : fixeds; r : INTEGER) return fixeds;\n function \"rem\" (l : INTEGER; r : fixeds) return fixeds;\n function \"mod\" (l : fixeds; r : REAL) return fixeds;\n function \"mod\" (l : REAL; r : fixeds) return fixeds;\n function \"mod\" (l : fixeds; r : INTEGER) return fixeds;\n function \"mod\" (l : INTEGER; r : fixeds) return fixeds;\n\n -- This version of divide gives the user more control\n -- fixedu(a downto b) / fixedu(c downto d) = fixedu(a downto b)\n function divide (\n l, r : fixedu;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu;\n\n -- This version of divide gives the user more control\n -- fixeds(a downto b) / fixeds(c downto d) = fixeds(a downto b)\n function divide (\n l, r : fixeds;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixeds;\n\n -- These functions return 1/X\n -- 1 / fixedu (a downto b) = fixedu (a downto b)\n function reciprocal (\n arg : fixedu; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu;\n\n -- 1 / fixedu (a downto b) = fixedu (a downto b)\n function reciprocal (\n arg : fixeds; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixeds;\n\n -- REM function\n -- fixedu(a downto b) rem fixedu(c downto d) = fixedu(c downto d)\n function remainder (\n l, r : fixedu;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu;\n\n -- fixeds(a downto b) rem fixeds(c downto d) = fixeds(c downto d)\n function remainder (\n l, r : fixeds;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixeds;\n\n -- mod function\n -- fixedu(a downto b) mod fixedu(c downto d) = fixedu(c downto d)\n function modulo (\n l, r : fixedu;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu;\n\n -- fixeds(a downto b) mod fixeds(c downto d) = fixeds(c downto d)\n function modulo (\n l, r : fixeds;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixeds;\n\n -- Procedure for those who need an \"accumulator\" function.\n -- add_carry (fixedu(a downto b), fixedu (c downto d))\n -- = fixedu (maximum(a,c) downto minimum(b,d))\n procedure add_carry (\n L, R : in fixedu;\n c_in : in STD_ULOGIC;\n result : out fixedu;\n c_out : out STD_ULOGIC);\n\n -- add_carry (fixeds(a downto b), fixeds (c downto d))\n -- = fixeds (maximum(a,c) downto minimum(b,d))\n procedure add_carry (\n L, R : in fixeds;\n c_in : in STD_ULOGIC;\n result : out fixeds;\n c_out : out STD_ULOGIC);\n\n -- Scales the result by a power of 2. Width of input = width of output with\n -- the binary point moved.\n function scalb (y : fixedu; N : INTEGER) return fixedu;\n function scalb (y : fixedu; N : SIGNED) return fixedu;\n function scalb (y : fixeds; N : INTEGER) return fixeds;\n function scalb (y : fixeds; N : SIGNED) return fixeds;\n\n function Is_Negative (arg : fixeds) return BOOLEAN;\n\n -- ===========================================================================\n -- Comparison Operators\n -- ===========================================================================\n\n function \">\" (l, r : fixedu) return BOOLEAN;\n function \">\" (l, r : fixeds) return BOOLEAN;\n function \"<\" (l, r : fixedu) return BOOLEAN;\n function \"<\" (l, r : fixeds) return BOOLEAN;\n function \"<=\" (l, r : fixedu) return BOOLEAN;\n function \"<=\" (l, r : fixeds) return BOOLEAN;\n function \">=\" (l, r : fixedu) return BOOLEAN;\n function \">=\" (l, r : fixeds) return BOOLEAN;\n function \"=\" (l, r : fixedu) return BOOLEAN;\n function \"=\" (l, r : fixeds) return BOOLEAN;\n function \"/=\" (l, r : fixedu) return BOOLEAN;\n function \"/=\" (l, r : fixeds) return BOOLEAN;\n\n -- These will be replace with \"?=\", etc operators in VHDL-2006\n function \\?=\\ (l, r : fixedu) return STD_ULOGIC;\n function \\?/=\\ (l, r : fixedu) return STD_ULOGIC;\n function \\?>\\ (l, r : fixedu) return STD_ULOGIC;\n function \\?>=\\ (l, r : fixedu) return STD_ULOGIC;\n function \\?<\\ (l, r : fixedu) return STD_ULOGIC;\n function \\?<=\\ (l, r : fixedu) return STD_ULOGIC;\n function \\?=\\ (l, r : fixeds) return STD_ULOGIC;\n function \\?/=\\ (l, r : fixeds) return STD_ULOGIC;\n function \\?>\\ (l, r : fixeds) return STD_ULOGIC;\n function \\?>=\\ (l, r : fixeds) return STD_ULOGIC;\n function \\?<\\ (l, r : fixeds) return STD_ULOGIC;\n function \\?<=\\ (l, r : fixeds) return STD_ULOGIC;\n\n function std_match (l, r : fixedu) return BOOLEAN;\n function std_match (l, r : fixeds) return BOOLEAN;\n\n -- Overloads the default \"maximum\" and \"minimum\" function\n\n function maximum (l, r : fixedu) return fixedu;\n function minimum (l, r : fixedu) return fixedu;\n function maximum (l, r : fixeds) return fixeds;\n function minimum (l, r : fixeds) return fixeds;\n\n ----------------------------------------------------------------------------\n -- In these compare functions a natural is converted into a\n -- fixed point number of the bounds \"maximum(l'high,0) downto 0\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : fixedu; r : NATURAL) return BOOLEAN;\n function \"/=\" (l : fixedu; r : NATURAL) return BOOLEAN;\n function \">=\" (l : fixedu; r : NATURAL) return BOOLEAN;\n function \"<=\" (l : fixedu; r : NATURAL) return BOOLEAN;\n function \">\" (l : fixedu; r : NATURAL) return BOOLEAN;\n function \"<\" (l : fixedu; r : NATURAL) return BOOLEAN;\n\n function \"=\" (l : NATURAL; r : fixedu) return BOOLEAN;\n function \"/=\" (l : NATURAL; r : fixedu) return BOOLEAN;\n function \">=\" (l : NATURAL; r : fixedu) return BOOLEAN;\n function \"<=\" (l : NATURAL; r : fixedu) return BOOLEAN;\n function \">\" (l : NATURAL; r : fixedu) return BOOLEAN;\n function \"<\" (l : NATURAL; r : fixedu) return BOOLEAN;\n\n function \\?=\\ (l : fixedu; r : NATURAL) return STD_ULOGIC;\n function \\?/=\\ (l : fixedu; r : NATURAL) return STD_ULOGIC;\n function \\?>=\\ (l : fixedu; r : NATURAL) return STD_ULOGIC;\n function \\?<=\\ (l : fixedu; r : NATURAL) return STD_ULOGIC;\n function \\?>\\ (l : fixedu; r : NATURAL) return STD_ULOGIC;\n function \\?<\\ (l : fixedu; r : NATURAL) return STD_ULOGIC;\n\n function \\?=\\ (l : NATURAL; r : fixedu) return STD_ULOGIC;\n function \\?/=\\ (l : NATURAL; r : fixedu) return STD_ULOGIC;\n function \\?>=\\ (l : NATURAL; r : fixedu) return STD_ULOGIC;\n function \\?<=\\ (l : NATURAL; r : fixedu) return STD_ULOGIC;\n function \\?>\\ (l : NATURAL; r : fixedu) return STD_ULOGIC;\n function \\?<\\ (l : NATURAL; r : fixedu) return STD_ULOGIC;\n\n function maximum (l : fixedu; r : NATURAL)\n return fixedu;\n function minimum (l : fixedu; r : NATURAL)\n return fixedu;\n function maximum (l : NATURAL; r : fixedu)\n return fixedu;\n function minimum (l : NATURAL; r : fixedu)\n return fixedu;\n ----------------------------------------------------------------------------\n -- In these compare functions a real is converted into a\n -- fixed point number of the bounds \"l'high+1 downto l'low\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : fixedu; r : REAL) return BOOLEAN;\n function \"/=\" (l : fixedu; r : REAL) return BOOLEAN;\n function \">=\" (l : fixedu; r : REAL) return BOOLEAN;\n function \"<=\" (l : fixedu; r : REAL) return BOOLEAN;\n function \">\" (l : fixedu; r : REAL) return BOOLEAN;\n function \"<\" (l : fixedu; r : REAL) return BOOLEAN;\n\n function \"=\" (l : REAL; r : fixedu) return BOOLEAN;\n function \"/=\" (l : REAL; r : fixedu) return BOOLEAN;\n function \">=\" (l : REAL; r : fixedu) return BOOLEAN;\n function \"<=\" (l : REAL; r : fixedu) return BOOLEAN;\n function \">\" (l : REAL; r : fixedu) return BOOLEAN;\n function \"<\" (l : REAL; r : fixedu) return BOOLEAN;\n\n function \\?=\\ (l : fixedu; r : REAL) return STD_ULOGIC;\n function \\?/=\\ (l : fixedu; r : REAL) return STD_ULOGIC;\n function \\?>=\\ (l : fixedu; r : REAL) return STD_ULOGIC;\n function \\?<=\\ (l : fixedu; r : REAL) return STD_ULOGIC;\n function \\?>\\ (l : fixedu; r : REAL) return STD_ULOGIC;\n function \\?<\\ (l : fixedu; r : REAL) return STD_ULOGIC;\n\n function \\?=\\ (l : REAL; r : fixedu) return STD_ULOGIC;\n function \\?/=\\ (l : REAL; r : fixedu) return STD_ULOGIC;\n function \\?>=\\ (l : REAL; r : fixedu) return STD_ULOGIC;\n function \\?<=\\ (l : REAL; r : fixedu) return STD_ULOGIC;\n function \\?>\\ (l : REAL; r : fixedu) return STD_ULOGIC;\n function \\?<\\ (l : REAL; r : fixedu) return STD_ULOGIC;\n\n function maximum (l : fixedu; r : REAL) return fixedu;\n function maximum (l : REAL; r : fixedu) return fixedu;\n function minimum (l : fixedu; r : REAL) return fixedu;\n function minimum (l : REAL; r : fixedu) return fixedu;\n ----------------------------------------------------------------------------\n -- In these compare functions an integer is converted into a\n -- fixed point number of the bounds \"maximum(l'high,1) downto 0\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : fixeds; r : INTEGER) return BOOLEAN;\n function \"/=\" (l : fixeds; r : INTEGER) return BOOLEAN;\n function \">=\" (l : fixeds; r : INTEGER) return BOOLEAN;\n function \"<=\" (l : fixeds; r : INTEGER) return BOOLEAN;\n function \">\" (l : fixeds; r : INTEGER) return BOOLEAN;\n function \"<\" (l : fixeds; r : INTEGER) return BOOLEAN;\n\n function \"=\" (l : INTEGER; r : fixeds) return BOOLEAN;\n function \"/=\" (l : INTEGER; r : fixeds) return BOOLEAN;\n function \">=\" (l : INTEGER; r : fixeds) return BOOLEAN;\n function \"<=\" (l : INTEGER; r : fixeds) return BOOLEAN;\n function \">\" (l : INTEGER; r : fixeds) return BOOLEAN;\n function \"<\" (l : INTEGER; r : fixeds) return BOOLEAN;\n\n function \\?=\\ (l : fixeds; r : INTEGER) return STD_ULOGIC;\n function \\?/=\\ (l : fixeds; r : INTEGER) return STD_ULOGIC;\n function \\?>=\\ (l : fixeds; r : INTEGER) return STD_ULOGIC;\n function \\?<=\\ (l : fixeds; r : INTEGER) return STD_ULOGIC;\n function \\?>\\ (l : fixeds; r : INTEGER) return STD_ULOGIC;\n function \\?<\\ (l : fixeds; r : INTEGER) return STD_ULOGIC;\n\n function \\?=\\ (l : INTEGER; r : fixeds) return STD_ULOGIC;\n function \\?/=\\ (l : INTEGER; r : fixeds) return STD_ULOGIC;\n function \\?>=\\ (l : INTEGER; r : fixeds) return STD_ULOGIC;\n function \\?<=\\ (l : INTEGER; r : fixeds) return STD_ULOGIC;\n function \\?>\\ (l : INTEGER; r : fixeds) return STD_ULOGIC;\n function \\?<\\ (l : INTEGER; r : fixeds) return STD_ULOGIC;\n\n function maximum (l : fixeds; r : INTEGER)\n return fixeds;\n function maximum (l : INTEGER; r : fixeds)\n return fixeds;\n function minimum (l : fixeds; r : INTEGER)\n return fixeds;\n function minimum (l : INTEGER; r : fixeds)\n return fixeds;\n ----------------------------------------------------------------------------\n -- In these compare functions a real is converted into a\n -- fixed point number of the bounds \"l'high+1 downto l'low\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : fixeds; r : REAL) return BOOLEAN;\n function \"/=\" (l : fixeds; r : REAL) return BOOLEAN;\n function \">=\" (l : fixeds; r : REAL) return BOOLEAN;\n function \"<=\" (l : fixeds; r : REAL) return BOOLEAN;\n function \">\" (l : fixeds; r : REAL) return BOOLEAN;\n function \"<\" (l : fixeds; r : REAL) return BOOLEAN;\n\n function \"=\" (l : REAL; r : fixeds) return BOOLEAN;\n function \"/=\" (l : REAL; r : fixeds) return BOOLEAN;\n function \">=\" (l : REAL; r : fixeds) return BOOLEAN;\n function \"<=\" (l : REAL; r : fixeds) return BOOLEAN;\n function \">\" (l : REAL; r : fixeds) return BOOLEAN;\n function \"<\" (l : REAL; r : fixeds) return BOOLEAN;\n\n function \\?=\\ (l : fixeds; r : REAL) return STD_ULOGIC;\n function \\?/=\\ (l : fixeds; r : REAL) return STD_ULOGIC;\n function \\?>=\\ (l : fixeds; r : REAL) return STD_ULOGIC;\n function \\?<=\\ (l : fixeds; r : REAL) return STD_ULOGIC;\n function \\?>\\ (l : fixeds; r : REAL) return STD_ULOGIC;\n function \\?<\\ (l : fixeds; r : REAL) return STD_ULOGIC;\n\n function \\?=\\ (l : REAL; r : fixeds) return STD_ULOGIC;\n function \\?/=\\ (l : REAL; r : fixeds) return STD_ULOGIC;\n function \\?>=\\ (l : REAL; r : fixeds) return STD_ULOGIC;\n function \\?<=\\ (l : REAL; r : fixeds) return STD_ULOGIC;\n function \\?>\\ (l : REAL; r : fixeds) return STD_ULOGIC;\n function \\?<\\ (l : REAL; r : fixeds) return STD_ULOGIC;\n\n function maximum (l : fixeds; r : REAL) return fixeds;\n function maximum (l : REAL; r : fixeds) return fixeds;\n function minimum (l : fixeds; r : REAL) return fixeds;\n function minimum (l : REAL; r : fixeds) return fixeds;\n -- ===========================================================================\n -- Shift and Rotate Functions.\n -- Note that sra and sla are not the same as the BIT_VECTOR version\n -- ===========================================================================\n\n function \"sll\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu;\n function \"srl\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu;\n function \"rol\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu;\n function \"ror\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu;\n function \"sla\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu;\n function \"sra\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu;\n function \"sll\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds;\n function \"srl\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds;\n function \"rol\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds;\n function \"ror\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds;\n function \"sla\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds;\n function \"sra\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds;\n function SHIFT_LEFT (ARG : fixedu; COUNT : NATURAL)\n return fixedu;\n function SHIFT_RIGHT (ARG : fixedu; COUNT : NATURAL)\n return fixedu;\n function SHIFT_LEFT (ARG : fixeds; COUNT : NATURAL)\n return fixeds;\n function SHIFT_RIGHT (ARG : fixeds; COUNT : NATURAL)\n return fixeds;\n\n ----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n\n function \"not\" (l : fixedu) return fixedu;\n function \"and\" (l, r : fixedu) return fixedu;\n function \"or\" (l, r : fixedu) return fixedu;\n function \"nand\" (l, r : fixedu) return fixedu;\n function \"nor\" (l, r : fixedu) return fixedu;\n function \"xor\" (l, r : fixedu) return fixedu;\n function \"xnor\" (l, r : fixedu) return fixedu;\n function \"not\" (l : fixeds) return fixeds;\n function \"and\" (l, r : fixeds) return fixeds;\n function \"or\" (l, r : fixeds) return fixeds;\n function \"nand\" (l, r : fixeds) return fixeds;\n function \"nor\" (l, r : fixeds) return fixeds;\n function \"xor\" (l, r : fixeds) return fixeds;\n function \"xnor\" (l, r : fixeds) return fixeds;\n\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (l : STD_ULOGIC; r : fixedu)\n return fixedu;\n function \"and\" (l : fixedu; r : STD_ULOGIC)\n return fixedu;\n function \"or\" (l : STD_ULOGIC; r : fixedu)\n return fixedu;\n function \"or\" (l : fixedu; r : STD_ULOGIC)\n return fixedu;\n function \"nand\" (l : STD_ULOGIC; r : fixedu)\n return fixedu;\n function \"nand\" (l : fixedu; r : STD_ULOGIC)\n return fixedu;\n function \"nor\" (l : STD_ULOGIC; r : fixedu)\n return fixedu;\n function \"nor\" (l : fixedu; r : STD_ULOGIC)\n return fixedu;\n function \"xor\" (l : STD_ULOGIC; r : fixedu)\n return fixedu;\n function \"xor\" (l : fixedu; r : STD_ULOGIC)\n return fixedu;\n function \"xnor\" (l : STD_ULOGIC; r : fixedu)\n return fixedu;\n function \"xnor\" (l : fixedu; r : STD_ULOGIC)\n return fixedu;\n function \"and\" (l : STD_ULOGIC; r : fixeds)\n return fixeds;\n function \"and\" (l : fixeds; r : STD_ULOGIC)\n return fixeds;\n function \"or\" (l : STD_ULOGIC; r : fixeds)\n return fixeds;\n function \"or\" (l : fixeds; r : STD_ULOGIC)\n return fixeds;\n function \"nand\" (l : STD_ULOGIC; r : fixeds)\n return fixeds;\n function \"nand\" (l : fixeds; r : STD_ULOGIC)\n return fixeds;\n function \"nor\" (l : STD_ULOGIC; r : fixeds)\n return fixeds;\n function \"nor\" (l : fixeds; r : STD_ULOGIC)\n return fixeds;\n function \"xor\" (l : STD_ULOGIC; r : fixeds)\n return fixeds;\n function \"xor\" (l : fixeds; r : STD_ULOGIC)\n return fixeds;\n function \"xnor\" (l : STD_ULOGIC; r : fixeds)\n return fixeds;\n function \"xnor\" (l : fixeds; r : STD_ULOGIC)\n return fixeds;\n\n -- Reduction operators, same as numeric_std functions\n function and_reduce (l : fixedu) return STD_ULOGIC;\n function nand_reduce (l : fixedu) return STD_ULOGIC;\n function or_reduce (l : fixedu) return STD_ULOGIC;\n function nor_reduce (l : fixedu) return STD_ULOGIC;\n function xor_reduce (l : fixedu) return STD_ULOGIC;\n function xnor_reduce (l : fixedu) return STD_ULOGIC;\n function and_reduce (l : fixeds) return STD_ULOGIC;\n function nand_reduce (l : fixeds) return STD_ULOGIC;\n function or_reduce (l : fixeds) return STD_ULOGIC;\n function nor_reduce (l : fixeds) return STD_ULOGIC;\n function xor_reduce (l : fixeds) return STD_ULOGIC;\n function xnor_reduce (l : fixeds) return STD_ULOGIC;\n\n -- returns arg'low-1 if not found\n function find_leftmost (arg : fixedu; y : STD_ULOGIC)\n return INTEGER;\n function find_leftmost (arg : fixeds; y : STD_ULOGIC)\n return INTEGER;\n\n -- returns arg'high+1 if not found\n function find_rightmost (arg : fixedu; y : STD_ULOGIC)\n return INTEGER;\n function find_rightmost (arg : fixeds; y : STD_ULOGIC)\n return INTEGER;\n\n -- ===========================================================================\n -- RESIZE Functions\n -- ===========================================================================\n -- resizes the number (larger or smaller)\n -- The returned result will be fixedu (left_index downto right_index)\n -- If \"round_style\" is fixed_round, then the result will be rounded.\n -- If the MSB of the remainder is a \"1\" AND the LSB of the unrounded result\n -- is a '1' or the lower bits of the remainder include a '1' then the result\n -- will be increased by the smallest representable number for that type.\n -- \"overflow_style\" can be fixed_saturate or fixed_wrap.\n -- In saturate mode, if the number overflows then the largest possible\n -- representable number is returned. If wrap mode, then the upper bits\n -- of the number are truncated.\n \n function resize (\n arg : fixedu; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu;\n\n -- \"size_res\" functions create the size of the output from the length\n -- of the \"size_res\" input. The actual value of \"size_res\" is not used.\n function resize (\n arg : fixedu; -- input\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu;\n\n -- Note that in \"wrap\" mode the sign bit is not replicated. Thus the\n -- resize of a negative number can have a positive result in wrap mode.\n function resize (\n arg : fixeds; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds;\n\n function resize (\n arg : fixeds; -- input\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds;\n\n -- ===========================================================================\n -- Conversion Functions\n -- ===========================================================================\n\n -- integer (natural) to unsigned fixed point.\n -- arguments are the upper and lower bounds of the number, thus\n -- fixedu (7 downto -3) <= to_fixedu (int, 7, -3);\n function to_fixedu (\n arg : NATURAL; -- integer\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu;\n\n function to_fixedu (\n arg : NATURAL; -- integer\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu;\n\n -- real to unsigned fixed point\n function to_fixedu (\n arg : REAL; -- real\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixedu;\n\n function to_fixedu (\n arg : REAL; -- real\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixedu;\n\n -- unsigned to unsigned fixed point\n function to_fixedu (\n arg : UNSIGNED; -- unsigned\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu;\n\n function to_fixedu (\n arg : UNSIGNED; -- unsigned\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu;\n\n -- Performs a conversion. fixedu (arg'range) is returned\n function to_fixedu (\n arg : UNSIGNED) -- unsigned\n return fixedu;\n\n -- Conversion from fixeds to fixedu (performs an \"abs\" function)\n function to_fixedu (\n arg : fixeds)\n return fixedu;\n\n -- unsigned fixed point to unsigned\n function to_unsigned (\n arg : fixedu; -- fixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED;\n\n -- unsigned fixed point to unsigned\n function to_unsigned (\n arg : fixedu; -- fixed point input\n size_res : UNSIGNED; -- used for length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED;\n\n -- unsigned fixed point to real\n function to_real (\n arg : fixedu) -- fixed point input\n return REAL;\n\n -- unsigned fixed point to integer\n function to_integer (\n arg : fixedu; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return NATURAL;\n\n -- Integer to fixeds\n function to_fixeds (\n arg : INTEGER; -- integer\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds;\n\n function to_fixeds (\n arg : INTEGER; -- integer\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds;\n\n -- Real to fixeds\n function to_fixeds (\n arg : REAL; -- real\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixeds;\n\n function to_fixeds (\n arg : REAL; -- real\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixeds;\n\n -- signed to fixeds\n function to_fixeds (\n arg : SIGNED; -- signed\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds;\n\n function to_fixeds (\n arg : SIGNED; -- signed\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds;\n\n -- signed to fixeds (output assumed to be size of signed input)\n function to_fixeds (\n arg : SIGNED) -- signed\n return fixeds;\n\n -- Conversion from fixedu to fixeds\n function to_fixeds (\n arg : fixedu)\n return fixeds;\n\n -- signed fixed point to signed\n function to_signed (\n arg : fixeds; -- fixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED;\n\n -- signed fixed point to signed\n function to_signed (\n arg : fixeds; -- fixed point input\n size_res : SIGNED; -- used for length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED;\n\n -- signed fixed point to real\n function to_real (\n arg : fixeds) -- fixed point input\n return REAL;\n\n -- signed fixed point to integer\n function to_integer (\n arg : fixeds; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return INTEGER;\n\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu;\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds;\n\n function saturate (\n size_res : fixedu) -- only the size of this is used\n return fixedu;\n\n function saturate (\n size_res : fixeds) -- only the size of this is used\n return fixeds;\n\n -- ===========================================================================\n -- Translation Functions\n -- ===========================================================================\n\n -- maps meta-logical values\n function to_01 (\n s : fixedu; -- fixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return fixedu;\n\n -- maps meta-logical values\n function to_01 (\n s : fixeds; -- fixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return fixeds;\n\n function Is_X (arg : fixedu) return BOOLEAN;\n function Is_X (arg : fixeds) return BOOLEAN;\n function to_X01 (arg : fixedu) return fixedu;\n function to_X01 (arg : fixeds) return fixeds;\n function to_X01Z (arg : fixedu) return fixedu;\n function to_X01Z (arg : fixeds) return fixeds;\n function to_UX01 (arg : fixedu) return fixedu;\n function to_UX01 (arg : fixeds) return fixeds;\n\n -- straight vector conversion routines, needed for synthesis.\n -- These functions are here so that a std_logic_vector can be\n -- converted to and from fixeds and fixedu. Note that you can\n -- not convert these vectors because of their negative index.\n \n function to_slv (\n arg : fixedu) -- fixed point vector\n return STD_LOGIC_VECTOR;\n alias to_StdLogicVector is to_slv [fixedu\n return STD_LOGIC_VECTOR];\n alias to_Std_Logic_Vector is to_slv [fixedu\n return STD_LOGIC_VECTOR];\n\n function to_slv (\n arg : fixeds) -- fixed point vector\n return STD_LOGIC_VECTOR;\n alias to_StdLogicVector is to_slv [fixeds\n return STD_LOGIC_VECTOR];\n alias to_Std_Logic_Vector is to_slv [fixeds\n return STD_LOGIC_VECTOR];\n\n function to_sulv (\n arg : fixedu) -- fixed point vector\n return STD_ULOGIC_VECTOR;\n alias to_StdULogicVector is to_sulv [fixedu\n return STD_ULOGIC_VECTOR];\n alias to_Std_ULogic_Vector is to_sulv [fixedu\n return STD_ULOGIC_VECTOR];\n\n function to_sulv (\n arg : fixeds) -- fixed point vector\n return STD_ULOGIC_VECTOR;\n alias to_StdULogicVector is to_sulv [fixeds\n return STD_ULOGIC_VECTOR];\n alias to_Std_ULogic_Vector is to_sulv [fixeds\n return STD_ULOGIC_VECTOR];\n\n function to_fixedu (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu;\n\n function to_fixedu (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : fixedu) -- for size only\n return fixedu;\n\n function to_fixeds (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds;\n\n function to_fixeds (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : fixeds) -- for size only\n return fixeds;\n\n -- As a concession to those who use a graphical DSP environment,\n -- these functions take parameters in those tools format and create\n -- fixed point numbers. These functions are designed to convert from\n -- a std_logic_vector to the VHDL fixed point format using the conventions\n -- of these packages. In a pure VHDL environment you should use the\n -- \"to_fixedu\" and \"to_fixeds\" routines.\n\n -- unsigned fixed point\n function to_FixU (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixedu;\n\n -- signed fixed point\n function to_FixS (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixeds;\n\n-- rtl_synthesis off\n-- pragma synthesis_off\n -- ===========================================================================\n -- string and textio Functions\n -- ===========================================================================\n\n -- purpose: writes fixed point into a line\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in fixedu; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n -- purpose: writes fixed point into a line\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in fixeds; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure READ(L : inout LINE;\n VALUE : out fixedu);\n\n procedure READ(L : inout LINE;\n VALUE : out fixedu;\n GOOD : out BOOLEAN);\n\n procedure READ(L : inout LINE;\n VALUE : out fixeds);\n\n procedure READ(L : inout LINE;\n VALUE : out fixeds;\n GOOD : out BOOLEAN);\n\n alias bwrite is WRITE [LINE, fixedu, SIDE, width];\n alias bwrite is WRITE [LINE, fixeds, SIDE, width];\n alias bread is READ [LINE, fixedu];\n alias bread is READ [LINE, fixedu, BOOLEAN];\n alias bread is READ [LINE, fixeds];\n alias bread is READ [LINE, fixeds, BOOLEAN];\n alias BINARY_WRITE is WRITE [LINE, fixedu, SIDE, width];\n alias BINARY_WRITE is WRITE [LINE, fixeds, SIDE, width];\n alias BINARY_READ is READ [LINE, fixedu, BOOLEAN];\n alias BINARY_READ is READ [LINE, fixedu];\n alias BINARY_READ is READ [LINE, fixeds, BOOLEAN];\n alias BINARY_READ is READ [LINE, fixeds];\n\n -- octal read and write\n procedure OWRITE (\n L : inout LINE; -- input line\n VALUE : in fixedu; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure OWRITE (\n L : inout LINE; -- input line\n VALUE : in fixeds; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixedu);\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixedu;\n GOOD : out BOOLEAN);\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixeds);\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixeds;\n GOOD : out BOOLEAN);\n alias OCTAL_READ is OREAD [LINE, fixedu, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, fixedu];\n alias OCTAL_READ is OREAD [LINE, fixeds, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, fixeds];\n alias OCTAL_WRITE is OWRITE [LINE, fixedu, SIDE, WIDTH];\n alias OCTAL_WRITE is OWRITE [LINE, fixeds, SIDE, WIDTH];\n\n -- hex read and write\n procedure HWRITE (\n L : inout LINE; -- input line\n VALUE : in fixedu; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n -- purpose: writes fixed point into a line\n procedure HWRITE (\n L : inout LINE; -- input line\n VALUE : in fixeds; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixedu);\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixedu;\n GOOD : out BOOLEAN);\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixeds);\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixeds;\n GOOD : out BOOLEAN);\n alias HEX_READ is HREAD [LINE, fixedu, BOOLEAN];\n alias HEX_READ is HREAD [LINE, fixeds, BOOLEAN];\n alias HEX_READ is HREAD [LINE, fixedu];\n alias HEX_READ is HREAD [LINE, fixeds];\n alias HEX_WRITE is HWRITE [LINE, fixedu, SIDE, WIDTH];\n alias HEX_WRITE is HWRITE [LINE, fixeds, SIDE, WIDTH];\n\n -- returns a string, useful for:\n -- assert (x = y) report \"error found \" & to_string(x) severity error;\n function to_string (value : fixedu) return STRING;\n\n alias to_bstring is to_string [fixedu return STRING];\n alias TO_BINARY_STRING is TO_STRING [fixedu return STRING];\n\n function to_ostring (value : fixedu) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [fixedu return STRING];\n\n function to_hstring (value : fixedu) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [fixedu return STRING];\n\n function to_string (value : fixeds) return STRING;\n alias to_bstring is to_string [fixeds return STRING];\n alias TO_BINARY_STRING is TO_STRING [fixeds return STRING];\n\n function to_ostring (value : fixeds) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [fixeds return STRING];\n\n function to_hstring (value : fixeds) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [fixeds return STRING];\n\n -- From string functions allow you to convert a string into a fixed\n -- point number. Example:\n -- signal uf1 : fixedu (3 downto -3);\n -- uf1 <= from_string (\"0110.100\", uf1'high, uf1'low); -- 6.5\n -- The \".\" is optional in this syntax, however it exist and is\n -- in the wrong location an error is produced. Overflow will\n -- result in saturation.\n \n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu;\n alias from_bstring is from_string [STRING, INTEGER, INTEGER\n return fixedu];\n alias from_binary_string is from_string [STRING, INTEGER, INTEGER\n return fixedu];\n\n -- Octal and hex conversions work as follows:\n -- uf1 <= from_hstring (\"6.8\", 3, -3); -- 6.5 (bottom zeros dropped)\n -- uf1 <= from_ostring (\"06.4\", 3, -3); -- 6.5 (top zeros dropped)\n \n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu;\n alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER\n return fixedu];\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu;\n alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER\n return fixedu];\n\n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds;\n alias from_bstring is from_string [STRING, INTEGER, INTEGER\n return fixeds];\n alias from_binary_string is from_string [STRING, INTEGER, INTEGER\n return fixeds];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds;\n alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER\n return fixeds];\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds;\n alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER\n return fixeds];\n\n -- Same as above, \"size_res\" is used for it's range only.\n function from_string (\n bstring : STRING; -- binary string\n size_res : fixedu)\n return fixedu;\n alias from_bstring is from_string [STRING, fixedu\n return fixedu];\n alias from_binary_string is from_string [STRING, fixedu\n return fixedu];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : fixedu)\n return fixedu;\n alias from_octal_string is from_ostring [STRING, fixedu\n return fixedu];\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : fixedu)\n return fixedu;\n alias from_hex_string is from_hstring [STRING, fixedu\n return fixedu];\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : fixeds)\n return fixeds;\n alias from_bstring is from_string [STRING, fixeds\n return fixeds];\n alias from_binary_string is from_string [STRING, fixeds\n return fixeds];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : fixeds)\n return fixeds;\n alias from_octal_string is from_ostring [STRING, fixeds\n return fixeds];\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : fixeds)\n return fixeds;\n alias from_hex_string is from_hstring [STRING, fixeds\n return fixeds];\n\n -- Direct conversion functions. Example:\n -- signal uf1 : fixedu (3 downto -3);\n -- uf1 <= from_string (\"0110.100\"); -- 6.5\n -- In this case the \".\" is not optional, and the size of\n -- the output must match exactly.\n \n function from_string (\n bstring : STRING) -- binary string\n return fixedu;\n alias from_bstring is from_string [STRING return fixedu];\n alias from_binary_string is from_string [STRING return fixedu];\n\n -- Direct octal and hex conversion functions. In this case\n -- the string lengths must match. Example:\n -- signal sf1 := fixeds (5 downto -3);\n -- sf1 <= from_ostring (\"71.4\") -- -6.5\n \n function from_ostring (\n ostring : STRING) -- Octal string\n return fixedu;\n alias from_octal_string is from_ostring [STRING return fixedu];\n\n function from_hstring (\n hstring : STRING) -- hex string\n return fixedu;\n alias from_hex_string is from_hstring [STRING return fixedu];\n\n function from_string (\n bstring : STRING) -- binary string\n return fixeds;\n alias from_bstring is from_string [STRING return fixeds];\n alias from_binary_string is from_string [STRING return fixeds];\n\n function from_ostring (\n ostring : STRING) -- Octal string\n return fixeds;\n alias from_octal_string is from_ostring [STRING return fixeds];\n\n function from_hstring (\n hstring : STRING) -- hex string\n return fixeds;\n alias from_hex_string is from_hstring [STRING return fixeds];\n-- rtl_synthesis on\n-- pragma synthesis_on\n\n -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these\n -- extra functions are needed for compatability.\n function to_fixedu (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu;\n\n function to_fixedu (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : fixedu) -- for size only\n return fixedu;\n\n function to_fixeds (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds;\n\n function to_fixeds (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : fixeds) -- for size only\n return fixeds;\n\n -- unsigned fixed point\n function to_FixU (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixedu;\n\n -- signed fixed point\n function to_FixS (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixeds;\n\nend package fixed_noresize;\n\npackage body fixed_noresize is\n\n -- %%% Replicated functions\n function maximum (\n l, r : INTEGER) -- inputs\n return INTEGER is\n begin -- function max\n if l > r then return l;\n else return r;\n end if;\n end function maximum;\n\n function minimum (\n l, r : INTEGER) -- inputs\n return INTEGER is\n begin -- function min\n if l > r then return r;\n else return l;\n end if;\n end function minimum;\n -- %%% end replicated functions\n\n -- ===========================================================================\n -- Arithmetic Operators:\n -- ===========================================================================\n\n -- Absolute value, 2's complement\n function \"abs\" (arg : fixeds) return fixeds is\n variable argt : sfixed (arg'range);\n begin\n argt := resize (arg => abs (sfixed(arg)),\n left_index => arg'high,\n right_index => arg'low);\n return fixeds (argt);\n end function \"abs\";\n\n -- Negation, 2's complement\n -- - fixeds(a downto b) = fixeds(a+1 downto b)\n function \"-\" (arg : fixeds)return fixeds is\n variable argt : sfixed (arg'range);\n begin\n argt := resize (arg => - (sfixed(arg)),\n left_index => arg'high,\n right_index => arg'low);\n return fixeds (argt);\n end function \"-\";\n\n -- Addition\n function \"+\" (l, r : fixedu) return fixedu is\n variable result : ufixed (maximum (L'high, R'high) downto\n minimum (L'low, R'low));\n begin\n result := resize (arg => ufixed(l) + ufixed(r),\n left_index => result'high,\n right_index => result'low);\n return fixedu (result);\n end function \"+\";\n\n function \"+\" (l, r : fixeds) return fixeds is\n variable result : sfixed (maximum (L'high, R'high) downto\n minimum (L'low, R'low));\n begin\n result := resize (arg => sfixed(l) + sfixed(r),\n left_index => result'high,\n right_index => result'low);\n return fixeds (result);\n end function \"+\";\n\n -- Subtraction\n function \"-\" (l, r : fixedu) return fixedu is\n variable result : ufixed (maximum (L'high, R'high) downto\n minimum (L'low, R'low));\n begin\n result := resize (arg => ufixed(l) - ufixed(r),\n left_index => result'high,\n right_index => result'low);\n return fixedu (result);\n end function \"-\";\n\n\n function \"-\" (l, r : fixeds) return fixeds is\n variable result : sfixed (maximum (L'high, R'high) downto\n minimum (L'low, R'low));\n begin\n result := resize (arg => sfixed(l) - sfixed(r),\n left_index => result'high,\n right_index => result'low);\n return fixeds (result);\n end function \"-\";\n\n -- Multiplication\n function \"*\" (l, r : fixedu) return fixedu is\n variable result : ufixed (l'high + r'high + 1 downto r'low + l'low);\n begin\n result := ufixed(l) * ufixed(r); -- No resize necessary\n return fixedu (result);\n end function \"*\";\n\n function \"*\" (l, r : fixeds) return fixeds is\n variable result : sfixed (l'high + r'high + 1 downto r'low + l'low);\n begin\n result := sfixed(l) * sfixed(r); -- No resize necessary\n return fixeds (result);\n end function \"*\";\n\n -- Division\n function \"/\" (l, r : fixedu) return fixedu is\n begin\n return divide (l, r);\n end function \"/\";\n\n function \"/\" (l, r : fixeds) return fixeds is\n begin\n return divide (l, r);\n end function \"/\";\n\n -- Remainder\n function \"rem\" (l, r : fixedu) return fixedu is\n begin\n return remainder (l, r);\n end function \"rem\";\n\n function \"rem\" (l, r : fixeds) return fixeds is\n begin\n return remainder (l, r);\n end function \"rem\";\n\n -- Modulo\n function \"mod\" (l, r : fixedu) return fixedu is\n begin\n return modulo (l, r);\n end function \"mod\";\n\n function \"mod\" (l, r : fixeds) return fixeds is\n begin\n return modulo (l, r);\n end function \"mod\";\n\n function \">\" (l, r : fixedu) return BOOLEAN is\n begin\n return ufixed(l) > ufixed(r);\n end function \">\";\n function \">\" (l, r : fixeds) return BOOLEAN is\n begin\n return sfixed(l) > sfixed(r);\n end function \">\";\n function \"<\" (l, r : fixedu) return BOOLEAN is\n begin\n return ufixed(l) < ufixed(r);\n end function \"<\";\n function \"<\" (l, r : fixeds) return BOOLEAN is\n begin\n return sfixed(l) < sfixed(r);\n end function \"<\";\n function \"<=\" (l, r : fixedu) return BOOLEAN is\n begin\n return ufixed(l) <= ufixed(r);\n end function \"<=\";\n function \"<=\" (l, r : fixeds) return BOOLEAN is\n begin\n return sfixed(l) <= sfixed(r);\n end function \"<=\";\n function \">=\" (l, r : fixedu) return BOOLEAN is\n begin\n return ufixed(l) >= ufixed(r);\n end function \">=\";\n function \">=\" (l, r : fixeds) return BOOLEAN is\n begin\n return sfixed(l) >= sfixed(r);\n end function \">=\";\n function \"=\" (l, r : fixedu) return BOOLEAN is\n begin\n return ufixed(l) = ufixed(r);\n end function \"=\";\n function \"=\" (l, r : fixeds) return BOOLEAN is\n begin\n return sfixed(l) = sfixed(r);\n end function \"=\";\n function \"/=\" (l, r : fixedu) return BOOLEAN is\n begin\n return ufixed(l) /= ufixed(r);\n end function \"/=\";\n function \"/=\" (l, r : fixeds) return BOOLEAN is\n begin\n return sfixed(l) /= sfixed(r);\n end function \"/=\";\n\n function \\?=\\ (l, r : fixedu) return STD_ULOGIC is\n begin\n return \\?=\\ (ufixed(l), ufixed(r));\n end function \\?=\\;\n function \\?/=\\ (l, r : fixedu) return STD_ULOGIC is\n begin\n return \\?/=\\ (ufixed(l), ufixed(r));\n end function \\?/=\\;\n function \\?>\\ (l, r : fixedu) return STD_ULOGIC is\n begin\n return \\?>\\ (ufixed(l), ufixed(r));\n end function \\?>\\;\n function \\?>=\\ (l, r : fixedu) return STD_ULOGIC is\n begin\n return \\?>=\\ (ufixed(l), ufixed(r));\n end function \\?>=\\;\n function \\?<\\ (l, r : fixedu) return STD_ULOGIC is\n begin\n return \\?<\\ (ufixed(l), ufixed(r));\n end function \\?<\\;\n function \\?<=\\ (l, r : fixedu) return STD_ULOGIC is\n begin\n return \\?<=\\ (ufixed(l), ufixed(r));\n end function \\?<=\\;\n function \\?=\\ (l, r : fixeds) return STD_ULOGIC is\n begin\n return \\?=\\ (sfixed(l), sfixed(r));\n end function \\?=\\;\n function \\?/=\\ (l, r : fixeds) return STD_ULOGIC is\n begin\n return \\?/=\\ (sfixed(l), sfixed(r));\n end function \\?/=\\;\n function \\?>\\ (l, r : fixeds) return STD_ULOGIC is\n begin\n return \\?>\\ (sfixed(l), sfixed(r));\n end function \\?>\\;\n function \\?>=\\ (l, r : fixeds) return STD_ULOGIC is\n begin\n return \\?>=\\ (sfixed(l), sfixed(r));\n end function \\?>=\\;\n function \\?<\\ (l, r : fixeds) return STD_ULOGIC is\n begin\n return \\?<\\ (sfixed(l), sfixed(r));\n end function \\?<\\;\n function \\?<=\\ (l, r : fixeds) return STD_ULOGIC is\n begin\n return \\?<=\\ (sfixed(l), sfixed(r));\n end function \\?<=\\;\n\n function std_match (l, r : fixedu) return BOOLEAN is\n begin\n return std_match (ufixed(l), ufixed(r));\n end function std_match;\n function std_match (l, r : fixeds) return BOOLEAN is\n begin\n return std_match (sfixed(l), sfixed(r));\n end function std_match;\n\n function maximum (l, r : fixedu) return fixedu is\n begin\n return fixedu (maximum (ufixed(l), ufixed(r)));\n end function maximum;\n function minimum (l, r : fixedu) return fixedu is\n begin\n return fixedu (minimum (ufixed(l), ufixed(r)));\n end function minimum;\n function maximum (l, r : fixeds) return fixeds is\n begin\n return fixeds (maximum (sfixed(l), sfixed(r)));\n end function maximum;\n function minimum (l, r : fixeds) return fixeds is\n begin\n return fixeds (minimum (sfixed(l), sfixed(r)));\n end function minimum;\n -- Overloaded math functions for real\n function \"+\" (\n l : fixedu; -- fixed point input\n r : REAL)\n return fixedu is\n begin\n return (l + to_fixedu (r, l'high, l'low));\n end function \"+\";\n\n function \"+\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, r'low) + r);\n end function \"+\";\n\n function \"+\" (\n l : fixeds; -- fixed point input\n r : REAL)\n return fixeds is\n begin\n return (l + to_fixeds (r, l'high, l'low));\n end function \"+\";\n\n function \"+\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, r'low) + r);\n end function \"+\";\n\n function \"-\" (\n l : fixedu; -- fixed point input\n r : REAL)\n return fixedu is\n begin\n return (l - to_fixedu (r, l'high, l'low));\n end function \"-\";\n\n function \"-\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, r'low) - r);\n end function \"-\";\n\n function \"-\" (\n l : fixeds; -- fixed point input\n r : REAL)\n return fixeds is\n begin\n return (l - to_fixeds (r, l'high, l'low));\n end function \"-\";\n\n function \"-\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, r'low) - r);\n end function \"-\";\n\n function \"*\" (\n l : fixedu; -- fixed point input\n r : REAL)\n return fixedu is\n begin\n return (l * to_fixedu (r, l'high, l'low));\n end function \"*\";\n\n function \"*\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, r'low) * r);\n end function \"*\";\n\n function \"*\" (\n l : fixeds; -- fixed point input\n r : REAL)\n return fixeds is\n begin\n return (l * to_fixeds (r, l'high, l'low));\n end function \"*\";\n\n function \"*\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, r'low) * r);\n end function \"*\";\n\n function \"/\" (\n l : fixedu; -- fixed point input\n r : REAL)\n return fixedu is\n begin\n return (l / to_fixedu (r, l'high, l'low));\n end function \"/\";\n\n function \"/\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, r'low) / r);\n end function \"/\";\n\n function \"/\" (\n l : fixeds; -- fixed point input\n r : REAL)\n return fixeds is\n begin\n return (l / to_fixeds (r, l'high, l'low));\n end function \"/\";\n\n function \"/\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, r'low) / r);\n end function \"/\";\n\n function \"rem\" (\n l : fixedu; -- fixed point input\n r : REAL)\n return fixedu is\n begin\n return (l rem to_fixedu (r, l'high, l'low));\n end function \"rem\";\n\n function \"rem\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, r'low) rem r);\n end function \"rem\";\n\n function \"rem\" (\n l : fixeds; -- fixed point input\n r : REAL)\n return fixeds is\n begin\n return (l rem to_fixeds (r, l'high, l'low));\n end function \"rem\";\n\n function \"rem\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, r'low) rem r);\n end function \"rem\";\n\n function \"mod\" (\n l : fixedu; -- fixed point input\n r : REAL)\n return fixedu is\n begin\n return (l mod to_fixedu (r, l'high, l'low));\n end function \"mod\";\n\n function \"mod\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, r'low) mod r);\n end function \"mod\";\n\n function \"mod\" (\n l : fixeds; -- fixed point input\n r : REAL)\n return fixeds is\n begin\n return (l mod to_fixeds (r, l'high, l'low));\n end function \"mod\";\n\n function \"mod\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, r'low) mod r);\n end function \"mod\";\n\n -- Overloaded math functions for integers\n function \"+\" (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return (l + to_fixedu (r, l'high, 0));\n end function \"+\";\n\n function \"+\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, 0) + r);\n end function \"+\";\n\n function \"+\" (\n l : fixeds; -- fixed point input\n r : INTEGER)\n return fixeds is\n begin\n return (l + to_fixeds (r, l'high, 0));\n end function \"+\";\n\n function \"+\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, 0) + r);\n end function \"+\";\n\n -- Overloaded functions\n function \"-\" (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return (l - to_fixedu (r, l'high, 0));\n end function \"-\";\n\n function \"-\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, 0) - r);\n end function \"-\";\n\n function \"-\" (\n l : fixeds; -- fixed point input\n r : INTEGER)\n return fixeds is\n begin\n return (l - to_fixeds (r, l'high, 0));\n end function \"-\";\n\n function \"-\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, 0) - r);\n end function \"-\";\n\n -- Overloaded functions\n function \"*\" (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return (l * to_fixedu (r, l'high, 0));\n end function \"*\";\n\n function \"*\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, 0) * r);\n end function \"*\";\n\n function \"*\" (\n l : fixeds; -- fixed point input\n r : INTEGER)\n return fixeds is\n begin\n return (l * to_fixeds (r, l'high, 0));\n end function \"*\";\n\n function \"*\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, 0) * r);\n end function \"*\";\n\n -- Overloaded functions\n function \"/\" (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return (l / to_fixedu (r, l'high, 0));\n end function \"/\";\n\n function \"/\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, 0) / r);\n end function \"/\";\n\n function \"/\" (\n l : fixeds; -- fixed point input\n r : INTEGER)\n return fixeds is\n begin\n return (l / to_fixeds (r, l'high, 0));\n end function \"/\";\n\n function \"/\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, 0) / r);\n end function \"/\";\n\n function \"rem\" (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return (l rem to_fixedu (r, l'high, 0));\n end function \"rem\";\n\n function \"rem\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, 0) rem r);\n end function \"rem\";\n\n function \"rem\" (\n l : fixeds; -- fixed point input\n r : INTEGER)\n return fixeds is\n begin\n return (l rem to_fixeds (r, l'high, 0));\n end function \"rem\";\n\n function \"rem\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, 0) rem r);\n end function \"rem\";\n\n function \"mod\" (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return (l mod to_fixedu (r, l'high, 0));\n end function \"mod\";\n\n function \"mod\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return (to_fixedu (l, r'high, 0) mod r);\n end function \"mod\";\n\n function \"mod\" (\n l : fixeds; -- fixed point input\n r : INTEGER)\n return fixeds is\n begin\n return (l mod to_fixeds (r, l'high, 0));\n end function \"mod\";\n\n function \"mod\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return fixeds is\n begin\n return (to_fixeds (l, r'high, 0) mod r);\n end function \"mod\";\n\n -- overloaded fixedu compare functions with integer\n function \"=\" (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l = to_fixedu (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l /= to_fixedu (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l >= to_fixedu (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l <= to_fixedu (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l > to_fixedu (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l < to_fixedu (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : fixedu;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return maximum (l, to_fixedu (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : fixedu; -- fixed point input\n r : NATURAL)\n return fixedu is\n begin\n return minimum (l, to_fixedu (r, l'high, l'low));\n end function minimum;\n\n -- NATURAL to fixedu\n function \"=\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?<\\;\n\n function maximum (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return maximum (to_fixedu (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : NATURAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return minimum (to_fixedu (l, r'high, r'low), r);\n end function minimum;\n\n -- overloaded fixedu compare functions with real\n function \"=\" (\n l : fixedu;\n r : REAL)\n return BOOLEAN is\n begin\n return (l = to_fixedu (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : fixedu;\n r : REAL)\n return BOOLEAN is\n begin\n return (l /= to_fixedu (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : fixedu;\n r : REAL)\n return BOOLEAN is\n begin\n return (l >= to_fixedu (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : fixedu;\n r : REAL)\n return BOOLEAN is\n begin\n return (l <= to_fixedu (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : fixedu;\n r : REAL)\n return BOOLEAN is\n begin\n return (l > to_fixedu (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : fixedu;\n r : REAL)\n return BOOLEAN is\n begin\n return (l < to_fixedu (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : fixedu;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : fixedu;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : fixedu;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : fixedu;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : fixedu;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : fixedu;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_fixedu (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : fixedu;\n r : REAL)\n return fixedu is\n begin\n return maximum (l, to_fixedu (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : fixedu;\n r : REAL)\n return fixedu is\n begin\n return minimum (l, to_fixedu (r, l'high, l'low));\n end function minimum;\n\n -- real and fixedu\n function \"=\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : REAL;\n r : fixedu) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixedu (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : REAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : REAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : REAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : REAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : REAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : REAL;\n r : fixedu) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_fixedu (l, r'high, r'low), r);\n end function \\?<\\;\n \n function maximum (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return maximum (to_fixedu (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : REAL;\n r : fixedu) -- fixed point input\n return fixedu is\n begin\n return minimum (to_fixedu (l, r'high, r'low), r);\n end function minimum;\n\n -- overloaded fixeds compare functions with integer\n function \"=\" (\n l : fixeds;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l = to_fixeds (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : fixeds;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l /= to_fixeds (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : fixeds;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l >= to_fixeds (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : fixeds;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l <= to_fixeds (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : fixeds;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l > to_fixeds (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : fixeds;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l < to_fixeds (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : fixeds;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : fixeds;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : fixeds;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : fixeds;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : fixeds;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : fixeds;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : fixeds;\n r : INTEGER)\n return fixeds is\n begin\n return maximum (l, to_fixeds (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : fixeds;\n r : INTEGER)\n return fixeds is\n begin\n return minimum (l, to_fixeds (r, l'high, l'low));\n end function minimum;\n\n -- integer and fixeds\n function \"=\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : INTEGER;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?<\\;\n\n function maximum (\n l : INTEGER;\n r : fixeds)\n return fixeds is\n begin\n return maximum (to_fixeds (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : INTEGER;\n r : fixeds)\n return fixeds is\n begin\n return minimum (to_fixeds (l, r'high, r'low), r);\n end function minimum;\n\n -- overloaded fixeds compare functions with real\n function \"=\" (\n l : fixeds;\n r : REAL)\n return BOOLEAN is\n begin\n return (l = to_fixeds (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : fixeds;\n r : REAL)\n return BOOLEAN is\n begin\n return (l /= to_fixeds (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : fixeds;\n r : REAL)\n return BOOLEAN is\n begin\n return (l >= to_fixeds (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : fixeds;\n r : REAL)\n return BOOLEAN is\n begin\n return (l <= to_fixeds (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : fixeds;\n r : REAL)\n return BOOLEAN is\n begin\n return (l > to_fixeds (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : fixeds;\n r : REAL)\n return BOOLEAN is\n begin\n return (l < to_fixeds (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : fixeds;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : fixeds;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : fixeds;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : fixeds;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : fixeds;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : fixeds;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_fixeds (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : fixeds;\n r : REAL)\n return fixeds is\n begin\n return maximum (l, to_fixeds (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : fixeds;\n r : REAL)\n return fixeds is\n begin\n return minimum (l, to_fixeds (r, l'high, l'low));\n end function minimum;\n\n -- REAL and fixeds\n function \"=\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : REAL;\n r : fixeds) -- fixed point input\n return BOOLEAN is\n begin\n return (to_fixeds (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : REAL;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : REAL;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : REAL;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : REAL;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : REAL;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : REAL;\n r : fixeds) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_fixeds (l, r'high, r'low), r);\n end function \\?<\\;\n\n function maximum (\n l : REAL;\n r : fixeds)\n return fixeds is\n begin\n return maximum (to_fixeds (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : REAL;\n r : fixeds)\n return fixeds is\n begin\n return minimum (to_fixeds (l, r'high, r'low), r);\n end function minimum;\n\n -- This version of divide gives the user more control\n function divide (\n l, r : fixedu;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu is\n variable result : ufixed (l'high downto l'low);\n begin\n result := resize (divide (l => ufixed(l),\n r => ufixed(r),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => result'high,\n right_index => result'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixedu(result);\n end function divide;\n\n -- This version of divide gives the user more control\n function divide (\n l, r : fixeds;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixeds is\n variable result : sfixed (l'high downto l'low);\n begin\n result := resize (arg => divide (l => sfixed(l),\n r => sfixed(r),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => result'high,\n right_index => result'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixeds(result);\n end function divide;\n\n -- These functions return 1/X\n function reciprocal (\n arg : fixedu; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu is\n variable result : ufixed (arg'high downto arg'low);\n begin\n result := resize (arg => reciprocal(arg => ufixed(arg),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => arg'high,\n right_index => arg'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixedu(result);\n end function reciprocal;\n\n function reciprocal (\n arg : fixeds; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixeds is\n variable result : sfixed (arg'high downto arg'low);\n begin\n result := resize (arg => reciprocal(arg => sfixed(arg),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => arg'high,\n right_index => arg'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixeds(result);\n end function reciprocal;\n\n -- REM function\n function remainder (\n l, r : fixedu;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu is\n variable result : ufixed (r'high downto r'low);\n begin\n result := resize (arg => remainder (l => ufixed(l),\n r => ufixed(r),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => result'high,\n right_index => result'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixedu(result);\n end function remainder;\n\n function remainder (\n l, r : fixeds;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixeds is\n variable result : sfixed (l'high downto l'low);\n begin\n result := resize (arg => remainder (l => sfixed(l),\n r => sfixed(r),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => result'high,\n right_index => result'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixeds(result);\n end function remainder;\n\n -- mod function\n function modulo (\n l, r : fixedu;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return fixedu is\n variable result : ufixed (r'high downto r'low);\n begin\n result := resize (arg => modulo (l => ufixed(l),\n r => ufixed(r),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => result'high,\n right_index => result'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixedu(result);\n end function modulo;\n\n function modulo (\n l, r : fixeds;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixeds is\n variable result : sfixed (l'high downto l'low);\n begin\n result := resize (arg => modulo (l => sfixed(l),\n r => sfixed(r),\n round_style => round_style,\n guard_bits => guard_bits),\n left_index => result'high,\n right_index => result'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return fixeds(result);\n end function modulo;\n\n -- Procedure for those who need an \"accumulator\" function.\n -- add_carry (fixedu(a downto b), fixedu (c downto d))\n -- = fixedu (maximum(a,c) downto minimum(b,d))\n procedure add_carry (\n L, R : in fixedu;\n c_in : in STD_ULOGIC;\n result : out fixedu;\n c_out : out STD_ULOGIC) is\n variable resultx : ufixed (maximum (L'high, R'high) downto\n minimum (L'low, R'low));\n begin\n add_carry (L => ufixed (L),\n R => ufixed (R),\n c_in => c_in,\n result => resultx,\n c_out => c_out);\n result := fixedu(resultx);\n end procedure add_carry;\n\n -- add_carry (fixeds(a downto b), fixeds (c downto d))\n -- = fixeds (maximum(a,c) downto minimum(b,d))\n procedure add_carry (\n L, R : in fixeds;\n c_in : in STD_ULOGIC;\n result : out fixeds;\n c_out : out STD_ULOGIC) is\n variable resultx : sfixed (maximum (L'high, R'high) downto\n minimum (L'low, R'low));\n begin\n add_carry (L => sfixed (L),\n R => sfixed (R),\n c_in => c_in,\n result => resultx,\n c_out => c_out);\n result := fixeds (resultx);\n end procedure add_carry;\n\n -- Scales the result by a power of 2. Width of input = width of output with\n -- the binary point moved.\n function scalb (y : fixedu; N : INTEGER) return fixedu is\n begin\n return fixedu (scalb (ufixed(y), N));\n end function scalb;\n function scalb (y : fixedu; N : SIGNED) return fixedu is\n begin\n return fixedu (scalb (ufixed(y), N));\n end function scalb;\n function scalb (y : fixeds; N : INTEGER) return fixeds is\n begin\n return fixeds (scalb (sfixed(y), N));\n end function scalb;\n function scalb (y : fixeds; N : SIGNED) return fixeds is\n begin\n return fixeds (scalb (sfixed(y), N));\n end function scalb;\n\n function Is_Negative (arg : fixeds) return BOOLEAN is\n begin\n return to_x01 (arg (arg'high)) = '1';\n end function Is_Negative;\n\n -- ===========================================================================\n -- Shift and Rotate Functions.\n -- Note that sra and sla are not the same as the BIT_VECTOR version\n -- ===========================================================================\n\n function \"sll\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu is\n begin\n return fixedu (ufixed(ARG) sll COUNT);\n end function \"sll\";\n function \"srl\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu is\n begin\n return fixedu (ufixed(ARG) srl COUNT);\n end function \"srl\";\n function \"rol\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu is\n begin\n return fixedu (ufixed(ARG) rol COUNT);\n end function \"rol\";\n function \"ror\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu is\n begin\n return fixedu (ufixed(ARG) ror COUNT);\n end function \"ror\";\n function \"sla\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu is\n begin\n return fixedu (ufixed(ARG) sla COUNT);\n end function \"sla\";\n function \"sra\" (ARG : fixedu; COUNT : INTEGER)\n return fixedu is\n begin\n return fixedu (ufixed(ARG) sra COUNT);\n end function \"sra\";\n function \"sll\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds is\n begin\n return fixeds (sfixed(ARG) sll COUNT);\n end function \"sll\";\n function \"srl\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds is\n begin\n return fixeds (sfixed(ARG) srl COUNT);\n end function \"srl\";\n function \"rol\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds is\n begin\n return fixeds (sfixed(ARG) rol COUNT);\n end function \"rol\";\n function \"ror\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds is\n begin\n return fixeds (sfixed(ARG) ror COUNT);\n end function \"ror\";\n function \"sla\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds is\n begin\n return fixeds (sfixed(ARG) sla COUNT);\n end function \"sla\";\n function \"sra\" (ARG : fixeds; COUNT : INTEGER)\n return fixeds is\n begin\n return fixeds (sfixed(ARG) sra COUNT);\n end function \"sra\";\n function SHIFT_LEFT (ARG : fixedu; COUNT : NATURAL)\n return fixedu is\n begin\n return fixedu (SHIFT_LEFT (ufixed(ARG), COUNT));\n end function SHIFT_LEFT;\n function SHIFT_RIGHT (ARG : fixedu; COUNT : NATURAL)\n return fixedu is\n begin\n return fixedu (SHIFT_RIGHT (ufixed(ARG), COUNT));\n end function SHIFT_RIGHT;\n function SHIFT_LEFT (ARG : fixeds; COUNT : NATURAL)\n return fixeds is\n begin\n return fixeds (SHIFT_LEFT (sfixed(ARG), COUNT));\n end function SHIFT_LEFT;\n function SHIFT_RIGHT (ARG : fixeds; COUNT : NATURAL)\n return fixeds is\n begin\n return fixeds (SHIFT_RIGHT (sfixed(ARG), COUNT));\n end function SHIFT_RIGHT;\n\n ----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n\n function \"not\" (l : fixedu) return fixedu is\n begin\n return fixedu (not ufixed(l));\n end function \"not\";\n function \"and\" (l, r : fixedu) return fixedu is\n begin\n return fixedu (ufixed(l) and ufixed(r));\n end function \"and\";\n function \"or\" (l, r : fixedu) return fixedu is\n begin\n return fixedu (ufixed(l) or ufixed(r));\n end function \"or\";\n function \"nand\" (l, r : fixedu) return fixedu is\n begin\n return fixedu (ufixed(l) nand ufixed(r));\n end function \"nand\";\n function \"nor\" (l, r : fixedu) return fixedu is\n begin\n return fixedu (ufixed(l) nor ufixed(r));\n end function \"nor\";\n function \"xor\" (l, r : fixedu) return fixedu is\n begin\n return fixedu (ufixed(l) xor ufixed(r));\n end function \"xor\";\n function \"xnor\" (l, r : fixedu) return fixedu is\n begin\n return fixedu (ufixed(l) xnor ufixed(r));\n end function \"xnor\";\n function \"not\" (l : fixeds) return fixeds is\n begin\n return fixeds (not sfixed(l));\n end function \"not\";\n function \"and\" (l, r : fixeds) return fixeds is\n begin\n return fixeds (sfixed(l) and sfixed(r));\n end function \"and\";\n function \"or\" (l, r : fixeds) return fixeds is\n begin\n return fixeds (sfixed(l) or sfixed(r));\n end function \"or\";\n function \"nand\" (l, r : fixeds) return fixeds is\n begin\n return fixeds (sfixed(l) nand sfixed(r));\n end function \"nand\";\n function \"nor\" (l, r : fixeds) return fixeds is\n begin\n return fixeds (sfixed(l) nor sfixed(r));\n end function \"nor\";\n function \"xor\" (l, r : fixeds) return fixeds is\n begin\n return fixeds (sfixed(l) xor sfixed(r));\n end function \"xor\";\n function \"xnor\" (l, r : fixeds) return fixeds is\n begin\n return fixeds (sfixed(l) xnor sfixed(r));\n end function \"xnor\";\n\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (l : STD_ULOGIC; r : fixedu)\n return fixedu is\n begin\n return fixedu (l and ufixed(r));\n end function \"and\";\n function \"and\" (l : fixedu; r : STD_ULOGIC)\n return fixedu is\n begin\n return fixedu (ufixed(l) and r);\n end function \"and\";\n function \"or\" (l : STD_ULOGIC; r : fixedu)\n return fixedu is\n begin\n return fixedu (l or ufixed(r));\n end function \"or\";\n function \"or\" (l : fixedu; r : STD_ULOGIC)\n return fixedu is\n begin\n return fixedu (ufixed(l) or r);\n end function \"or\";\n function \"nand\" (l : STD_ULOGIC; r : fixedu)\n return fixedu is\n begin\n return fixedu (l nand ufixed(r));\n end function \"nand\";\n function \"nand\" (l : fixedu; r : STD_ULOGIC)\n return fixedu is\n begin\n return fixedu (ufixed(l) nand r);\n end function \"nand\";\n function \"nor\" (l : STD_ULOGIC; r : fixedu)\n return fixedu is\n begin\n return fixedu (l nor ufixed(r));\n end function \"nor\";\n function \"nor\" (l : fixedu; r : STD_ULOGIC)\n return fixedu is\n begin\n return fixedu (ufixed(l) nor r);\n end function \"nor\";\n function \"xor\" (l : STD_ULOGIC; r : fixedu)\n return fixedu is\n begin\n return fixedu (l xor ufixed(r));\n end function \"xor\";\n function \"xor\" (l : fixedu; r : STD_ULOGIC)\n return fixedu is\n begin\n return fixedu (ufixed(l) xor r);\n end function \"xor\";\n function \"xnor\" (l : STD_ULOGIC; r : fixedu)\n return fixedu is\n begin\n return fixedu (l xnor ufixed(r));\n end function \"xnor\";\n function \"xnor\" (l : fixedu; r : STD_ULOGIC)\n return fixedu is\n begin\n return fixedu (ufixed(l) xnor r);\n end function \"xnor\";\n function \"and\" (l : STD_ULOGIC; r : fixeds)\n return fixeds is\n begin\n return fixeds (l and sfixed(r));\n end function \"and\";\n function \"and\" (l : fixeds; r : STD_ULOGIC)\n return fixeds is\n begin\n return fixeds (sfixed(l) and r);\n end function \"and\";\n function \"or\" (l : STD_ULOGIC; r : fixeds)\n return fixeds is\n begin\n return fixeds (l or sfixed(r));\n end function \"or\";\n function \"or\" (l : fixeds; r : STD_ULOGIC)\n return fixeds is\n begin\n return fixeds (sfixed(l) or r);\n end function \"or\";\n function \"nand\" (l : STD_ULOGIC; r : fixeds)\n return fixeds is\n begin\n return fixeds (l nand sfixed(r));\n end function \"nand\";\n function \"nand\" (l : fixeds; r : STD_ULOGIC)\n return fixeds is\n begin\n return fixeds (sfixed(l) nand r);\n end function \"nand\";\n function \"nor\" (l : STD_ULOGIC; r : fixeds)\n return fixeds is\n begin\n return fixeds (l nor sfixed(r));\n end function \"nor\";\n function \"nor\" (l : fixeds; r : STD_ULOGIC)\n return fixeds is\n begin\n return fixeds (sfixed(l) nor r);\n end function \"nor\";\n function \"xor\" (l : STD_ULOGIC; r : fixeds)\n return fixeds is\n begin\n return fixeds (l xor sfixed(r));\n end function \"xor\";\n function \"xor\" (l : fixeds; r : STD_ULOGIC)\n return fixeds is\n begin\n return fixeds (sfixed(l) xor r);\n end function \"xor\";\n function \"xnor\" (l : STD_ULOGIC; r : fixeds)\n return fixeds is\n begin\n return fixeds (l xnor sfixed(r));\n end function \"xnor\";\n function \"xnor\" (l : fixeds; r : STD_ULOGIC)\n return fixeds is\n begin\n return fixeds (sfixed(l) xnor r);\n end function \"xnor\";\n\n -- Reduction operators, same as numeric_std functions\n function and_reduce (l : fixedu) return STD_ULOGIC is\n begin\n return and_reduce (ufixed(l));\n end function and_reduce;\n function nand_reduce (l : fixedu) return STD_ULOGIC is\n begin\n return nand_reduce (ufixed(l));\n end function nand_reduce;\n function or_reduce (l : fixedu) return STD_ULOGIC is\n begin\n return or_reduce (ufixed(l));\n end function or_reduce;\n function nor_reduce (l : fixedu) return STD_ULOGIC is\n begin\n return nor_reduce (ufixed(l));\n end function nor_reduce;\n function xor_reduce (l : fixedu) return STD_ULOGIC is\n begin\n return xor_reduce (ufixed(l));\n end function xor_reduce;\n function xnor_reduce (l : fixedu) return STD_ULOGIC is\n begin\n return xnor_reduce (ufixed(l));\n end function xnor_reduce;\n function and_reduce (l : fixeds) return STD_ULOGIC is\n begin\n return and_reduce (sfixed(l));\n end function and_reduce;\n function nand_reduce (l : fixeds) return STD_ULOGIC is\n begin\n return nand_reduce (sfixed(l));\n end function nand_reduce;\n function or_reduce (l : fixeds) return STD_ULOGIC is\n begin\n return or_reduce (sfixed(l));\n end function or_reduce;\n function nor_reduce (l : fixeds) return STD_ULOGIC is\n begin\n return nor_reduce (sfixed(l));\n end function nor_reduce;\n function xor_reduce (l : fixeds) return STD_ULOGIC is\n begin\n return xor_reduce (sfixed(l));\n end function xor_reduce;\n function xnor_reduce (l : fixeds) return STD_ULOGIC is\n begin\n return xnor_reduce (sfixed(l));\n end function xnor_reduce;\n\n -- returns arg'low-1 if not found\n function find_leftmost (arg : fixedu; y : STD_ULOGIC)\n return INTEGER is\n begin\n return find_leftmost (ufixed(arg), y);\n end function find_leftmost;\n function find_leftmost (arg : fixeds; y : STD_ULOGIC)\n return INTEGER is\n begin\n return find_leftmost (sfixed(arg), y);\n end function find_leftmost;\n\n -- returns arg'high+1 if not found\n function find_rightmost (arg : fixedu; y : STD_ULOGIC)\n return INTEGER is\n begin\n return find_rightmost (ufixed(arg), y);\n end function find_rightmost;\n function find_rightmost (arg : fixeds; y : STD_ULOGIC)\n return INTEGER is\n begin\n return find_rightmost (sfixed(arg), y);\n end function find_rightmost;\n\n -- ===========================================================================\n -- RESIZE Functions\n -- ===========================================================================\n -- resizes the number (larger or smaller)\n -- The returned result will be fixedu (left_index downto right_index)\n -- If \"round_style\" is fixed_round, then the result will be rounded.\n -- If the MSB of the remainder is a \"1\" AND the LSB of the unrounded result\n -- is a '1' or the lower bits of the remainder include a '1' then the result\n -- will be increased by the smallest representable number for that type.\n -- \"overflow_style\" can be fixed_saturate or fixed_wrap.\n -- In saturate mode, if the number overflows then the largest possible\n -- representable number is returned. If wrap mode, then the upper bits\n -- of the number are truncated.\n \n function resize (\n arg : fixedu; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := resize (arg => ufixed (arg),\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixedu(result);\n end function resize;\n\n -- \"size_res\" functions create the size of the output from the length\n -- of the \"size_res\" input. The actual value of \"size_res\" is not used.\n function resize (\n arg : fixedu; -- input\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := resize (arg => ufixed (arg),\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixedu(result);\n end function resize;\n\n -- Note that in \"wrap\" mode the sign bit is not replicated. Thus the\n -- resize of a negative number can have a positive result in wrap mode.\n function resize (\n arg : fixeds; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := resize (arg => sfixed (arg),\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixeds(result);\n end function resize;\n\n function resize (\n arg : fixeds; -- input\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := resize (arg => sfixed (arg),\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixeds(result);\n end function resize;\n\n -- ===========================================================================\n -- Conversion Functions\n -- ===========================================================================\n\n -- integer (natural) to unsigned fixed point.\n -- arguments are the upper and lower bounds of the number, thus\n -- fixedu (7 downto -3) <= to_fixedu (int, 7, -3);\n function to_fixedu (\n arg : NATURAL; -- integer\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := to_ufixed (arg => arg,\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixedu (result);\n end function to_fixedu;\n\n function to_fixedu (\n arg : NATURAL; -- integer\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixedu (result);\n end function to_fixedu;\n\n -- real to unsigned fixed point\n function to_fixedu (\n arg : REAL; -- real\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := to_ufixed (arg => arg,\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style,\n guard_bits => guard_bits);\n return fixedu (result);\n end function to_fixedu;\n\n function to_fixedu (\n arg : REAL; -- real\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style,\n guard_bits => guard_bits);\n return fixedu (result);\n end function to_fixedu;\n\n -- unsigned to unsigned fixed point\n function to_fixedu (\n arg : UNSIGNED; -- unsigned\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := to_ufixed (arg => arg,\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixedu (result);\n end function to_fixedu;\n\n function to_fixedu (\n arg : UNSIGNED; -- unsigned\n size_res : fixedu; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixedu (result);\n end function to_fixedu;\n\n -- Performs a conversion. fixedu (arg'range) is returned\n function to_fixedu (\n arg : UNSIGNED) -- unsigned\n return fixedu is\n variable result : ufixed (arg'range);\n begin\n result := to_ufixed (arg);\n return fixedu (result);\n end function to_fixedu;\n\n -- Conversion from fixeds to fixedu (performs an \"abs\" function)\n function to_fixedu (\n arg : fixeds)\n return fixedu is\n begin\n return fixedu (abs (arg));\n end function to_fixedu;\n\n -- unsigned fixed point to unsigned\n function to_unsigned (\n arg : fixedu; -- fixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED is\n begin\n return to_unsigned (arg => ufixed (arg),\n size => size,\n overflow_style => overflow_style,\n round_style => round_style);\n end function to_unsigned;\n\n -- unsigned fixed point to unsigned\n function to_unsigned (\n arg : fixedu; -- fixed point input\n size_res : UNSIGNED; -- used for length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED is\n begin\n return to_unsigned (arg => ufixed (arg),\n size => size_res'length,\n overflow_style => overflow_style,\n round_style => round_style);\n end function to_unsigned;\n\n -- unsigned fixed point to real\n function to_real (\n arg : fixedu) -- fixed point input\n return REAL is\n begin\n return to_real (ufixed (arg));\n end function to_real;\n\n -- unsigned fixed point to integer\n function to_integer (\n arg : fixedu; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return NATURAL is\n begin\n return to_integer (arg => ufixed (arg),\n overflow_style => overflow_style,\n round_style => round_style);\n end function to_integer;\n\n -- Integer to fixeds\n function to_fixeds (\n arg : INTEGER; -- integer\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := to_sfixed (arg => arg,\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixeds (result);\n end function to_fixeds;\n\n function to_fixeds (\n arg : INTEGER; -- integer\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixeds (result);\n end function to_fixeds;\n\n -- Real to fixeds\n function to_fixeds (\n arg : REAL; -- real\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := to_sfixed (arg => arg,\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style,\n guard_bits => guard_bits);\n return fixeds (result);\n end function to_fixeds;\n\n function to_fixeds (\n arg : REAL; -- real\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style,\n guard_bits => guard_bits);\n return fixeds (result);\n end function to_fixeds;\n\n -- signed to fixeds\n function to_fixeds (\n arg : SIGNED; -- signed\n constant left_index : INTEGER; -- size of integer portion\n constant right_index : INTEGER := 0; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := to_sfixed (arg => arg,\n left_index => left_index,\n right_index => right_index,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixeds (result);\n end function to_fixeds;\n\n function to_fixeds (\n arg : SIGNED; -- signed\n size_res : fixeds; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style);\n return fixeds (result);\n end function to_fixeds;\n\n -- signed to fixeds (output assumed to be size of signed input)\n function to_fixeds (\n arg : SIGNED) -- signed\n return fixeds is\n variable result : sfixed (arg'range);\n begin\n result := to_sfixed (arg);\n return fixeds (result);\n end function to_fixeds;\n\n -- Conversion from fixedu to fixeds\n function to_fixeds (\n arg : fixedu)\n return fixeds is\n variable result : sfixed (arg'high+1 downto arg'low);\n begin\n result := to_sfixed (ufixed (arg));\n return fixeds (result);\n end function to_fixeds;\n\n -- signed fixed point to signed\n function to_signed (\n arg : fixeds; -- fixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED is\n begin\n return to_signed (arg => sfixed (arg),\n size => size,\n overflow_style => overflow_style,\n round_style => round_style);\n end function to_signed;\n\n -- signed fixed point to signed\n function to_signed (\n arg : fixeds; -- fixed point input\n size_res : SIGNED; -- used for length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED is\n begin\n return to_signed (arg => sfixed (arg),\n size => size_res'length,\n overflow_style => overflow_style,\n round_style => round_style);\n end function to_signed;\n\n -- signed fixed point to real\n function to_real (\n arg : fixeds) -- fixed point input\n return REAL is\n begin\n return to_real (sfixed(arg));\n end function to_real;\n\n -- signed fixed point to integer\n function to_integer (\n arg : fixeds; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return INTEGER is\n begin\n return to_integer (arg => sfixed (arg),\n overflow_style => overflow_style,\n round_style => round_style);\n end function to_integer;\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := saturate (left_index, right_index);\n return fixedu (result);\n end function saturate;\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := saturate (left_index, right_index);\n return fixeds (result);\n end function saturate;\n\n function saturate (\n size_res : fixedu) -- only the size of this is used\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := saturate (size_res'high, size_res'low);\n return fixedu (result);\n end function saturate;\n\n function saturate (\n size_res : fixeds) -- only the size of this is used\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := saturate (size_res'high, size_res'low);\n return fixeds (result);\n end function saturate;\n\n -- ===========================================================================\n -- Translation Functions\n -- ===========================================================================\n\n -- maps meta-logical values\n function to_01 (\n s : fixedu; -- fixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return fixedu is\n variable result : ufixed (s'range);\n begin\n result := to_01 (ufixed(s), XMAP);\n return fixedu (result);\n end function to_01;\n\n -- maps meta-logical values\n function to_01 (\n s : fixeds; -- fixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return fixeds is\n variable result : sfixed (s'range);\n begin\n result := to_01 (sfixed(s), XMAP);\n return fixeds (result);\n end function to_01;\n\n function Is_X (arg : fixedu) return BOOLEAN is\n begin\n return Is_X (ufixed(arg));\n end function Is_X;\n function Is_X (arg : fixeds) return BOOLEAN is\n begin\n return Is_X (sfixed(arg));\n end function Is_X;\n function to_X01 (arg : fixedu) return fixedu is\n variable result : ufixed (arg'range);\n begin\n result := to_X01 (ufixed(arg));\n return fixedu (result);\n end function to_X01;\n function to_X01 (arg : fixeds) return fixeds is\n variable result : sfixed (arg'range);\n begin\n result := to_X01 (sfixed(arg));\n return fixeds (result);\n end function to_X01;\n function to_X01Z (arg : fixedu) return fixedu is\n variable result : ufixed (arg'range);\n begin\n result := to_X01Z (ufixed(arg));\n return fixedu (result);\n end function to_X01Z;\n function to_X01Z (arg : fixeds) return fixeds is\n variable result : sfixed (arg'range);\n begin\n result := to_X01Z (sfixed(arg));\n return fixeds (result);\n end function to_X01Z;\n function to_UX01 (arg : fixedu) return fixedu is\n variable result : ufixed (arg'range);\n begin\n result := to_UX01 (ufixed(arg));\n return fixedu (result);\n end function to_UX01;\n function to_UX01 (arg : fixeds) return fixeds is\n variable result : sfixed (arg'range);\n begin\n result := to_UX01 (sfixed(arg));\n return fixeds (result);\n end function to_UX01;\n\n -- straight vector conversion routines, needed for synthesis.\n -- These functions are here so that a std_logic_vector can be\n -- converted to and from fixeds and fixedu. Note that you can\n -- not convert these vectors because of their negative index.\n \n function to_slv (\n arg : fixedu) -- fixed point vector\n return STD_LOGIC_VECTOR is\n begin\n return to_slv (ufixed(arg));\n end function to_slv;\n\n function to_slv (\n arg : fixeds) -- fixed point vector\n return STD_LOGIC_VECTOR is\n begin\n return to_slv (sfixed(arg));\n end function to_slv;\n\n function to_sulv (\n arg : fixedu) -- fixed point vector\n return STD_ULOGIC_VECTOR is\n begin\n return to_sulv (ufixed(arg));\n end function to_sulv;\n\n\n function to_sulv (\n arg : fixeds) -- fixed point vector\n return STD_ULOGIC_VECTOR is\n begin\n return to_sulv (sfixed(arg));\n end function to_sulv;\n\n function to_fixedu (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := to_ufixed (arg => arg,\n left_index => left_index,\n right_index => right_index);\n return fixedu (result);\n end function to_fixedu;\n\n function to_fixedu (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : fixedu) -- for size only\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixedu (result);\n end function to_fixedu;\n\n function to_fixeds (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := to_sfixed (arg => arg,\n left_index => left_index,\n right_index => right_index);\n return fixeds (result);\n end function to_fixeds;\n\n function to_fixeds (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : fixeds) -- for size only\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixeds (result);\n end function to_fixeds;\n\n -- As a concession to those who use a graphical DSP environment,\n -- these functions take parameters in those tools format and create\n -- fixed point numbers. These functions are designed to convert from\n -- a std_logic_vector to the VHDL fixed point format using the conventions\n -- of these packages. In a pure VHDL environment you should use the\n -- \"to_fixedu\" and \"to_fixeds\" routines.\n\n -- unsigned fixed point\n function to_FixU (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixedu is\n begin\n return to_fixedu (arg, width-fraction, -fraction);\n end function to_FixU;\n\n -- signed fixed point\n function to_FixS (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixeds is\n begin\n return to_fixeds (arg, width-fraction, -fraction);\n end function to_FixS;\n\n-- rtl_synthesis off\n-- pragma synthesis_off\n -- ===========================================================================\n -- string and textio Functions\n -- ===========================================================================\n\n -- purpose: writes fixed point into a line\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in fixedu; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is \n begin\n WRITE (L => L,\n VALUE => ufixed(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure WRITE;\n\n -- purpose: writes fixed point into a line\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in fixeds; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is \n begin\n WRITE (L => L,\n VALUE => sfixed(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure WRITE;\n\n procedure READ(L : inout LINE;\n VALUE : out fixedu) is \n variable result : ufixed (VALUE'range);\n begin\n READ (L => L,\n VALUE => result);\n VALUE := fixedu (result);\n end procedure READ;\n\n procedure READ(L : inout LINE;\n VALUE : out fixedu;\n GOOD : out BOOLEAN) is \n", "right_context": " begin\n READ (L => L,\n VALUE => result,\n GOOD => GOOD);\n VALUE := fixedu (result);\n end procedure READ;\n\n procedure READ(L : inout LINE;\n VALUE : out fixeds) is \n variable result : sfixed (VALUE'range);\n begin\n READ (L => L,\n VALUE => result);\n VALUE := fixeds (result);\n end procedure READ;\n\n procedure READ(L : inout LINE;\n VALUE : out fixeds;\n GOOD : out BOOLEAN) is \n variable result : sfixed (VALUE'range);\n begin\n READ (L => L,\n VALUE => result,\n GOOD => GOOD);\n VALUE := fixeds (result);\n end procedure READ;\n\n -- octal read and write\n procedure OWRITE (\n L : inout LINE; -- input line\n VALUE : in fixedu; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is \n begin\n OWRITE (L => L,\n VALUE => ufixed(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure OWRITE;\n\n procedure OWRITE (\n L : inout LINE; -- input line\n VALUE : in fixeds; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is \n begin\n OWRITE (L => L,\n VALUE => sfixed(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure OWRITE;\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixedu) is \n variable result : ufixed (VALUE'range);\n begin\n OREAD (L => L,\n VALUE => result);\n VALUE := fixedu (result);\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixedu;\n GOOD : out BOOLEAN) is \n variable result : ufixed (VALUE'range);\n begin\n OREAD (L => L,\n VALUE => result,\n GOOD => GOOD);\n VALUE := fixedu (result);\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixeds) is \n variable result : sfixed (VALUE'range);\n begin\n OREAD (L => L,\n VALUE => result);\n VALUE := fixeds (result);\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE;\n VALUE : out fixeds;\n GOOD : out BOOLEAN) is \n variable result : sfixed (VALUE'range);\n begin\n OREAD (L => L,\n VALUE => result,\n GOOD => GOOD);\n VALUE := fixeds (result);\n end procedure OREAD;\n\n -- hex read and write\n procedure HWRITE (\n L : inout LINE; -- input line\n VALUE : in fixedu; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is \n begin\n HWRITE (L => L,\n VALUE => ufixed(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure HWRITE;\n\n -- purpose: writes fixed point into a line\n procedure HWRITE (\n L : inout LINE; -- input line\n VALUE : in fixeds; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is \n begin\n HWRITE (L => L,\n VALUE => sfixed(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure HWRITE;\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixedu) is \n variable result : ufixed (VALUE'range);\n begin\n HREAD (L => L,\n VALUE => result);\n VALUE := fixedu (result);\n end procedure HREAD;\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixedu;\n GOOD : out BOOLEAN) is \n variable result : ufixed (VALUE'range);\n begin\n HREAD (L => L,\n VALUE => result,\n GOOD => GOOD);\n VALUE := fixedu (result);\n end procedure HREAD;\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixeds) is \n variable result : sfixed (VALUE'range);\n begin\n HREAD (L => L,\n VALUE => result);\n VALUE := fixeds (result);\n end procedure HREAD;\n\n procedure HREAD(L : inout LINE;\n VALUE : out fixeds;\n GOOD : out BOOLEAN) is \n variable result : sfixed (VALUE'range);\n begin\n HREAD (L => L,\n VALUE => result,\n GOOD => GOOD);\n VALUE := fixeds (result);\n end procedure HREAD;\n\n -- returns a string, useful for:\n -- assert (x = y) report \"error found \" & to_string(x) severity error;\n function to_string (value : fixedu) return STRING is\n begin\n return to_string (ufixed (value));\n end function to_string;\n\n function to_ostring (value : fixedu) return STRING is\n begin\n return to_ostring (ufixed (value));\n end function to_ostring;\n\n function to_hstring (value : fixedu) return STRING is\n begin\n return to_hstring (ufixed (value));\n end function to_hstring;\n\n function to_string (value : fixeds) return STRING is\n begin\n return to_string (sfixed (value));\n end function to_string;\n\n function to_ostring (value : fixeds) return STRING is\n begin\n return to_ostring (sfixed (value));\n end function to_ostring;\n\n function to_hstring (value : fixeds) return STRING is\n begin\n return to_hstring (sfixed (value));\n end function to_hstring;\n\n -- From string functions allow you to convert a string into a fixed\n -- point number. Example:\n -- signal uf1 : fixedu (3 downto -3);\n -- uf1 <= from_string (\"0110.100\", uf1'high, uf1'low); -- 6.5\n -- The \".\" is optional in this syntax, however it exist and is\n -- in the wrong location an error is produced. Overflow will\n -- result in saturation.\n \n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := from_string (bstring => bstring,\n left_index => left_index,\n right_index => right_index);\n return fixedu (result);\n end function from_string;\n\n -- Octal and hex conversions work as follows:\n -- uf1 <= from_hstring (\"6.8\", 3, -3); -- 6.5 (bottom zeros dropped)\n -- uf1 <= from_ostring (\"06.4\", 3, -3); -- 6.5 (top zeros dropped)\n \n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := from_ostring (ostring => ostring,\n left_index => left_index,\n right_index => right_index);\n return fixedu (result);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := from_hstring (hstring => hstring,\n left_index => left_index,\n right_index => right_index);\n return fixedu (result);\n end function from_hstring;\n\n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := from_string (bstring => bstring,\n left_index => left_index,\n right_index => right_index);\n return fixeds (result);\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := from_ostring (ostring => ostring,\n left_index => left_index,\n right_index => right_index);\n return fixeds (result);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := from_hstring (hstring => hstring,\n left_index => left_index,\n right_index => right_index);\n return fixeds (result);\n end function from_hstring;\n\n -- Same as above, \"size_res\" is used for it's range only.\n function from_string (\n bstring : STRING; -- binary string\n size_res : fixedu)\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := from_string (bstring => bstring,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixedu (result);\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : fixedu)\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := from_ostring (ostring => ostring,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixedu (result);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : fixedu)\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := from_hstring (hstring => hstring,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixedu (result);\n end function from_hstring;\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : fixeds)\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := from_string (bstring => bstring,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixeds (result);\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : fixeds)\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := from_ostring (ostring => ostring,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixeds (result);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : fixeds)\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := from_hstring (hstring => hstring,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixeds (result);\n end function from_hstring;\n\n -- purpose: find a dot in a string, return -1 if no dot (internal function)\n function finddot (\n arg : STRING)\n return INTEGER is\n alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto\n begin\n for i in xarg'reverse_range loop\n if (xarg(i) = '.') then\n return i-1;\n end if;\n end loop;\n return -1;\n end function finddot;\n\n -- Direct conversion functions. Example:\n -- signal uf1 : fixedu (3 downto -3);\n -- uf1 <= from_string (\"0110.100\"); -- 6.5\n -- In this case the \".\" is not optional, and the size of\n -- the output must match exactly.\n \n function from_string (\n bstring : STRING) -- binary string\n return fixedu is\n variable result : ufixed (bstring'length-2 downto 0);\n variable dot : NATURAL;\n begin \n dot := finddot(bstring);\n result := from_string (bstring);\n return to_fixedu (to_sulv (result), result'high-dot, -dot);\n end function from_string;\n -- Direct octal and hex conversion functions. In this case\n -- the string lengths must match. Example:\n -- signal sf1 := fixeds (5 downto -3);\n -- sf1 <= from_ostring (\"71.4\") -- -6.5\n \n function from_ostring (\n ostring : STRING) -- Octal string\n return fixedu is\n variable result : ufixed ((ostring'length-1)*3-1 downto 0);\n variable dot : NATURAL;\n begin \n dot := finddot(ostring);\n result := from_ostring (ostring);\n return to_fixedu (to_sulv (result), (ostring'length-1-dot)*3-1, -dot*3);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING) -- hex string\n return fixedu is\n variable result : ufixed ((hstring'length-1)*4-1 downto 0);\n variable dot : NATURAL;\n begin \n dot := finddot(hstring);\n result := from_hstring (hstring);\n return to_fixedu (to_sulv (result), (hstring'length-1-dot)*4-1, -dot*4);\n end function from_hstring;\n\n function from_string (\n bstring : STRING) -- binary string\n return fixeds is\n variable result : sfixed (bstring'length-2 downto 0);\n variable dot : NATURAL;\n begin \n dot := finddot(bstring);\n result := from_string (bstring);\n return to_fixeds (to_sulv (result), result'high-dot, -dot);\n end function from_string;\n\n function from_ostring (\n ostring : STRING) -- Octal string\n return fixeds is\n variable result : sfixed ((ostring'length-1)*3-1 downto 0);\n variable dot : NATURAL;\n begin \n dot := finddot(ostring);\n result := from_ostring (ostring);\n return to_fixeds (to_sulv (result), (ostring'length-1-dot)*3-1, -dot*3);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING) -- hex string\n return fixeds is\n variable result : sfixed ((hstring'length-1)*4-1 downto 0);\n variable dot : NATURAL;\n begin \n dot := finddot(hstring);\n result := from_hstring (hstring);\n return to_fixeds (to_sulv (result), (hstring'length-1-dot)*4-1, -dot*4);\n end function from_hstring;\n-- rtl_synthesis on\n-- pragma synthesis_on\n\n -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these\n -- extra functions are needed for compatability.\n function to_fixedu (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixedu is\n variable result : ufixed (left_index downto right_index);\n begin\n result := to_ufixed (arg => arg,\n left_index => left_index,\n right_index => right_index);\n return fixedu (result);\n end function to_fixedu;\n\n function to_fixedu (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : fixedu) -- for size only\n return fixedu is\n variable result : ufixed (size_res'range);\n begin\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixedu (result);\n end function to_fixedu;\n\n function to_fixeds (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return fixeds is\n variable result : sfixed (left_index downto right_index);\n begin\n result := to_sfixed (arg => arg,\n left_index => left_index,\n right_index => right_index);\n return fixeds (result);\n end function to_fixeds;\n\n function to_fixeds (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : fixeds) -- for size only\n return fixeds is\n variable result : sfixed (size_res'range);\n begin\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low);\n return fixeds (result);\n end function to_fixeds;\n\n -- unsigned fixed point\n function to_FixU (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixedu is\n begin\n return to_fixedu (arg, width-fraction, -fraction);\n end function to_FixU;\n\n -- signed fixed point\n function to_FixS (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return fixeds is\n begin\n return to_fixeds (arg, width-fraction, -fraction);\n end function to_FixS;\n\n\nend package body fixed_noresize;\n", "groundtruth": " variable result : ufixed (VALUE'range);\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/fixed_pkg_c.vhdl", "left_context": "-- --------------------------------------------------------------------\n-- \"fixed_pkg_c.vhdl\" package contains functions for fixed point math.\n-- Please see the documentation for the fixed point package.\n-- This package should be compiled into \"ieee_proposed\" and used as follows:\n-- use ieee.std_logic_1164.all;\n-- use ieee.numeric_std.all;\n-- use ieee_proposed.fixed_float_types.all;\n-- use ieee_proposed.fixed_pkg.all;\n--\n-- This verison is designed to work with the VHDL-93 compilers \n-- synthesis tools. Please note the \"%%%\" comments. These are where we\n-- diverge from the VHDL-200X LRM.\n-- --------------------------------------------------------------------\n-- Version : $Revision: 2.0 $\n-- Date : $Date: 2011/01/26 15:55:27 $\n-- --------------------------------------------------------------------\n\nuse STD.TEXTIO.all;\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\nuse IEEE.NUMERIC_STD.all;\nlibrary IEEE_PROPOSED;\nuse IEEE_PROPOSED.fixed_float_types.all;\n\npackage fixed_pkg is\n-- generic (\n -- Rounding routine to use in fixed point, fixed_round or fixed_truncate\n constant fixed_round_style : fixed_round_style_type := fixed_round;\n -- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap\n constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;\n -- Extra bits used in divide routines\n constant fixed_guard_bits : NATURAL := 3;\n -- If TRUE, then turn off warnings on \"X\" propagation\n constant no_warning : BOOLEAN := (false\n );\n\n -- Author David Bishop (dbishop@vhdl.org)\n\n -- base Unsigned fixed point type, downto direction assumed\n type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;\n -- base Signed fixed point type, downto direction assumed\n type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;\n\n subtype U_ufixed is UNRESOLVED_ufixed;\n subtype U_sfixed is UNRESOLVED_sfixed;\n\n subtype ufixed is UNRESOLVED_ufixed;\n subtype sfixed is UNRESOLVED_sfixed;\n\n --===========================================================================\n -- Arithmetic Operators:\n --===========================================================================\n\n -- Absolute value, 2's complement\n -- abs sfixed(a downto b) = sfixed(a+1 downto b)\n function \"abs\" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- Negation, 2's complement\n -- - sfixed(a downto b) = sfixed(a+1 downto b)\n function \"-\" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;\n\n -- Addition\n -- ufixed(a downto b) + ufixed(c downto d)\n -- = ufixed(maximum(a,c)+1 downto minimum(b,d))\n function \"+\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- sfixed(a downto b) + sfixed(c downto d)\n -- = sfixed(maximum(a,c)+1 downto minimum(b,d))\n function \"+\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- Subtraction\n -- ufixed(a downto b) - ufixed(c downto d)\n -- = ufixed(maximum(a,c)+1 downto minimum(b,d))\n function \"-\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- sfixed(a downto b) - sfixed(c downto d)\n -- = sfixed(maximum(a,c)+1 downto minimum(b,d))\n function \"-\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- Multiplication\n -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)\n function \"*\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)\n function \"*\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- Division\n -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)\n function \"/\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)\n function \"/\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- Remainder\n -- ufixed (a downto b) rem ufixed (c downto d)\n -- = ufixed (minimum(a,c) downto minimum(b,d))\n function \"rem\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- sfixed (a downto b) rem sfixed (c downto d)\n -- = sfixed (minimum(a,c) downto minimum(b,d))\n function \"rem\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- Modulo\n -- ufixed (a downto b) mod ufixed (c downto d)\n -- = ufixed (minimum(a,c) downto minimum(b, d))\n function \"mod\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- sfixed (a downto b) mod sfixed (c downto d)\n -- = sfixed (c downto minimum(b, d))\n function \"mod\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n ----------------------------------------------------------------------------\n -- In these routines the \"real\" or \"natural\" (integer)\n -- are converted into a fixed point number and then the operation is\n -- performed. It is assumed that the array will be large enough.\n -- If the input is \"real\" then the real number is converted into a fixed of\n -- the same size as the fixed point input. If the number is an \"integer\"\n -- then it is converted into fixed with the range (l'high downto 0).\n ----------------------------------------------------------------------------\n\n -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)\n function \"+\" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n\n -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)\n function \"+\" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))\n function \"+\" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))\n function \"+\" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)\n function \"-\" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n\n -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)\n function \"-\" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))\n function \"-\" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))\n function \"-\" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)\n function \"*\" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n\n -- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)\n function \"*\" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)\n function \"*\" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;\n\n -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)\n function \"*\" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)\n function \"/\" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)\n function \"/\" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)\n function \"/\" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;\n\n -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)\n function \"/\" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)\n function \"rem\" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n\n -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)\n function \"rem\" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))\n function \"rem\" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;\n\n -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))\n function \"rem\" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)\n function \"mod\" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n\n -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)\n function \"mod\" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))\n function \"mod\" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;\n\n -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))\n function \"mod\" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n\n -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)\n function \"+\" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)\n function \"+\" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))\n function \"+\" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))\n function \"+\" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)\n function \"-\" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)\n function \"-\" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))\n function \"-\" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))\n function \"-\" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)\n function \"*\" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)\n function \"*\" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)\n function \"*\" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)\n function \"*\" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)\n function \"/\" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)\n function \"/\" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)\n function \"/\" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;\n\n -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)\n function \"/\" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)\n function \"rem\" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n\n -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)\n function \"rem\" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))\n function \"rem\" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;\n\n -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))\n function \"rem\" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)\n function \"mod\" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n\n -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)\n function \"mod\" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))\n function \"mod\" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;\n\n -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))\n function \"mod\" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- This version of divide gives the user more control\n -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)\n function divide (\n l, r : UNRESOLVED_ufixed;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed;\n\n -- This version of divide gives the user more control\n -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)\n function divide (\n l, r : UNRESOLVED_sfixed;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed;\n\n -- These functions return 1/X\n -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)\n function reciprocal (\n arg : UNRESOLVED_ufixed; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed;\n\n -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)\n function reciprocal (\n arg : UNRESOLVED_sfixed; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed;\n\n -- REM function\n -- ufixed (a downto b) rem ufixed (c downto d)\n -- = ufixed (minimum(a,c) downto minimum(b,d))\n function remainder (\n l, r : UNRESOLVED_ufixed;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed;\n\n -- sfixed (a downto b) rem sfixed (c downto d)\n -- = sfixed (minimum(a,c) downto minimum(b,d))\n function remainder (\n l, r : UNRESOLVED_sfixed;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed;\n\n -- mod function\n -- ufixed (a downto b) mod ufixed (c downto d)\n -- = ufixed (minimum(a,c) downto minimum(b, d))\n function modulo (\n l, r : UNRESOLVED_ufixed;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed;\n\n -- sfixed (a downto b) mod sfixed (c downto d)\n -- = sfixed (c downto minimum(b, d))\n function modulo (\n l, r : UNRESOLVED_sfixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed;\n\n -- Procedure for those who need an \"accumulator\" function.\n -- add_carry (ufixed(a downto b), ufixed (c downto d))\n -- = ufixed (maximum(a,c) downto minimum(b,d))\n procedure add_carry (\n L, R : in UNRESOLVED_ufixed;\n c_in : in STD_ULOGIC;\n result : out UNRESOLVED_ufixed;\n c_out : out STD_ULOGIC);\n\n -- add_carry (sfixed(a downto b), sfixed (c downto d))\n -- = sfixed (maximum(a,c) downto minimum(b,d))\n procedure add_carry (\n L, R : in UNRESOLVED_sfixed;\n c_in : in STD_ULOGIC;\n result : out UNRESOLVED_sfixed;\n c_out : out STD_ULOGIC);\n\n -- Scales the result by a power of 2. Width of input = width of output with\n -- the binary point moved.\n function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;\n function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;\n function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;\n function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;\n\n function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;\n\n --===========================================================================\n -- Comparison Operators\n --===========================================================================\n\n function \">\" (l, r : UNRESOLVED_ufixed) return BOOLEAN;\n function \">\" (l, r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"<\" (l, r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"<\" (l, r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"<=\" (l, r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"<=\" (l, r : UNRESOLVED_sfixed) return BOOLEAN;\n function \">=\" (l, r : UNRESOLVED_ufixed) return BOOLEAN;\n function \">=\" (l, r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"=\" (l, r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"=\" (l, r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"/=\" (l, r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"/=\" (l, r : UNRESOLVED_sfixed) return BOOLEAN;\n\n function \\?=\\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?/=\\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?>\\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?>=\\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?<\\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?<=\\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?=\\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?/=\\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?>\\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?>=\\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?<\\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?<=\\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;\n\n function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;\n function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;\n\n -- Overloads the default \"maximum\" and \"minimum\" function\n\n function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n ----------------------------------------------------------------------------\n -- In these compare functions a natural is converted into a\n -- fixed point number of the bounds \"maximum(l'high,0) downto 0\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;\n function \">\" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;\n\n function \"=\" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"/=\" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \">=\" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"<=\" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \">\" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"<\" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n \n function \\?=\\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;\n\n function \\?=\\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?/=\\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?>=\\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?<=\\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?>\\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?<\\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n\n function maximum (l : UNRESOLVED_ufixed; r : NATURAL)\n return UNRESOLVED_ufixed;\n function minimum (l : UNRESOLVED_ufixed; r : NATURAL)\n return UNRESOLVED_ufixed;\n function maximum (l : NATURAL; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n function minimum (l : NATURAL; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n ----------------------------------------------------------------------------\n -- In these compare functions a real is converted into a\n -- fixed point number of the bounds \"l'high+1 downto l'low\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;\n function \">\" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;\n\n function \"=\" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"/=\" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \">=\" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"<=\" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \">\" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n function \"<\" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;\n\n function \\?=\\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;\n\n function \\?=\\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?/=\\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?>=\\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?<=\\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?>\\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n function \\?<\\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;\n\n function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;\n function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n ----------------------------------------------------------------------------\n -- In these compare functions an integer is converted into a\n -- fixed point number of the bounds \"maximum(l'high,1) downto 0\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;\n function \">\" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;\n\n function \"=\" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"/=\" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \">=\" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"<=\" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \">\" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"<\" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;\n\n function \\?=\\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;\n\n function \\?=\\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?/=\\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?>=\\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?<=\\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?>\\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?<\\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n\n function maximum (l : UNRESOLVED_sfixed; r : INTEGER)\n return UNRESOLVED_sfixed;\n function maximum (l : INTEGER; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n function minimum (l : UNRESOLVED_sfixed; r : INTEGER)\n return UNRESOLVED_sfixed;\n function minimum (l : INTEGER; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n ----------------------------------------------------------------------------\n -- In these compare functions a real is converted into a\n -- fixed point number of the bounds \"l'high+1 downto l'low\"\n ----------------------------------------------------------------------------\n\n function \"=\" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;\n function \">\" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;\n\n function \"=\" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"/=\" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \">=\" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"<=\" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \">\" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;\n function \"<\" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;\n\n function \\?=\\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;\n\n function \\?=\\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?/=\\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?>=\\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?<=\\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?>\\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n function \\?<\\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;\n\n function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;\n function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n --===========================================================================\n -- Shift and Rotate Functions.\n -- Note that sra and sla are not the same as the BIT_VECTOR version\n --===========================================================================\n\n function \"sll\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed;\n function \"srl\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed;\n function \"rol\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed;\n function \"ror\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed;\n function \"sla\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed;\n function \"sra\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed;\n function \"sll\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed;\n function \"srl\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed;\n function \"rol\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed;\n function \"ror\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed;\n function \"sla\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed;\n function \"sra\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed;\n function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)\n return UNRESOLVED_ufixed;\n function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)\n return UNRESOLVED_ufixed;\n function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)\n return UNRESOLVED_sfixed;\n function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)\n return UNRESOLVED_sfixed;\n\n ----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n\n function \"not\" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function \"and\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function \"or\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function \"nand\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function \"nor\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function \"xor\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function \"xnor\" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function \"not\" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function \"and\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function \"or\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function \"nand\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function \"nor\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function \"xor\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function \"xnor\" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n function \"and\" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)\n return UNRESOLVED_ufixed;\n function \"or\" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n function \"or\" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)\n return UNRESOLVED_ufixed;\n function \"nand\" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n function \"nand\" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)\n return UNRESOLVED_ufixed;\n function \"nor\" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n function \"nor\" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)\n return UNRESOLVED_ufixed;\n function \"xor\" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n function \"xor\" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)\n return UNRESOLVED_ufixed;\n function \"xnor\" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n function \"xnor\" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)\n return UNRESOLVED_ufixed;\n function \"and\" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n function \"and\" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)\n return UNRESOLVED_sfixed;\n function \"or\" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n function \"or\" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)\n return UNRESOLVED_sfixed;\n function \"nand\" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n function \"nand\" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)\n return UNRESOLVED_sfixed;\n function \"nor\" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n function \"nor\" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)\n return UNRESOLVED_sfixed;\n function \"xor\" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n function \"xor\" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)\n return UNRESOLVED_sfixed;\n function \"xnor\" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n function \"xnor\" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)\n return UNRESOLVED_sfixed;\n\n -- Reduction operators, same as numeric_std functions\n function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;\n function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;\n function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;\n function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;\n function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;\n function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;\n function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;\n function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;\n function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;\n function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;\n function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;\n function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;\n\n -- returns arg'low-1 if not found\n function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)\n return INTEGER;\n function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)\n return INTEGER;\n\n -- returns arg'high+1 if not found\n function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)\n return INTEGER;\n function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)\n return INTEGER;\n\n --===========================================================================\n -- RESIZE Functions\n --===========================================================================\n -- resizes the number (larger or smaller)\n -- The returned result will be ufixed (left_index downto right_index)\n -- If \"round_style\" is fixed_round, then the result will be rounded.\n -- If the MSB of the remainder is a \"1\" AND the LSB of the unrounded result\n -- is a '1' or the lower bits of the remainder include a '1' then the result\n -- will be increased by the smallest representable number for that type.\n -- \"overflow_style\" can be fixed_saturate or fixed_wrap.\n -- In saturate mode, if the number overflows then the largest possible\n -- representable number is returned. If wrap mode, then the upper bits\n -- of the number are truncated.\n \n function resize (\n arg : UNRESOLVED_ufixed; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed;\n\n -- \"size_res\" functions create the size of the output from the indices\n -- of the \"size_res\" input. The actual value of \"size_res\" is not used.\n function resize (\n arg : UNRESOLVED_ufixed; -- input\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed;\n\n -- Note that in \"wrap\" mode the sign bit is not replicated. Thus the\n -- resize of a negative number can have a positive result in wrap mode.\n function resize (\n arg : UNRESOLVED_sfixed; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed;\n\n function resize (\n arg : UNRESOLVED_sfixed; -- input\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed;\n\n --===========================================================================\n -- Conversion Functions\n --===========================================================================\n\n -- integer (natural) to unsigned fixed point.\n -- arguments are the upper and lower bounds of the number, thus\n -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);\n function to_ufixed (\n arg : NATURAL; -- integer\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed;\n\n function to_ufixed (\n arg : NATURAL; -- integer\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed;\n\n -- real to unsigned fixed point\n function to_ufixed (\n arg : REAL; -- real\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed;\n\n function to_ufixed (\n arg : REAL; -- real\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed;\n\n -- unsigned to unsigned fixed point\n function to_ufixed (\n arg : UNSIGNED; -- unsigned\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed;\n\n function to_ufixed (\n arg : UNSIGNED; -- unsigned\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed;\n\n -- Performs a conversion. ufixed (arg'range) is returned\n function to_ufixed (\n arg : UNSIGNED) -- unsigned\n return UNRESOLVED_ufixed;\n\n -- unsigned fixed point to unsigned\n function to_unsigned (\n arg : UNRESOLVED_ufixed; -- fixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED;\n\n -- unsigned fixed point to unsigned\n function to_unsigned (\n arg : UNRESOLVED_ufixed; -- fixed point input\n size_res : UNSIGNED; -- used for length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED;\n\n -- unsigned fixed point to real\n function to_real (\n arg : UNRESOLVED_ufixed) -- fixed point input\n return REAL;\n\n -- unsigned fixed point to integer\n function to_integer (\n arg : UNRESOLVED_ufixed; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return NATURAL;\n\n -- Integer to UNRESOLVED_sfixed\n function to_sfixed (\n arg : INTEGER; -- integer\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed;\n\n function to_sfixed (\n arg : INTEGER; -- integer\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed;\n\n -- Real to sfixed\n function to_sfixed (\n arg : REAL; -- real\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed;\n\n function to_sfixed (\n arg : REAL; -- real\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed;\n\n -- signed to sfixed\n function to_sfixed (\n arg : SIGNED; -- signed\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed;\n\n function to_sfixed (\n arg : SIGNED; -- signed\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed;\n\n -- signed to sfixed (output assumed to be size of signed input)\n function to_sfixed (\n arg : SIGNED) -- signed\n return UNRESOLVED_sfixed;\n\n -- Conversion from ufixed to sfixed\n function to_sfixed (\n arg : UNRESOLVED_ufixed)\n return UNRESOLVED_sfixed;\n\n -- signed fixed point to signed\n function to_signed (\n arg : UNRESOLVED_sfixed; -- fixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED;\n\n -- signed fixed point to signed\n function to_signed (\n arg : UNRESOLVED_sfixed; -- fixed point input\n size_res : SIGNED; -- used for length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED;\n\n -- signed fixed point to real\n function to_real (\n arg : UNRESOLVED_sfixed) -- fixed point input\n return REAL;\n\n -- signed fixed point to integer\n function to_integer (\n arg : UNRESOLVED_sfixed; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return INTEGER;\n\n -- Because of the fairly complicated sizing rules in the fixed point\n -- packages these functions are provided to compute the result ranges\n -- Example:\n -- signal uf1 : ufixed (3 downto -3);\n -- signal uf2 : ufixed (4 downto -2);\n -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto\n -- ufixed_low (3, -3, '*', 4, -2));\n -- uf1multuf2 <= uf1 * uf2;\n -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),\n -- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)\n function ufixed_high (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER;\n \n function ufixed_low (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER;\n \n function sfixed_high (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER;\n \n function sfixed_low (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER;\n\n -- Same as above, but using the \"size_res\" input only for their ranges:\n -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto\n -- ufixed_low (uf1, '*', uf2));\n -- uf1multuf2 <= uf1 * uf2;\n -- \n function ufixed_high (size_res : UNRESOLVED_ufixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_ufixed)\n return INTEGER;\n \n function ufixed_low (size_res : UNRESOLVED_ufixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_ufixed)\n return INTEGER;\n \n function sfixed_high (size_res : UNRESOLVED_sfixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_sfixed)\n return INTEGER;\n \n function sfixed_low (size_res : UNRESOLVED_sfixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_sfixed)\n return INTEGER;\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed;\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed;\n\n function saturate (\n size_res : UNRESOLVED_ufixed) -- only the size of this is used\n return UNRESOLVED_ufixed;\n\n function saturate (\n size_res : UNRESOLVED_sfixed) -- only the size of this is used\n return UNRESOLVED_sfixed;\n\n --===========================================================================\n -- Translation Functions\n --===========================================================================\n\n -- maps meta-logical values\n function to_01 (\n s : UNRESOLVED_ufixed; -- fixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return UNRESOLVED_ufixed;\n\n -- maps meta-logical values\n function to_01 (\n s : UNRESOLVED_sfixed; -- fixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return UNRESOLVED_sfixed;\n\n function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;\n function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;\n function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;\n function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;\n\n -- straight vector conversion routines, needed for synthesis.\n -- These functions are here so that a std_logic_vector can be\n -- converted to and from sfixed and ufixed. Note that you can\n -- not convert these vectors because of their negative index.\n \n function to_slv (\n arg : UNRESOLVED_ufixed) -- fixed point vector\n return STD_LOGIC_VECTOR;\n alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed\n return STD_LOGIC_VECTOR];\n alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed\n return STD_LOGIC_VECTOR];\n\n function to_slv (\n arg : UNRESOLVED_sfixed) -- fixed point vector\n return STD_LOGIC_VECTOR;\n alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed\n return STD_LOGIC_VECTOR];\n alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed\n return STD_LOGIC_VECTOR];\n\n function to_sulv (\n arg : UNRESOLVED_ufixed) -- fixed point vector\n return STD_ULOGIC_VECTOR;\n alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed\n return STD_ULOGIC_VECTOR];\n alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed\n return STD_ULOGIC_VECTOR];\n\n function to_sulv (\n arg : UNRESOLVED_sfixed) -- fixed point vector\n return STD_ULOGIC_VECTOR;\n alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed\n return STD_ULOGIC_VECTOR];\n alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed\n return STD_ULOGIC_VECTOR];\n\n function to_ufixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed;\n\n function to_ufixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_ufixed) -- for size only\n return UNRESOLVED_ufixed;\n\n function to_sfixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed;\n\n function to_sfixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_sfixed) -- for size only\n return UNRESOLVED_sfixed;\n\n -- As a concession to those who use a graphical DSP environment,\n -- these functions take parameters in those tools format and create\n -- fixed point numbers. These functions are designed to convert from\n -- a std_logic_vector to the VHDL fixed point format using the conventions\n -- of these packages. In a pure VHDL environment you should use the\n -- \"to_ufixed\" and \"to_sfixed\" routines.\n\n -- unsigned fixed point\n function to_UFix (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_ufixed;\n\n -- signed fixed point\n function to_SFix (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_sfixed;\n\n -- finding the bounds of a number. These functions can be used like this:\n -- signal xxx : ufixed (7 downto -3);\n -- -- Which is the same as \"ufixed (UFix_high (11,3) downto UFix_low(11,3))\"\n -- signal yyy : ufixed (UFix_high (11, 3, \"+\", 11, 3)\n -- downto UFix_low(11, 3, \"+\", 11, 3));\n -- Where \"11\" is the width of xxx (xxx'length),\n -- and 3 is the lower bound (abs (xxx'low))\n -- In a pure VHDL environment use \"ufixed_high\" and \"ufixed_low\"\n \n function UFix_high (width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER;\n \n function UFix_low (width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER;\n\n -- Same as above but for signed fixed point. Note that the width\n -- of a signed fixed point number ignores the sign bit, thus\n -- width = sxxx'length-1\n \n function SFix_high (width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER;\n \n function SFix_low (width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER;\n-- rtl_synthesis off\n-- pragma synthesis_off\n --===========================================================================\n -- string and textio Functions\n --===========================================================================\n\n -- purpose: writes fixed point into a line\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_ufixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n -- purpose: writes fixed point into a line\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_sfixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed);\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed;\n GOOD : out BOOLEAN);\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed);\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed;\n GOOD : out BOOLEAN);\n\n alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];\n alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];\n alias bread is READ [LINE, UNRESOLVED_ufixed];\n alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];\n alias bread is READ [LINE, UNRESOLVED_sfixed];\n alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];\n alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];\n alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];\n alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];\n alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];\n alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];\n alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];\n\n -- octal read and write\n procedure OWRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_ufixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure OWRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_sfixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure OREAD(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed);\n\n procedure OREAD(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed;\n GOOD : out BOOLEAN);\n\n procedure OREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed);\n\n procedure OREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed;\n GOOD : out BOOLEAN);\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];\n alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];\n alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];\n\n -- hex read and write\n procedure HWRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_ufixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n -- purpose: writes fixed point into a line\n procedure HWRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_sfixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0);\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed);\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed;\n GOOD : out BOOLEAN);\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed);\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed;\n GOOD : out BOOLEAN);\n alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];\n alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];\n alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];\n alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];\n alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];\n alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];\n\n -- returns a string, useful for:\n -- assert (x = y) report \"error found \" & to_string(x) severity error;\n function to_string (value : UNRESOLVED_ufixed) return STRING;\n alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];\n alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];\n\n function to_ostring (value : UNRESOLVED_ufixed) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];\n\n function to_hstring (value : UNRESOLVED_ufixed) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];\n\n function to_string (value : UNRESOLVED_sfixed) return STRING;\n alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];\n alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];\n\n function to_ostring (value : UNRESOLVED_sfixed) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];\n\n function to_hstring (value : UNRESOLVED_sfixed) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];\n\n -- From string functions allow you to convert a string into a fixed\n -- point number. Example:\n -- signal uf1 : ufixed (3 downto -3);\n -- uf1 <= from_string (\"0110.100\", uf1'high, uf1'low); -- 6.5\n -- The \".\" is optional in this syntax, however it exist and is\n -- in the wrong location an error is produced. Overflow will\n -- result in saturation.\n \n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed;\n alias from_bstring is from_string [STRING, INTEGER, INTEGER\n return UNRESOLVED_ufixed];\n alias from_binary_string is from_string [STRING, INTEGER, INTEGER\n return UNRESOLVED_ufixed];\n\n -- Octal and hex conversions work as follows:\n -- uf1 <= from_hstring (\"6.8\", 3, -3); -- 6.5 (bottom zeros dropped)\n -- uf1 <= from_ostring (\"06.4\", 3, -3); -- 6.5 (top zeros dropped)\n \n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed;\n alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER\n return UNRESOLVED_ufixed];\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed;\n alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER\n return UNRESOLVED_ufixed];\n\n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed;\n alias from_bstring is from_string [STRING, INTEGER, INTEGER\n return UNRESOLVED_sfixed];\n alias from_binary_string is from_string [STRING, INTEGER, INTEGER\n return UNRESOLVED_sfixed];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed;\n alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER\n return UNRESOLVED_sfixed];\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed;\n alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER\n return UNRESOLVED_sfixed];\n\n -- Same as above, \"size_res\" is used for it's range only.\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n alias from_bstring is from_string [STRING, UNRESOLVED_ufixed\n return UNRESOLVED_ufixed];\n alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed\n return UNRESOLVED_ufixed];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed\n return UNRESOLVED_ufixed];\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed;\n alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed\n return UNRESOLVED_ufixed];\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n alias from_bstring is from_string [STRING, UNRESOLVED_sfixed\n return UNRESOLVED_sfixed];\n alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed\n return UNRESOLVED_sfixed];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed\n return UNRESOLVED_sfixed];\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed;\n alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed\n return UNRESOLVED_sfixed];\n\n -- Direct conversion functions. Example:\n -- signal uf1 : ufixed (3 downto -3);\n -- uf1 <= from_string (\"0110.100\"); -- 6.5\n -- In this case the \".\" is not optional, and the size of\n -- the output must match exactly.\n \n function from_string (\n bstring : STRING) -- binary string\n return UNRESOLVED_ufixed;\n alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];\n alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];\n\n -- Direct octal and hex conversion functions. In this case\n -- the string lengths must match. Example:\n -- signal sf1 := sfixed (5 downto -3);\n -- sf1 <= from_ostring (\"71.4\") -- -6.5\n \n function from_ostring (\n ostring : STRING) -- Octal string\n return UNRESOLVED_ufixed;\n alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];\n\n function from_hstring (\n hstring : STRING) -- hex string\n return UNRESOLVED_ufixed;\n alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];\n\n function from_string (\n bstring : STRING) -- binary string\n return UNRESOLVED_sfixed;\n alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];\n alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];\n\n function from_ostring (\n ostring : STRING) -- Octal string\n return UNRESOLVED_sfixed;\n alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];\n\n function from_hstring (\n hstring : STRING) -- hex string\n return UNRESOLVED_sfixed;\n alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];\n-- rtl_synthesis on\n-- pragma synthesis_on\n\n -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these\n -- extra functions are needed for compatability.\n function to_ufixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed;\n\n function to_ufixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_ufixed) -- for size only\n return UNRESOLVED_ufixed;\n\n function to_sfixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed;\n\n function to_sfixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_sfixed) -- for size only\n return UNRESOLVED_sfixed;\n\n -- unsigned fixed point\n function to_UFix (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_ufixed;\n\n -- signed fixed point\n function to_SFix (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_sfixed;\n\nend package fixed_pkg;\n-------------------------------------------------------------------------------\n-- Proposed package body for the VHDL-200x-FT fixed_pkg package\n-- (Fixed point math package)\n-- This package body supplies a recommended implementation of these functions\n-- Version : $Revision: 2.0 $\n-- Date : $Date: 2011/01/26 15:55:27 $\n--\n-- Created for VHDL-200X-ft, David Bishop (dbishop@vhdl.org)\n-------------------------------------------------------------------------------\nlibrary IEEE;\nuse IEEE.MATH_REAL.all;\n\npackage body fixed_pkg is\n -- Author David Bishop (dbishop@vhdl.org)\n -- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton\n -- null array constants\n constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');\n constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');\n constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');\n\n -- This differed constant will tell you if the package body is synthesizable\n -- or implemented as real numbers, set to \"true\" if synthesizable.\n constant fixedsynth_or_real : BOOLEAN := true;\n\n -- %%% Replicated functions\n function maximum (\n l, r : integer) -- inputs\n return integer is\n begin -- function max\n if l > r then return l;\n else return r;\n end if;\n end function maximum;\n\n function minimum (\n l, r : integer) -- inputs\n return integer is\n begin -- function min\n if l > r then return r;\n else return l;\n end if;\n end function minimum;\n\n function \"sra\" (arg : SIGNED; count : INTEGER)\n return SIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_RIGHT(arg, count);\n else\n return SHIFT_LEFT(arg, -count);\n end if;\n end function \"sra\";\n \n function or_reduce (arg : STD_ULOGIC_VECTOR)\n return STD_LOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC;\n begin\n if (arg'length < 1) then -- In the case of a NULL range\n Result := '0';\n else\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := or_reduce (BUS_int (BUS_int'left downto Half));\n Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper or Lower;\n end if;\n end if;\n return Result;\n end function or_reduce;\n\n -- purpose: AND all of the bits in a vector together\n -- This is a copy of the proposed \"and_reduce\" from 1076.3\n function and_reduce (arg : STD_ULOGIC_VECTOR)\n return STD_LOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC;\n begin\n if (arg'length < 1) then -- In the case of a NULL range\n Result := '1';\n else\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := and_reduce (BUS_int (BUS_int'left downto Half));\n Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper and Lower;\n end if;\n end if;\n return Result;\n end function and_reduce;\n\n function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range\n begin\n if (arg'length >= 1) then\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := xor_reduce (BUS_int (BUS_int'left downto Half));\n Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper xor Lower;\n end if;\n end if;\n return Result;\n end function xor_reduce;\n\n function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is\n begin\n return not and_reduce (arg);\n end function nand_reduce;\n function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is\n begin\n return not or_reduce (arg);\n end function nor_reduce;\n function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is\n begin\n return not xor_reduce (arg);\n end function xnor_reduce;\n -- Match table, copied form new std_logic_1164\n type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;\n constant match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |\n ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |\n );\n\n constant no_match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |\n ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |\n );\n\n -------------------------------------------------------------------\n -- ?= functions, Similar to \"std_match\", but returns \"std_ulogic\".\n -------------------------------------------------------------------\n function \\?=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return match_logic_table (l, r);\n end function \\?=\\;\n function \\?/=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return no_match_logic_table (l, r);\n end function \\?/=\\;\n -- \"?=\" operator is similar to \"std_match\", but returns a std_ulogic..\n -- Id: M.2B\n function \\?=\\ (L, R: UNSIGNED) return STD_ULOGIC is\n constant L_LEFT : INTEGER := L'LENGTH-1;\n constant R_LEFT : INTEGER := R'LENGTH-1;\n alias XL : UNSIGNED(L_LEFT downto 0) is L;\n alias XR : UNSIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);\n variable LX : UNSIGNED(SIZE-1 downto 0);\n variable RX : UNSIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin\n -- Logically identical to an \"=\" operator.\n if ((L'LENGTH < 1) or (R'LENGTH < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '1';\n for i in LX'low to LX'high loop\n result1 := \\?=\\(LX(i), RX(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result and result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?=\\;\n\n -- Id: M.3B\n function \\?=\\ (L, R: SIGNED) return std_ulogic is\n constant L_LEFT : INTEGER := L'LENGTH-1;\n constant R_LEFT : INTEGER := R'LENGTH-1;\n alias XL : SIGNED(L_LEFT downto 0) is L;\n alias XR : SIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);\n variable LX : SIGNED(SIZE-1 downto 0);\n variable RX : SIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin -- ?=\n if ((L'LENGTH < 1) or (R'LENGTH < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '1';\n for i in LX'low to LX'high loop\n result1 := \\?=\\ (LX(i), RX(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result and result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : UNSIGNED) return std_ulogic is\n constant L_LEFT : INTEGER := L'LENGTH-1;\n constant R_LEFT : INTEGER := R'LENGTH-1;\n alias XL : UNSIGNED(L_LEFT downto 0) is L;\n alias XR : UNSIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);\n variable LX : UNSIGNED(SIZE-1 downto 0);\n variable RX : UNSIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin -- ?=\n if ((L'LENGTH < 1) or (R'LENGTH < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '0';\n for i in LX'low to LX'high loop\n result1 := \\?/=\\ (LX(i), RX(i));\n if result1 = 'U' then\n result := 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result or result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?/=\\;\n\n function \\?/=\\ (L, R : SIGNED) return std_ulogic is\n constant L_LEFT : INTEGER := L'LENGTH-1;\n constant R_LEFT : INTEGER := R'LENGTH-1;\n alias XL : SIGNED(L_LEFT downto 0) is L;\n alias XR : SIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);\n variable LX : SIGNED(SIZE-1 downto 0);\n variable RX : SIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin -- ?=\n if ((L'LENGTH < 1) or (R'LENGTH < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '0';\n for i in LX'low to LX'high loop\n result1 := \\?/=\\ (LX(i), RX(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result or result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?/=\\;\n function Is_X ( s : UNSIGNED ) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n \n function Is_X ( s : SIGNED ) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n function \\?>\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l > r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>\\;\n -- %%% function \"?>\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?>\"\\;\n function \\?>\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l > r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>\\;\n function \\?>=\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l >= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>=\\;\n -- %%% function \"?>=\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?>=\";\n function \\?>=\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l >= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>=\\;\n function \\?<\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l < r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<\\;\n -- %%% function \"?<\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?<\";\n function \\?<\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l < r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<\\;\n function \\?<=\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l <= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<=\\;\n -- %%% function \"?<=\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?<=\";\n function \\?<=\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l <= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<=\\;\n\n-- %%% END replicated functions\n -- Special version of \"minimum\" to do some boundary checking without errors\n function mins (l, r : INTEGER)\n return INTEGER is\n begin -- function mins\n if (L = INTEGER'low or R = INTEGER'low) then\n return 0; -- error condition, silent\n end if;\n return minimum (L, R);\n end function mins;\n\n -- Special version of \"minimum\" to do some boundary checking with errors\n function mine (l, r : INTEGER)\n return INTEGER is\n begin -- function mine\n if (L = INTEGER'low or R = INTEGER'low) then\n report fixed_pkg'instance_name\n & \" Unbounded number passed, was a literal used?\"\n severity error;\n return 0;\n end if;\n return minimum (L, R);\n end function mine;\n\n -- The following functions are used only internally. Every function\n -- calls \"cleanvec\" either directly or indirectly.\n -- purpose: Fixes \"downto\" problem and resolves meta states\n function cleanvec (\n arg : UNRESOLVED_sfixed) -- input\n return UNRESOLVED_sfixed is\n constant left_index : INTEGER := maximum(arg'left, arg'right);\n constant right_index : INTEGER := mins(arg'left, arg'right);\n variable result : UNRESOLVED_sfixed (arg'range);\n begin -- function cleanvec\n assert not (arg'ascending and (arg'low /= INTEGER'low))\n report fixed_pkg'instance_name\n & \" Vector passed using a \"\"to\"\" range, expected is \"\"downto\"\"\"\n severity error;\n return arg;\n end function cleanvec;\n\n -- purpose: Fixes \"downto\" problem and resolves meta states\n function cleanvec (\n arg : UNRESOLVED_ufixed) -- input\n return UNRESOLVED_ufixed is\n constant left_index : INTEGER := maximum(arg'left, arg'right);\n constant right_index : INTEGER := mins(arg'left, arg'right);\n variable result : UNRESOLVED_ufixed (arg'range);\n begin -- function cleanvec\n assert not (arg'ascending and (arg'low /= INTEGER'low))\n report fixed_pkg'instance_name\n & \" Vector passed using a \"\"to\"\" range, expected is \"\"downto\"\"\"\n severity error;\n return arg;\n end function cleanvec;\n\n -- Type convert a \"unsigned\" into a \"ufixed\", used internally\n function to_fixed (\n arg : UNSIGNED; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n begin -- function to_fixed\n result := UNRESOLVED_ufixed(arg);\n return result;\n end function to_fixed;\n\n -- Type convert a \"signed\" into an \"sfixed\", used internally\n function to_fixed (\n arg : SIGNED; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n begin -- function to_fixed\n result := UNRESOLVED_sfixed(arg);\n return result;\n end function to_fixed;\n\n -- Type convert a \"ufixed\" into an \"unsigned\", used internally\n function to_uns (\n arg : UNRESOLVED_ufixed) -- fp vector\n return UNSIGNED is\n subtype t is UNSIGNED(arg'high - arg'low downto 0);\n variable slv : t;\n begin -- function to_uns\n slv := t(arg);\n return slv;\n end function to_uns;\n\n -- Type convert an \"sfixed\" into a \"signed\", used internally\n function to_s (\n arg : UNRESOLVED_sfixed) -- fp vector\n return SIGNED is\n subtype t is SIGNED(arg'high - arg'low downto 0);\n variable slv : t;\n begin -- function to_s\n slv := t(arg);\n return slv;\n end function to_s;\n\n -- adds 1 to the LSB of the number\n procedure round_up (arg : in UNRESOLVED_ufixed;\n result : out UNRESOLVED_ufixed;\n overflowx : out BOOLEAN) is\n variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)\n := (others => '0');\n begin -- round_up\n arguns (arguns'high-1 downto 0) := to_uns (arg);\n resuns := arguns + 1;\n result := to_fixed(resuns(arg'high-arg'low\n downto 0), arg'high, arg'low);\n overflowx := (resuns(resuns'high) = '1');\n end procedure round_up;\n\n -- adds 1 to the LSB of the number\n procedure round_up (arg : in UNRESOLVED_sfixed;\n result : out UNRESOLVED_sfixed;\n overflowx : out BOOLEAN) is\n variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);\n begin -- round_up\n args (args'high-1 downto 0) := to_s (arg);\n args(args'high) := arg(arg'high); -- sign extend\n ress := args + 1;\n result := to_fixed(ress (ress'high-1\n downto 0), arg'high, arg'low);\n overflowx := ((arg(arg'high) /= ress(ress'high-1))\n and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));\n end procedure round_up;\n\n -- Rounding - Performs a \"round_nearest\" (IEEE 754) which rounds up\n -- when the remainder is > 0.5. If the remainder IS 0.5 then if the\n -- bottom bit is a \"1\" it is rounded, otherwise it remains the same.\n function round_fixed (arg : UNRESOLVED_ufixed;\n remainder : UNRESOLVED_ufixed;\n overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return UNRESOLVED_ufixed is\n variable rounds : BOOLEAN;\n variable round_overflow : BOOLEAN;\n variable result : UNRESOLVED_ufixed (arg'range);\n begin\n rounds := false;\n if (remainder'length > 1) then\n if (remainder (remainder'high) = '1') then\n rounds := (arg(arg'low) = '1')\n or (or_reduce (to_sulv(remainder(remainder'high-1 downto\n remainder'low))) = '1');\n end if;\n else\n rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');\n end if;\n if rounds then\n round_up(arg => arg,\n result => result,\n overflowx => round_overflow);\n else\n result := arg;\n end if;\n if (overflow_style = fixed_saturate) and round_overflow then\n result := saturate (result'high, result'low);\n end if;\n return result;\n end function round_fixed;\n\n -- Rounding case statement\n function round_fixed (arg : UNRESOLVED_sfixed;\n remainder : UNRESOLVED_sfixed;\n overflow_style : fixed_overflow_style_type := fixed_overflow_style)\n return UNRESOLVED_sfixed is\n variable rounds : BOOLEAN;\n variable round_overflow : BOOLEAN;\n variable result : UNRESOLVED_sfixed (arg'range);\n begin\n rounds := false;\n if (remainder'length > 1) then\n if (remainder (remainder'high) = '1') then\n rounds := (arg(arg'low) = '1')\n or (or_reduce (to_sulv(remainder(remainder'high-1 downto\n remainder'low))) = '1');\n end if;\n else\n rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');\n end if;\n if rounds then\n round_up(arg => arg,\n result => result,\n overflowx => round_overflow);\n else\n result := arg;\n end if;\n if round_overflow then\n if (overflow_style = fixed_saturate) then\n if arg(arg'high) = '0' then\n result := saturate (result'high, result'low);\n else\n result := not saturate (result'high, result'low);\n end if;\n -- Sign bit not fixed when wrapping\n end if;\n end if;\n return result;\n end function round_fixed;\n\n -- converts an sfixed into a ufixed. The output is the same length as the\n -- input, because abs(\"1000\") = \"1000\" = 8.\n function to_ufixed (\n arg : UNRESOLVED_sfixed)\n return UNRESOLVED_ufixed\n is\n constant left_index : INTEGER := arg'high;\n constant right_index : INTEGER := mine(arg'low, arg'low);\n variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);\n variable result : UNRESOLVED_ufixed(left_index downto right_index);\n begin\n if arg'length < 1 then\n return NAUF;\n end if;\n xarg := abs(arg);\n result := UNRESOLVED_ufixed (xarg (left_index downto right_index));\n return result;\n end function to_ufixed;\n\n-----------------------------------------------------------------------------\n-- Visible functions\n-----------------------------------------------------------------------------\n\n -- Conversion functions. These are needed for synthesis where typically\n -- the only input and output type is a std_logic_vector.\n function to_sulv (\n arg : UNRESOLVED_ufixed) -- fixed point vector\n return STD_ULOGIC_VECTOR is\n variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);\n begin\n if arg'length < 1 then\n return NSLV;\n end if;\n result := STD_ULOGIC_VECTOR (arg);\n return result;\n end function to_sulv;\n\n function to_sulv (\n arg : UNRESOLVED_sfixed) -- fixed point vector\n return STD_ULOGIC_VECTOR is\n variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);\n begin\n if arg'length < 1 then\n return NSLV;\n end if;\n result := STD_ULOGIC_VECTOR (arg);\n return result;\n end function to_sulv;\n\n function to_slv (\n arg : UNRESOLVED_ufixed) -- fixed point vector\n return STD_LOGIC_VECTOR is\n begin\n return to_stdlogicvector(to_sulv(arg));\n end function to_slv;\n\n function to_slv (\n arg : UNRESOLVED_sfixed) -- fixed point vector\n return STD_LOGIC_VECTOR is\n begin\n return to_stdlogicvector(to_sulv(arg));\n end function to_slv;\n\n function to_ufixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return unresolved_ufixed is\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n begin\n if (arg'length < 1 or right_index > left_index) then\n return NAUF;\n end if;\n if (arg'length /= result'length) then\n report fixed_pkg'instance_name & \"TO_UFIXED(SLV) \"\n & \"Vector lengths do not match. Input length is \"\n & INTEGER'image(arg'length) & \" and output will be \"\n & INTEGER'image(result'length) & \" wide.\"\n severity error;\n return NAUF;\n else\n result := to_fixed (arg => UNSIGNED(arg),\n left_index => left_index,\n right_index => right_index);\n return result;\n end if;\n end function to_ufixed;\n\n function to_sfixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return unresolved_sfixed is\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n begin\n if (arg'length < 1 or right_index > left_index) then\n return NASF;\n end if;\n if (arg'length /= result'length) then\n report fixed_pkg'instance_name & \"TO_SFIXED(SLV) \"\n & \"Vector lengths do not match. Input length is \"\n & INTEGER'image(arg'length) & \" and output will be \"\n & INTEGER'image(result'length) & \" wide.\"\n severity error;\n return NASF;\n else\n result := to_fixed (arg => SIGNED(arg),\n left_index => left_index,\n right_index => right_index);\n return result;\n end if;\n end function to_sfixed;\n\n -- Two's complement number, Grows the vector by 1 bit.\n -- because \"abs (1000.000) = 01000.000\" or abs(-16) = 16.\n function \"abs\" (\n arg : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n constant left_index : INTEGER := arg'high;\n constant right_index : INTEGER := mine(arg'low, arg'low);\n variable ressns : SIGNED (arg'length downto 0);\n variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);\n begin\n if (arg'length < 1 or result'length < 1) then\n return NASF;\n end if;\n ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));\n ressns (arg'length) := ressns (arg'length-1); -- expand sign bit\n result := to_fixed (abs(ressns), left_index+1, right_index);\n return result;\n end function \"abs\";\n\n -- also grows the vector by 1 bit.\n function \"-\" (\n arg : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n constant left_index : INTEGER := arg'high+1;\n constant right_index : INTEGER := mine(arg'low, arg'low);\n variable ressns : SIGNED (arg'length downto 0);\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n begin\n if (arg'length < 1 or result'length < 1) then\n return NASF;\n end if;\n ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));\n ressns (arg'length) := ressns (arg'length-1); -- expand sign bit\n result := to_fixed (-ressns, left_index, right_index);\n return result;\n end function \"-\";\n\n -- Addition\n function \"+\" (\n l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =\n return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))\n constant left_index : INTEGER := maximum(l'high, r'high)+1;\n constant right_index : INTEGER := mine(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (left_index-right_index\n downto 0);\n variable result_slv : UNSIGNED (left_index-right_index\n downto 0);\n begin\n if (l'length < 1 or r'length < 1 or result'length < 1) then\n return NAUF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n result_slv := lslv + rslv;\n result := to_fixed(result_slv, left_index, right_index);\n return result;\n end function \"+\";\n\n function \"+\" (\n l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) = \n return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))\n constant left_index : INTEGER := maximum(l'high, r'high)+1;\n constant right_index : INTEGER := mine(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (left_index-right_index downto 0);\n variable result_slv : SIGNED (left_index-right_index downto 0);\n begin\n if (l'length < 1 or r'length < 1 or result'length < 1) then\n return NASF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n result_slv := lslv + rslv;\n result := to_fixed(result_slv, left_index, right_index);\n return result;\n end function \"+\";\n\n -- Subtraction\n function \"-\" (\n l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =\n return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))\n constant left_index : INTEGER := maximum(l'high, r'high)+1;\n constant right_index : INTEGER := mine(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (left_index-right_index\n downto 0);\n variable result_slv : UNSIGNED (left_index-right_index\n downto 0);\n begin\n if (l'length < 1 or r'length < 1 or result'length < 1) then\n return NAUF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n result_slv := lslv - rslv;\n result := to_fixed(result_slv, left_index, right_index);\n return result;\n end function \"-\";\n\n function \"-\" (\n l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) = \n return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))\n constant left_index : INTEGER := maximum(l'high, r'high)+1;\n constant right_index : INTEGER := mine(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (left_index-right_index downto 0);\n variable result_slv : SIGNED (left_index-right_index downto 0);\n begin\n if (l'length < 1 or r'length < 1 or result'length < 1) then\n return NASF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n result_slv := lslv - rslv;\n result := to_fixed(result_slv, left_index, right_index);\n return result;\n end function \"-\";\n\n function \"*\" (\n l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =\n return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)\n variable lslv : UNSIGNED (l'length-1 downto 0);\n variable rslv : UNSIGNED (r'length-1 downto 0);\n variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);\n variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto\n mine(l'low, l'low) + mine(r'low, r'low));\n begin\n if (l'length < 1 or r'length < 1 or\n result'length /= result_slv'length) then\n return NAUF;\n end if;\n lslv := to_uns (cleanvec(l));\n rslv := to_uns (cleanvec(r));\n result_slv := lslv * rslv;\n result := to_fixed (result_slv, result'high, result'low);\n return result;\n end function \"*\";\n\n function \"*\" (\n l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) = \n return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)\n variable lslv : SIGNED (l'length-1 downto 0);\n variable rslv : SIGNED (r'length-1 downto 0);\n variable result_slv : SIGNED (r'length+l'length-1 downto 0);\n variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto\n mine(l'low, l'low) + mine(r'low, r'low));\n begin\n if (l'length < 1 or r'length < 1 or\n result'length /= result_slv'length) then\n return NASF;\n end if;\n lslv := to_s (cleanvec(l));\n rslv := to_s (cleanvec(r));\n result_slv := lslv * rslv;\n result := to_fixed (result_slv, result'high, result'low);\n return result;\n end function \"*\";\n\n function \"/\" (\n l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) = \n return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)\n begin\n return divide (l, r);\n end function \"/\";\n\n function \"/\" (\n l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) = \n return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)\n begin\n return divide (l, r);\n end function \"/\";\n\n -- This version of divide gives the user more control\n -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)\n function divide (\n l, r : UNRESOLVED_ufixed;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto\n mine (l'low, l'low) - r'high -1);\n variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);\n variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);\n variable lslv : UNSIGNED (lresize'length-1 downto 0);\n variable rslv : UNSIGNED (r'length-1 downto 0);\n variable result_slv : UNSIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1 or\n mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then\n return NAUF;\n end if;\n lresize := resize (arg => l,\n left_index => lresize'high,\n right_index => lresize'low,\n overflow_style => fixed_wrap, -- vector only grows\n round_style => fixed_truncate);\n lslv := to_uns (cleanvec (lresize));\n rslv := to_uns (cleanvec (r));\n if (rslv = 0) then\n report fixed_pkg'instance_name\n & \"DIVIDE(ufixed) Division by zero\" severity error;\n result := saturate (result'high, result'low); -- saturate\n else\n result_slv := lslv / rslv;\n dresult := to_fixed (result_slv, dresult'high, dresult'low);\n result := resize (arg => dresult,\n left_index => result'high,\n right_index => result'low,\n overflow_style => fixed_wrap, -- overflow impossible\n round_style => round_style);\n end if;\n return result;\n end function divide;\n\n -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)\n function divide (\n l, r : UNRESOLVED_sfixed;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto \n mine (l'low, l'low) - r'high);\n variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);\n variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);\n variable lslv : SIGNED (lresize'length-1 downto 0);\n variable rslv : SIGNED (r'length-1 downto 0);\n variable result_slv : SIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1 or\n mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then\n return NASF;\n end if;\n lresize := resize (arg => l,\n left_index => lresize'high,\n right_index => lresize'low,\n overflow_style => fixed_wrap, -- vector only grows\n round_style => fixed_truncate);\n lslv := to_s (cleanvec (lresize));\n rslv := to_s (cleanvec (r));\n if (rslv = 0) then\n report fixed_pkg'instance_name\n & \"DIVIDE(sfixed) Division by zero\" severity error;\n result := saturate (result'high, result'low);\n else\n result_slv := lslv / rslv;\n dresult := to_fixed (result_slv, dresult'high, dresult'low);\n result := resize (arg => dresult,\n left_index => result'high,\n right_index => result'low,\n overflow_style => fixed_wrap, -- overflow impossible\n round_style => round_style);\n end if;\n return result;\n end function divide;\n\n -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)\n function reciprocal (\n arg : UNRESOLVED_ufixed; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed is\n constant one : UNRESOLVED_ufixed (0 downto 0) := \"1\";\n begin\n return divide (l => one,\n r => arg,\n round_style => round_style,\n guard_bits => guard_bits);\n end function reciprocal;\n\n -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)\n function reciprocal (\n arg : UNRESOLVED_sfixed; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed is\n constant one : UNRESOLVED_sfixed (1 downto 0) := \"01\"; -- extra bit.\n variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);\n begin\n if (arg'length < 1 or resultx'length < 1) then\n return NASF;\n else\n resultx := divide (l => one,\n r => arg,\n round_style => round_style,\n guard_bits => guard_bits);\n return resultx (resultx'high-1 downto resultx'low); -- remove extra bit\n end if;\n end function reciprocal;\n\n -- ufixed (a downto b) rem ufixed (c downto d)\n -- = ufixed (min(a,c) downto min(b,d))\n function \"rem\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return remainder (l, r);\n end function \"rem\";\n\n -- remainder\n -- sfixed (a downto b) rem sfixed (c downto d)\n -- = sfixed (min(a,c) downto min(b,d))\n function \"rem\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return remainder (l, r);\n end function \"rem\";\n\n -- ufixed (a downto b) rem ufixed (c downto d)\n -- = ufixed (min(a,c) downto min(b,d))\n function remainder (\n l, r : UNRESOLVED_ufixed; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto\n mine(l'low, r'low));\n variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto\n mins(r'low, r'low)-guard_bits);\n variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);\n variable dresult : UNRESOLVED_ufixed (rresize'range);\n variable lslv : UNSIGNED (lresize'length-1 downto 0);\n variable rslv : UNSIGNED (rresize'length-1 downto 0);\n variable result_slv : UNSIGNED (rslv'range);\n begin\n if (l'length < 1 or r'length < 1 or\n mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then\n return NAUF;\n end if;\n lresize := resize (arg => l,\n left_index => lresize'high,\n right_index => lresize'low,\n overflow_style => fixed_wrap, -- vector only grows\n round_style => fixed_truncate);\n lslv := to_uns (lresize);\n rresize := resize (arg => r,\n left_index => rresize'high,\n right_index => rresize'low,\n overflow_style => fixed_wrap, -- vector only grows\n round_style => fixed_truncate);\n rslv := to_uns (rresize);\n if (rslv = 0) then\n report fixed_pkg'instance_name\n & \"remainder(ufixed) Division by zero\" severity error;\n result := saturate (result'high, result'low); -- saturate\n else\n if (r'low <= l'high) then\n result_slv := lslv rem rslv;\n dresult := to_fixed (result_slv, dresult'high, dresult'low);\n result := resize (arg => dresult,\n left_index => result'high,\n right_index => result'low,\n overflow_style => fixed_wrap, -- can't overflow\n round_style => round_style);\n end if;\n if l'low < r'low then\n result(mins(r'low-1, l'high) downto l'low) :=\n cleanvec(l(mins(r'low-1, l'high) downto l'low));\n end if;\n end if;\n return result;\n end function remainder;\n\n -- remainder\n -- sfixed (a downto b) rem sfixed (c downto d)\n -- = sfixed (min(a,c) downto min(b,d))\n function remainder (\n l, r : UNRESOLVED_sfixed; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed is\n variable l_abs : UNRESOLVED_ufixed (l'range);\n variable r_abs : UNRESOLVED_ufixed (r'range);\n variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto\n mine(r'low, l'low));\n variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto\n mins(r'low, l'low));\n begin\n if (l'length < 1 or r'length < 1 or\n mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then\n return NASF;\n end if;\n l_abs := to_ufixed (l);\n r_abs := to_ufixed (r);\n result := UNRESOLVED_sfixed (remainder (\n l => l_abs,\n r => r_abs,\n round_style => round_style));\n neg_result := -result;\n if l(l'high) = '1' then\n result := neg_result(result'range);\n end if;\n return result;\n end function remainder;\n\n -- modulo\n -- ufixed (a downto b) mod ufixed (c downto d)\n -- = ufixed (min(a,c) downto min(b, d))\n function \"mod\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return modulo (l, r);\n end function \"mod\";\n\n -- sfixed (a downto b) mod sfixed (c downto d)\n -- = sfixed (c downto min(b, d))\n function \"mod\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return modulo(l, r);\n end function \"mod\";\n\n -- modulo\n -- ufixed (a downto b) mod ufixed (c downto d)\n -- = ufixed (min(a,c) downto min(b, d))\n function modulo (\n l, r : UNRESOLVED_ufixed; -- fixed point input\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_ufixed is\n begin\n return remainder(l => l,\n r => r,\n round_style => round_style,\n guard_bits => guard_bits);\n end function modulo;\n\n -- sfixed (a downto b) mod sfixed (c downto d)\n -- = sfixed (c downto min(b, d))\n function modulo (\n l, r : UNRESOLVED_sfixed; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits)\n return UNRESOLVED_sfixed is\n variable l_abs : UNRESOLVED_ufixed (l'range);\n variable r_abs : UNRESOLVED_ufixed (r'range);\n variable result : UNRESOLVED_sfixed (r'high downto\n mine(r'low, l'low));\n variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto\n mins(r'low, l'low));\n variable dresult_not_zero : BOOLEAN;\n begin\n if (l'length < 1 or r'length < 1 or\n mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then\n return NASF;\n end if;\n l_abs := to_ufixed (l);\n r_abs := to_ufixed (r);\n dresult := \"0\" & UNRESOLVED_sfixed(remainder (l => l_abs,\n r => r_abs,\n round_style => round_style));\n if (to_s(dresult) = 0) then\n dresult_not_zero := false;\n else\n dresult_not_zero := true;\n end if;\n if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'\n and dresult_not_zero then\n result := resize (arg => r - dresult,\n left_index => result'high,\n right_index => result'low,\n overflow_style => overflow_style,\n round_style => round_style);\n elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then\n result := resize (arg => -dresult,\n left_index => result'high,\n right_index => result'low,\n overflow_style => overflow_style,\n round_style => round_style);\n elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'\n and dresult_not_zero then\n result := resize (arg => dresult + r,\n left_index => result'high,\n right_index => result'low,\n overflow_style => overflow_style,\n round_style => round_style);\n else\n result := resize (arg => dresult,\n left_index => result'high,\n right_index => result'low,\n overflow_style => overflow_style,\n round_style => round_style);\n end if;\n return result;\n end function modulo;\n\n -- Procedure for those who need an \"accumulator\" function\n procedure add_carry (\n L, R : in UNRESOLVED_ufixed;\n c_in : in STD_ULOGIC;\n result : out UNRESOLVED_ufixed;\n c_out : out STD_ULOGIC) is\n constant left_index : INTEGER := maximum(l'high, r'high)+1;\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (left_index-right_index\n downto 0);\n variable result_slv : UNSIGNED (left_index-right_index\n downto 0);\n variable cx : UNSIGNED (0 downto 0); -- Carry in\n begin\n if (l'length < 1 or r'length < 1) then\n result := NAUF;\n c_out := '0';\n else\n cx (0) := c_in;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n result_slv := lslv + rslv + cx;\n c_out := result_slv(left_index-right_index);\n result := to_fixed(result_slv (left_index-right_index-1 downto 0),\n left_index-1, right_index);\n end if;\n end procedure add_carry;\n\n procedure add_carry (\n L, R : in UNRESOLVED_sfixed;\n c_in : in STD_ULOGIC;\n result : out UNRESOLVED_sfixed;\n c_out : out STD_ULOGIC) is\n constant left_index : INTEGER := maximum(l'high, r'high)+1;\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (left_index-right_index\n downto 0);\n variable result_slv : SIGNED (left_index-right_index\n downto 0);\n variable cx : SIGNED (1 downto 0); -- Carry in\n begin\n if (l'length < 1 or r'length < 1) then\n result := NASF;\n c_out := '0';\n else\n cx (1) := '0';\n cx (0) := c_in;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n result_slv := lslv + rslv + cx;\n c_out := result_slv(left_index-right_index);\n result := to_fixed(result_slv (left_index-right_index-1 downto 0),\n left_index-1, right_index);\n end if;\n end procedure add_carry;\n\n -- Scales the result by a power of 2. Width of input = width of output with\n -- the decimal point moved.\n function scalb (y : UNRESOLVED_ufixed; N : INTEGER)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);\n begin\n if y'length < 1 then\n return NAUF;\n else\n result := y;\n return result;\n end if;\n end function scalb;\n\n function scalb (y : UNRESOLVED_ufixed; N : SIGNED)\n return UNRESOLVED_ufixed is\n begin\n return scalb (y => y,\n N => to_integer(N));\n end function scalb;\n\n function scalb (y : UNRESOLVED_sfixed; N : INTEGER)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);\n begin\n if y'length < 1 then\n return NASF;\n else\n result := y;\n return result;\n end if;\n end function scalb;\n\n function scalb (y : UNRESOLVED_sfixed; N : SIGNED)\n return UNRESOLVED_sfixed is\n begin\n return scalb (y => y,\n N => to_integer(N));\n end function scalb;\n\n function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is\n begin\n if to_X01(arg(arg'high)) = '1' then\n return true;\n else\n return false;\n end if;\n end function Is_Negative;\n\n function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)\n return INTEGER is\n begin\n for_loop : for i in arg'reverse_range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'high+1; -- return out of bounds 'high\n end function find_rightmost;\n\n function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)\n return INTEGER is\n begin\n for_loop : for i in arg'range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'low-1; -- return out of bounds 'low\n end function find_leftmost;\n\n function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)\n return INTEGER is\n begin\n for_loop : for i in arg'reverse_range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'high+1; -- return out of bounds 'high\n end function find_rightmost;\n\n function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)\n return INTEGER is\n begin\n for_loop : for i in arg'range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'low-1; -- return out of bounds 'low\n end function find_leftmost;\n\n function \"sll\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed is\n variable argslv : UNSIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_ufixed (arg'range);\n begin\n argslv := to_uns (arg);\n argslv := argslv sll COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"sll\";\n\n function \"srl\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed is\n variable argslv : UNSIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_ufixed (arg'range);\n begin\n argslv := to_uns (arg);\n argslv := argslv srl COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"srl\";\n\n function \"rol\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed is\n variable argslv : UNSIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_ufixed (arg'range);\n begin\n argslv := to_uns (arg);\n argslv := argslv rol COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"rol\";\n\n function \"ror\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed is\n variable argslv : UNSIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_ufixed (arg'range);\n begin\n argslv := to_uns (arg);\n argslv := argslv ror COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"ror\";\n\n function \"sla\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed is\n variable argslv : UNSIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_ufixed (arg'range);\n begin\n argslv := to_uns (arg);\n -- Arithmetic shift on an unsigned is a logical shift\n argslv := argslv sll COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"sla\";\n\n function \"sra\" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)\n return UNRESOLVED_ufixed is\n variable argslv : UNSIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_ufixed (arg'range);\n begin\n argslv := to_uns (arg);\n -- Arithmetic shift on an unsigned is a logical shift\n argslv := argslv srl COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"sra\";\n\n function \"sll\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed is\n variable argslv : SIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_sfixed (arg'range);\n begin\n argslv := to_s (arg);\n argslv := argslv sll COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"sll\";\n\n function \"srl\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed is\n variable argslv : SIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_sfixed (arg'range);\n begin\n argslv := to_s (arg);\n argslv := argslv srl COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"srl\";\n\n function \"rol\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed is\n variable argslv : SIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_sfixed (arg'range);\n begin\n argslv := to_s (arg);\n argslv := argslv rol COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"rol\";\n\n function \"ror\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed is\n variable argslv : SIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_sfixed (arg'range);\n begin\n argslv := to_s (arg);\n argslv := argslv ror COUNT;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"ror\";\n\n function \"sla\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed is\n variable argslv : SIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_sfixed (arg'range);\n begin\n argslv := to_s (arg);\n if COUNT > 0 then\n -- Arithmetic shift left on a 2's complement number is a logic shift\n argslv := argslv sll COUNT;\n else\n argslv := argslv sra -COUNT;\n end if;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"sla\";\n\n function \"sra\" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)\n return UNRESOLVED_sfixed is\n variable argslv : SIGNED (arg'length-1 downto 0);\n variable result : UNRESOLVED_sfixed (arg'range);\n begin\n argslv := to_s (arg);\n if COUNT > 0 then\n argslv := argslv sra COUNT;\n else\n -- Arithmetic shift left on a 2's complement number is a logic shift\n argslv := argslv sll -COUNT;\n end if;\n result := to_fixed (argslv, result'high, result'low);\n return result;\n end function \"sra\";\n\n -- Because some people want the older functions.\n function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n if (ARG'length < 1) then\n return NAUF;\n end if;\n return ARG sla COUNT;\n end function SHIFT_LEFT;\n\n function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n if (ARG'length < 1) then\n return NAUF;\n end if;\n return ARG sra COUNT;\n end function SHIFT_RIGHT;\n\n function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)\n return UNRESOLVED_sfixed is\n begin\n if (ARG'length < 1) then\n return NASF;\n end if;\n return ARG sla COUNT;\n end function SHIFT_LEFT;\n\n function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)\n return UNRESOLVED_sfixed is\n begin\n if (ARG'length < 1) then\n return NASF;\n end if;\n return ARG sra COUNT;\n end function SHIFT_RIGHT;\n\n ----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n function \"not\" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n RESULT := not to_sulv(L);\n return to_ufixed(RESULT, L'high, L'low);\n end function \"not\";\n\n function \"and\" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) and to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"and\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_ufixed(RESULT, L'high, L'low);\n end function \"and\";\n\n function \"or\" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) or to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"or\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_ufixed(RESULT, L'high, L'low);\n end function \"or\";\n\n function \"nand\" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nand to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"nand\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_ufixed(RESULT, L'high, L'low);\n end function \"nand\";\n\n function \"nor\" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nor to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"nor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_ufixed(RESULT, L'high, L'low);\n end function \"nor\";\n\n function \"xor\" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xor to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"xor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_ufixed(RESULT, L'high, L'low);\n end function \"xor\";\n\n function \"xnor\" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xnor to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"xnor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_ufixed(RESULT, L'high, L'low);\n end function \"xnor\";\n\n function \"not\" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n RESULT := not to_sulv(L);\n return to_sfixed(RESULT, L'high, L'low);\n end function \"not\";\n\n function \"and\" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) and to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"and\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_sfixed(RESULT, L'high, L'low);\n end function \"and\";\n\n function \"or\" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) or to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"or\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_sfixed(RESULT, L'high, L'low);\n end function \"or\";\n\n function \"nand\" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nand to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"nand\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_sfixed(RESULT, L'high, L'low);\n end function \"nand\";\n\n function \"nor\" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nor to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"nor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_sfixed(RESULT, L'high, L'low);\n end function \"nor\";\n\n function \"xor\" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xor to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"xor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_sfixed(RESULT, L'high, L'low);\n end function \"xor\";\n\n function \"xnor\" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xnor to_sulv(R);\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"xnor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_sfixed(RESULT, L'high, L'low);\n end function \"xnor\";\n\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (R'range);\n begin\n for i in result'range loop\n result(i) := L and R(i);\n end loop;\n return result;\n end function \"and\";\n\n function \"and\" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) and R;\n end loop;\n return result;\n end function \"and\";\n\n function \"or\" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (R'range);\n begin\n for i in result'range loop\n result(i) := L or R(i);\n end loop;\n return result;\n end function \"or\";\n\n function \"or\" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) or R;\n end loop;\n return result;\n end function \"or\";\n\n function \"nand\" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (R'range);\n begin\n for i in result'range loop\n result(i) := L nand R(i);\n end loop;\n return result;\n end function \"nand\";\n\n function \"nand\" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nand R;\n end loop;\n return result;\n end function \"nand\";\n\n function \"nor\" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (R'range);\n begin\n for i in result'range loop\n result(i) := L nor R(i);\n end loop;\n return result;\n end function \"nor\";\n\n function \"nor\" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nor R;\n end loop;\n return result;\n end function \"nor\";\n\n function \"xor\" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (R'range);\n begin\n for i in result'range loop\n result(i) := L xor R(i);\n end loop;\n return result;\n end function \"xor\";\n\n function \"xor\" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xor R;\n end loop;\n return result;\n end function \"xor\";\n\n function \"xnor\" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (R'range);\n begin\n for i in result'range loop\n result(i) := L xnor R(i);\n end loop;\n return result;\n end function \"xnor\";\n\n function \"xnor\" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xnor R;\n end loop;\n return result;\n end function \"xnor\";\n\n function \"and\" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (R'range);\n begin\n for i in result'range loop\n result(i) := L and R(i);\n end loop;\n return result;\n end function \"and\";\n\n function \"and\" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) and R;\n end loop;\n return result;\n end function \"and\";\n\n function \"or\" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (R'range);\n begin\n for i in result'range loop\n result(i) := L or R(i);\n end loop;\n return result;\n end function \"or\";\n\n function \"or\" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) or R;\n end loop;\n return result;\n end function \"or\";\n\n function \"nand\" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (R'range);\n begin\n for i in result'range loop\n result(i) := L nand R(i);\n end loop;\n return result;\n end function \"nand\";\n\n function \"nand\" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nand R;\n end loop;\n return result;\n end function \"nand\";\n\n function \"nor\" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (R'range);\n begin\n for i in result'range loop\n result(i) := L nor R(i);\n end loop;\n return result;\n end function \"nor\";\n\n function \"nor\" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nor R;\n end loop;\n return result;\n end function \"nor\";\n\n function \"xor\" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (R'range);\n begin\n for i in result'range loop\n result(i) := L xor R(i);\n end loop;\n return result;\n end function \"xor\";\n\n function \"xor\" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xor R;\n end loop;\n return result;\n end function \"xor\";\n\n function \"xnor\" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (R'range);\n begin\n for i in result'range loop\n result(i) := L xnor R(i);\n end loop;\n return result;\n end function \"xnor\";\n\n function \"xnor\" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xnor R;\n end loop;\n return result;\n end function \"xnor\";\n\n -- Reduction operator_reduces\n function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is\n begin\n return and_reduce (to_sulv(l));\n end function and_reduce;\n\n function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is\n begin\n return nand_reduce (to_sulv(l));\n end function nand_reduce;\n\n function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is\n begin\n return or_reduce (to_sulv(l));\n end function or_reduce;\n\n function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is\n begin\n return nor_reduce (to_sulv(l));\n end function nor_reduce;\n\n function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is\n begin\n return xor_reduce (to_sulv(l));\n end function xor_reduce;\n\n function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is\n begin\n return xnor_reduce (to_sulv(l));\n end function xnor_reduce;\n\n function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is\n begin\n return and_reduce (to_sulv(l));\n end function and_reduce;\n\n function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is\n begin\n return nand_reduce (to_sulv(l));\n end function nand_reduce;\n\n function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is\n begin\n return or_reduce (to_sulv(l));\n end function or_reduce;\n\n function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is\n begin\n return nor_reduce (to_sulv(l));\n end function nor_reduce;\n\n function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is\n begin\n return xor_reduce (to_sulv(l));\n end function xor_reduce;\n\n function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is\n begin\n return xnor_reduce (to_sulv(l));\n end function xnor_reduce;\n -- End reduction operator_reduces\n\n function \\?=\\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin -- ?=\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return \\?=\\ (lslv, rslv);\n end if;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin -- ?/=\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return \\?/=\\ (lslv, rslv);\n end if;\n end function \\?/=\\;\n\n function \\?>\\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin -- ?>\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?>\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return \\?>\\ (lslv, rslv);\n end if;\n end function \\?>\\;\n\n function \\?>=\\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin -- ?>=\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?>=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return \\?>=\\ (lslv, rslv);\n end if;\n end function \\?>=\\;\n\n function \\?<\\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin -- ?<\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?<\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return \\?<\\ (lslv, rslv);\n end if;\n end function \\?<\\;\n\n function \\?<=\\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin -- ?<=\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?<=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return \\?<=\\ (lslv, rslv);\n end if;\n end function \\?<=\\;\n\n function \\?=\\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin -- ?=\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return \\?=\\ (lslv, rslv);\n end if;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin -- ?/=\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return \\?/=\\ (lslv, rslv);\n end if;\n end function \\?/=\\;\n\n function \\?>\\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin -- ?>\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?>\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return \\?>\\ (lslv, rslv);\n end if;\n end function \\?>\\;\n\n function \\?>=\\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin -- ?>=\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?>=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return \\?>=\\ (lslv, rslv);\n end if;\n end function \\?>=\\;\n\n function \\?<\\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin -- ?<\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?<\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return \\?<\\ (lslv, rslv);\n end if;\n end function \\?<\\;\n\n function \\?<=\\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin -- ?<=\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"?<=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return \\?<=\\ (lslv, rslv);\n end if;\n end function \\?<=\\;\n\n -- Match function, similar to \"std_match\" from numeric_std\n function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is\n begin\n if (L'high = R'high and L'low = R'low) then\n return std_match(to_sulv(L), to_sulv(R));\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"STD_MATCH: L'RANGE /= R'RANGE, returning FALSE\"\n severity warning;\n return false;\n end if;\n end function std_match;\n\n function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is\n begin\n if (L'high = R'high and L'low = R'low) then\n return std_match(to_sulv(L), to_sulv(R));\n else\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"STD_MATCH: L'RANGE /= R'RANGE, returning FALSE\"\n severity warning;\n return false;\n end if;\n end function std_match;\n\n -- compare functions\n function \"=\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"=\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"=\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return lslv = rslv;\n end function \"=\";\n\n function \"=\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"=\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"=\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return lslv = rslv;\n end function \"=\";\n\n function \"/=\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"/=\"\": null argument detected, returning TRUE\"\n severity warning;\n return true;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"/=\"\": metavalue detected, returning TRUE\"\n severity warning;\n return true;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return lslv /= rslv;\n end function \"/=\";\n\n function \"/=\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"/=\"\": null argument detected, returning TRUE\"\n severity warning;\n return true;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"/=\"\": metavalue detected, returning TRUE\"\n severity warning;\n return true;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return lslv /= rslv;\n end function \"/=\";\n\n function \">\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return lslv > rslv;\n end function \">\";\n\n function \">\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return lslv > rslv;\n end function \">\";\n\n function \"<\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return lslv < rslv;\n end function \"<\";\n\n function \"<\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return lslv < rslv;\n end function \"<\";\n\n function \">=\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">=\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">=\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return lslv >= rslv;\n end function \">=\";\n\n function \">=\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">=\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\">=\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return lslv >= rslv;\n end function \">=\";\n\n function \"<=\" (\n l, r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<=\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<=\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_uns (lresize);\n rslv := to_uns (rresize);\n return lslv <= rslv;\n end function \"<=\";\n\n function \"<=\" (\n l, r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n variable lslv, rslv : SIGNED (lresize'length-1 downto 0);\n begin\n if (l'length < 1 or r'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<=\"\": null argument detected, returning FALSE\"\n severity warning;\n return false;\n elsif (Is_X(l) or Is_X(r)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"\"\"<=\"\": metavalue detected, returning FALSE\"\n severity warning;\n return false;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n lslv := to_s (lresize);\n rslv := to_s (rresize);\n return lslv <= rslv;\n end function \"<=\";\n\n -- overloads of the default maximum and minimum functions\n function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n begin\n if (l'length < 1 or r'length < 1) then\n return NAUF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n if lresize > rresize then return lresize;\n else return rresize;\n end if;\n end function maximum;\n\n function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n begin\n if (l'length < 1 or r'length < 1) then\n return NASF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n if lresize > rresize then return lresize;\n else return rresize;\n end if;\n end function maximum;\n\n function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);\n begin\n if (l'length < 1 or r'length < 1) then\n return NAUF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n if lresize > rresize then return rresize;\n else return lresize;\n end if;\n end function minimum;\n\n function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is\n constant left_index : INTEGER := maximum(l'high, r'high);\n constant right_index : INTEGER := mins(l'low, r'low);\n variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);\n begin\n if (l'length < 1 or r'length < 1) then\n return NASF;\n end if;\n lresize := resize (l, left_index, right_index);\n rresize := resize (r, left_index, right_index);\n if lresize > rresize then return rresize;\n else return lresize;\n end if;\n end function minimum;\n\n function to_ufixed (\n arg : NATURAL; -- integer\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed is\n constant fw : INTEGER := mins (right_index, right_index); -- catch literals\n variable result : UNRESOLVED_ufixed (left_index downto fw);\n variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=\n (others => '0'); -- integer portion\n variable argx : NATURAL; -- internal version of arg\n begin\n if (result'length < 1) then\n return NAUF;\n end if;\n if arg /= 0 then\n argx := arg;\n for I in 0 to sresult'left loop\n if (argx mod 2) = 0 then\n sresult(I) := '0';\n else\n sresult(I) := '1';\n end if;\n argx := argx/2;\n end loop;\n if argx /= 0 then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_UFIXED(NATURAL): vector truncated\"\n severity warning;\n if overflow_style = fixed_saturate then\n return saturate (left_index, right_index);\n end if;\n end if;\n result := resize (arg => sresult,\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n else\n result := (others => '0');\n end if;\n return result;\n end function to_ufixed;\n\n function to_sfixed (\n arg : INTEGER; -- integer\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed is\n constant fw : INTEGER := mins (right_index, right_index); -- catch literals\n variable result : UNRESOLVED_sfixed (left_index downto fw);\n variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=\n (others => '0'); -- integer portion\n variable argx : INTEGER; -- internal version of arg\n variable sign : STD_ULOGIC; -- sign of input\n begin\n if (result'length < 1) then -- null range\n return NASF;\n end if;\n if arg /= 0 then\n if (arg < 0) then\n sign := '1';\n argx := -(arg + 1);\n else\n sign := '0';\n argx := arg;\n end if;\n for I in 0 to sresult'left loop\n if (argx mod 2) = 0 then\n sresult(I) := sign;\n else\n sresult(I) := not sign;\n end if;\n argx := argx/2;\n end loop;\n if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_SFIXED(INTEGER): vector truncated\"\n severity warning;\n if overflow_style = fixed_saturate then -- saturate\n if arg < 0 then\n result := not saturate (result'high, result'low); -- underflow\n else\n result := saturate (result'high, result'low); -- overflow\n end if;\n return result;\n end if;\n end if;\n result := resize (arg => sresult,\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n else\n result := (others => '0');\n end if;\n return result;\n end function to_sfixed;\n\n function to_ufixed (\n arg : REAL; -- real\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits\n return UNRESOLVED_ufixed is\n constant fw : INTEGER := mins (right_index, right_index); -- catch literals\n variable result : UNRESOLVED_ufixed (left_index downto fw) :=\n (others => '0');\n variable Xresult : UNRESOLVED_ufixed (left_index downto\n fw-guard_bits) :=\n (others => '0');\n variable presult : REAL;\n-- variable overflow_needed : BOOLEAN;\n begin\n -- If negative or null range, return.\n if (left_index < fw) then\n return NAUF;\n end if;\n if (arg < 0.0) then\n report fixed_pkg'instance_name\n & \"TO_UFIXED: Negative argument passed \"\n & REAL'image(arg) severity error;\n return result;\n end if;\n presult := arg;\n if presult >= (2.0**(left_index+1)) then\n assert NO_WARNING report fixed_pkg'instance_name\n & \"TO_UFIXED(REAL): vector truncated\"\n severity warning;\n if overflow_style = fixed_wrap then\n presult := presult mod (2.0**(left_index+1)); -- wrap\n else\n return saturate (result'high, result'low);\n end if;\n end if;\n for i in Xresult'range loop\n if presult >= 2.0**i then\n Xresult(i) := '1';\n presult := presult - 2.0**i;\n else\n Xresult(i) := '0';\n end if;\n end loop;\n if guard_bits > 0 and round_style = fixed_round then\n result := round_fixed (arg => Xresult (left_index\n downto right_index),\n remainder => Xresult (right_index-1 downto\n right_index-guard_bits),\n overflow_style => overflow_style);\n else\n result := Xresult (result'range);\n end if;\n return result;\n end function to_ufixed;\n\n function to_sfixed (\n arg : REAL; -- real\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits\n return UNRESOLVED_sfixed is\n constant fw : INTEGER := mins (right_index, right_index); -- catch literals\n variable result : UNRESOLVED_sfixed (left_index downto fw) :=\n (others => '0');\n variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=\n (others => '0');\n variable presult : REAL;\n begin\n if (left_index < fw) then -- null range\n return NASF;\n end if;\n if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then\n assert NO_WARNING report fixed_pkg'instance_name\n & \"TO_SFIXED(REAL): vector truncated\"\n severity warning;\n if overflow_style = fixed_saturate then\n if arg < 0.0 then -- saturate\n result := not saturate (result'high, result'low); -- underflow\n else\n result := saturate (result'high, result'low); -- overflow\n end if;\n return result;\n else\n presult := abs(arg) mod (2.0**(left_index+1)); -- wrap\n end if;\n else\n presult := abs(arg);\n end if;\n for i in Xresult'range loop\n if presult >= 2.0**i then\n Xresult(i) := '1';\n presult := presult - 2.0**i;\n else\n Xresult(i) := '0';\n end if;\n end loop;\n if arg < 0.0 then\n Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);\n end if;\n if guard_bits > 0 and round_style = fixed_round then\n result := round_fixed (arg => Xresult (left_index\n downto right_index),\n remainder => Xresult (right_index-1 downto\n right_index-guard_bits),\n overflow_style => overflow_style);\n else\n result := Xresult (result'range);\n end if;\n return result;\n end function to_sfixed;\n\n function to_ufixed (\n arg : UNSIGNED; -- unsigned\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed is\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n begin\n if arg'length < 1 or (left_index < right_index) then\n return NAUF;\n end if;\n result := resize (arg => UNRESOLVED_ufixed (XARG),\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end function to_ufixed;\n\n -- converted version\n function to_ufixed (\n arg : UNSIGNED) -- unsigned\n return UNRESOLVED_ufixed is\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;\n begin\n if arg'length < 1 then\n return NAUF;\n end if;\n return UNRESOLVED_ufixed(xarg);\n end function to_ufixed;\n\n function to_sfixed (\n arg : SIGNED; -- signed\n constant left_index : INTEGER; -- left index (high index)\n constant right_index : INTEGER := 0; -- right index\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed is\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n begin\n if arg'length < 1 or (left_index < right_index) then\n return NASF;\n end if;\n result := resize (arg => UNRESOLVED_sfixed (XARG),\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end function to_sfixed;\n\n -- converted version\n function to_sfixed (\n arg : SIGNED) -- signed\n return UNRESOLVED_sfixed is\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;\n begin\n if arg'length < 1 then\n return NASF;\n end if;\n return UNRESOLVED_sfixed(xarg);\n end function to_sfixed;\n\n function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);\n begin\n if arg'length < 1 then\n return NASF;\n end if;\n result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));\n result (arg'high+1) := '0';\n return result;\n end function to_sfixed;\n\n -- Because of the fairly complicated sizing rules in the fixed point\n -- packages these functions are provided to compute the result ranges\n -- Example:\n -- signal uf1 : ufixed (3 downto -3);\n -- signal uf2 : ufixed (4 downto -2);\n -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto\n -- ufixed_low (3, -3, '*', 4, -2));\n -- uf1multuf2 <= uf1 * uf2;\n -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),\n -- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)\n function ufixed_high (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER is\n begin\n case operation is\n when '+'| '-' => return maximum (left_index, left_index2) + 1;\n when '*' => return left_index + left_index2 + 1;\n when '/' => return left_index - right_index2;\n when '1' => return -right_index; -- reciprocal\n when 'R'|'r' => return mins (left_index, left_index2); -- \"rem\"\n when 'M'|'m' => return mins (left_index, left_index2); -- \"mod\"\n when others => return left_index; -- For abs and default\n end case;\n end function ufixed_high;\n \n function ufixed_low (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER is\n begin\n case operation is\n when '+'| '-' => return mins (right_index, right_index2);\n when '*' => return right_index + right_index2;\n when '/' => return right_index - left_index2 - 1;\n when '1' => return -left_index - 1; -- reciprocal\n when 'R'|'r' => return mins (right_index, right_index2); -- \"rem\"\n when 'M'|'m' => return mins (right_index, right_index2); -- \"mod\"\n when others => return right_index; -- for abs and default\n end case;\n end function ufixed_low;\n \n function sfixed_high (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER is\n begin\n case operation is\n when '+'| '-' => return maximum (left_index, left_index2) + 1;\n when '*' => return left_index + left_index2 + 1;\n when '/' => return left_index - right_index2 + 1;\n when '1' => return -right_index + 1; -- reciprocal\n when 'R'|'r' => return mins (left_index, left_index2); -- \"rem\"\n when 'M'|'m' => return left_index2; -- \"mod\"\n when 'A'|'a' => return left_index + 1; -- \"abs\"\n when 'N'|'n' => return left_index + 1; -- -sfixed\n when others => return left_index;\n end case;\n end function sfixed_high;\n\n function sfixed_low (left_index, right_index : INTEGER;\n operation : CHARACTER := 'X';\n left_index2, right_index2 : INTEGER := 0)\n return INTEGER is\n begin\n case operation is\n when '+'| '-' => return mins (right_index, right_index2);\n when '*' => return right_index + right_index2;\n when '/' => return right_index - left_index2;\n when '1' => return -left_index; -- reciprocal\n when 'R'|'r' => return mins (right_index, right_index2); -- \"rem\"\n when 'M'|'m' => return mins (right_index, right_index2); -- \"mod\"\n when others => return right_index; -- default for abs, neg and default\n end case;\n end function sfixed_low;\n\n -- Same as above, but using the \"size_res\" input only for their ranges:\n -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto\n -- ufixed_low (uf1, '*', uf2));\n -- uf1multuf2 <= uf1 * uf2; \n function ufixed_high (size_res : UNRESOLVED_ufixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_ufixed)\n return INTEGER is\n begin\n return ufixed_high (left_index => size_res'high,\n right_index => size_res'low,\n operation => operation,\n left_index2 => size_res2'high,\n right_index2 => size_res2'low);\n end function ufixed_high;\n\n function ufixed_low (size_res : UNRESOLVED_ufixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_ufixed)\n return INTEGER is\n begin\n return ufixed_low (left_index => size_res'high,\n right_index => size_res'low,\n operation => operation,\n left_index2 => size_res2'high,\n right_index2 => size_res2'low);\n end function ufixed_low;\n\n function sfixed_high (size_res : UNRESOLVED_sfixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_sfixed)\n return INTEGER is\n begin\n return sfixed_high (left_index => size_res'high,\n right_index => size_res'low,\n operation => operation,\n left_index2 => size_res2'high,\n right_index2 => size_res2'low);\n end function sfixed_high;\n\n function sfixed_low (size_res : UNRESOLVED_sfixed;\n operation : CHARACTER := 'X';\n size_res2 : UNRESOLVED_sfixed)\n return INTEGER is\n begin\n return sfixed_low (left_index => size_res'high,\n right_index => size_res'low,\n operation => operation,\n left_index2 => size_res2'high,\n right_index2 => size_res2'low);\n end function sfixed_low;\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed is\n constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=\n (others => '1');\n begin\n return sat;\n end function saturate;\n\n -- purpose: returns a saturated number\n function saturate (\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed is\n variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=\n (others => '1');\n begin\n -- saturate positive, to saturate negative, just do \"not saturate()\"\n sat (left_index) := '0';\n return sat;\n end function saturate;\n\n function saturate (\n size_res : UNRESOLVED_ufixed) -- only the size of this is used\n return UNRESOLVED_ufixed is\n begin\n return saturate (size_res'high, size_res'low);\n end function saturate;\n\n function saturate (\n size_res : UNRESOLVED_sfixed) -- only the size of this is used\n return UNRESOLVED_sfixed is\n begin\n return saturate (size_res'high, size_res'low);\n end function saturate;\n\n -- As a concession to those who use a graphical DSP environment,\n -- these functions take parameters in those tools format and create\n -- fixed point numbers. These functions are designed to convert from\n -- a std_logic_vector to the VHDL fixed point format using the conventions\n -- of these packages. In a pure VHDL environment you should use the\n -- \"to_ufixed\" and \"to_sfixed\" routines.\n -- Unsigned fixed point\n function to_UFix (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);\n begin\n if (arg'length /= result'length) then\n report fixed_pkg'instance_name\n & \"TO_UFIX (STD_ULOGIC_VECTOR) \"\n & \"Vector lengths do not match. Input length is \"\n & INTEGER'image(arg'length) & \" and output will be \"\n & INTEGER'image(result'length) & \" wide.\"\n severity error;\n return NAUF;\n else\n result := to_ufixed (arg, result'high, result'low);\n return result;\n end if;\n end function to_UFix;\n\n -- signed fixed point\n function to_SFix (\n arg : STD_ULOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);\n begin\n if (arg'length /= result'length) then\n report fixed_pkg'instance_name\n & \"TO_SFIX (STD_ULOGIC_VECTOR) \"\n & \"Vector lengths do not match. Input length is \"\n & INTEGER'image(arg'length) & \" and output will be \"\n & INTEGER'image(result'length) & \" wide.\"\n severity error;\n return NASF;\n else\n result := to_sfixed (arg, result'high, result'low);\n return result;\n end if;\n end function to_SFix;\n\n -- finding the bounds of a number. These functions can be used like this:\n -- signal xxx : ufixed (7 downto -3);\n -- -- Which is the same as \"ufixed (UFix_high (11,3) downto UFix_low(11,3))\"\n -- signal yyy : ufixed (UFix_high (11, 3, \"+\", 11, 3)\n -- downto UFix_low(11, 3, \"+\", 11, 3));\n -- Where \"11\" is the width of xxx (xxx'length),\n -- and 3 is the lower bound (abs (xxx'low))\n -- In a pure VHDL environment use \"ufixed_high\" and \"ufixed_low\"\n function ufix_high (\n width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER is\n begin\n return ufixed_high (left_index => width - 1 - fraction,\n right_index => -fraction,\n operation => operation,\n left_index2 => width2 - 1 - fraction2,\n right_index2 => -fraction2);\n end function ufix_high;\n\n function ufix_low (\n width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER is\n begin\n return ufixed_low (left_index => width - 1 - fraction,\n right_index => -fraction,\n operation => operation,\n left_index2 => width2 - 1 - fraction2,\n right_index2 => -fraction2);\n end function ufix_low;\n\n function sfix_high (\n width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER is\n begin\n return sfixed_high (left_index => width - fraction,\n right_index => -fraction,\n operation => operation,\n left_index2 => width2 - fraction2,\n right_index2 => -fraction2);\n end function sfix_high;\n\n function sfix_low (\n width, fraction : NATURAL;\n operation : CHARACTER := 'X';\n width2, fraction2 : NATURAL := 0)\n return INTEGER is\n begin\n return sfixed_low (left_index => width - fraction,\n right_index => -fraction,\n operation => operation,\n left_index2 => width2 - fraction2,\n right_index2 => -fraction2);\n end function sfix_low;\n\n function to_unsigned (\n arg : UNRESOLVED_ufixed; -- ufixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED is\n begin\n return to_uns(resize (arg => arg,\n left_index => size-1,\n right_index => 0,\n round_style => round_style,\n overflow_style => overflow_style));\n end function to_unsigned;\n\n function to_unsigned (\n arg : UNRESOLVED_ufixed; -- ufixed point input\n size_res : UNSIGNED; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNSIGNED is\n begin\n return to_unsigned (arg => arg,\n size => size_res'length,\n round_style => round_style,\n overflow_style => overflow_style);\n end function to_unsigned;\n\n function to_signed (\n arg : UNRESOLVED_sfixed; -- sfixed point input\n constant size : NATURAL; -- length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED is\n begin\n return to_s(resize (arg => arg,\n left_index => size-1,\n right_index => 0,\n round_style => round_style,\n overflow_style => overflow_style));\n end function to_signed;\n\n function to_signed (\n arg : UNRESOLVED_sfixed; -- sfixed point input\n size_res : SIGNED; -- used for length of output\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return SIGNED is\n begin\n return to_signed (arg => arg,\n size => size_res'length,\n round_style => round_style,\n overflow_style => overflow_style);\n end function to_signed;\n \n function to_real (\n arg : UNRESOLVED_ufixed) -- ufixed point input\n return REAL is\n constant left_index : INTEGER := arg'high;\n constant right_index : INTEGER := arg'low;\n variable result : REAL; -- result\n variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);\n begin\n if (arg'length < 1) then\n return 0.0;\n end if;\n arg_int := to_x01(cleanvec(arg));\n if (Is_X(arg_int)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_REAL (ufixed): metavalue detected, returning 0.0\"\n severity warning;\n return 0.0;\n end if;\n result := 0.0;\n for i in arg_int'range loop\n if (arg_int(i) = '1') then\n result := result + (2.0**i);\n end if;\n end loop;\n return result;\n end function to_real;\n\n function to_real (\n arg : UNRESOLVED_sfixed) -- ufixed point input\n return REAL is\n constant left_index : INTEGER := arg'high;\n constant right_index : INTEGER := arg'low;\n variable result : REAL; -- result\n variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);\n -- unsigned version of argument\n variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);\n -- absolute of argument\n begin\n if (arg'length < 1) then\n return 0.0;\n end if;\n arg_int := to_x01(cleanvec(arg));\n if (Is_X(arg_int)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_REAL (sfixed): metavalue detected, returning 0.0\"\n severity warning;\n return 0.0;\n end if;\n arg_uns := to_ufixed (arg_int);\n result := to_real (arg_uns);\n if (arg_int(arg_int'high) = '1') then\n result := -result;\n end if;\n return result;\n end function to_real;\n\n function to_integer (\n arg : UNRESOLVED_ufixed; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return NATURAL is\n constant left_index : INTEGER := arg'high;\n variable arg_uns : UNSIGNED (left_index+1 downto 0)\n := (others => '0');\n begin\n if (arg'length < 1) then\n return 0;\n end if;\n if (Is_X (arg)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_INTEGER (ufixed): metavalue detected, returning 0\"\n severity warning;\n return 0;\n end if;\n if (left_index < -1) then\n return 0;\n end if;\n arg_uns := to_uns(resize (arg => arg,\n left_index => arg_uns'high,\n right_index => 0,\n round_style => round_style,\n overflow_style => overflow_style));\n return to_integer (arg_uns);\n end function to_integer;\n\n function to_integer (\n arg : UNRESOLVED_sfixed; -- fixed point input\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return INTEGER is\n constant left_index : INTEGER := arg'high;\n constant right_index : INTEGER := arg'low;\n variable arg_s : SIGNED (left_index+1 downto 0);\n begin\n if (arg'length < 1) then\n return 0;\n end if;\n if (Is_X (arg)) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_INTEGER (sfixed): metavalue detected, returning 0\"\n severity warning;\n return 0;\n end if;\n if (left_index < -1) then\n return 0;\n end if;\n arg_s := to_s(resize (arg => arg,\n left_index => arg_s'high,\n right_index => 0,\n round_style => round_style,\n overflow_style => overflow_style));\n return to_integer (arg_s);\n end function to_integer;\n\n function to_01 (\n s : UNRESOLVED_ufixed; -- ufixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (s'range); -- result\n begin\n if (s'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_01(ufixed): null detected, returning NULL\"\n severity warning;\n return NAUF;\n end if;\n return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);\n end function to_01;\n\n function to_01 (\n s : UNRESOLVED_sfixed; -- sfixed point input\n constant XMAP : STD_ULOGIC := '0') -- Map x to\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (s'range);\n begin\n if (s'length < 1) then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"TO_01(sfixed): null detected, returning NULL\"\n severity warning;\n return NASF;\n end if;\n return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);\n end function to_01;\n\n function Is_X (\n arg : UNRESOLVED_ufixed)\n return BOOLEAN is\n variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv\n begin\n argslv := to_sulv(arg);\n return Is_X (argslv);\n end function Is_X;\n \n function Is_X (\n arg : UNRESOLVED_sfixed)\n return BOOLEAN is\n variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv\n begin\n argslv := to_sulv(arg);\n return Is_X (argslv);\n end function Is_X;\n\n function To_X01 (\n arg : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n begin\n return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);\n end function To_X01;\n\n function to_X01 (\n arg : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);\n end function To_X01;\n\n function To_X01Z (\n arg : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n begin\n return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);\n end function To_X01Z;\n\n function to_X01Z (\n arg : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);\n end function To_X01Z;\n\n function To_UX01 (\n arg : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n begin\n return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);\n end function To_UX01;\n\n function to_UX01 (\n arg : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);\n end function To_UX01;\n \n function resize (\n arg : UNRESOLVED_ufixed; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed is\n constant arghigh : INTEGER := maximum (arg'high, arg'low);\n constant arglow : INTEGER := mine (arg'high, arg'low);\n variable invec : UNRESOLVED_ufixed (arghigh downto arglow);\n variable result : UNRESOLVED_ufixed(left_index downto right_index) :=\n (others => '0');\n variable needs_rounding : BOOLEAN := false;\n begin -- resize\n if (arg'length < 1) or (result'length < 1) then\n return NAUF;\n elsif (invec'length < 1) then\n return result; -- string literal value\n else\n invec := cleanvec(arg);\n if (right_index > arghigh) then -- return top zeros\n needs_rounding := (round_style = fixed_round) and\n (right_index = arghigh+1);\n elsif (left_index < arglow) then -- return overflow\n if (overflow_style = fixed_saturate) and\n (or_reduce(to_sulv(invec)) = '1') then\n result := saturate (result'high, result'low); -- saturate\n end if;\n elsif (arghigh > left_index) then\n -- wrap or saturate?\n if (overflow_style = fixed_saturate and\n or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')\n then\n result := saturate (result'high, result'low); -- saturate\n else\n if (arglow >= right_index) then\n result (left_index downto arglow) :=\n invec(left_index downto arglow);\n else\n result (left_index downto right_index) :=\n invec (left_index downto right_index);\n needs_rounding := (round_style = fixed_round); -- round\n end if;\n end if;\n else -- arghigh <= integer width\n if (arglow >= right_index) then\n result (arghigh downto arglow) := invec;\n else\n result (arghigh downto right_index) :=\n invec (arghigh downto right_index);\n needs_rounding := (round_style = fixed_round); -- round\n end if;\n end if;\n -- Round result\n if needs_rounding then\n result := round_fixed (arg => result,\n remainder => invec (right_index-1\n downto arglow),\n overflow_style => overflow_style);\n end if;\n return result;\n end if;\n end function resize;\n\n function resize (\n arg : UNRESOLVED_sfixed; -- input\n constant left_index : INTEGER; -- integer portion\n constant right_index : INTEGER; -- size of fraction\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed is\n constant arghigh : INTEGER := maximum (arg'high, arg'low);\n constant arglow : INTEGER := mine (arg'high, arg'low);\n variable invec : UNRESOLVED_sfixed (arghigh downto arglow);\n variable result : UNRESOLVED_sfixed(left_index downto right_index) :=\n (others => '0');\n variable reduced : STD_ULOGIC;\n variable needs_rounding : BOOLEAN := false; -- rounding\n begin -- resize\n if (arg'length < 1) or (result'length < 1) then\n return NASF;\n elsif (invec'length < 1) then\n return result; -- string literal value\n else\n invec := cleanvec(arg);\n if (right_index > arghigh) then -- return top zeros\n if (arg'low /= INTEGER'low) then -- check for a literal\n result := (others => arg(arghigh)); -- sign extend\n end if;\n needs_rounding := (round_style = fixed_round) and\n (right_index = arghigh+1);\n elsif (left_index < arglow) then -- return overflow\n if (overflow_style = fixed_saturate) then\n reduced := or_reduce (to_sulv(invec));\n if (reduced = '1') then\n if (invec(arghigh) = '0') then\n -- saturate POSITIVE\n result := saturate (result'high, result'low);\n else\n -- saturate negative\n result := not saturate (result'high, result'low);\n end if;\n -- else return 0 (input was 0)\n end if;\n -- else return 0 (wrap)\n end if;\n elsif (arghigh > left_index) then\n if (invec(arghigh) = '0') then\n reduced := or_reduce (to_sulv(invec(arghigh-1 downto\n left_index)));\n if overflow_style = fixed_saturate and reduced = '1' then\n -- saturate positive\n result := saturate (result'high, result'low);\n else\n if (right_index > arglow) then\n result := invec (left_index downto right_index);\n needs_rounding := (round_style = fixed_round);\n else\n result (left_index downto arglow) :=\n invec (left_index downto arglow);\n end if;\n end if;\n else\n reduced := and_reduce (to_sulv(invec(arghigh-1 downto\n left_index)));\n if overflow_style = fixed_saturate and reduced = '0' then\n result := not saturate (result'high, result'low);\n else\n if (right_index > arglow) then\n result := invec (left_index downto right_index);\n needs_rounding := (round_style = fixed_round);\n else\n result (left_index downto arglow) :=\n invec (left_index downto arglow);\n end if;\n end if;\n end if;\n else -- arghigh <= integer width\n if (arglow >= right_index) then\n result (arghigh downto arglow) := invec;\n else\n result (arghigh downto right_index) :=\n invec (arghigh downto right_index);\n needs_rounding := (round_style = fixed_round); -- round\n end if;\n if (left_index > arghigh) then -- sign extend\n result(left_index downto arghigh+1) := (others => invec(arghigh));\n end if;\n end if;\n -- Round result\n if (needs_rounding) then\n result := round_fixed (arg => result,\n remainder => invec (right_index-1\n downto arglow),\n overflow_style => overflow_style);\n end if;\n return result;\n end if;\n end function resize;\n\n -- size_res functions\n -- These functions compute the size from a passed variable named \"size_res\"\n -- The only part of this variable used it it's size, it is never passed\n -- to a lower level routine.\n function to_ufixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_ufixed) -- for size only\n return UNRESOLVED_ufixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_ufixed (size_res'left downto fw);\n begin\n if (result'length < 1 or arg'length < 1) then\n return NAUF;\n else\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low);\n return result;\n end if;\n end function to_ufixed;\n\n function to_sfixed (\n arg : STD_ULOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_sfixed) -- for size only\n return UNRESOLVED_sfixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_sfixed (size_res'left downto fw);\n begin\n if (result'length < 1 or arg'length < 1) then\n return NASF;\n else\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low);\n return result;\n end if;\n end function to_sfixed;\n\n function to_ufixed (\n arg : NATURAL; -- integer\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_ufixed (size_res'left downto fw);\n begin\n if (result'length < 1) then\n return NAUF;\n else\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function to_ufixed;\n\n function to_sfixed (\n arg : INTEGER; -- integer\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_sfixed (size_res'left downto fw);\n begin\n if (result'length < 1) then\n return NASF;\n else\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function to_sfixed;\n\n function to_ufixed (\n arg : REAL; -- real\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits\n return UNRESOLVED_ufixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_ufixed (size_res'left downto fw);\n begin\n if (result'length < 1) then\n return NAUF;\n else\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n guard_bits => guard_bits,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function to_ufixed;\n\n function to_sfixed (\n arg : REAL; -- real\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style;\n constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits\n return UNRESOLVED_sfixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_sfixed (size_res'left downto fw);\n begin\n if (result'length < 1) then\n return NASF;\n else\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n guard_bits => guard_bits,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function to_sfixed;\n\n function to_ufixed (\n arg : UNSIGNED; -- unsigned\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_ufixed (size_res'left downto fw);\n begin\n if (result'length < 1 or arg'length < 1) then\n return NAUF;\n else\n result := to_ufixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function to_ufixed;\n \n function to_sfixed (\n arg : SIGNED; -- signed\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_sfixed (size_res'left downto fw);\n begin\n if (result'length < 1 or arg'length < 1) then\n return NASF;\n else\n result := to_sfixed (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function to_sfixed;\n\n function resize (\n arg : UNRESOLVED_ufixed; -- input\n size_res : UNRESOLVED_ufixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_ufixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_ufixed (size_res'high downto fw);\n begin\n if (result'length < 1 or arg'length < 1) then\n return NAUF;\n else\n result := resize (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function resize;\n\n function resize (\n arg : UNRESOLVED_sfixed; -- input\n size_res : UNRESOLVED_sfixed; -- for size only\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;\n constant round_style : fixed_round_style_type := fixed_round_style)\n return UNRESOLVED_sfixed is\n constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals\n variable result : UNRESOLVED_sfixed (size_res'high downto fw);\n begin\n if (result'length < 1 or arg'length < 1) then\n return NASF;\n else\n result := resize (arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end if;\n end function resize;\n\n -- Overloaded math functions for real\n function \"+\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return (l + to_ufixed (r, l'high, l'low));\n end function \"+\";\n\n function \"+\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, r'low) + r);\n end function \"+\";\n\n function \"+\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return (l + to_sfixed (r, l'high, l'low));\n end function \"+\";\n\n function \"+\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, r'low) + r);\n end function \"+\";\n\n function \"-\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return (l - to_ufixed (r, l'high, l'low));\n end function \"-\";\n\n function \"-\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, r'low) - r);\n end function \"-\";\n\n function \"-\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return (l - to_sfixed (r, l'high, l'low));\n end function \"-\";\n\n function \"-\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, r'low) - r);\n end function \"-\";\n\n function \"*\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return (l * to_ufixed (r, l'high, l'low));\n end function \"*\";\n\n function \"*\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, r'low) * r);\n end function \"*\";\n\n function \"*\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return (l * to_sfixed (r, l'high, l'low));\n end function \"*\";\n\n function \"*\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, r'low) * r);\n end function \"*\";\n\n function \"/\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return (l / to_ufixed (r, l'high, l'low));\n end function \"/\";\n\n function \"/\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, r'low) / r);\n end function \"/\";\n\n function \"/\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return (l / to_sfixed (r, l'high, l'low));\n end function \"/\";\n\n function \"/\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, r'low) / r);\n end function \"/\";\n\n function \"rem\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return (l rem to_ufixed (r, l'high, l'low));\n end function \"rem\";\n\n function \"rem\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, r'low) rem r);\n end function \"rem\";\n\n function \"rem\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return (l rem to_sfixed (r, l'high, l'low));\n end function \"rem\";\n\n function \"rem\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, r'low) rem r);\n end function \"rem\";\n\n function \"mod\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return (l mod to_ufixed (r, l'high, l'low));\n end function \"mod\";\n\n function \"mod\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, r'low) mod r);\n end function \"mod\";\n\n function \"mod\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return (l mod to_sfixed (r, l'high, l'low));\n end function \"mod\";\n\n function \"mod\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, r'low) mod r);\n end function \"mod\";\n\n -- Overloaded math functions for integers\n function \"+\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return (l + to_ufixed (r, l'high, 0));\n end function \"+\";\n\n function \"+\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, 0) + r);\n end function \"+\";\n\n function \"+\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return (l + to_sfixed (r, l'high, 0));\n end function \"+\";\n\n function \"+\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, 0) + r);\n end function \"+\";\n\n -- Overloaded functions\n function \"-\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return (l - to_ufixed (r, l'high, 0));\n end function \"-\";\n\n function \"-\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, 0) - r);\n end function \"-\";\n\n function \"-\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return (l - to_sfixed (r, l'high, 0));\n end function \"-\";\n\n function \"-\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, 0) - r);\n end function \"-\";\n\n -- Overloaded functions\n function \"*\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return (l * to_ufixed (r, l'high, 0));\n end function \"*\";\n\n function \"*\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, 0) * r);\n end function \"*\";\n\n function \"*\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return (l * to_sfixed (r, l'high, 0));\n end function \"*\";\n\n function \"*\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, 0) * r);\n end function \"*\";\n\n -- Overloaded functions\n function \"/\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return (l / to_ufixed (r, l'high, 0));\n end function \"/\";\n\n function \"/\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, 0) / r);\n end function \"/\";\n\n function \"/\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return (l / to_sfixed (r, l'high, 0));\n end function \"/\";\n\n function \"/\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, 0) / r);\n end function \"/\";\n\n function \"rem\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return (l rem to_ufixed (r, l'high, 0));\n end function \"rem\";\n\n function \"rem\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, 0) rem r);\n end function \"rem\";\n\n function \"rem\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return (l rem to_sfixed (r, l'high, 0));\n end function \"rem\";\n\n function \"rem\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, 0) rem r);\n end function \"rem\";\n\n function \"mod\" (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return (l mod to_ufixed (r, l'high, 0));\n end function \"mod\";\n\n function \"mod\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return (to_ufixed (l, r'high, 0) mod r);\n end function \"mod\";\n\n function \"mod\" (\n l : UNRESOLVED_sfixed; -- fixed point input\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return (l mod to_sfixed (r, l'high, 0));\n end function \"mod\";\n\n function \"mod\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return UNRESOLVED_sfixed is\n begin\n return (to_sfixed (l, r'high, 0) mod r);\n end function \"mod\";\n\n -- overloaded ufixed compare functions with integer\n function \"=\" (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l = to_ufixed (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l /= to_ufixed (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l >= to_ufixed (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l <= to_ufixed (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l > to_ufixed (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return BOOLEAN is\n begin\n return (l < to_ufixed (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : UNRESOLVED_ufixed;\n r : NATURAL) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return maximum (l, to_ufixed (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : UNRESOLVED_ufixed; -- fixed point input\n r : NATURAL)\n return UNRESOLVED_ufixed is\n begin\n return minimum (l, to_ufixed (r, l'high, l'low));\n end function minimum;\n\n -- NATURAL to ufixed\n function \"=\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?<\\;\n\n function maximum (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return maximum (to_ufixed (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : NATURAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return minimum (to_ufixed (l, r'high, r'low), r);\n end function minimum;\n\n -- overloaded ufixed compare functions with real\n function \"=\" (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l = to_ufixed (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l /= to_ufixed (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l >= to_ufixed (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l <= to_ufixed (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l > to_ufixed (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l < to_ufixed (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_ufixed (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return maximum (l, to_ufixed (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : UNRESOLVED_ufixed;\n r : REAL)\n return UNRESOLVED_ufixed is\n begin\n return minimum (l, to_ufixed (r, l'high, l'low));\n end function minimum;\n\n -- real and ufixed\n function \"=\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_ufixed (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_ufixed (l, r'high, r'low), r);\n end function \\?<\\;\n \n function maximum (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return maximum (to_ufixed (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : REAL;\n r : UNRESOLVED_ufixed) -- fixed point input\n return UNRESOLVED_ufixed is\n begin\n return minimum (to_ufixed (l, r'high, r'low), r);\n end function minimum;\n\n -- overloaded sfixed compare functions with integer\n function \"=\" (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l = to_sfixed (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l /= to_sfixed (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l >= to_sfixed (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l <= to_sfixed (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l > to_sfixed (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return BOOLEAN is\n begin\n return (l < to_sfixed (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return maximum (l, to_sfixed (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : UNRESOLVED_sfixed;\n r : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return minimum (l, to_sfixed (r, l'high, l'low));\n end function minimum;\n\n -- integer and sfixed\n function \"=\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : INTEGER;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?<\\;\n\n function maximum (\n l : INTEGER;\n r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return maximum (to_sfixed (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : INTEGER;\n r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return minimum (to_sfixed (l, r'high, r'low), r);\n end function minimum;\n\n -- overloaded sfixed compare functions with real\n function \"=\" (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l = to_sfixed (r, l'high, l'low));\n end function \"=\";\n\n function \"/=\" (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l /= to_sfixed (r, l'high, l'low));\n end function \"/=\";\n\n function \">=\" (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l >= to_sfixed (r, l'high, l'low));\n end function \">=\";\n\n function \"<=\" (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l <= to_sfixed (r, l'high, l'low));\n end function \"<=\";\n\n function \">\" (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l > to_sfixed (r, l'high, l'low));\n end function \">\";\n\n function \"<\" (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return BOOLEAN is\n begin\n return (l < to_sfixed (r, l'high, l'low));\n end function \"<\";\n\n function \\?=\\ (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?=\\;\n\n function \\?/=\\ (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?/=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<=\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?<=\\;\n\n function \\?>\\ (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?>\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?>\\;\n\n function \\?<\\ (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return STD_ULOGIC is\n begin\n return \\?<\\ (l, to_sfixed (r, l'high, l'low));\n end function \\?<\\;\n\n function maximum (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return maximum (l, to_sfixed (r, l'high, l'low));\n end function maximum;\n\n function minimum (\n l : UNRESOLVED_sfixed;\n r : REAL)\n return UNRESOLVED_sfixed is\n begin\n return minimum (l, to_sfixed (r, l'high, l'low));\n end function minimum;\n\n -- REAL and sfixed\n function \"=\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) = r);\n end function \"=\";\n\n function \"/=\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) /= r);\n end function \"/=\";\n\n function \">=\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) >= r);\n end function \">=\";\n\n function \"<=\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) <= r);\n end function \"<=\";\n\n function \">\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) > r);\n end function \">\";\n\n function \"<\" (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return BOOLEAN is\n begin\n return (to_sfixed (l, r'high, r'low) < r);\n end function \"<\";\n\n function \\?=\\ (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?=\\;\n\n function \\?/=\\ (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?/=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?/=\\;\n\n function \\?>=\\ (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?>=\\;\n\n function \\?<=\\ (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<=\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?<=\\;\n\n function \\?>\\ (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?>\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?>\\;\n\n function \\?<\\ (\n l : REAL;\n r : UNRESOLVED_sfixed) -- fixed point input\n return STD_ULOGIC is\n begin\n return \\?<\\ (to_sfixed (l, r'high, r'low), r);\n end function \\?<\\;\n\n function maximum (\n l : REAL;\n r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return maximum (to_sfixed (l, r'high, r'low), r);\n end function maximum;\n\n function minimum (\n l : REAL;\n r : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return minimum (to_sfixed (l, r'high, r'low), r);\n end function minimum;\n-- rtl_synthesis off\n-- pragma synthesis_off\n -- copied from std_logic_textio\n type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);\n type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;\n type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;\n type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;\n\n constant MVL9_to_char : char_indexed_by_MVL9 := \"UX01ZWLH-\";\n constant char_to_MVL9 : MVL9_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');\n constant char_to_MVL9plus : MVL9plus_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);\n constant NBSP : CHARACTER := CHARACTER'val(160); -- space character\n constant NUS : STRING(2 to 1) := (others => ' ');\n\n -- %%% Replicated Textio functions\n procedure Char2TriBits (C : CHARACTER;\n RESULT : out STD_ULOGIC_VECTOR(2 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n when '4' => result := o\"4\"; good := true;\n when '5' => result := o\"5\"; good := true;\n when '6' => result := o\"6\"; good := true;\n when '7' => result := o\"7\"; good := true;\n when 'Z' => result := \"ZZZ\"; good := true;\n when 'X' => result := \"XXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report fixed_pkg'instance_name\n & \"OREAD Error: Read a '\" & c &\n \"', expected an Octal character (0-7).\"\n severity error;\n result := \"UUU\";\n good := false;\n end case;\n end procedure Char2TriBits;\n -- Hex Read and Write procedures for STD_ULOGIC_VECTOR.\n -- Modified from the original to be more forgiving.\n\n procedure Char2QuadBits (C : CHARACTER;\n RESULT : out STD_ULOGIC_VECTOR(3 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := x\"0\"; good := true;\n when '1' => result := x\"1\"; good := true;\n when '2' => result := x\"2\"; good := true;\n when '3' => result := x\"3\"; good := true;\n when '4' => result := x\"4\"; good := true;\n when '5' => result := x\"5\"; good := true;\n when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n", "right_context": " when 'E' | 'e' => result := x\"E\"; good := true;\n when 'F' | 'f' => result := x\"F\"; good := true;\n when 'Z' => result := \"ZZZZ\"; good := true;\n when 'X' => result := \"XXXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report fixed_pkg'instance_name\n & \"HREAD Error: Read a '\" & c &\n \"', expected a Hex character (0-F).\"\n severity error;\n result := \"UUUU\";\n good := false;\n end case;\n end procedure Char2QuadBits;\n\n -- purpose: Skips white space\n procedure skip_whitespace (\n L : inout LINE) is\n variable readOk : BOOLEAN;\n variable c : CHARACTER;\n begin\n while L /= null and L.all'length /= 0 loop\n if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then\n read (l, c, readOk);\n else\n exit;\n end if;\n end loop;\n end procedure skip_whitespace;\n\n function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+2)/3;\n variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);\n variable result : STRING(1 to ne);\n variable tri : STD_ULOGIC_VECTOR(0 to 2);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n tri := To_X01Z(ivalue(3*i to 3*i+2));\n case tri is\n when o\"0\" => result(i+1) := '0';\n when o\"1\" => result(i+1) := '1';\n when o\"2\" => result(i+1) := '2';\n when o\"3\" => result(i+1) := '3';\n when o\"4\" => result(i+1) := '4';\n when o\"5\" => result(i+1) := '5';\n when o\"6\" => result(i+1) := '6';\n when o\"7\" => result(i+1) := '7';\n when \"ZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_ostring;\n ------------------------------------------------------------------- \n function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+3)/4;\n variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);\n variable result : STRING(1 to ne);\n variable quad : STD_ULOGIC_VECTOR(0 to 3);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n quad := To_X01Z(ivalue(4*i to 4*i+3));\n case quad is\n when x\"0\" => result(i+1) := '0';\n when x\"1\" => result(i+1) := '1';\n when x\"2\" => result(i+1) := '2';\n when x\"3\" => result(i+1) := '3';\n when x\"4\" => result(i+1) := '4';\n when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n when x\"7\" => result(i+1) := '7';\n when x\"8\" => result(i+1) := '8';\n when x\"9\" => result(i+1) := '9';\n when x\"A\" => result(i+1) := 'A';\n when x\"B\" => result(i+1) := 'B';\n when x\"C\" => result(i+1) := 'C';\n when x\"D\" => result(i+1) := 'D';\n when x\"E\" => result(i+1) := 'E';\n when x\"F\" => result(i+1) := 'F';\n when \"ZZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_hstring;\n\n\n-- %%% END replicated textio functions\n \n -- purpose: writes fixed point into a line\n procedure write (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_ufixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n variable s : STRING(1 to value'length +1) := (others => ' ');\n variable sindx : INTEGER;\n begin -- function write Example: 0011.1100\n sindx := 1;\n for i in value'high downto value'low loop\n if i = -1 then\n s(sindx) := '.';\n sindx := sindx + 1;\n end if;\n s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));\n sindx := sindx + 1;\n end loop;\n write(l, s, justified, field);\n end procedure write;\n\n -- purpose: writes fixed point into a line\n procedure write (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_sfixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n variable s : STRING(1 to value'length +1);\n variable sindx : INTEGER;\n begin -- function write Example: 0011.1100\n sindx := 1;\n for i in value'high downto value'low loop\n if i = -1 then\n s(sindx) := '.';\n sindx := sindx + 1;\n end if;\n s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));\n sindx := sindx + 1;\n end loop;\n write(l, s, justified, field);\n end procedure write;\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed) is\n -- Possible data: 00000.0000000\n -- 000000000000\n variable c : CHARACTER;\n variable readOk : BOOLEAN;\n variable i : INTEGER; -- index variable\n variable mv : ufixed (VALUE'range);\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable founddot : BOOLEAN := false; -- found a \".\"\n begin -- READ\n VALUE := (VALUE'range => 'U');\n Skip_whitespace (L);\n if VALUE'length > 0 then -- non Null input string\n read (l, c, readOk);\n i := value'high;\n while i >= VALUE'low loop\n if readOk = false then -- Bail out if there was a bad read\n report fixed_pkg'instance_name & \"READ(ufixed) \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif c = '_' then\n if i = value'high then\n report fixed_pkg'instance_name & \"READ(ufixed) \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report fixed_pkg'instance_name & \"READ(ufixed) \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n elsif c = '.' then -- binary point\n if founddot then\n report fixed_pkg'instance_name & \"READ(ufixed) \"\n & \"Two binary points found in input string\" severity error;\n return;\n elsif i /= -1 then -- Seperator in the wrong spot\n report fixed_pkg'instance_name & \"READ(ufixed) \"\n & \"Decimal point does not match number format \"\n severity error;\n return;\n end if;\n founddot := true;\n lastu := false;\n elsif c = ' ' or c = NBSP or c = HT then -- reading done.\n report fixed_pkg'instance_name & \"READ(ufixed) \"\n & \"Short read, Space encounted in input string\"\n severity error;\n return;\n elsif char_to_MVL9plus(c) = error then\n report fixed_pkg'instance_name & \"READ(ufixed) \"\n & \"Character '\" &\n c & \"' read, expected STD_ULOGIC literal.\"\n severity error;\n return;\n else\n mv(i) := char_to_MVL9(c);\n i := i - 1;\n if i < mv'low then\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n read(L, c, readOk);\n end loop;\n end if;\n end procedure READ;\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed;\n GOOD : out BOOLEAN) is\n -- Possible data: 00000.0000000\n -- 000000000000\n variable c : CHARACTER;\n variable readOk : BOOLEAN;\n variable mv : ufixed (VALUE'range);\n variable i : INTEGER; -- index variable\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable founddot : BOOLEAN := false; -- found a \".\"\n begin -- READ\n VALUE := (VALUE'range => 'U');\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, readOk);\n i := value'high;\n GOOD := false;\n while i >= VALUE'low loop\n if not readOk then -- Bail out if there was a bad read\n return;\n elsif c = '_' then\n if i = value'high then -- Begins with an \"_\"\n return;\n elsif lastu then -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n elsif c = '.' then -- binary point\n if founddot then\n return;\n elsif i /= -1 then -- Seperator in the wrong spot\n return;\n end if;\n founddot := true;\n lastu := false;\n elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read\n return;\n else\n mv(i) := char_to_MVL9(c);\n i := i - 1;\n if i < mv'low then -- reading done\n GOOD := true;\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n read(L, c, readOk);\n end loop;\n else\n GOOD := true; -- read into a null array\n end if;\n end procedure READ;\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed) is\n variable c : CHARACTER;\n variable readOk : BOOLEAN;\n variable i : INTEGER; -- index variable\n variable mv : sfixed (VALUE'range);\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable founddot : BOOLEAN := false; -- found a \".\"\n begin -- READ\n VALUE := (VALUE'range => 'U');\n Skip_whitespace (L);\n if VALUE'length > 0 then -- non Null input string\n read (l, c, readOk);\n i := value'high;\n while i >= VALUE'low loop\n if readOk = false then -- Bail out if there was a bad read\n report fixed_pkg'instance_name & \"READ(sfixed) \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif c = '_' then\n if i = value'high then\n report fixed_pkg'instance_name & \"READ(sfixed) \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report fixed_pkg'instance_name & \"READ(sfixed) \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n elsif c = '.' then -- binary point\n if founddot then\n report fixed_pkg'instance_name & \"READ(sfixed) \"\n & \"Two binary points found in input string\" severity error;\n return;\n elsif i /= -1 then -- Seperator in the wrong spot\n report fixed_pkg'instance_name & \"READ(sfixed) \"\n & \"Decimal point does not match number format \"\n severity error;\n return;\n end if;\n founddot := true;\n lastu := false;\n elsif c = ' ' or c = NBSP or c = HT then -- reading done.\n report fixed_pkg'instance_name & \"READ(sfixed) \"\n & \"Short read, Space encounted in input string\"\n severity error;\n return;\n elsif char_to_MVL9plus(c) = error then\n report fixed_pkg'instance_name & \"READ(sfixed) \"\n & \"Character '\" &\n c & \"' read, expected STD_ULOGIC literal.\"\n severity error;\n return;\n else\n mv(i) := char_to_MVL9(c);\n i := i - 1;\n if i < mv'low then\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n read(L, c, readOk);\n end loop;\n end if;\n end procedure READ;\n\n procedure READ(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed;\n GOOD : out BOOLEAN) is\n variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);\n begin -- READ\n READ (L => L, VALUE => value_ufixed, GOOD => GOOD);\n VALUE := UNRESOLVED_sfixed (value_ufixed);\n end procedure READ;\n\n -- octal read and write\n procedure owrite (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_ufixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n begin -- Example 03.30\n write (L => L,\n VALUE => to_ostring (VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure owrite;\n\n procedure owrite (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_sfixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n begin -- Example 03.30\n write (L => L,\n VALUE => to_ostring (VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure owrite;\n\n -- purpose: Routines common to the OREAD routines\n procedure OREAD_common (\n L : inout LINE;\n slv : out STD_ULOGIC_VECTOR;\n igood : out BOOLEAN;\n idex : out INTEGER;\n constant bpoint : in INTEGER; -- binary point\n constant message : in BOOLEAN;\n constant smath : in BOOLEAN) is\n\n -- purpose: error message routine\n procedure errmes (\n constant mess : in STRING) is -- error message\n begin\n if message then\n if smath then\n report fixed_pkg'instance_name\n & \"OREAD(sfixed) \"\n & mess\n severity error;\n else\n report fixed_pkg'instance_name\n & \"OREAD(ufixed) \"\n & mess\n severity error;\n end if;\n end if;\n end procedure errmes;\n variable xgood : BOOLEAN;\n variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits\n variable c : CHARACTER;\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable founddot : BOOLEAN := false; -- found a dot.\n begin\n Skip_whitespace (L);\n if slv'length > 0 then\n i := slv'high;\n read (l, c, xgood);\n while i > 0 loop\n if xgood = false then\n errmes (\"Error: end of string encountered\");\n exit;\n elsif c = '_' then\n if i = slv'length then\n errmes (\"Error: String begins with an \"\"_\"\"\");\n xgood := false;\n exit;\n elsif lastu then\n errmes (\"Error: Two underscores detected in input string \"\"__\"\"\");\n xgood := false;\n exit;\n else\n lastu := true;\n end if;\n elsif (c = '.') then\n if (i + 1 /= bpoint) then\n errmes (\"encountered \"\".\"\" at wrong index\");\n xgood := false;\n exit;\n elsif i = slv'length then\n errmes (\"encounted a \"\".\"\" at the beginning of the line\");\n xgood := false;\n exit;\n elsif founddot then\n errmes (\"Two \"\".\"\" encounted in input string\");\n xgood := false;\n exit;\n end if;\n founddot := true;\n lastu := false;\n else\n Char2triBits(c, nybble, xgood, message);\n if not xgood then\n exit;\n end if;\n slv (i downto i-2) := nybble;\n i := i - 3;\n lastu := false;\n end if; \n if i > 0 then\n read (L, c, xgood);\n end if;\n end loop;\n idex := i;\n igood := xgood;\n else\n igood := true; -- read into a null array\n idex := -1;\n end if;\n end procedure OREAD_common;\n\n -- Note that for Octal and Hex read, you can not start with a \".\",\n -- the read is for numbers formatted \"A.BC\". These routines go to\n -- the nearest bounds, so \"F.E\" will fit into an sfixed (2 downto -3).\n procedure OREAD (L : inout LINE;\n VALUE : out UNRESOLVED_ufixed) is\n constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_ufixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n OREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => true,\n smath => false);\n if igood then -- We did not get another error\n if not ((i = -1) and -- We read everything, and high bits 0\n (or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then\n report fixed_pkg'instance_name\n & \"OREAD(ufixed): Vector truncated.\"\n severity error;\n else\n if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"OREAD(ufixed): Vector truncated\"\n severity warning;\n end if;\n valuex := to_ufixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n end if;\n end if;\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed;\n GOOD : out BOOLEAN) is\n constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_ufixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n OREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => false,\n smath => false);\n if (igood and -- We did not get another error\n (i = -1) and -- We read everything, and high bits 0\n (or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then\n valuex := to_ufixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n good := true;\n else\n good := false;\n end if;\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed) is\n constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_sfixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n OREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => true,\n smath => true);\n if igood then -- We did not get another error\n if not ((i = -1) and -- We read everything\n ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits\n or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or\n (slv(VALUE'high-lbv) = '1' and\n and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then\n report fixed_pkg'instance_name\n & \"OREAD(sfixed): Vector truncated.\"\n severity error;\n else\n if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"OREAD(sfixed): Vector truncated\"\n severity warning;\n end if;\n valuex := to_sfixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n end if;\n end if;\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed;\n GOOD : out BOOLEAN) is\n constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_sfixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n OREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => false,\n smath => true);\n if (igood -- We did not get another error\n and (i = -1) -- We read everything\n and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits\n or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or\n (slv(VALUE'high-lbv) = '1' and\n and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then\n valuex := to_sfixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n good := true;\n else\n good := false;\n end if;\n end procedure OREAD;\n\n -- hex read and write\n procedure hwrite (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_ufixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n begin -- Example 03.30\n write (L => L,\n VALUE => to_hstring (VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure hwrite;\n\n -- purpose: writes fixed point into a line\n procedure hwrite (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_sfixed; -- fixed point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n begin -- Example 03.30\n write (L => L,\n VALUE => to_hstring (VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure hwrite;\n\n -- purpose: Routines common to the OREAD routines\n procedure HREAD_common (\n L : inout LINE;\n slv : out STD_ULOGIC_VECTOR;\n igood : out BOOLEAN;\n idex : out INTEGER;\n constant bpoint : in INTEGER; -- binary point\n constant message : in BOOLEAN;\n constant smath : in BOOLEAN) is\n\n -- purpose: error message routine\n procedure errmes (\n constant mess : in STRING) is -- error message\n begin\n if message then\n if smath then\n report fixed_pkg'instance_name\n & \"HREAD(sfixed) \"\n & mess\n severity error;\n else\n report fixed_pkg'instance_name\n & \"HREAD(ufixed) \"\n & mess\n severity error;\n end if;\n end if;\n end procedure errmes;\n variable xgood : BOOLEAN;\n variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits\n variable c : CHARACTER;\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable founddot : BOOLEAN := false; -- found a dot.\n begin\n Skip_whitespace (L); \n if slv'length > 0 then\n i := slv'high;\n read (l, c, xgood);\n while i > 0 loop\n if xgood = false then\n errmes (\"Error: end of string encountered\");\n exit;\n elsif c = '_' then\n if i = slv'length then\n errmes (\"Error: String begins with an \"\"_\"\"\");\n xgood := false;\n exit;\n elsif lastu then\n errmes (\"Error: Two underscores detected in input string \"\"__\"\"\");\n xgood := false;\n exit;\n else\n lastu := true;\n end if;\n elsif (c = '.') then\n if (i + 1 /= bpoint) then\n errmes (\"encountered \"\".\"\" at wrong index\");\n xgood := false;\n exit;\n elsif i = slv'length then\n errmes (\"encounted a \"\".\"\" at the beginning of the line\");\n xgood := false;\n exit;\n elsif founddot then\n errmes (\"Two \"\".\"\" encounted in input string\");\n xgood := false;\n exit;\n end if;\n founddot := true;\n lastu := false;\n else\n Char2QuadBits(c, nybble, xgood, message);\n if not xgood then\n exit;\n end if;\n slv (i downto i-3) := nybble;\n i := i - 4;\n lastu := false;\n end if; \n if i > 0 then\n read (L, c, xgood);\n end if;\n end loop;\n idex := i;\n igood := xgood;\n else\n idex := -1;\n igood := true; -- read null string\n end if;\n end procedure HREAD_common;\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed) is\n constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_ufixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n HREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => false,\n smath => false);\n if igood then\n if not ((i = -1) and -- We read everything, and high bits 0\n (or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then\n report fixed_pkg'instance_name\n & \"HREAD(ufixed): Vector truncated.\"\n severity error;\n else\n if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"HREAD(ufixed): Vector truncated\"\n severity warning;\n end if;\n valuex := to_ufixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n end if;\n end if;\n end procedure HREAD;\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_ufixed;\n GOOD : out BOOLEAN) is\n constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_ufixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n HREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => false,\n smath => false);\n if (igood and -- We did not get another error\n (i = -1) and -- We read everything, and high bits 0\n (or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then\n valuex := to_ufixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n good := true;\n else\n good := false;\n end if;\n end procedure HREAD;\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed) is\n constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_sfixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n HREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => true,\n smath => true);\n if igood then -- We did not get another error\n if not ((i = -1) -- We read everything\n and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits\n or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or\n (slv(VALUE'high-lbv) = '1' and\n and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then\n report fixed_pkg'instance_name\n & \"HREAD(sfixed): Vector truncated.\"\n severity error;\n else\n if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then\n assert NO_WARNING\n report fixed_pkg'instance_name\n & \"HREAD(sfixed): Vector truncated\"\n severity warning;\n end if;\n valuex := to_sfixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n end if;\n end if;\n end procedure HREAD;\n\n procedure HREAD(L : inout LINE;\n VALUE : out UNRESOLVED_sfixed;\n GOOD : out BOOLEAN) is\n constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;\n constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;\n variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits\n variable valuex : UNRESOLVED_sfixed (hbv downto lbv);\n variable igood : BOOLEAN;\n variable i : INTEGER;\n begin\n VALUE := (VALUE'range => 'U');\n HREAD_common ( L => L,\n slv => slv,\n igood => igood,\n idex => i,\n bpoint => -lbv,\n message => false,\n smath => true);\n if (igood and -- We did not get another error\n (i = -1) and -- We read everything\n ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits\n or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or\n (slv(VALUE'high-lbv) = '1' and\n and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then\n valuex := to_sfixed (slv, hbv, lbv);\n VALUE := valuex (VALUE'range);\n good := true;\n else\n good := false;\n end if;\n end procedure HREAD;\n\n function to_string (value : UNRESOLVED_ufixed) return STRING is\n variable s : STRING(1 to value'length +1) := (others => ' ');\n variable subval : UNRESOLVED_ufixed (value'high downto -1);\n variable sindx : INTEGER;\n begin\n if value'length < 1 then\n return NUS;\n else\n if value'high < 0 then\n if value(value'high) = 'Z' then\n return to_string (resize (sfixed(value), 0, value'low));\n else\n return to_string (resize (value, 0, value'low));\n end if;\n elsif value'low >= 0 then\n if Is_X (value(value'low)) then\n subval := (others => value(value'low));\n subval (value'range) := value;\n return to_string(subval);\n else\n return to_string (resize (value, value'high, -1));\n end if;\n else\n sindx := 1;\n for i in value'high downto value'low loop\n if i = -1 then\n s(sindx) := '.';\n sindx := sindx + 1;\n end if;\n s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));\n sindx := sindx + 1;\n end loop;\n return s;\n end if;\n end if;\n end function to_string;\n\n function to_string (value : UNRESOLVED_sfixed) return STRING is\n variable s : STRING(1 to value'length + 1) := (others => ' ');\n variable subval : UNRESOLVED_sfixed (value'high downto -1);\n variable sindx : INTEGER;\n begin\n if value'length < 1 then\n return NUS;\n else\n if value'high < 0 then\n return to_string (resize (value, 0, value'low));\n elsif value'low >= 0 then\n if Is_X (value(value'low)) then\n subval := (others => value(value'low));\n subval (value'range) := value;\n return to_string(subval);\n else\n return to_string (resize (value, value'high, -1));\n end if;\n else\n sindx := 1;\n for i in value'high downto value'low loop\n if i = -1 then\n s(sindx) := '.';\n sindx := sindx + 1;\n end if;\n s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));\n sindx := sindx + 1;\n end loop;\n return s;\n end if;\n end if;\n end function to_string;\n\n function to_ostring (value : UNRESOLVED_ufixed) return STRING is\n constant lne : INTEGER := (-VALUE'low+2)/3;\n variable subval : UNRESOLVED_ufixed (value'high downto -3);\n variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);\n variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value'high < 0 then\n if value(value'high) = 'Z' then\n return to_ostring (resize (sfixed(value), 2, value'low));\n else\n return to_ostring (resize (value, 2, value'low));\n end if;\n elsif value'low >= 0 then\n if Is_X (value(value'low)) then\n subval := (others => value(value'low));\n subval (value'range) := value;\n return to_ostring(subval);\n else\n return to_ostring (resize (value, value'high, -3));\n end if;\n else\n slv := to_sulv (value);\n if Is_X (value (value'low)) then\n lpad := (others => value (value'low));\n else\n lpad := (others => '0');\n end if;\n return to_ostring(slv(slv'high downto slv'high-VALUE'high))\n & \".\"\n & to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);\n end if;\n end if;\n end function to_ostring;\n\n function to_hstring (value : UNRESOLVED_ufixed) return STRING is\n constant lne : INTEGER := (-VALUE'low+3)/4;\n variable subval : UNRESOLVED_ufixed (value'high downto -4);\n variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);\n variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value'high < 0 then\n if value(value'high) = 'Z' then\n return to_hstring (resize (sfixed(value), 3, value'low));\n else\n return to_hstring (resize (value, 3, value'low));\n end if;\n elsif value'low >= 0 then\n if Is_X (value(value'low)) then\n subval := (others => value(value'low));\n subval (value'range) := value;\n return to_hstring(subval);\n else\n return to_hstring (resize (value, value'high, -4));\n end if;\n else\n slv := to_sulv (value);\n if Is_X (value (value'low)) then\n lpad := (others => value(value'low));\n else\n lpad := (others => '0');\n end if;\n return to_hstring(slv(slv'high downto slv'high-VALUE'high))\n & \".\"\n & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);\n end if;\n end if;\n end function to_hstring;\n\n function to_ostring (value : UNRESOLVED_sfixed) return STRING is\n constant ne : INTEGER := ((value'high+1)+2)/3;\n variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);\n constant lne : INTEGER := (-VALUE'low+2)/3;\n variable subval : UNRESOLVED_sfixed (value'high downto -3);\n variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);\n variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value'high < 0 then\n return to_ostring (resize (value, 2, value'low));\n elsif value'low >= 0 then\n if Is_X (value(value'low)) then\n subval := (others => value(value'low));\n subval (value'range) := value;\n return to_ostring(subval);\n else\n return to_ostring (resize (value, value'high, -3));\n end if;\n else\n pad := (others => value(value'high));\n slv := to_sulv (value);\n if Is_X (value (value'low)) then\n lpad := (others => value(value'low));\n else\n lpad := (others => '0');\n end if;\n return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))\n & \".\"\n & to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);\n end if;\n end if;\n end function to_ostring;\n\n function to_hstring (value : UNRESOLVED_sfixed) return STRING is\n constant ne : INTEGER := ((value'high+1)+3)/4;\n variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);\n constant lne : INTEGER := (-VALUE'low+3)/4;\n variable subval : UNRESOLVED_sfixed (value'high downto -4);\n variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);\n variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value'high < 0 then\n return to_hstring (resize (value, 3, value'low));\n elsif value'low >= 0 then\n if Is_X (value(value'low)) then\n subval := (others => value(value'low));\n subval (value'range) := value;\n return to_hstring(subval);\n else\n return to_hstring (resize (value, value'high, -4));\n end if;\n else\n slv := to_sulv (value);\n pad := (others => value(value'high));\n if Is_X (value (value'low)) then\n lpad := (others => value(value'low));\n else\n lpad := (others => '0');\n end if;\n return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))\n & \".\"\n & to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);\n end if;\n end if;\n end function to_hstring;\n\n -- From string functions allow you to convert a string into a fixed\n -- point number. Example:\n -- signal uf1 : ufixed (3 downto -3);\n -- uf1 <= from_string (\"0110.100\", uf1'high, uf1'low); -- 6.5\n -- The \".\" is optional in this syntax, however it exist and is\n -- in the wrong location an error is produced. Overflow will\n -- result in saturation.\n\n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(bstring);\n read (L, result, good);\n deallocate (L);\n assert (good)\n report fixed_pkg'instance_name\n & \"from_string: Bad string \"& bstring severity error;\n return result;\n end function from_string;\n\n -- Octal and hex conversions work as follows:\n -- uf1 <= from_hstring (\"6.8\", 3, -3); -- 6.5 (bottom zeros dropped)\n -- uf1 <= from_ostring (\"06.4\", 3, -3); -- 6.5 (top zeros dropped)\n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(ostring);\n oread (L, result, good);\n deallocate (L);\n assert (good)\n report fixed_pkg'instance_name\n & \"from_ostring: Bad string \"& ostring severity error;\n return result;\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (left_index downto right_index);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(hstring);\n hread (L, result, good);\n deallocate (L);\n assert (good)\n report fixed_pkg'instance_name\n & \"from_hstring: Bad string \"& hstring severity error;\n return result;\n end function from_hstring;\n \n function from_string (\n bstring : STRING; -- binary string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(bstring);\n read (L, result, good);\n deallocate (L);\n assert (good)\n report fixed_pkg'instance_name\n & \"from_string: Bad string \"& bstring severity error;\n return result;\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(ostring);\n oread (L, result, good);\n deallocate (L);\n assert (good)\n report fixed_pkg'instance_name\n & \"from_ostring: Bad string \"& ostring severity error;\n return result;\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (left_index downto right_index);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(hstring);\n hread (L, result, good);\n deallocate (L);\n assert (good)\n report fixed_pkg'instance_name\n & \"from_hstring: Bad string \"& hstring severity error;\n return result;\n end function from_hstring;\n\n -- Same as above, \"size_res\" is used for it's range only.\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n begin\n return from_string (bstring, size_res'high, size_res'low);\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n begin\n return from_ostring (ostring, size_res'high, size_res'low);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_ufixed)\n return UNRESOLVED_ufixed is\n begin\n return from_hstring(hstring, size_res'high, size_res'low);\n end function from_hstring;\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return from_string (bstring, size_res'high, size_res'low);\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return from_ostring (ostring, size_res'high, size_res'low);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_sfixed)\n return UNRESOLVED_sfixed is\n begin\n return from_hstring (hstring, size_res'high, size_res'low);\n end function from_hstring;\n\n -- purpose: Calculate the string boundaries\n procedure calculate_string_boundry (\n arg : in STRING; -- input string\n left_index : out INTEGER; -- left\n right_index : out INTEGER) is -- right\n -- examples \"10001.111\" would return +4, -3\n -- \"07X.44\" would return +2, -2 (then the octal routine would multiply)\n -- \"A_B_._C\" would return +1, -1 (then the hex routine would multiply)\n alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range\n variable l, r : INTEGER; -- internal indexes\n variable founddot : BOOLEAN := false;\n begin\n if arg'length > 0 then\n l := xarg'high - 1;\n r := 0;\n for i in xarg'range loop\n if xarg(i) = '_' then\n if r = 0 then\n l := l - 1;\n else\n r := r + 1;\n end if;\n elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then\n report fixed_pkg'instance_name\n & \"Found a space in the input STRING \" & xarg\n severity error;\n elsif xarg(i) = '.' then\n if founddot then\n report fixed_pkg'instance_name\n & \"Found two binary points in input string \" & xarg\n severity error;\n else\n l := l - i;\n r := -i + 1;\n founddot := true;\n end if;\n end if;\n end loop;\n left_index := l;\n right_index := r;\n else\n left_index := 0;\n right_index := 0;\n end if;\n end procedure calculate_string_boundry;\n\n -- Direct conversion functions. Example:\n -- signal uf1 : ufixed (3 downto -3);\n -- uf1 <= from_string (\"0110.100\"); -- 6.5\n -- In this case the \".\" is not optional, and the size of\n -- the output must match exactly.\n function from_string (\n bstring : STRING) -- binary string\n return UNRESOLVED_ufixed is\n variable left_index, right_index : INTEGER;\n begin\n calculate_string_boundry (bstring, left_index, right_index);\n return from_string (bstring, left_index, right_index);\n end function from_string;\n\n -- Direct octal and hex conversion functions. In this case\n -- the string lengths must match. Example:\n -- signal sf1 := sfixed (5 downto -3);\n -- sf1 <= from_ostring (\"71.4\") -- -6.5\n function from_ostring (\n ostring : STRING) -- Octal string\n return UNRESOLVED_ufixed is\n variable left_index, right_index : INTEGER;\n begin\n calculate_string_boundry (ostring, left_index, right_index);\n return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING) -- hex string\n return UNRESOLVED_ufixed is\n variable left_index, right_index : INTEGER;\n begin\n calculate_string_boundry (hstring, left_index, right_index);\n return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);\n end function from_hstring;\n\n function from_string (\n bstring : STRING) -- binary string\n return UNRESOLVED_sfixed is\n variable left_index, right_index : INTEGER;\n begin\n calculate_string_boundry (bstring, left_index, right_index);\n return from_string (bstring, left_index, right_index);\n end function from_string;\n\n function from_ostring (\n ostring : STRING) -- Octal string\n return UNRESOLVED_sfixed is\n variable left_index, right_index : INTEGER;\n begin\n calculate_string_boundry (ostring, left_index, right_index);\n return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING) -- hex string\n return UNRESOLVED_sfixed is\n variable left_index, right_index : INTEGER;\n begin\n calculate_string_boundry (hstring, left_index, right_index);\n return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);\n end function from_hstring;\n-- pragma synthesis_on\n-- rtl_synthesis on\n -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these\n -- extra functions are needed for compatability.\n function to_ufixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_ufixed is\n begin\n return to_ufixed (\n arg => to_stdulogicvector (arg),\n left_index => left_index,\n right_index => right_index);\n end function to_ufixed;\n\n function to_ufixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_ufixed) -- for size only\n return UNRESOLVED_ufixed is\n begin\n return to_ufixed (\n arg => to_stdulogicvector (arg),\n size_res => size_res);\n end function to_ufixed;\n\n function to_sfixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n constant left_index : INTEGER;\n constant right_index : INTEGER)\n return UNRESOLVED_sfixed is\n begin\n return to_sfixed (\n arg => to_stdulogicvector (arg),\n left_index => left_index,\n right_index => right_index);\n end function to_sfixed;\n\n function to_sfixed (\n arg : STD_LOGIC_VECTOR; -- shifted vector\n size_res : UNRESOLVED_sfixed) -- for size only\n return UNRESOLVED_sfixed is\n begin\n return to_sfixed (\n arg => to_stdulogicvector (arg),\n size_res => size_res);\n end function to_sfixed;\n\n -- unsigned fixed point\n function to_UFix (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_ufixed is\n begin\n return to_UFix (\n arg => to_stdulogicvector (arg),\n width => width,\n fraction => fraction);\n end function to_UFix;\n\n -- signed fixed point\n function to_SFix (\n arg : STD_LOGIC_VECTOR;\n width : NATURAL; -- width of vector\n fraction : NATURAL) -- width of fraction\n return UNRESOLVED_sfixed is\n begin\n return to_SFix (\n arg => to_stdulogicvector (arg),\n width => width,\n fraction => fraction);\n end function to_SFix;\n\nend package body fixed_pkg;\n", "groundtruth": " when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n when 'B' | 'b' => result := x\"B\"; good := true;\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/fixed_synth.vhdl", "left_context": "-- Synthesis test for the fixed point math package\n-- This test is designed to be synthesizable and exercise much of the package.\n-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)\n-- --------------------------------------------------------------------\n-- modification history : Last Modified $Date: 2006-06-08 10:49:35-04 $\n-- Version $Id: fixed_synth.vhdl,v 1.1 2006-06-08 10:49:35-04 l435385 Exp $\n-- --------------------------------------------------------------------\n\n\nlibrary ieee, ieee_proposed;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee_proposed.fixed_float_types.all;\nuse ieee_proposed.fixed_pkg.all;\nentity fixed_synth is\n \n port (\n in1, in2 : in STD_LOGIC_VECTOR (15 downto 0); -- inputs\n out1 : out STD_LOGIC_VECTOR (15 downto 0); -- output\n cmd : in STD_LOGIC_VECTOR (3 downto 0);\n clk, rst_n : in STD_ULOGIC); -- clk and reset\n\nend entity fixed_synth;\n\narchitecture rtl of fixed_synth is\n\n subtype sfixed7 is sfixed (3 downto -3); -- 7 bit\n subtype sfixed16 is sfixed (7 downto -8); -- 16 bit\n type cmd_type is array (1 to 15) of STD_ULOGIC_VECTOR (cmd'range); -- cmd\n signal cmdarray : cmd_type; -- command pipeline\n type cry_type is array (0 to 4) of sfixed16; -- arrays\n signal outarray0, outarray1, outarray2, outarray3, outarray4,\n outarray5, outarray6, outarray7, outarray8, outarray9, outarray10,\n outarray11, outarray12, outarray13, outarray14, outarray15 : sfixed16;\n signal in1reg3, in2reg3 : sfixed16; -- register stages\nbegin -- architecture rtl\n\n -- purpose: \"0000\" test the \"+\" operator\n cmd0reg : process (clk, rst_n) is\n variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto\n SFixed_low(7, -8, '+', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray0 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray0 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n in1pin2 := in1array(3) + in2array(3);\n outarray(0) := resize (in1pin2, outarray(0));\n end if;\n end process cmd0reg;\n\n -- purpose: \"0001\" test the \"-\" operator\n cmd1reg : process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n variable in1min2 : sfixed (SFixed_high(in1array(0), '-', in2array(0)) downto\n SFixed_low(in1array(0), '-', in2array(0)));\n-- variable in1min2 : sfixed (SFixed_high(7, -8, '-', 7, -8) downto\n-- SFixed_low(7, -8, '-', 7, -8));\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray1 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray1 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n in1min2 := in1array(3) - in2array(3);\n outarray(0) := resize (in1min2, outarray(0));\n end if;\n end process cmd1reg;\n\n -- purpose: \"0010\" test the \"*\" operator\n cmd2reg : process (clk, rst_n) is\n-- variable in1min2 : sfixed (SFixed_high(in1reg3, '*', in2reg3) downto\n-- SFixed_low(in1reg3, '*', in2reg3));\n variable in1min2 : sfixed (SFixed_high(7, -8, '*', 7, -8) downto\n SFixed_low(7, -8, '*', 7, -8));\n", "right_context": " if rst_n = '0' then -- asynchronous reset (active low)\n outarray2 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray2 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n in1min2 := in1array(3) * in2array(3);\n outarray(0) := resize (in1min2, outarray(0));\n end if;\n end process cmd2reg;\n\n -- purpose: \"0011\" test the \"/\" operator\n cmd3reg : process (clk, rst_n) is\n variable in1min2 : sfixed (SFixed_high(in1reg3'high, in1reg3'low,\n '/', in2reg3'high, in2reg3'low)\n downto\n SFixed_low(in1reg3'high, in1reg3'low,\n '/', in2reg3'high, in2reg3'low));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd3reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray3 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := to_sfixed(1, in2array(0));\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray3 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n if (in2reg3 = 0) then\n in2array(0) := to_sfixed(1.0, in2array(0));\n else\n in2array(0) := in2reg3;\n end if;\n in1min2 := in1array(3) / in2array(3);\n outarray(0) := resize (in1min2, outarray(0));\n end if;\n end process cmd3reg;\n\n -- purpose: \"0100\" test the \"+\" operator\n cmd4reg : process (clk, rst_n) is\n variable in1pin2 : ufixed (uFixed_high(7, -8, '+', 7, -8) downto\n uFixed_low(7, -8, '+', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray4 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray4 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n in1pin2 := ufixed(in1array(3)) + ufixed(in2array(3));\n outarray(0) := sfixed (resize (in1pin2, outarray4'high, outarray4'low));\n end if;\n end process cmd4reg;\n\n -- purpose: \"0101\" test the \"-\" operator\n cmd5reg : process (clk, rst_n) is\n variable in1min2 : ufixed (uFixed_high(7, -8, '-', 7, -8) downto\n uFixed_low(7, -8, '-', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray5 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray5 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n in1min2 := ufixed(in1array(3)) - ufixed(in2array(3));\n outarray(0) := sfixed(resize (in1min2, outarray5'high, outarray5'low));\n end if;\n end process cmd5reg;\n\n -- purpose: \"0110\" test the \"*\" operator\n cmd6reg : process (clk, rst_n) is\n variable in1min2 : ufixed (uFixed_high(7, -8, '*', 7, -8) downto\n uFixed_low(7, -8, '*', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray6 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray6 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n in1min2 := ufixed(in1array(3)) * ufixed(in2array(3));\n outarray(0) := sfixed(resize (in1min2, outarray6'high, outarray6'low));\n end if;\n end process cmd6reg;\n\n -- purpose: \"0111\" test the \"/\" operator\n cmd7reg : process (clk, rst_n) is\n variable in1min2 : ufixed (uFixed_high(7, -8, '/', 7, -8) downto\n uFixed_low(7, -8, '/', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray7 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := sfixed(to_ufixed(1, in2reg3'high, in2reg3'low));\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray7 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n if (in2reg3 = 0) then\n in2array(0) := sfixed(to_ufixed(1.0, in2reg3'high, in2reg3'low));\n else\n in2array(0) := in2reg3;\n end if;\n in1min2 := ufixed(in1array(3)) / ufixed(in2array(3));\n outarray(0) := sfixed(resize (in1min2, outarray7'high, outarray7'low));\n end if;\n end process cmd7reg;\n\n -- purpose: \"1000\" test the resize test\n cmd8reg : process (clk, rst_n) is\n variable tmpfp71, tmpfp72 : sfixed7; -- 8 bit fp number\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray8 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray8 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n -- Resize test Convert inputs into two 8 bit numbers\n tmpfp71 := resize (in1array(3), tmpfp71'high, tmpfp71'low,\n fixed_wrap, fixed_truncate);\n tmpfp72 := resize (in2array(3), tmpfp72'high, tmpfp72'low,\n fixed_saturate, fixed_round);\n outarray(0) := (others => '0');\n fx1 : for i in tmpfp71'range loop\n outarray(0)(i+4) := tmpfp71(i);\n end loop fx1;\n fx2 : for i in tmpfp72'range loop\n outarray(0)(i-4) := tmpfp72(i);\n end loop fx2;\n end if;\n end process cmd8reg;\n\n -- purpose: \"1001\" test the to_signed/unsigned test\n cmd9reg : process (clk, rst_n) is\n variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp\n variable tmpsig : SIGNED (7 downto 0); -- signed number\n variable tmpuns : UNSIGNED (15 downto 0); -- unsigned number\n variable tmpint : INTEGER;\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray9 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray9 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));\n if (tmp = \"00\") then\n -- Signed to sfixed and back\n tmpsig := to_signed (in1array(3), tmpsig'length);\n outarray(0) := to_sfixed (tmpsig, outarray(0));\n elsif (tmp = \"01\") then\n -- unsigned to ufixed and back\n tmpuns := to_unsigned (ufixed(in1array(3)), tmpuns'length);\n outarray(0) := sfixed(to_ufixed (tmpuns, outarray(0)'high,\n outarray(0)'low));\n elsif (tmp = \"10\") then\n tmpint := to_integer (in1array(3));\n outarray(0) := to_sfixed (tmpint, outarray(0));\n else\n tmpint := to_integer (ufixed(in1array(3)));\n outarray(0) := sfixed(to_ufixed (tmpint, outarray(0)'high,\n outarray(0)'low));\n\n end if;\n end if;\n end process cmd9reg;\n\n -- purpose: \"1010\" test the reciprocal, abs, - test\n cmd10reg : process (clk, rst_n) is\n variable tmp : STD_LOGIC_VECTOR (1 downto 0); -- temp\n variable in1recip : sfixed (-in1reg3'low+1 downto -in1reg3'high);\n variable uin1recip : ufixed (-in1reg3'low downto -in1reg3'high-1);\n variable in1pin2 : sfixed (SFixed_high(7, -8, '+', 7, -8) downto\n SFixed_low(7, -8, '+', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray10 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := to_sfixed(1, in1reg3);\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray10 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n if (in1reg3 = 0) then\n in1array(0) := to_sfixed(1, in1reg3);\n else\n in1array(0) := in1reg3;\n end if;\n in2array(0) := in2reg3;\n tmp := to_slv (in2array(3)(in2reg3'high downto in2reg3'high-1));\n if (tmp = \"00\") then\n in1recip := reciprocal (in1array(3));\n outarray(0) := resize (in1recip, outarray(0)'high,\n outarray(0)'low);\n elsif (tmp = \"01\") then\n uin1recip := reciprocal (ufixed(in1array(3)));\n outarray(0) := sfixed(resize (uin1recip, outarray(0)'high,\n outarray(0)'low)); \n elsif (tmp = \"10\") then\n -- abs\n in1pin2 := abs(in1array(3));\n outarray(0) := resize (in1pin2,\n outarray(0)'high,\n outarray(0)'low);\n else\n -- -\n in1pin2 := - in1array(3);\n outarray(0) := resize (in1pin2,\n outarray(0)'high,\n outarray(0)'low);\n end if;\n end if;\n end process cmd10reg;\n\n -- purpose: \"1011\" test the mod operator\n cmd11reg : process (clk, rst_n) is\n variable in1min2 : sfixed (SFixed_high(7, -8, 'M', 7, -8) downto\n SFixed_low(7, -8, 'm', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray11 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := to_sfixed(1, in2array(0));\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray11 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n if (in2reg3 = 0) then\n in2array(0) := to_sfixed(1, in2array(0));\n else\n in2array(0) := in2reg3;\n end if;\n in1min2 := in1array(3) mod in2array(3);\n outarray(0) := resize (in1min2, outarray(0));\n end if;\n end process cmd11reg;\n\n -- purpose: \"1100\" test the rem operator\n cmd12reg : process (clk, rst_n) is\n variable in1min2 : sfixed (SFixed_high(7, -8, 'R', 7, -8) downto\n SFixed_low(7, -8, 'r', 7, -8));\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray12 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := to_sfixed(1, in2array(0));\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray12 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n if (in2reg3 = 0) then\n in2array(0) := to_sfixed(1, in2array(0));\n else\n in2array(0) := in2reg3;\n end if;\n in1min2 := in1array(3) rem in2array(3);\n outarray(0) := resize (in1min2, outarray(0));\n end if;\n end process cmd12reg;\n\n -- purpose: \"1101\" test the srl operator\n cmd13reg : process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray13 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray13 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n outarray(0) := in1array(3) srl to_integer(in2array(3));\n end if;\n end process cmd13reg;\n\n -- purpose: \"1110\" test the sra operator\n cmd14reg : process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray14 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray14 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n outarray(0) := in1array(3) sra to_integer(in2array(3));\n end if;\n end process cmd14reg;\n\n -- purpose: \"1111\" test the sra operator\n cmd15reg : process (clk, rst_n) is\n constant match_data : sfixed16 := \"01HL----10HL----\"; -- for ?= command\n variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n begin -- process cmd0reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outarray15 <= (others => '0');\n jrloop : for j in 0 to 4 loop\n outarray (j) := (others => '0');\n in1array (j) := (others => '0');\n in2array (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outarray15 <= outarray(4);\n jcloop : for j in 4 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n j1loop : for j in 3 downto 1 loop\n in1array (j) := in1array(j-1);\n end loop j1loop;\n j2loop : for j in 3 downto 1 loop\n in2array (j) := in2array(j-1);\n end loop j2loop;\n in1array(0) := in1reg3;\n in2array(0) := in2reg3;\n -- compare test\n if (in1array(3) = in2array(3)) then\n outarray(0)(-8) := '1';\n else\n outarray(0)(-8) := '0';\n end if;\n if (in1array(3) /= in2array(3)) then\n outarray(0)(-7) := '1';\n else\n outarray(0)(-7) := '0';\n end if;\n if (in1array(3) < in2array(3)) then\n outarray(0)(-6) := '1';\n else\n outarray(0)(-6) := '0';\n end if;\n if (in1array(3) > in2array(3)) then\n outarray(0)(-5) := '1';\n else\n outarray(0)(-5) := '0';\n end if;\n if (in1array(3) <= in2array(3)) then\n outarray(0)(-4) := '1';\n else\n outarray(0)(-4) := '0';\n end if;\n if (in1array(3) >= in2array(3)) then\n outarray(0)(-3) := '1';\n else\n outarray(0)(-3) := '0';\n end if;\n if (in1array(3) = 45) then\n outarray(0)(-2) := '1';\n else\n outarray(0)(-2) := '0';\n end if;\n if (in1array(3) = 3.125) then\n outarray(0)(-1) := '1';\n else\n outarray(0)(-1) := '0';\n end if;\n -- add integer and real\n outarray(0)(0) := \\?=\\ (in1array(3), in2array(3) + 45);\n if (in1array(3) = in2array(3) + 3.125) then\n outarray(0)(1) := '1';\n else\n outarray(0)(1) := '0';\n end if;\n if (std_match (in1array(3), match_data)) then\n outarray(0)(2) := '1';\n else\n outarray(0)(2) := '0';\n end if;\n outarray(0)(3) := nor_reduce (in1array(3) or in2array(3));\n outarray(0)(4) := xnor_reduce (in1array(3) xor in2array(3));\n outarray(0)(5) := nand_reduce (not in1array(3));\n outarray(0)(6) := or_reduce ('1' and ufixed(in1array(3)));\n if find_leftmost(in1array(3), '1') = 3 then\n outarray(0)(7) := '1';\n else\n outarray(0)(7) := '0';\n end if;\n end if;\n end process cmd15reg;\n\n -- purpose: register the inputs and the outputs\n -- type : sequential\n -- inputs : clk, rst_n, in1, in2\n -- outputs: out1\n cmdreg : process (clk, rst_n) is\n variable outreg : sfixed16; -- register stages\n variable in1reg, in2reg : sfixed16; -- register stages\n variable in1reg2, in2reg2 : sfixed16; -- register stages\n begin -- process mulreg\n if rst_n = '0' then -- asynchronous reset (active low)\n in1reg := (others => '0');\n in2reg := (others => '0');\n in1reg2 := (others => '0');\n in2reg2 := (others => '0');\n in1reg3 <= (others => '0');\n in2reg3 <= (others => '0');\n out1 <= (others => '0');\n outreg := (others => '0');\n rcloop : for i in 1 to 15 loop\n cmdarray (i) <= (others => '0');\n end loop rcloop;\n elsif rising_edge(clk) then -- rising clock edge\n out1 <= to_slv (outreg);\n outregc : case cmdarray (13) is\n when \"0000\" => outreg := outarray0;\n when \"0001\" => outreg := outarray1;\n when \"0010\" => outreg := outarray2;\n when \"0011\" => outreg := outarray3;\n when \"0100\" => outreg := outarray4;\n when \"0101\" => outreg := outarray5;\n when \"0110\" => outreg := outarray6;\n when \"0111\" => outreg := outarray7;\n when \"1000\" => outreg := outarray8;\n when \"1001\" => outreg := outarray9;\n when \"1010\" => outreg := outarray10;\n when \"1011\" => outreg := outarray11;\n when \"1100\" => outreg := outarray12;\n when \"1101\" => outreg := outarray13;\n when \"1110\" => outreg := outarray14;\n when \"1111\" => outreg := outarray15;\n when others => null;\n end case outregc;\n cmdpipe : for i in 15 downto 3 loop\n cmdarray (i) <= cmdarray (i-1);\n end loop cmdpipe;\n cmdarray (2) <= STD_ULOGIC_VECTOR(cmd);\n in1reg3 <= in1reg2;\n in2reg3 <= in2reg2;\n in1reg2 := in1reg;\n in2reg2 := in2reg;\n in1reg := to_sfixed (in1, in1reg);\n in2reg := to_sfixed (in2, in2reg);\n end if;\n end process cmdreg;\n\nend architecture rtl;\n", "groundtruth": " variable outarray : cry_type; -- array for output\n variable in1array, in2array : cry_type; -- array for input\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/float_noround_pkg.vhdl", "left_context": "-- --------------------------------------------------------------------\n-- \"float_noround_pkg\" package is a copy of \"float_pkg\" with several of\n-- the initial constants changed. This was done to make synthesis more\n-- practical. In VHDL-2008, this package would be equivalent to:\n-------------------------------------------------------------------------------\n--library ieee;\n--use ieee.fixed_pkg.all;\n--package float_noround_pkg is new ieee.float_generic_pkg\n-- generic map (\n-- float_round_style => round_zero,\n-- float_denormalize => false,\n-- float_check_error => false,\n-- float_guard_bits => 0,\n-- NO_WARNING => true);\n-------------------------------------------------------------------------------\n-- I also recommend the following:\n-- subtype float26 : float (8 downto -17);\n-- This subtype will cost you 6 bits of precision, but with architecture\n-- that have 18 bit built in ALU blocks it will save a great deal of area.\n--\n-- Please see the documentation for the floating point package.\n-- This package should be compiled into \"ieee_proposed\" and used as follows:\n-- use ieee.std_logic_1164.all;\n-- use ieee.numeric_std.all;\n-- use ieee_proposed.fixed_float_types.all;\n-- use ieee_proposed.fixed_pkg.all;\n-- use ieee_proposed.float_noround_pkg.all;\n--\n-- This verison is designed to work with the VHDL-93 compilers. Please\n-- note the \"%%%\" comments. These are where we diverge from the\n-- VHDL-200X LRM.\n--\n-- --------------------------------------------------------------------\n-- Version : $Revision: 2.0 $\n-- Date : $Date: 2009/01/27 20:45:30 $\n-- --------------------------------------------------------------------\n\nuse STD.TEXTIO.all;\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\nuse IEEE.NUMERIC_STD.all;\nlibrary ieee_proposed;\nuse ieee_proposed.fixed_float_types.all;\nuse ieee_proposed.fixed_pkg.all;\n\npackage float_noround_pkg is\n-- generic (\n -- Defaults for sizing routines, when you do a \"to_float\" this will be\n -- the default size. Example float32 would be 8 and 23 (8 downto -23)\n constant float_exponent_width : NATURAL := 8;\n constant float_fraction_width : NATURAL := 17;\n -- Rounding algorithm, \"round_nearest\" is default, other valid values\n -- are \"round_zero\" (truncation), \"round_inf\" (round up), and\n -- \"round_neginf\" (round down)\n constant float_round_style : round_type := round_zero;\n -- Denormal numbers (very small numbers near zero) true or false\n constant float_denormalize : BOOLEAN := false;\n -- Turns on NAN processing (invalid numbers and overflow) true of false\n constant float_check_error : BOOLEAN := false;\n -- Guard bits are added to the bottom of every operation for rounding.\n -- any natural number (including 0) are valid.\n constant float_guard_bits : NATURAL := 0;\n -- If TRUE, then turn off warnings on \"X\" propagation\n constant no_warning : BOOLEAN := (true\n );\n\n -- Author David Bishop (dbishop@vhdl.org)\n\n -- Note that the size of the vector is not defined here, but in\n -- the package which calls this one.\n type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type\n subtype U_float is UNRESOLVED_float;\n\n subtype float is UNRESOLVED_float;\n -----------------------------------------------------------------------------\n -- Use the float type to define your own floating point numbers.\n -- There must be a negative index or the packages will error out.\n -- Minimum supported is \"subtype float7 is float (3 downto -3);\"\n -- \"subtype float16 is float (6 downto -9);\" is probably the smallest\n -- practical one to use.\n -----------------------------------------------------------------------------\n\n -- IEEE 754 single precision\n subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);\n alias U_float32 is UNRESOLVED_float32;\n subtype float32 is float (8 downto -23);\n -----------------------------------------------------------------------------\n -- IEEE-754 single precision floating point. This is a \"float\"\n -- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and\n -- the fraction is 23 bits wide. This format can hold roughly 7 decimal\n -- digits. Infinity is 2**127 = 1.7E38 in this number system.\n -- The bit representation is as follows:\n -- 1 09876543 21098765432109876543210\n -- 8 76543210 12345678901234567890123\n -- 0 00000000 00000000000000000000000\n -- 8 7 0 -1 -23\n -- +/- exp. fraction\n -----------------------------------------------------------------------------\n\n -- IEEE 754 double precision\n subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);\n alias U_float64 is UNRESOLVED_float64;\n subtype float64 is float (11 downto -52);\n -----------------------------------------------------------------------------\n -- IEEE-754 double precision floating point. This is a \"double float\"\n -- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and\n -- the fraction is 52 bits wide. This format can hold roughly 15 decimal\n -- digits. Infinity is 2**2047 in this number system.\n -- The bit representation is as follows:\n -- 3 21098765432 1098765432109876543210987654321098765432109876543210\n -- 1 09876543210 1234567890123456789012345678901234567890123456789012\n -- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF\n -- 11 10 0 -1 -52\n -- +/- exponent fraction\n -----------------------------------------------------------------------------\n\n -- IEEE 854 & C extended precision\n subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);\n alias U_float128 is UNRESOLVED_float128;\n subtype float128 is float (15 downto -112);\n -----------------------------------------------------------------------------\n -- The 128 bit floating point number is \"long double\" in C (on\n -- some systems this is a 70 bit floating point number) and FLOAT*32\n -- in Fortran. The exponent is 15 bits wide and the fraction is 112\n -- bits wide. This number can handle approximately 33 decimal digits.\n -- Infinity is 2**32,767 in this number system.\n -----------------------------------------------------------------------------\n\n -- purpose: Checks for a valid floating point number\n type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)\n quiet_nan, -- Quiet NaN (C FP_NAN)\n neg_inf, -- Negative infinity (C FP_INFINITE)\n neg_normal, -- negative normalized nonzero\n neg_denormal, -- negative denormalized (FP_SUBNORMAL)\n neg_zero, -- -0 (C FP_ZERO)\n pos_zero, -- +0 (C FP_ZERO)\n pos_denormal, -- Positive denormalized (FP_SUBNORMAL)\n pos_normal, -- positive normalized nonzero\n pos_inf, -- positive infinity\n isx); -- at least one input is unknown\n\n -- This deferred constant will tell you if the package body is synthesizable\n -- or implemented as real numbers.\n constant fphdlsynth_or_real : BOOLEAN; -- deferred constant\n\n -- Returns the class which X falls into\n function Classfp (\n x : UNRESOLVED_float; -- floating point input\n check_error : BOOLEAN := float_check_error) -- check for errors\n return valid_fpstate;\n\n -- Arithmetic functions, these operators do not require parameters.\n function \"abs\" (arg : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (arg : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- These allows the base math functions to use the default values\n -- of their parameters. Thus they do full IEEE floating point.\n\n function \"+\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"*\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"/\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"rem\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"mod\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- Basic parameter list\n -- round_style - Selects the rounding algorithm to use\n -- guard - extra bits added to the end if the operation to add precision\n -- check_error - When \"false\" turns off NAN and overflow checks\n -- denormalize - When \"false\" turns off denormal number processing\n\n function add (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function subtract (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function multiply (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function divide (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function remainder (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function modulo (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- reciprocal\n function reciprocal (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function dividebyp2 (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- Multiply accumulate result = l*r + c\n function mac (\n l, r, c : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- Square root (all 754 based implementations need this)\n function sqrt (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style;\n constant guard : NATURAL := float_guard_bits;\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float;\n\n function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;\n\n -----------------------------------------------------------------------------\n -- compare functions\n -- =, /=, >=, <=, <, >, maximum, minimum\n\n function eq ( -- equal =\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function ne ( -- not equal /=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function lt ( -- less than <\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function gt ( -- greater than >\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function le ( -- less than or equal to <=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function ge ( -- greater than or equal to >=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n -- Need to overload the default versions of these\n function \"=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \"/=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \">=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \"<=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \">\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \"<\" (l, r : UNRESOLVED_float) return BOOLEAN;\n\n function \\?=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?/=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n\n function std_match (l, r : UNRESOLVED_float) return BOOLEAN;\n function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)\n return INTEGER;\n function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)\n return INTEGER;\n function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- conversion functions\n -- Converts one floating point number into another.\n\n function resize (\n arg : UNRESOLVED_float; -- Floating point input\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function resize (\n arg : UNRESOLVED_float; -- Floating point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function to_float32 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float32;\n\n function to_float64 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float64;\n\n function to_float128 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float128;\n\n -- Converts an fp into an SLV (needed for synthesis)\n function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;\n alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];\n alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];\n\n -- Converts an fp into an std_ulogic_vector (sulv)\n function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;\n alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];\n alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];\n\n -- std_ulogic_vector to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float;\n\n -- Integer to float\n function to_float (\n arg : INTEGER;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- real to float\n function to_float (\n arg : REAL;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- unsigned to float\n function to_float (\n arg : UNSIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- signed to float\n function to_float (\n arg : SIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- unsigned fixed point to float\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n constant exponent_width : NATURAL := float_exponent_width; -- width of exponent\n constant fraction_width : NATURAL := float_fraction_width; -- width of fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float;\n\n -- signed fixed point to float\n function to_float (\n arg : UNRESOLVED_sfixed;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float;\n\n -- size_res functions\n -- Integer to float\n function to_float (\n arg : INTEGER;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- real to float\n function to_float (\n arg : REAL;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- unsigned to float\n function to_float (\n arg : UNSIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- signed to float\n function to_float (\n arg : SIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- sulv to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float;\n\n -- unsigned fixed point to float\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float;\n\n -- signed fixed point to float\n function to_float (\n arg : UNRESOLVED_sfixed;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float;\n\n -- float to unsigned\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED;\n\n -- float to signed\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED;\n\n -- purpose: Converts a float to unsigned fixed point\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed;\n\n -- float to signed fixed point\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed;\n\n -- size_res versions\n -- float to unsigned\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n size_res : UNSIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED;\n\n -- float to signed\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n size_res : SIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED;\n\n -- purpose: Converts a float to unsigned fixed point\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_ufixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed;\n\n -- float to signed fixed point\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_sfixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed;\n\n -- float to real\n function to_real (\n arg : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return REAL;\n\n -- float to integer\n function to_integer (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return INTEGER;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;\n function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;\n\n -- Maps metalogical values\n function to_01 (\n arg : UNRESOLVED_float; -- floating point input\n XMAP : STD_LOGIC := '0')\n return UNRESOLVED_float;\n\n function Is_X (arg : UNRESOLVED_float) return BOOLEAN;\n function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;\n function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;\n function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- These two procedures were copied out of the body because they proved\n -- very useful for vendor specific algorithm development\n -- Break_number converts a floating point number into it's parts\n -- Exponent is biased by -1\n\n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out UNSIGNED;\n expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!\n sign : out STD_ULOGIC);\n\n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out ufixed; -- a number between 1.0 and 2.0\n expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!\n sign : out STD_ULOGIC);\n\n -- Normalize takes a fraction and and exponent and converts them into\n -- a floating point number. Does the shifting and the rounding.\n -- Exponent is assumed to be biased by -1\n\n function normalize (\n fract : UNSIGNED; -- fraction, unnormalized\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n -- Exponent is assumed to be biased by -1\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n function normalize (\n fract : UNSIGNED; -- unsigned\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n -- Exponent is assumed to be biased by -1\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n -- overloaded versions\n function \"+\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"+\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"+\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"+\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"-\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"-\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"*\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"*\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"*\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"*\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"/\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"/\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"/\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"/\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"rem\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"rem\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"rem\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"rem\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"mod\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"mod\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"mod\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"mod\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- overloaded compare functions\n function \"=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \">\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"/=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \">=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"<=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \">\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"<\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \">\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \"/=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \">=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \"<=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \">\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \"<\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \\?=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?/=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?/=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n -- minimum and maximum overloads\n function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n\n function \"not\" (l : UNRESOLVED_float) return UNRESOLVED_float;\n function \"and\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"or\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"nand\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"nor\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"xor\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"xnor\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"and\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"or\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"or\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"nand\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"nand\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"nor\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"nor\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"xor\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"xor\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"xnor\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"xnor\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n -- Reduction operators, same as numeric_std functions\n function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n\n -- Note: \"sla\", \"sra\", \"sll\", \"slr\", \"rol\" and \"ror\" not implemented.\n\n -----------------------------------------------------------------------------\n -- Recommended Functions from the IEEE 754 Appendix\n -----------------------------------------------------------------------------\n\n -- returns x with the sign of y.\n function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : INTEGER; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : SIGNED; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- returns the unbiased exponent of x\n function Logb (x : UNRESOLVED_float) return INTEGER;\n function Logb (x : UNRESOLVED_float) return SIGNED;\n\n -- returns the next representable neighbor of x in the direction toward y\n function Nextafter (\n x, y : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float;\n\n -- Returns TRUE if X is unordered with Y.\n function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;\n function Finite (x : UNRESOLVED_float) return BOOLEAN;\n function Isnan (x : UNRESOLVED_float) return BOOLEAN;\n\n -- Function to return constants.\n function zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function nanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function qnanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function pos_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function neg_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function neg_zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n -- size_res versions\n function zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function nanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function qnanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function pos_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function neg_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function neg_zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n\n -- ===========================================================================\n -- string and textio Functions\n -- ===========================================================================\n-- rtl_synthesis off\n-- pragma synthesis_off\n -- writes S:EEEE:FFFFFFFF\n procedure WRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0); -- width of field\n\n -- Reads SEEEEFFFFFFFF, \".\" and \":\" are ignored\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;\n GOOD : out BOOLEAN);\n\n alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];\n alias BREAD is READ [LINE, UNRESOLVED_float];\n alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];\n alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];\n alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];\n alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];\n\n procedure OWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0); -- width of field\n\n -- Octal read with padding, no separators used\n procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);\n procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;\n GOOD : out BOOLEAN);\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];\n alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];\n\n -- Hex write with padding, no separators\n procedure HWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0); -- width of field\n\n -- Hex read with padding, no separators used\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;\n GOOD : out BOOLEAN);\n alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];\n alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];\n alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];\n\n -- returns \"S:EEEE:FFFFFFFF\"\n function to_string (value : UNRESOLVED_float) return STRING;\n alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];\n alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];\n\n -- Returns a HEX string, with padding\n function to_hstring (value : UNRESOLVED_float) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];\n\n -- Returns and octal string, with padding\n function to_ostring (value : UNRESOLVED_float) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];\n\n function from_string (\n bstring : STRING; -- binary string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float;\n alias from_bstring is from_string [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n alias from_binary_string is from_string [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n function from_ostring (\n ostring : STRING; -- Octal string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float;\n alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float;\n alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float;\n alias from_bstring is from_string [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n alias from_binary_string is from_string [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float;\n alias from_octal_string is from_ostring [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float;\n alias from_hex_string is from_hstring [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n-- rtl_synthesis on\n-- pragma synthesis_on\n -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these\n -- extra functions are needed for compatability.\n function to_float (\n arg : STD_LOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float;\n\n function to_float (\n arg : STD_LOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_LOGIC_VECTOR;\n function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;\n\nend package float_noround_pkg;\n-------------------------------------------------------------------------------\n-- Proposed package body for the VHDL-200x-FT float_pkg package\n-- This version is optimized for Synthesis, and not for simulation.\n-- Note that there are functional differences between the synthesis and\n-- simulation packages bodies. The Synthesis version is preferred.\n-- This package body supplies a recommended implementation of these functions\n-- Version : $Revision: 2.0 $\n-- Date : $Date: 2009/01/27 20:45:30 $\n--\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n-------------------------------------------------------------------------------\n\npackage body float_noround_pkg is\n\n -- Author David Bishop (dbishop@vhdl.org)\n -----------------------------------------------------------------------------\n -- type declarations\n -----------------------------------------------------------------------------\n\n -- This deferred constant will tell you if the package body is synthesizable\n -- or implemented as real numbers, set to \"true\" if synthesizable.\n constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant\n\n -- types of boundary conditions\n type boundary_type is (normal, infinity, zero, denormal);\n\n -- null range array constant\n constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');\n constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');\n\n -- %%% Replicated functions\n -- These functions are replicated so that we don't need to reference the new\n -- 2006 package std.standard, std_logic_1164 and numeric_std.\n function maximum (\n l, r : INTEGER) -- inputs\n return INTEGER is\n begin -- function max\n if l > r then return l;\n else return r;\n end if;\n end function maximum;\n\n function minimum (\n l, r : INTEGER) -- inputs\n return INTEGER is\n begin -- function min\n if l > r then return r;\n else return l;\n end if;\n end function minimum;\n\n function or_reduce (arg : STD_ULOGIC_VECTOR)\n return STD_LOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC;\n begin\n if (arg'length < 1) then -- In the case of a NULL range\n Result := '0';\n else\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := or_reduce (BUS_int (BUS_int'left downto Half));\n Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper or Lower;\n end if;\n end if;\n return Result;\n end function or_reduce;\n\n function or_reduce (arg : UNSIGNED)\n return STD_ULOGIC is\n begin\n return or_reduce (STD_ULOGIC_VECTOR (arg));\n end function or_reduce;\n\n function or_reduce (arg : SIGNED)\n return STD_ULOGIC is\n begin\n return or_reduce (STD_ULOGIC_VECTOR (arg));\n end function or_reduce;\n\n function or_reduce (arg : STD_LOGIC_VECTOR)\n return STD_ULOGIC is\n begin\n return or_reduce (STD_ULOGIC_VECTOR (arg));\n end function or_reduce;\n\n -- purpose: AND all of the bits in a vector together\n -- This is a copy of the proposed \"and_reduce\" from 1076.3\n function and_reduce (arg : STD_ULOGIC_VECTOR)\n return STD_LOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC;\n begin\n if (arg'length < 1) then -- In the case of a NULL range\n Result := '1';\n else\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := and_reduce (BUS_int (BUS_int'left downto Half));\n Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper and Lower;\n end if;\n end if;\n return Result;\n end function and_reduce;\n\n function and_reduce (arg : UNSIGNED)\n return STD_ULOGIC is\n begin\n return and_reduce (STD_ULOGIC_VECTOR (arg));\n end function and_reduce;\n\n function and_reduce (arg : SIGNED)\n return STD_ULOGIC is\n begin\n return and_reduce (STD_ULOGIC_VECTOR (arg));\n end function and_reduce;\n\n function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range\n begin\n if (arg'length >= 1) then\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := xor_reduce (BUS_int (BUS_int'left downto Half));\n Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper xor Lower;\n end if;\n end if;\n return Result;\n end function xor_reduce;\n\n function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not and_reduce (arg);\n end function nand_reduce;\n\n function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not or_reduce (arg);\n end function nor_reduce;\n\n function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not xor_reduce (arg);\n end function xnor_reduce;\n\n function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)\n return INTEGER is\n begin\n for INDEX in ARG'range loop\n if ARG(INDEX) = Y then\n return INDEX;\n end if;\n end loop;\n return -1;\n end function find_leftmost;\n\n -- Match table, copied form new std_logic_1164\n type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;\n constant match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |\n ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |\n );\n\n constant no_match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |\n ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |\n );\n\n -------------------------------------------------------------------\n -- ?= functions, Similar to \"std_match\", but returns \"std_ulogic\".\n -------------------------------------------------------------------\n -- %%% FUNCTION \"?=\" ( l, r : std_ulogic ) RETURN std_ulogic IS\n function \\?=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return match_logic_table (l, r);\n end function \\?=\\;\n -- %%% END FUNCTION \"?=\";\n\n -- %%% FUNCTION \"?/=\" ( l, r : std_ulogic ) RETURN std_ulogic is\n function \\?/=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return no_match_logic_table (l, r);\n end function \\?/=\\;\n -- %%% END FUNCTION \"?/=\";\n\n function \\?=\\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?=\\ (ufixed(l), ufixed(r));\n end function \\?=\\;\n\n function Is_X (s : UNSIGNED) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n\n function Is_X (s : SIGNED) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n-- %%% END replicated functions\n\n -- Special version of \"minimum\" to do some boundary checking\n function mine (L, R : INTEGER)\n return INTEGER is\n begin -- function minimum\n if (L = INTEGER'low or R = INTEGER'low) then\n report float_pkg'instance_name\n & \" Unbounded number passed, was a literal used?\"\n severity error;\n return 0;\n end if;\n return minimum (L, R);\n end function mine;\n\n -- Generates the base number for the exponent normalization offset.\n function gen_expon_base (\n constant exponent_width : NATURAL)\n return SIGNED is\n variable result : SIGNED (exponent_width-1 downto 0);\n begin\n result := (others => '1');\n result (exponent_width-1) := '0';\n return result;\n end function gen_expon_base;\n\n -- Integer version of the \"log2\" command (contributed by Peter Ashenden)\n function log2 (A : NATURAL) return NATURAL is\n variable quotient : NATURAL;\n variable result : NATURAL := 0;\n begin\n quotient := A / 2;\n while quotient > 0 loop\n quotient := quotient / 2;\n result := result + 1;\n end loop;\n return result;\n end function log2;\n\n -- Function similar to the ILOGB function in MATH_REAL\n function log2 (A : REAL) return INTEGER is\n variable Y : REAL;\n variable N : INTEGER := 0;\n begin\n if (A = 1.0 or A = 0.0) then\n return 0;\n end if;\n Y := A;\n if(A > 1.0) then\n while Y >= 2.0 loop\n Y := Y / 2.0;\n N := N + 1;\n end loop;\n return N;\n end if;\n -- O < Y < 1\n while Y < 1.0 loop\n Y := Y * 2.0;\n N := N - 1;\n end loop;\n return N;\n end function log2;\n\n -- purpose: Test the boundary conditions of a Real number\n procedure test_boundary (\n arg : in REAL; -- Input, converted to real\n constant fraction_width : in NATURAL; -- length of FP output fraction\n constant exponent_width : in NATURAL; -- length of FP exponent\n constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP\n variable btype : out boundary_type;\n variable log2i : out INTEGER\n ) is\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n constant exp_min : SIGNED (12 downto 0) :=\n -(resize(expon_base, 13)) + 1; -- Minimum normal exponent\n constant exp_ext_min : SIGNED (12 downto 0) :=\n exp_min - fraction_width; -- Minimum for denormal exponent\n variable log2arg : INTEGER; -- log2 of argument\n begin -- function test_boundary\n -- Check to see if the exponent is big enough\n -- Note that the argument is always an absolute value at this point.\n log2arg := log2(arg);\n if arg = 0.0 then\n btype := zero;\n elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)\n btype := normal;\n else\n if log2arg < to_integer(exp_min) then\n if denormalize then\n if log2arg < to_integer(exp_ext_min) then\n btype := zero;\n else\n btype := denormal;\n end if;\n else\n if log2arg < to_integer(exp_min)-1 then\n btype := zero;\n else\n btype := normal; -- Can still represent this number\n end if;\n end if;\n elsif exponent_width < 11 then\n if log2arg > to_integer(expon_base)+1 then\n btype := infinity;\n else\n btype := normal;\n end if;\n else\n btype := normal;\n end if;\n end if;\n log2i := log2arg;\n end procedure test_boundary;\n\n -- purpose: Rounds depending on the state of the \"round_style\"\n -- Logic taken from\n -- \"What Every Computer Scientist Should Know About Floating Point Arithmetic\"\n -- by David Goldberg (1991)\n function check_round (\n fract_in : STD_ULOGIC; -- input fraction\n sign : STD_ULOGIC; -- sign bit\n remainder : UNSIGNED; -- remainder to round from\n sticky : STD_ULOGIC := '0'; -- Sticky bit\n constant round_style : round_type) -- rounding type\n return BOOLEAN is\n variable result : BOOLEAN;\n variable or_reduced : STD_ULOGIC;\n begin -- function check_round\n result := false;\n if (remainder'length > 0) then -- if remainder in a null array\n or_reduced := or_reduce (remainder & sticky);\n rounding_case : case round_style is\n when round_nearest => -- Round Nearest, default mode\n if remainder(remainder'high) = '1' then -- round\n if (remainder'length > 1) then\n if ((or_reduce (remainder(remainder'high-1\n downto remainder'low)) = '1'\n or sticky = '1')\n or fract_in = '1') then\n -- Make the bottom bit zero if possible if we are at 1/2\n result := true;\n end if;\n else\n result := (fract_in = '1' or sticky = '1');\n end if;\n end if;\n when round_inf => -- round up if positive, else truncate.\n if or_reduced = '1' and sign = '0' then\n result := true;\n end if;\n when round_neginf => -- round down if negative, else truncate.\n if or_reduced = '1' and sign = '1' then\n result := true;\n end if;\n when round_zero => -- round toward 0 Truncate\n null;\n end case rounding_case;\n end if;\n return result;\n end function check_round;\n\n -- purpose: Rounds depending on the state of the \"round_style\"\n -- unsigned version\n procedure fp_round (\n fract_in : in UNSIGNED; -- input fraction\n expon_in : in SIGNED; -- input exponent\n fract_out : out UNSIGNED; -- output fraction\n expon_out : out SIGNED) is -- output exponent\n begin -- procedure fp_round\n if and_reduce (fract_in) = '1' then -- Fraction is all \"1\"\n expon_out := expon_in + 1;\n fract_out := to_unsigned(0, fract_out'high+1);\n else\n expon_out := expon_in;\n fract_out := fract_in + 1;\n end if;\n end procedure fp_round;\n\n -- This version of break_number doesn't call \"classfp\"\n procedure break_number ( -- internal version\n arg : in UNRESOLVED_float;\n fptyp : in valid_fpstate;\n denormalize : in BOOLEAN := true;\n fract : out UNSIGNED;\n expon : out SIGNED) is\n constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction\n constant exponent_width : NATURAL := arg'high; -- length of FP output exponent\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable exp : SIGNED (expon'range);\n begin\n fract (fraction_width-1 downto 0) :=\n UNSIGNED (to_slv(arg(-1 downto -fraction_width)));\n breakcase : case fptyp is\n when pos_zero | neg_zero =>\n fract (fraction_width) := '0';\n exp := -expon_base;\n when pos_denormal | neg_denormal =>\n if denormalize then\n exp := -expon_base;\n fract (fraction_width) := '0';\n else\n exp := -expon_base - 1;\n fract (fraction_width) := '1';\n end if;\n when pos_normal | neg_normal | pos_inf | neg_inf =>\n fract (fraction_width) := '1';\n exp := SIGNED(arg(exponent_width-1 downto 0));\n exp (exponent_width-1) := not exp(exponent_width-1);\n when others =>\n assert NO_WARNING\n report float_pkg'instance_name\n & \"BREAK_NUMBER: \" &\n \"Meta state detected in fp_break_number process\"\n severity warning;\n -- complete the case, if a NAN goes in, a NAN comes out.\n exp := (others => '1');\n fract (fraction_width) := '1';\n end case breakcase;\n expon := exp;\n end procedure break_number;\n\n -- purpose: floating point to UNSIGNED\n -- Used by to_integer, to_unsigned, and to_signed functions\n procedure float_to_unsigned (\n arg : in UNRESOLVED_float; -- floating point input\n variable sign : out STD_ULOGIC; -- sign of output\n variable frac : out UNSIGNED; -- unsigned biased output\n constant denormalize : in BOOLEAN; -- turn on denormalization\n constant bias : in NATURAL; -- bias for fixed point\n constant round_style : in round_type) is -- rounding method\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n variable fract : UNSIGNED (frac'range); -- internal version of frac\n variable isign : STD_ULOGIC; -- internal version of sign\n variable exp : INTEGER; -- Exponent\n variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp\n -- Base to divide fraction by\n variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted\n variable shift : INTEGER;\n variable remainder : UNSIGNED (2 downto 0);\n variable round : STD_ULOGIC; -- round BIT\n begin\n isign := to_x01(arg(arg'high));\n -- exponent /= '0', normal floating point\n expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (expon);\n -- Figure out the fraction\n fract := (others => '0'); -- fill with zero\n fract (fract'high) := '1'; -- Add the \"1.0\".\n shift := (fract'high-1) - exp;\n if fraction_width > fract'high then -- Can only use size-2 bits\n fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto\n -fract'high)));\n else -- can use all bits\n fract (fract'high-1 downto fract'high-fraction_width) :=\n UNSIGNED (to_slv (arg(-1 downto -fraction_width)));\n end if;\n frac_shift := fract & \"000\";\n if shift < 0 then -- Overflow\n fract := (others => '1');\n else\n frac_shift := shift_right (frac_shift, shift);\n fract := frac_shift (frac_shift'high downto 3);\n remainder := frac_shift (2 downto 0);\n -- round (round_zero will bypass this and truncate)\n case round_style is\n when round_nearest =>\n round := remainder(2) and\n (fract (0) or (or_reduce (remainder (1 downto 0))));\n when round_inf =>\n round := remainder(2) and not isign;\n when round_neginf =>\n round := remainder(2) and isign;\n when others =>\n round := '0';\n end case;\n if round = '1' then\n fract := fract + 1;\n end if;\n end if;\n frac := fract;\n sign := isign;\n end procedure float_to_unsigned;\n\n -- purpose: returns a part of a vector, this function is here because\n -- or (fractr (to_integer(shiftx) downto 0));\n -- can't be synthesized in some synthesis tools.\n function smallfract (\n arg : UNSIGNED;\n shift : NATURAL)\n return STD_ULOGIC is\n variable orx : STD_ULOGIC;\n begin\n orx := arg(shift);\n for i in arg'range loop\n if i < shift then\n orx := arg(i) or orx;\n end if;\n end loop;\n return orx;\n end function smallfract;\n ---------------------------------------------------------------------------\n -- Visible functions\n ---------------------------------------------------------------------------\n\n -- purpose: converts the negative index to a positive one\n -- negative indices are illegal in 1164 and 1076.3\n function to_sulv (\n arg : UNRESOLVED_float) -- fp vector\n return STD_ULOGIC_VECTOR is\n variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);\n begin -- function to_std_ulogic_vector\n if arg'length < 1 then\n return NSLV;\n end if;\n result := STD_ULOGIC_VECTOR (arg);\n return result;\n end function to_sulv;\n\n -- Converts an fp into an SLV\n function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is\n begin\n return to_stdlogicvector (to_sulv (arg));\n end function to_slv;\n\n -- purpose: normalizes a floating point number\n -- This version assumes an \"unsigned\" input with\n function normalize (\n fract : UNSIGNED; -- fraction, unnormalized\n expon : SIGNED; -- exponent, normalized by -1\n sign : STD_ULOGIC; -- sign BIT\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction\n variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction\n variable exp : SIGNED (exponent_width+1 downto 0); -- exponent\n variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result\n variable shiftr : INTEGER; -- shift amount\n variable stickyx : STD_ULOGIC; -- version of sticky\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable round, zerores, infres : BOOLEAN;\n begin -- function normalize\n zerores := false;\n infres := false;\n round := false;\n shiftr := find_leftmost (to_01(fract), '1') -- Find the first \"1\"\n - fraction_width - nguard; -- subtract the length we want\n exp := resize (expon, exp'length) + shiftr;\n if (or_reduce (fract) = '0') then -- Zero\n zerores := true;\n elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)\n or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then\n if (exp >= -resize(expon_base, exp'length)-fraction_width-1)\n and denormalize then\n exp := -resize(expon_base, exp'length)-1;\n shiftr := -to_integer (expon + expon_base); -- new shift\n else -- return zero\n zerores := true;\n end if;\n elsif (exp > expon_base-1) then -- infinity\n infres := true;\n end if;\n if zerores then\n result := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif infres then\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n sfract := fract srl shiftr; -- shift\n if shiftr > 0 then\n-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));\n stickyx := sticky or smallfract (fract, shiftr-1);\n else\n stickyx := sticky;\n end if;\n if nguard > 0 then\n round := check_round (\n fract_in => sfract (nguard),\n sign => sign,\n remainder => sfract(nguard-1 downto 0),\n sticky => stickyx,\n round_style => round_style);\n end if;\n if round then\n fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),\n expon_in => exp(rexp'range),\n fract_out => rfract,\n expon_out => rexp);\n else\n rfract := sfract (fraction_width-1+nguard downto nguard);\n rexp := exp(rexp'range);\n end if;\n -- result\n rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));\n rexpon (exponent_width-1) := not rexpon(exponent_width-1);\n result (rexpon'range) := UNRESOLVED_float(rexpon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);\n end if;\n result (exponent_width) := sign; -- sign BIT\n return result;\n end function normalize;\n\n -- purpose: normalizes a floating point number\n -- This version assumes a \"ufixed\" input\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent, normalized by -1\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arguns : UNSIGNED (fract'high + fraction_width + nguard\n downto 0) := (others => '0');\n begin -- function normalize\n arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=\n UNSIGNED (to_slv (fract));\n result := normalize (fract => arguns,\n expon => expon,\n sign => sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => nguard);\n return result;\n end function normalize;\n\n -- purpose: normalizes a floating point number\n -- This version assumes a \"ufixed\" input with a \"size_res\" input\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent, normalized by -1\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -size_res'low;\n constant exponent_width : NATURAL := size_res'high;\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arguns : UNSIGNED (fract'high + fraction_width + nguard\n downto 0) := (others => '0');\n begin -- function normalize\n arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=\n UNSIGNED (to_slv (fract));\n result := normalize (fract => arguns,\n expon => expon,\n sign => sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => nguard);\n return result;\n end function normalize;\n\n -- Regular \"normalize\" function with a \"size_res\" input.\n function normalize (\n fract : UNSIGNED; -- unsigned\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n begin\n return normalize (fract => fract,\n expon => expon,\n sign => sign,\n sticky => sticky,\n fraction_width => -size_res'low,\n exponent_width => size_res'high,\n round_style => round_style,\n denormalize => denormalize,\n nguard => nguard);\n end function normalize;\n\n -- Returns the class which X falls into\n function Classfp (\n x : UNRESOLVED_float; -- floating point input\n check_error : BOOLEAN := float_check_error) -- check for errors\n return valid_fpstate is\n constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction\n constant exponent_width : INTEGER := x'high; -- length of FP output exponent\n variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- classfp\n if (arg'length < 1 or fraction_width < 3 or exponent_width < 3\n or x'left < x'right) then\n report float_pkg'instance_name\n & \"CLASSFP: \" &\n \"Floating point number detected with a bad range\"\n severity error;\n return isx;\n end if;\n -- Check for \"X\".\n arg := to_01 (x, 'X');\n if (arg(0) = 'X') then\n return isx; -- If there is an X in the number\n -- Special cases, check for illegal number\n elsif check_error and\n (and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))\n = '1') then -- Exponent is all \"1\".\n if or_reduce (to_slv (arg (-1 downto -fraction_width)))\n /= '0' then -- Fraction must be all \"0\" or this is not a number.\n if (arg(-1) = '1') then -- From \"W. Khan - IEEE standard\n return nan; -- 754 binary FP Signaling nan (Not a number)\n else\n return quiet_nan;\n end if;\n -- Check for infinity\n elsif arg(exponent_width) = '0' then\n return pos_inf; -- Positive infinity\n else\n return neg_inf; -- Negative infinity\n end if;\n -- check for \"0\"\n elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))\n = '0' then -- Exponent is all \"0\"\n if or_reduce (to_slv (arg (-1 downto -fraction_width)))\n = '0' then -- Fraction is all \"0\"\n if arg(exponent_width) = '0' then\n return pos_zero; -- Zero\n else\n return neg_zero;\n end if;\n else\n if arg(exponent_width) = '0' then\n return pos_denormal; -- Denormal number (ieee extended fp)\n else\n return neg_denormal;\n end if;\n end if;\n else\n if arg(exponent_width) = '0' then\n return pos_normal; -- Normal FP number\n else\n return neg_normal;\n end if;\n end if;\n end function Classfp;\n\n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out UNSIGNED;\n expon : out SIGNED;\n sign : out STD_ULOGIC) is\n constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction\n variable fptyp : valid_fpstate;\n begin\n fptyp := Classfp (arg, check_error);\n sign := to_x01(arg(arg'high));\n break_number (\n arg => arg,\n fptyp => fptyp,\n denormalize => denormalize,\n fract => fract,\n expon => expon);\n end procedure break_number;\n \n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out ufixed; -- 1 downto -fraction_width\n expon : out SIGNED; -- exponent_width-1 downto 0\n sign : out STD_ULOGIC) is\n constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction\n variable fptyp : valid_fpstate;\n variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction\n begin\n fptyp := Classfp (arg, check_error);\n sign := to_x01(arg(arg'high));\n break_number (\n arg => arg,\n fptyp => fptyp,\n denormalize => denormalize,\n fract => ufract,\n expon => expon);\n fract (0 downto -fraction_width) := ufixed (ufract);\n end procedure break_number;\n\n -- Arithmetic functions\n function \"abs\" (\n arg : UNRESOLVED_float) -- floating point input\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range); -- result\n begin\n if (arg'length > 0) then\n result := to_01 (arg, 'X');\n result (arg'high) := '0'; -- set the sign bit to positive \n return result;\n else\n return NAFP;\n end if;\n end function \"abs\";\n\n -- IEEE 754 \"negative\" function\n function \"-\" (\n arg : UNRESOLVED_float) -- floating point input\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range); -- result\n begin\n if (arg'length > 0) then\n result := to_01 (arg, 'X');\n result (arg'high) := not result (arg'high); -- invert sign bit\n return result;\n else\n return NAFP;\n end if;\n end function \"-\";\n\n -- Addition, adds two floating point numbers\n function add (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant addguard : NATURAL := guard; -- add one guard bit\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions\n variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables\n variable urfract, ulfract : UNSIGNED (fraction_width downto 0);\n variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width downto 0); -- result exponent\n variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions\n variable sign : STD_ULOGIC; -- sign of the output\n variable leftright : BOOLEAN; -- left or right used\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable sticky : STD_ULOGIC; -- Holds precision for rounding\n begin -- addition\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan)\n -- Return quiet NAN, IEEE754-1985-7.1,1\n or (lfptype = pos_inf and rfptype = neg_inf)\n or (lfptype = neg_inf and rfptype = pos_inf) then\n -- Return quiet NAN, IEEE754-1985-7.1,2\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf\n fpresult := neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0\n fpresult := neg_zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n fractl := (others => '0');\n fractl (fraction_width+addguard downto addguard) := ulfract;\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n fractr := (others => '0');\n fractr (fraction_width+addguard downto addguard) := urfract;\n shiftx := (exponl(exponent_width-1) & exponl) - exponr;\n if shiftx < -fractl'high then\n rexpon := exponr(exponent_width-1) & exponr;\n fractc := fractr;\n fracts := (others => '0'); -- add zero\n leftright := false;\n sticky := or_reduce (fractl);\n elsif shiftx < 0 then\n shiftx := - shiftx;\n fracts := shift_right (fractl, to_integer(shiftx));\n fractc := fractr;\n rexpon := exponr(exponent_width-1) & exponr;\n leftright := false;\n-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));\n sticky := smallfract (fractl, to_integer(shiftx));\n elsif shiftx = 0 then\n rexpon := exponl(exponent_width-1) & exponl;\n sticky := '0';\n if fractr > fractl then\n fractc := fractr;\n fracts := fractl;\n leftright := false;\n else\n fractc := fractl;\n fracts := fractr;\n leftright := true;\n end if;\n elsif shiftx > fractr'high then\n rexpon := exponl(exponent_width-1) & exponl;\n fracts := (others => '0'); -- add zero\n fractc := fractl;\n leftright := true;\n sticky := or_reduce (fractr);\n elsif shiftx > 0 then\n fracts := shift_right (fractr, to_integer(shiftx));\n fractc := fractl;\n rexpon := exponl(exponent_width-1) & exponl;\n leftright := true;\n-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));\n sticky := smallfract (fractr, to_integer(shiftx));\n end if;\n -- add\n fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB\n if l(l'high) = r(r'high) then\n ufract := fractc + fracts;\n sign := l(l'high);\n else -- signs are different\n ufract := fractc - fracts; -- always positive result\n if leftright then -- Figure out which sign to use\n sign := l(l'high);\n else\n sign := r(r'high);\n end if;\n end if;\n if or_reduce (ufract) = '0' then\n sign := '0'; -- IEEE 854, 6.3, paragraph 2.\n end if;\n -- normalize\n fpresult := normalize (fract => ufract,\n expon => rexpon,\n sign => sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => addguard);\n end if;\n return fpresult;\n end function add;\n\n -- Subtraction, Calls \"add\".\n function subtract (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable negr : UNRESOLVED_float (r'range); -- negative version of r\n begin\n negr := -r;\n return add (l => l,\n r => negr,\n round_style => round_style,\n guard => guard,\n check_error => check_error,\n denormalize => denormalize);\n end function subtract;\n\n -- Floating point multiply\n function multiply (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant multguard : NATURAL := guard; -- guard bits\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions\n variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction\n variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction\n variable shifty : INTEGER; -- denormal shift\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable sticky : STD_ULOGIC; -- Holds precision for rounding\n begin -- multiply\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif ((lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan)) then\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (((lfptype = pos_inf or lfptype = neg_inf) and\n (rfptype = pos_zero or rfptype = neg_zero)) or\n ((rfptype = pos_inf or rfptype = neg_inf) and\n (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf\n -- Return quiet NAN, IEEE754-1985-7.1,3\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = pos_inf or rfptype = pos_inf\n or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n -- figure out the sign\n fp_sign := l(l'high) xor r(r'high); -- figure out the sign\n fpresult (exponent_width) := fp_sign;\n else\n fp_sign := l(l'high) xor r(r'high); -- figure out the sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => fractl,\n expon => exponl);\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => fractr,\n expon => exponr);\n if (rfptype = pos_denormal or rfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractr, '1');\n fractr := shift_left (fractr, shifty);\n elsif (lfptype = pos_denormal or lfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractl, '1');\n fractl := shift_left (fractl, shifty);\n else\n shifty := 0;\n -- Note that a denormal number * a denormal number is always zero.\n end if;\n -- multiply\n -- add the exponents\n rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;\n rfract := fractl * fractr; -- Multiply the fraction\n sfract := rfract (rfract'high downto\n rfract'high - (fraction_width+1+multguard));\n sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)\n downto 0));\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => rexpon,\n sign => fp_sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => multguard);\n end if;\n return fpresult;\n end function multiply;\n\n function short_divide (\n lx, rx : UNSIGNED)\n return UNSIGNED is\n -- This is a special divider for the floating point routines.\n -- For a true unsigned divider, \"stages\" needs to = lx'high\n constant stages : INTEGER := lx'high - rx'high; -- number of stages\n variable partial : UNSIGNED (lx'range);\n variable q : UNSIGNED (stages downto 0);\n variable partial_argl : SIGNED (rx'high + 2 downto 0);\n variable partial_arg : SIGNED (rx'high + 2 downto 0);\n begin\n partial := lx;\n for i in stages downto 0 loop\n partial_argl := resize (\"0\" & SIGNED (partial(lx'high downto i)),\n partial_argl'length);\n partial_arg := partial_argl - SIGNED (\"0\" & rx);\n if (partial_arg (partial_arg'high) = '1') then -- negative\n q(i) := '0';\n else\n q(i) := '1';\n partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=\n UNSIGNED (partial_arg(rx'range));\n end if;\n end loop;\n -- to make the output look like that of the unsigned IEEE divide.\n return resize (q, lx'length);\n end function short_divide;\n\n -- 1/X function. Needed for algorithm development.\n function reciprocal (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : NATURAL := arg'high; -- length of FP output exponent\n constant divguard : NATURAL := guard; -- guard bits\n function onedivy (\n arg : UNSIGNED)\n return UNSIGNED is\n variable q : UNSIGNED((2*arg'high)+1 downto 0);\n variable one : UNSIGNED (q'range);\n begin\n one := (others => '0');\n one(one'high) := '1';\n q := short_divide (one, arg); -- Unsigned divide\n return resize (q, arg'length+1);\n end function onedivy;\n variable fptype : valid_fpstate;\n variable expon : SIGNED (exponent_width-1 downto 0); -- exponents\n variable denorm_offset : NATURAL range 0 to 2;\n variable fract : UNSIGNED (fraction_width downto 0);\n variable fractg : UNSIGNED (fraction_width+divguard downto 0);\n variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- reciprocal\n fptype := classfp(arg, check_error);\n classcase : case fptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf => -- 1/inf, return 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when neg_zero | pos_zero => -- 1/0\n report float_pkg'instance_name\n & \"RECIPROCAL: Floating Point divide by zero\"\n severity error;\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when others =>\n if (fptype = pos_denormal or fptype = neg_denormal)\n and ((arg (-1) or arg(-2)) /= '1') then\n -- 1/denormal = infinity, with the exception of 2**-expon_base\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fpresult (exponent_width) := to_x01 (arg (exponent_width));\n else\n break_number (\n arg => arg,\n fptyp => fptype,\n denormalize => denormalize,\n fract => fract,\n expon => expon);\n fractg := (others => '0');\n if (fptype = pos_denormal or fptype = neg_denormal) then\n -- The reciprocal of a denormal number is typically zero,\n -- except for two special cases which are trapped here.\n if (to_x01(arg (-1)) = '1') then\n fractg (fractg'high downto divguard+1) :=\n fract (fract'high-1 downto 0); -- Shift to not denormal\n denorm_offset := 1; -- add 1 to exponent compensate\n else -- arg(-2) = '1'\n fractg (fractg'high downto divguard+2) :=\n fract (fract'high-2 downto 0); -- Shift to not denormal\n denorm_offset := 2; -- add 2 to exponent compensate\n end if;\n else\n fractg (fractg'high downto divguard) := fract;\n denorm_offset := 0;\n end if;\n expon := - expon - 3 + denorm_offset;\n sfract := onedivy (fractg);\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => expon,\n sign => arg(exponent_width),\n sticky => '1',\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => divguard);\n end if;\n end case classcase;\n return fpresult;\n end function reciprocal;\n\n -- floating point division\n function divide (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant divguard : NATURAL := guard; -- division guard bits\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable ulfract, urfract : UNSIGNED (fraction_width downto 0);\n variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left\n variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right\n variable rfract : UNSIGNED (fractl'range); -- result fraction\n variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable fp_sign, sticky : STD_ULOGIC; -- sign of result\n variable shifty, shiftx : INTEGER; -- denormal number shift\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- divide\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n classcase : case rfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf =>\n if lfptype = pos_inf or lfptype = neg_inf -- inf / inf\n or lfptype = quiet_nan or lfptype = nan then\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else -- x / inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when pos_zero | neg_zero =>\n if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0\n or lfptype = quiet_nan or lfptype = nan then\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n report float_pkg'instance_name\n & \"DIVIDE: Floating Point divide by zero\"\n severity error;\n -- Infinity, define in 754-1985-7.2\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when others =>\n classcase2 : case lfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf => -- inf / x = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult(exponent_width) := fp_sign;\n when pos_zero | neg_zero => -- 0 / X = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult(exponent_width) := fp_sign;\n when others =>\n fp_sign := l(l'high) xor r(r'high); -- sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n -- right side\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n -- Compute the exponent\n rexpon := resize (exponl, rexpon'length) - exponr - 2;\n if (rfptype = pos_denormal or rfptype = neg_denormal) then\n -- Do the shifting here not after. That way we have a smaller\n -- shifter, and need a smaller divider, because the top\n -- bit in the divisor will always be a \"1\".\n shifty := fraction_width - find_leftmost(urfract, '1');\n urfract := shift_left (urfract, shifty);\n rexpon := rexpon + shifty;\n end if;\n fractr := (others => '0');\n fractr (fraction_width+divguard downto divguard) := urfract;\n if (lfptype = pos_denormal or lfptype = neg_denormal) then\n shiftx := fraction_width - find_leftmost(ulfract, '1');\n ulfract := shift_left (ulfract, shiftx);\n rexpon := rexpon - shiftx;\n end if;\n fractl := (others => '0');\n fractl (fractl'high downto fractl'high-fraction_width) := ulfract;\n -- divide\n rfract := short_divide (fractl, fractr); -- unsigned divide\n sfract := rfract (sfract'range); -- lower bits\n sticky := '1';\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => rexpon,\n sign => fp_sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => divguard);\n end case classcase2;\n end case classcase;\n return fpresult;\n end function divide;\n\n -- division by a power of 2\n function dividebyp2 (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable ulfract, urfract : UNSIGNED (fraction_width downto 0);\n variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED(exponent_width downto 0); -- result exponent\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- divisionbyp2\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n classcase : case rfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf =>\n if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else -- x / inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when pos_zero | neg_zero =>\n if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n report float_pkg'instance_name\n & \"DIVIDEBYP2: Floating Point divide by zero\"\n severity error;\n -- Infinity, define in 754-1985-7.2\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when others =>\n classcase2 : case lfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf => -- inf / x = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (exponent_width) := fp_sign; -- sign\n when pos_zero | neg_zero => -- 0 / X = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (exponent_width) := fp_sign; -- sign\n when others =>\n fp_sign := l(l'high) xor r(r'high); -- sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n -- right side\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')\n report float_pkg'instance_name\n & \"DIVIDEBYP2: \"\n & \"Dividebyp2 called with a non power of two divisor\"\n severity error;\n rexpon := (exponl(exponl'high)&exponl)\n - (exponr(exponr'high)&exponr) - 1;\n -- normalize\n fpresult := normalize (fract => ulfract,\n expon => rexpon,\n sign => fp_sign,\n sticky => '1',\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => 0);\n end case classcase2;\n end case classcase;\n return fpresult;\n end function dividebyp2;\n\n -- Multiply accumulate result = l*r + c\n function mac (\n l, r, c : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL :=\n -mine (mine(l'low, r'low), c'low); -- length of FP output fraction\n constant exponent_width : NATURAL :=\n maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent\n variable lfptype, rfptype, cfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions\n variable fractx : UNSIGNED (fraction_width+guard downto 0);\n variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);\n variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction\n variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction\n variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable shifty : INTEGER; -- denormal shift\n variable shiftx : SIGNED (rexpon'range); -- shift fractions\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);\n variable leftright : BOOLEAN; -- left or right used\n variable sticky : STD_ULOGIC; -- Holds precision for rounding\n begin -- multiply\n if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n cfptype := classfp (c, check_error);\n end if;\n if (lfptype = isx or rfptype = isx or cfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan or\n cfptype = nan or cfptype = quiet_nan) then\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (((lfptype = pos_inf or lfptype = neg_inf) and\n (rfptype = pos_zero or rfptype = neg_zero)) or\n ((rfptype = pos_inf or rfptype = neg_inf) and\n (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf\n -- Return quiet NAN, IEEE754-1985-7.1,3\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = pos_inf or rfptype = pos_inf\n or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf\n or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n -- figure out the sign\n fpresult (exponent_width) := l(l'high) xor r(r'high);\n else\n fp_sign := l(l'high) xor r(r'high); -- figure out the sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n cresize := resize (arg => to_x01(c),\n exponent_width => exponent_width,\n fraction_width => -cresize'low,\n denormalize_in => denormalize,\n denormalize => denormalize);\n cfptype := classfp (cresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => fractl,\n expon => exponl);\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => fractr,\n expon => exponr);\n break_number (\n arg => cresize,\n fptyp => cfptype,\n denormalize => denormalize,\n fract => fractx,\n expon => exponc);\n if (rfptype = pos_denormal or rfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractr, '1');\n fractr := shift_left (fractr, shifty);\n elsif (lfptype = pos_denormal or lfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractl, '1');\n fractl := shift_left (fractl, shifty);\n else\n shifty := 0;\n -- Note that a denormal number * a denormal number is always zero.\n end if;\n -- multiply\n rfract := fractl * fractr; -- Multiply the fraction\n -- add the exponents\n rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;\n shiftx := rexpon - exponc;\n if shiftx < -fractl'high then\n rexpon2 := resize (exponc, rexpon2'length);\n fractc := \"0\" & fractx;\n fracts := (others => '0');\n sticky := or_reduce (rfract);\n elsif shiftx < 0 then\n shiftx := - shiftx;\n fracts := shift_right (rfract (rfract'high downto rfract'high\n - fracts'length+1),\n to_integer(shiftx));\n fractc := \"0\" & fractx;\n rexpon2 := resize (exponc, rexpon2'length);\n leftright := false;\n sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high\n - fracts'length downto 0));\n elsif shiftx = 0 then\n rexpon2 := resize (exponc, rexpon2'length);\n sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));\n if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx\n then\n fractc := \"0\" & fractx;\n fracts := rfract (rfract'high downto rfract'high\n - fracts'length+1);\n leftright := false;\n else\n fractc := rfract (rfract'high downto rfract'high\n - fractc'length+1);\n fracts := \"0\" & fractx;\n leftright := true;\n end if;\n elsif shiftx > fractx'high then\n rexpon2 := rexpon;\n fracts := (others => '0');\n fractc := rfract (rfract'high downto rfract'high - fractc'length+1);\n leftright := true;\n sticky := or_reduce (fractx & rfract (rfract'high - fractc'length\n downto 0));\n else -- fractx'high > shiftx > 0\n rexpon2 := rexpon;\n fracts := \"0\" & shift_right (fractx, to_integer (shiftx));\n fractc := rfract (rfract'high downto rfract'high - fractc'length+1);\n leftright := true;\n sticky := or_reduce (fractx (to_integer (shiftx) downto 0)\n & rfract (rfract'high - fractc'length downto 0));\n end if;\n fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB\n if fp_sign = to_X01(c(c'high)) then\n ufract := fractc + fracts;\n fp_sign := fp_sign;\n else -- signs are different\n ufract := fractc - fracts; -- always positive result\n if leftright then -- Figure out which sign to use\n fp_sign := fp_sign;\n else\n fp_sign := c(c'high);\n end if;\n end if;\n -- normalize\n fpresult := normalize (fract => ufract,\n expon => rexpon2,\n sign => fp_sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => guard);\n end if;\n return fpresult;\n end function mac;\n\n -- \"rem\" function\n function remainder (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant divguard : NATURAL := guard; -- division guard bits\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable ulfract, urfract : UNSIGNED (fraction_width downto 0);\n variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right\n variable rfract : UNSIGNED (fractr'range); -- result fraction\n variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width downto 0); -- result exponent\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable shifty : INTEGER; -- denormal number shift\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- remainder\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan)\n or (rfptype = nan or rfptype = quiet_nan)\n -- Return quiet NAN, IEEE754-1985-7.1,1\n or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x\n -- Return quiet NAN, IEEE754-1985-7.1,5\n or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0\n -- Return quiet NAN, IEEE754-1985-7.1,5\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (abs(l) < abs(r)) then\n fpresult := l;\n else\n fp_sign := to_X01(l(l'high)); -- sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n fractl := (others => '0');\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n fractl (fraction_width+divguard downto divguard) := ulfract;\n -- right side\n fractr := (others => '0');\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n fractr (fraction_width+divguard downto divguard) := urfract;\n rexpon := (exponr(exponr'high)&exponr);\n shifty := to_integer(exponl - rexpon);\n if (shifty > 0) then\n fractr := shift_right (fractr, shifty);\n rexpon := rexpon + shifty;\n end if;\n if (fractr /= 0) then\n -- rem\n rfract := fractl rem fractr; -- unsigned rem\n sfract := rfract (sfract'range); -- lower bits\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => rexpon,\n sign => fp_sign,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => divguard);\n else\n -- If we shift \"fractr\" so far that it becomes zero, return zero.\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n end if;\n end if;\n return fpresult;\n end function remainder;\n\n -- \"mod\" function\n function modulo (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- remainder\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan)\n or (rfptype = nan or rfptype = quiet_nan)\n -- Return quiet NAN, IEEE754-1985-7.1,1\n or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x\n -- Return quiet NAN, IEEE754-1985-7.1,5\n or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0\n -- Return quiet NAN, IEEE754-1985-7.1,5\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n remres := remainder (l => abs(l),\n r => abs(r),\n round_style => round_style,\n guard => guard,\n check_error => false,\n denormalize => denormalize);\n -- MOD is the same as REM, but you do something different with\n -- negative values\n if (is_negative (l)) then\n remres := - remres;\n end if;\n if (is_negative (l) = is_negative (r) or remres = 0) then\n fpresult := remres;\n else\n fpresult := add (l => remres,\n r => r,\n round_style => round_style,\n guard => guard,\n check_error => false,\n denormalize => denormalize); \n end if;\n end if;\n return fpresult;\n end function modulo;\n\n -- Square root of a floating point number. Done using Newton's Iteration.\n function sqrt (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style;\n constant guard : NATURAL := float_guard_bits;\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction\n constant exponent_width : NATURAL := arg'high; -- length of FP output exponent\n variable sign : STD_ULOGIC;\n variable fpresult : float (arg'range);\n variable fptype : valid_fpstate;\n variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents\n variable expon : SIGNED(exponent_width downto 0); -- exponents\n variable ufact : ufixed (0 downto arg'low);\n variable fact : ufixed (2 downto -fraction_width); -- fraction\n variable resb : ufixed (fact'high+1 downto fact'low);\n begin -- square root\n fptype := Classfp (arg, check_error);\n classcase : case fptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan |\n -- Return quiet NAN, IEEE754-1985-7.1,1\n neg_normal | neg_denormal | neg_inf => -- sqrt (neg)\n -- Return quiet NAN, IEEE754-1985-7.1.6\n fpresult := qnanfp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when pos_inf => -- Sqrt (inf), return infinity\n fpresult := pos_inffp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when pos_zero => -- return 0\n fpresult := zerofp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when neg_zero => -- IEEE754-1985-6.3 return -0\n", "right_context": " check_error => false,\n fract => ufact,\n expon => iexpon,\n sign => sign);\n expon := resize (iexpon+1, expon'length); -- get exponent\n fact := resize (ufact, fact'high, fact'low);\n if (expon(0) = '1') then\n fact := fact sla 1; -- * 2.0\n end if;\n expon := shift_right (expon, 1); -- exponent/2\n -- Newton's iteration - root := (1 + arg) / 2\n resb := (fact + 1) sra 1;\n for j in 0 to fraction_width/4 loop\n -- root := (root + (arg/root))/2\n resb := resize (arg => (resb + (fact/resb)) sra 1,\n left_index => resb'high,\n right_index => resb'low,\n round_style => fixed_truncate,\n overflow_style => fixed_wrap);\n end loop;\n fpresult := normalize (fract => resb,\n expon => expon-1,\n sign => '0',\n exponent_width => arg'high,\n fraction_width => -arg'low,\n round_style => round_style,\n denormalize => denormalize,\n nguard => guard);\n end case classcase;\n return fpresult;\n end function sqrt;\n\n function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is\n -- Technically -0 should return \"false\", but I'm leaving that case out.\n begin\n return (to_x01(arg(arg'high)) = '1');\n end function Is_Negative;\n\n -- compare functions\n -- =, /=, >=, <=, <, >\n\n function eq ( -- equal =\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable lfptype, rfptype : valid_fpstate;\n variable is_equal, is_unordered : BOOLEAN;\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- equal\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return false;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = neg_zero or lfptype = pos_zero) and\n (rfptype = neg_zero or rfptype = pos_zero) then\n is_equal := true;\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n is_equal := (to_slv(lresize) = to_slv(rresize));\n end if;\n if (check_error) then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return is_equal and not is_unordered;\n end function eq;\n\n function lt ( -- less than <\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable expl, expr : UNSIGNED (exponent_width-1 downto 0);\n variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);\n variable is_less_than, is_unordered : BOOLEAN;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n is_less_than := false;\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits\n expl := UNSIGNED(lresize(exponent_width-1 downto 0));\n expr := UNSIGNED(rresize(exponent_width-1 downto 0));\n if expl = expr then\n fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));\n fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));\n if to_x01(l(l'high)) = '0' then -- positive number\n is_less_than := (fractl < fractr);\n else\n is_less_than := (fractl > fractr); -- negative\n end if;\n else\n if to_x01(l(l'high)) = '0' then -- positive number\n is_less_than := (expl < expr);\n else\n is_less_than := (expl > expr); -- negative\n end if;\n end if;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n if (lfptype = neg_zero and rfptype = pos_zero) then\n is_less_than := false; -- -0 < 0 returns false.\n else\n is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));\n end if;\n end if;\n end if;\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return is_less_than and not is_unordered;\n end function lt;\n\n function gt ( -- greater than >\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable expl, expr : UNSIGNED (exponent_width-1 downto 0);\n variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);\n variable is_greater_than : BOOLEAN;\n variable is_unordered : BOOLEAN;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- greater_than\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n is_greater_than := false;\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits\n expl := UNSIGNED(lresize(exponent_width-1 downto 0));\n expr := UNSIGNED(rresize(exponent_width-1 downto 0));\n if expl = expr then\n fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));\n fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));\n if to_x01(l(l'high)) = '0' then -- positive number\n is_greater_than := fractl > fractr;\n else\n is_greater_than := fractl < fractr; -- negative\n end if;\n else\n if to_x01(l(l'high)) = '0' then -- positive number\n is_greater_than := expl > expr;\n else\n is_greater_than := expl < expr; -- negative\n end if;\n end if;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n if (lfptype = pos_zero and rfptype = neg_zero) then\n is_greater_than := false; -- 0 > -0 returns false.\n else\n is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));\n end if;\n end if;\n end if;\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return is_greater_than and not is_unordered;\n end function gt;\n\n -- purpose: /= function\n function ne ( -- not equal /=\n l, r : UNRESOLVED_float;\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable is_equal, is_unordered : BOOLEAN;\n begin\n is_equal := eq (l => l,\n r => r,\n check_error => false,\n denormalize => denormalize);\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return not (is_equal and not is_unordered);\n end function ne;\n\n function le ( -- less than or equal to <=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable is_greater_than, is_unordered : BOOLEAN;\n begin\n is_greater_than := gt (l => l,\n r => r,\n check_error => false,\n denormalize => denormalize);\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return not is_greater_than and not is_unordered;\n end function le;\n\n function ge ( -- greater than or equal to >=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable is_less_than, is_unordered : BOOLEAN;\n begin\n is_less_than := lt (l => l,\n r => r,\n check_error => false,\n denormalize => denormalize);\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return not is_less_than and not is_unordered;\n end function ge;\n\n function \\?=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable is_equal, is_unordered : STD_ULOGIC;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- ?=\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n lfptype := classfp (l, float_check_error);\n rfptype := classfp (r, float_check_error);\n end if;\n if (lfptype = neg_zero or lfptype = pos_zero) and\n (rfptype = neg_zero or rfptype = pos_zero) then\n is_equal := '1';\n else\n lresize := resize (arg => l,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n rresize := resize (arg => r,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n is_equal := \\?=\\ (to_sulv(lresize), to_sulv(rresize));\n end if;\n if (float_check_error) then\n if (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan) then\n is_unordered := '1';\n else\n is_unordered := '0';\n end if;\n else\n is_unordered := '0';\n end if;\n return is_equal and not is_unordered;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable is_equal, is_unordered : STD_ULOGIC;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- ?/=\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n lfptype := classfp (l, float_check_error);\n rfptype := classfp (r, float_check_error);\n end if;\n if (lfptype = neg_zero or lfptype = pos_zero) and\n (rfptype = neg_zero or rfptype = pos_zero) then\n is_equal := '1';\n else\n lresize := resize (arg => l,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n rresize := resize (arg => r,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n is_equal := \\?=\\ (to_sulv(lresize), to_sulv(rresize));\n end if;\n if (float_check_error) then\n if (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan) then\n is_unordered := '1';\n else\n is_unordered := '0';\n end if;\n else\n is_unordered := '0';\n end if;\n return not (is_equal and not is_unordered);\n end function \\?/=\\;\n\n function \\?>\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l > r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>\\;\n\n function \\?>=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l >= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>=\\;\n\n function \\?<\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l < r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<\\;\n\n function \\?<=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l <= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<=\\;\n\n function std_match (L, R : UNRESOLVED_float) return BOOLEAN is\n begin\n if (L'high = R'high and L'low = R'low) then\n return std_match(to_sulv(L), to_sulv(R));\n else\n report float_pkg'instance_name\n & \"STD_MATCH: L'RANGE /= R'RANGE, returning FALSE\"\n severity warning;\n return false;\n end if;\n end function std_match;\n\n function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is\n begin\n for_loop : for i in arg'reverse_range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'high+1; -- return out of bounds 'high\n end function find_rightmost;\n\n function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is\n begin\n for_loop : for i in arg'range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'low-1; -- return out of bounds 'low\n end function find_leftmost;\n\n -- These override the defaults for the compare operators.\n function \"=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return eq(l, r);\n end function \"=\";\n\n function \"/=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return ne(l, r);\n end function \"/=\";\n\n function \">=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return ge(l, r);\n end function \">=\";\n\n function \"<=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return le(l, r);\n end function \"<=\";\n\n function \">\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return gt(l, r);\n end function \">\";\n\n function \"<\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return lt(l, r);\n end function \"<\";\n\n -- purpose: maximum of two numbers (overrides default)\n function maximum (\n L, R : UNRESOLVED_float)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAFP;\n end if;\n lresize := resize (l, exponent_width, fraction_width);\n rresize := resize (r, exponent_width, fraction_width);\n if lresize > rresize then return lresize;\n else return rresize;\n end if;\n end function maximum;\n\n function minimum (\n L, R : UNRESOLVED_float)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAFP;\n end if;\n lresize := resize (l, exponent_width, fraction_width);\n rresize := resize (r, exponent_width, fraction_width);\n if lresize > rresize then return rresize;\n else return lresize;\n end if;\n end function minimum;\n\n -----------------------------------------------------------------------------\n -- conversion functions\n -----------------------------------------------------------------------------\n\n -- Converts a floating point number of one format into another format\n function resize (\n arg : UNRESOLVED_float; -- Floating point input\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction\n constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n -- result value\n variable fptype : valid_fpstate;\n variable expon_in : SIGNED (in_exponent_width-1 downto 0);\n variable fract_in : UNSIGNED (in_fraction_width downto 0);\n variable round : BOOLEAN;\n variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract\n variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract\n variable passguard : NATURAL;\n begin\n fptype := classfp(arg, check_error);\n if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in\n and (in_exponent_width < exponent_width\n or in_fraction_width < fraction_width))\n or in_exponent_width > exponent_width\n or in_fraction_width > fraction_width then\n -- size reduction\n classcase : case fptype is\n when isx =>\n result := (others => 'X');\n when nan | quiet_nan =>\n result := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf =>\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when neg_inf =>\n result := neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_zero | neg_zero =>\n result := zerofp (fraction_width => fraction_width, -- hate -0\n exponent_width => exponent_width);\n when others =>\n break_number (\n arg => arg,\n fptyp => fptype,\n denormalize => denormalize_in,\n fract => fract_in,\n expon => expon_in);\n if fraction_width > in_fraction_width and denormalize_in then\n -- You only get here if you have a denormal input\n fract_out := (others => '0'); -- pad with zeros\n fract_out (fraction_width downto\n fraction_width - in_fraction_width) := fract_in;\n result := normalize (\n fract => fract_out,\n expon => expon_in,\n sign => arg(arg'high),\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => 0);\n else\n result := normalize (\n fract => fract_in,\n expon => expon_in,\n sign => arg(arg'high),\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => in_fraction_width - fraction_width);\n end if;\n end case classcase;\n else -- size increase or the same size\n if exponent_width > in_exponent_width then\n expon_in := SIGNED(arg (in_exponent_width-1 downto 0));\n if fptype = pos_zero or fptype = neg_zero then\n result (exponent_width-1 downto 0) := (others => '0');\n elsif expon_in = -1 then -- inf or nan (shorts out check_error)\n result (exponent_width-1 downto 0) := (others => '1');\n else\n -- invert top BIT\n expon_in(expon_in'high) := not expon_in(expon_in'high);\n expon_out := resize (expon_in, expon_out'length); -- signed expand\n -- Flip it back.\n expon_out(expon_out'high) := not expon_out(expon_out'high);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);\n end if;\n result (exponent_width) := arg (in_exponent_width); -- sign\n else -- exponent_width = in_exponent_width\n result (exponent_width downto 0) := arg (in_exponent_width downto 0);\n end if;\n if fraction_width > in_fraction_width then\n result (-1 downto -fraction_width) := (others => '0'); -- zeros\n result (-1 downto -in_fraction_width) :=\n arg (-1 downto -in_fraction_width);\n else -- fraction_width = in_fraciton_width\n result (-1 downto -fraction_width) :=\n arg (-1 downto -in_fraction_width);\n end if;\n end if;\n return result;\n end function resize;\n\n function resize (\n arg : UNRESOLVED_float; -- floating point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := resize (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n return result;\n end if;\n end function resize;\n\n function to_float32 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float32 is\n begin\n return resize (arg => arg,\n exponent_width => float32'high,\n fraction_width => -float32'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n end function to_float32;\n\n function to_float64 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float64 is\n begin\n return resize (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n end function to_float64;\n\n function to_float128 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float128 is\n begin\n return resize (arg => arg,\n exponent_width => float128'high,\n fraction_width => -float128'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n end function to_float128;\n\n -- to_float (Real)\n -- typically not Synthesizable unless the input is a constant.\n function to_float (\n arg : REAL;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arg_real : REAL; -- Real version of argument\n variable validfp : boundary_type; -- Check for valid results\n variable exp : INTEGER; -- Integer version of exponent\n variable expon : UNSIGNED (exponent_width - 1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable fract : UNSIGNED (fraction_width-1 downto 0);\n variable frac : REAL; -- Real version of fraction\n constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding\n variable round : BOOLEAN; -- to round or not to round\n begin\n result := (others => '0');\n arg_real := arg;\n if arg_real < 0.0 then\n result (exponent_width) := '1';\n arg_real := - arg_real; -- Make it positive.\n else\n result (exponent_width) := '0';\n end if;\n test_boundary (arg => arg_real,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n denormalize => denormalize,\n btype => validfp,\n log2i => exp);\n if validfp = zero then\n return result; -- Result initialized to \"0\".\n elsif validfp = infinity then\n result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all \"1\"\n -- return infinity.\n return result;\n else\n if validfp = denormal then -- Exponent will default to \"0\".\n expon := (others => '0');\n frac := arg_real * (2.0 ** (to_integer(expon_base)-1));\n else -- Number less than 1. \"normal\" number\n expon := UNSIGNED (to_signed (exp-1, exponent_width));\n expon(exponent_width-1) := not expon(exponent_width-1);\n frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.\n end if;\n for i in 0 to fract'high loop\n if frac >= 2.0 ** (-1 - i) then\n fract (fract'high - i) := '1';\n frac := frac - 2.0 ** (-1 - i);\n else\n fract (fract'high - i) := '0';\n end if;\n end loop;\n round := false;\n case round_style is\n when round_nearest =>\n if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then\n round := true;\n end if;\n when round_inf =>\n if frac /= 0.0 and result(exponent_width) = '0' then\n round := true;\n end if;\n when round_neginf =>\n if frac /= 0.0 and result(exponent_width) = '1' then\n round := true;\n end if;\n when others =>\n null; -- don't round\n end case;\n if (round) then\n if and_reduce (fract) = '1' then -- fraction is all \"1\"\n expon := expon + 1;\n fract := (others => '0');\n else\n fract := fract + 1;\n end if;\n end if;\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n return result;\n end if;\n end function to_float;\n\n -- to_float (Integer)\n function to_float (\n arg : INTEGER;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arg_int : NATURAL; -- Natural version of argument\n variable expon : SIGNED (exponent_width-1 downto 0);\n variable exptmp : SIGNED (exponent_width-1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');\n variable fracttmp : UNSIGNED (fraction_width-1 downto 0);\n variable round : BOOLEAN;\n variable shift : NATURAL;\n variable shiftr : NATURAL;\n variable roundfrac : NATURAL; -- used in rounding\n begin\n if arg < 0 then\n result (exponent_width) := '1';\n arg_int := -arg; -- Make it positive.\n else\n result (exponent_width) := '0';\n arg_int := arg;\n end if;\n if arg_int = 0 then\n result := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n -- If the number is larger than we can represent in this number system\n -- we need to return infinity.\n shift := log2(arg_int);\n if shift > to_integer(expon_base) then\n -- worry about infinity\n if result (exponent_width) = '0' then\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n -- return negative infinity.\n result := neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n end if;\n else -- Normal number (can't be denormal)\n -- Compute Exponent\n expon := to_signed (shift-1, expon'length); -- positive fraction.\n -- Compute Fraction\n arg_int := arg_int - 2**shift; -- Subtract off the 1.0\n shiftr := shift;\n for I in fract'high downto maximum (fract'high - shift + 1, 0) loop\n shiftr := shiftr - 1;\n if (arg_int >= 2**shiftr) then\n arg_int := arg_int - 2**shiftr;\n fract(I) := '1';\n else\n fract(I) := '0';\n end if;\n end loop;\n -- Rounding routine\n round := false;\n if arg_int > 0 then\n roundfrac := 2**(shiftr-1);\n case round_style is\n when round_nearest =>\n if arg_int > roundfrac or\n ((arg_int = roundfrac) and fract(0) = '1') then\n round := true;\n end if;\n when round_inf =>\n if arg_int /= 0 and result (exponent_width) = '0' then\n round := true;\n end if;\n when round_neginf =>\n if arg_int /= 0 and result (exponent_width) = '1' then\n round := true;\n end if;\n when others =>\n null;\n end case;\n end if;\n if round then\n fp_round(fract_in => fract,\n expon_in => expon,\n fract_out => fracttmp,\n expon_out => exptmp);\n fract := fracttmp;\n expon := exptmp;\n end if;\n -- Put the number together and return\n expon(exponent_width-1) := not expon(exponent_width-1);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n end if;\n end if;\n return result;\n end function to_float;\n\n -- to_float (unsigned)\n function to_float (\n arg : UNSIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;\n variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg\n begin\n if arg'length < 1 then\n return NAFP;\n end if;\n sarg (XARG'range) := SIGNED (XARG);\n sarg (sarg'high) := '0';\n result := to_float (arg => sarg,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n round_style => round_style);\n return result;\n end function to_float;\n\n -- to_float (signed)\n function to_float (\n arg : SIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;\n variable arg_int : UNSIGNED(xarg'range); -- Real version of argument\n variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input\n variable rexp : SIGNED (exponent_width - 1 downto 0);\n variable exp : SIGNED (exponent_width - 1 downto 0);\n -- signed version of exp.\n variable expon : UNSIGNED (exponent_width - 1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable round : BOOLEAN;\n variable fract : UNSIGNED (fraction_width-1 downto 0);\n variable rfract : UNSIGNED (fraction_width-1 downto 0);\n variable sign : STD_ULOGIC; -- sign bit\n begin\n if arg'length < 1 then\n return NAFP;\n end if;\n if Is_X (xarg) then\n result := (others => 'X');\n elsif (xarg = 0) then\n result := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else -- Normal number (can't be denormal)\n sign := to_X01(xarg (xarg'high));\n arg_int := UNSIGNED(abs (to_01(xarg)));\n -- Compute Exponent\n argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2\n if argb2 > UNSIGNED(expon_base) then\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n result (exponent_width) := sign;\n else\n exp := SIGNED(resize(argb2, exp'length));\n arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));\n if (arg_int'high > fraction_width) then\n fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));\n round := check_round (\n fract_in => fract (0),\n sign => sign,\n remainder => arg_int((arg_int'high-fraction_width-1)\n downto 0),\n round_style => round_style);\n if round then\n fp_round(fract_in => fract,\n expon_in => exp,\n fract_out => rfract,\n expon_out => rexp);\n else\n rfract := fract;\n rexp := exp;\n end if;\n else\n rexp := exp;\n rfract := (others => '0');\n rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=\n arg_int (arg_int'high-1 downto 0);\n end if;\n result (exponent_width) := sign;\n expon := UNSIGNED (rexp-1);\n expon(exponent_width-1) := not expon(exponent_width-1);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);\n end if;\n end if;\n return result;\n end function to_float;\n\n -- std_logic_vector to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float is\n variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if arg'length < 1 then\n return NAFP;\n end if;\n fpvar := UNRESOLVED_float(arg);\n return fpvar;\n end function to_float;\n\n -- purpose: converts a ufixed to a floating point\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n constant exponent_width : NATURAL := float_exponent_width; -- width of exponent\n constant fraction_width : NATURAL := float_fraction_width; -- width of fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float is\n variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- function to_float\n if (arg'length < 1) then\n return NAFP;\n end if;\n sarg (arg'range) := sfixed (arg);\n sarg (sarg'high) := '0';\n result := to_float (arg => sarg,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end function to_float;\n\n function to_float (\n arg : UNRESOLVED_sfixed; -- signed fixed point\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float is\n constant integer_width : INTEGER := arg'high;\n constant in_fraction_width : INTEGER := arg'low;\n variable xresult : sfixed (integer_width downto in_fraction_width);\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arg_int : UNSIGNED(integer_width - in_fraction_width\n downto 0); -- unsigned version of argument\n variable argx : SIGNED (integer_width - in_fraction_width downto 0);\n variable exp, exptmp : SIGNED (exponent_width downto 0);\n variable expon : UNSIGNED (exponent_width - 1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=\n (others => '0');\n variable round : BOOLEAN := false;\n begin\n if (arg'length < 1) then\n return NAFP;\n end if;\n xresult := to_01(arg, 'X');\n argx := SIGNED(to_slv(xresult));\n if (Is_X (arg)) then\n result := (others => 'X');\n elsif (argx = 0) then\n result := (others => '0');\n else\n result := (others => '0'); -- zero out the result\n if argx(argx'left) = '1' then -- toss the sign bit\n result (exponent_width) := '1'; -- Negative number\n arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement\n else\n result (exponent_width) := '0';\n arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned\n end if;\n -- Compute Exponent\n exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2\n if exp + in_fraction_width > expon_base then -- return infinity\n result (-1 downto -fraction_width) := (others => '0');\n result (exponent_width -1 downto 0) := (others => '1');\n return result;\n elsif (denormalize and\n (exp + in_fraction_width <= -resize(expon_base, exp'length))) then\n exp := -resize(expon_base, exp'length);\n -- shift by a constant\n arg_int := shift_left (arg_int,\n (arg_int'high + to_integer(expon_base)\n + in_fraction_width - 1));\n if (arg_int'high > fraction_width) then\n fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));\n round := check_round (\n fract_in => arg_int(arg_int'high-fraction_width),\n sign => result(result'high),\n remainder => arg_int((arg_int'high-fraction_width-1)\n downto 0),\n round_style => round_style);\n if (round) then\n fp_round (fract_in => arg_int (arg_int'high-1 downto\n (arg_int'high-fraction_width)),\n expon_in => exp,\n fract_out => fract,\n expon_out => exptmp);\n exp := exptmp;\n end if;\n else\n fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=\n arg_int (arg_int'high-1 downto 0);\n end if;\n else\n arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));\n exp := exp + in_fraction_width;\n if (arg_int'high > fraction_width) then\n fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));\n round := check_round (\n fract_in => fract(0),\n sign => result(result'high),\n remainder => arg_int((arg_int'high-fraction_width-1)\n downto 0),\n round_style => round_style);\n if (round) then\n fp_round (fract_in => fract,\n expon_in => exp,\n fract_out => fracttmp,\n expon_out => exptmp);\n fract := fracttmp;\n exp := exptmp;\n end if;\n else\n fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=\n arg_int (arg_int'high-1 downto 0);\n end if;\n end if;\n expon := UNSIGNED (resize(exp-1, exponent_width));\n expon(exponent_width-1) := not expon(exponent_width-1);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n end if;\n return result;\n end function to_float;\n\n -- size_res functions\n -- Integer to float\n function to_float (\n arg : INTEGER;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style);\n return result;\n end if;\n end function to_float;\n\n -- real to float\n function to_float (\n arg : REAL;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end if;\n end function to_float;\n\n -- unsigned to float\n function to_float (\n arg : UNSIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style);\n return result;\n end if;\n end function to_float;\n\n -- signed to float\n function to_float (\n arg : SIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style);\n return result;\n end if;\n end function to_float;\n\n -- std_ulogic_vector to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n return result;\n end if;\n end function to_float;\n\n -- unsigned fixed point to float\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end if;\n end function to_float;\n\n -- signed fixed point to float\n function to_float (\n arg : UNRESOLVED_sfixed;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end if;\n end function to_float;\n\n -- to_integer (float)\n function to_integer (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return INTEGER is\n variable validfp : valid_fpstate; -- Valid FP state\n variable frac : UNSIGNED (-arg'low downto 0); -- Fraction\n variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction\n variable expon : SIGNED (arg'high-1 downto 0);\n variable isign : STD_ULOGIC; -- internal version of sign\n variable round : STD_ULOGIC; -- is rounding needed?\n variable result : INTEGER;\n variable base : INTEGER; -- Integer exponent\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>\n result := 0; -- return 0\n when pos_inf =>\n result := INTEGER'high;\n when neg_inf =>\n result := INTEGER'low;\n when others =>\n break_number (\n arg => arg,\n fptyp => validfp,\n denormalize => false,\n fract => frac,\n expon => expon);\n fract (fract'high) := '0'; -- Add extra bit for 0.6 case\n fract (fract'high-1 downto 0) := frac;\n isign := to_x01 (arg (arg'high));\n base := to_integer (expon) + 1;\n if base < -1 then\n result := 0;\n elsif base >= frac'high then\n result := to_integer (fract) * 2**(base - frac'high);\n else -- We need to round\n if base = -1 then -- trap for 0.6 case.\n result := 0;\n else\n result := to_integer (fract (frac'high downto frac'high-base));\n end if;\n -- rounding routine\n case round_style is\n when round_nearest =>\n if frac'high - base > 1 then\n round := fract (frac'high - base - 1) and\n (fract (frac'high - base)\n or (or_reduce (fract (frac'high - base - 2 downto 0))));\n else\n round := fract (frac'high - base - 1) and\n fract (frac'high - base);\n end if;\n when round_inf =>\n round := fract(frac'high - base - 1) and not isign;\n when round_neginf =>\n round := fract(frac'high - base - 1) and isign;\n when others =>\n round := '0';\n end case;\n if round = '1' then\n result := result + 1;\n end if;\n end if;\n if isign = '1' then\n result := - result;\n end if;\n end case classcase;\n return result;\n end function to_integer;\n\n -- to_unsigned (float)\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED is\n variable validfp : valid_fpstate; -- Valid FP state\n variable frac : UNSIGNED (size-1 downto 0); -- Fraction\n variable sign : STD_ULOGIC; -- not used\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n frac := (others => 'X');\n when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>\n frac := (others => '0'); -- return 0\n when pos_inf =>\n frac := (others => '1');\n when others =>\n float_to_unsigned (\n arg => arg,\n frac => frac,\n sign => sign,\n denormalize => false,\n bias => 0,\n round_style => round_style);\n end case classcase;\n return (frac);\n end function to_unsigned;\n\n -- to_signed (float)\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED is\n variable sign : STD_ULOGIC; -- true if negative\n variable validfp : valid_fpstate; -- Valid FP state\n variable frac : UNSIGNED (size-1 downto 0); -- Fraction\n variable result : SIGNED (size-1 downto 0);\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n result := (others => 'X');\n when pos_zero | neg_zero | pos_denormal | neg_denormal =>\n result := (others => '0'); -- return 0\n when pos_inf =>\n result := (others => '1');\n result (result'high) := '0';\n when neg_inf =>\n result := (others => '0');\n result (result'high) := '1';\n when others =>\n float_to_unsigned (\n arg => arg,\n sign => sign,\n frac => frac,\n denormalize => false,\n bias => 0,\n round_style => round_style);\n result (size-1) := '0';\n result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));\n if sign = '1' then\n -- Because the most negative signed number is 1 less than the most\n -- positive signed number, we need this code.\n if frac(frac'high) = '1' then -- return most negative number\n result := (others => '0');\n result (result'high) := '1';\n else\n result := -result;\n end if;\n else\n if frac(frac'high) = '1' then -- return most positive number\n result := (others => '1');\n result (result'high) := '0';\n end if;\n end if;\n end case classcase;\n return result;\n end function to_signed;\n\n -- purpose: Converts a float to ufixed\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed is\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n constant size : INTEGER := left_index - right_index + 4; -- unsigned size\n variable expon_base : INTEGER; -- exponent offset\n variable validfp : valid_fpstate; -- Valid FP state\n variable exp : INTEGER; -- Exponent\n variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent\n -- Base to divide fraction by\n variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction\n variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted\n variable shift : INTEGER;\n variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);\n variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result\n begin -- function to_ufixed\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n frac := (others => 'X');\n when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>\n frac := (others => '0'); -- return 0\n when pos_inf =>\n frac := (others => '1'); -- always saturate\n when others =>\n expon_base := 2**(exponent_width-1) -1; -- exponent offset\n -- Figure out the fraction\n if (validfp = pos_denormal) and denormalize then\n exp := -expon_base +1;\n frac (frac'high) := '0'; -- Remove the \"1.0\".\n else\n -- exponent /= '0', normal floating point\n expon := UNSIGNED(arg (exponent_width-1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (SIGNED(expon)) +1;\n frac (frac'high) := '1'; -- Add the \"1.0\".\n end if;\n shift := (frac'high - 3 + right_index) - exp;\n if fraction_width > frac'high then -- Can only use size-2 bits\n frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto\n -frac'high)));\n else -- can use all bits\n frac (frac'high-1 downto frac'high-fraction_width) :=\n UNSIGNED (to_slv (arg(-1 downto -fraction_width)));\n end if;\n frac_shift := frac srl shift;\n if shift < 0 then -- Overflow\n frac := (others => '1');\n else\n frac := frac_shift;\n end if;\n end case classcase;\n result_big := to_ufixed (\n arg => STD_ULOGIC_VECTOR(frac),\n left_index => left_index,\n right_index => (right_index-3));\n result := resize (arg => result_big,\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end function to_ufixed;\n\n -- purpose: Converts a float to sfixed\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed is\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n constant size : INTEGER := left_index - right_index + 4; -- unsigned size\n variable expon_base : INTEGER; -- exponent offset\n variable validfp : valid_fpstate; -- Valid FP state\n variable exp : INTEGER; -- Exponent\n variable sign : BOOLEAN; -- true if negative\n variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent\n -- Base to divide fraction by\n variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction\n variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted\n variable shift : INTEGER;\n variable rsigned : SIGNED (size-1 downto 0); -- signed version of result\n variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);\n variable result : UNRESOLVED_sfixed (left_index downto right_index)\n := (others => '0'); -- result\n begin -- function to_sfixed\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n result := (others => 'X');\n when pos_zero | neg_zero =>\n result := (others => '0'); -- return 0\n when neg_inf =>\n result (left_index) := '1'; -- return smallest negative number\n when pos_inf =>\n result := (others => '1'); -- return largest number\n result (left_index) := '0';\n when others =>\n expon_base := 2**(exponent_width-1) -1; -- exponent offset\n if arg(exponent_width) = '0' then\n sign := false;\n else\n sign := true;\n end if;\n -- Figure out the fraction\n if (validfp = pos_denormal or validfp = neg_denormal)\n and denormalize then\n exp := -expon_base +1;\n frac (frac'high) := '0'; -- Add the \"1.0\".\n else\n -- exponent /= '0', normal floating point\n expon := UNSIGNED(arg (exponent_width-1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (SIGNED(expon)) +1;\n frac (frac'high) := '1'; -- Add the \"1.0\".\n end if;\n shift := (frac'high - 3 + right_index) - exp;\n if fraction_width > frac'high then -- Can only use size-2 bits\n frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto\n -frac'high)));\n else -- can use all bits\n frac (frac'high-1 downto frac'high-fraction_width) :=\n UNSIGNED (to_slv (arg(-1 downto -fraction_width)));\n end if;\n frac_shift := frac srl shift;\n if shift < 0 then -- Overflow\n frac := (others => '1');\n else\n frac := frac_shift;\n end if;\n if not sign then\n rsigned := SIGNED(\"0\" & frac);\n else\n rsigned := -(SIGNED(\"0\" & frac));\n end if;\n result_big := to_sfixed (\n arg => STD_LOGIC_VECTOR(rsigned),\n left_index => left_index,\n right_index => (right_index-3));\n result := resize (arg => result_big,\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n end case classcase;\n return result;\n end function to_sfixed;\n\n -- size_res versions\n -- float to unsigned\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n size_res : UNSIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED is\n variable result : UNSIGNED (size_res'range);\n begin\n if (SIZE_RES'length = 0) then\n return result;\n else\n result := to_unsigned (\n arg => arg,\n size => size_res'length,\n round_style => round_style,\n check_error => check_error);\n return result;\n end if;\n end function to_unsigned;\n\n -- float to signed\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n size_res : SIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED is\n variable result : SIGNED (size_res'range);\n begin\n if (SIZE_RES'length = 0) then\n return result;\n else\n result := to_signed (\n arg => arg,\n size => size_res'length,\n round_style => round_style,\n check_error => check_error);\n return result;\n end if;\n end function to_signed;\n\n -- purpose: Converts a float to unsigned fixed point\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_ufixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_ufixed (\n arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style,\n check_error => check_error,\n denormalize => denormalize);\n return result;\n end if;\n end function to_ufixed;\n\n -- float to signed fixed point\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_sfixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_sfixed (\n arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style,\n check_error => check_error,\n denormalize => denormalize);\n return result;\n end if;\n end function to_sfixed;\n\n -- to_real (float)\n -- typically not Synthesizable unless the input is a constant.\n function to_real (\n arg : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return REAL is\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n variable sign : REAL; -- Sign, + or - 1\n variable exp : INTEGER; -- Exponent\n variable expon_base : INTEGER; -- exponent offset\n variable frac : REAL := 0.0; -- Fraction\n variable validfp : valid_fpstate; -- Valid FP state\n variable expon : UNSIGNED (exponent_width - 1 downto 0)\n := (others => '1'); -- Vectorized exponent\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | pos_zero | neg_zero | nan | quiet_nan =>\n return 0.0;\n when neg_inf =>\n return REAL'low; -- Negative infinity.\n when pos_inf =>\n return REAL'high; -- Positive infinity\n when others =>\n expon_base := 2**(exponent_width-1) -1;\n if to_X01(arg(exponent_width)) = '0' then\n sign := 1.0;\n else\n sign := -1.0;\n end if;\n -- Figure out the fraction\n for i in 0 to fraction_width-1 loop\n if to_X01(arg (-1 - i)) = '1' then\n frac := frac + (2.0 **(-1 - i));\n end if;\n end loop; -- i\n if validfp = pos_normal or validfp = neg_normal or not denormalize then\n -- exponent /= '0', normal floating point\n expon := UNSIGNED(arg (exponent_width-1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (SIGNED(expon)) +1;\n sign := sign * (2.0 ** exp) * (1.0 + frac);\n else -- exponent = '0', IEEE extended floating point\n exp := 1 - expon_base;\n sign := sign * (2.0 ** exp) * frac;\n end if;\n return sign;\n end case classcase;\n end function to_real;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is\n variable result : float64; -- 64 bit floating point\n begin\n result := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_sulv (result);\n end function realtobits;\n\n function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is\n variable arg64 : float64; -- arg converted to float\n begin\n arg64 := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_real (arg64);\n end function bitstoreal;\n\n -- purpose: Removes meta-logical values from FP string\n function to_01 (\n arg : UNRESOLVED_float; -- floating point input\n XMAP : STD_LOGIC := '0')\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin -- function to_01\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_01: null detected, returning NULL\"\n severity warning;\n return NAFP;\n end if;\n result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));\n return result;\n end function to_01;\n\n function Is_X\n (arg : UNRESOLVED_float)\n return BOOLEAN is\n begin\n return Is_X (to_slv(arg));\n end function Is_X;\n\n function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_X01: null detected, returning NULL\"\n severity warning;\n return NAFP;\n else\n result := UNRESOLVED_float (to_X01(to_slv(arg)));\n return result;\n end if;\n end function to_X01;\n\n function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_X01Z: null detected, returning NULL\"\n severity warning;\n return NAFP;\n else\n result := UNRESOLVED_float (to_X01Z(to_slv(arg)));\n return result;\n end if;\n end function to_X01Z;\n\n function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_UX01: null detected, returning NULL\"\n severity warning;\n return NAFP;\n else\n result := UNRESOLVED_float (to_UX01(to_slv(arg)));\n return result;\n end if;\n end function to_UX01;\n\n -- These allows the base math functions to use the default values\n -- of their parameters. Thus they do full IEEE floating point.\n function \"+\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return add (l, r);\n end function \"+\";\n\n function \"-\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return subtract (l, r);\n end function \"-\";\n\n function \"*\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return multiply (l, r);\n end function \"*\";\n\n function \"/\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return divide (l, r);\n end function \"/\";\n\n function \"rem\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return remainder (l, r);\n end function \"rem\";\n\n function \"mod\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return modulo (l, r);\n end function \"mod\";\n\n -- overloaded versions\n function \"+\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return add (l, r_float);\n end function \"+\";\n\n function \"+\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return add (l_float, r);\n end function \"+\";\n\n function \"+\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return add (l, r_float);\n end function \"+\";\n\n function \"+\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return add (l_float, r);\n end function \"+\";\n\n function \"-\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return subtract (l, r_float);\n end function \"-\";\n\n function \"-\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return subtract (l_float, r);\n end function \"-\";\n\n function \"-\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return subtract (l, r_float);\n end function \"-\";\n\n function \"-\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return subtract (l_float, r);\n end function \"-\";\n\n function \"*\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return multiply (l, r_float);\n end function \"*\";\n\n function \"*\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return multiply (l_float, r);\n end function \"*\";\n\n function \"*\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return multiply (l, r_float);\n end function \"*\";\n\n function \"*\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return multiply (l_float, r);\n end function \"*\";\n\n function \"/\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return divide (l, r_float);\n end function \"/\";\n\n function \"/\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return divide (l_float, r);\n end function \"/\";\n\n function \"/\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return divide (l, r_float);\n end function \"/\";\n\n function \"/\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return divide (l_float, r);\n end function \"/\";\n\n function \"rem\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return remainder (l, r_float);\n end function \"rem\";\n\n function \"rem\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return remainder (l_float, r);\n end function \"rem\";\n\n function \"rem\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return remainder (l, r_float);\n end function \"rem\";\n\n function \"rem\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return remainder (l_float, r);\n end function \"rem\";\n\n function \"mod\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return modulo (l, r_float);\n end function \"mod\";\n\n function \"mod\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return modulo (l_float, r);\n end function \"mod\";\n\n function \"mod\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return modulo (l, r_float);\n end function \"mod\";\n\n function \"mod\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return modulo (l_float, r);\n end function \"mod\";\n\n function \"=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return eq (l, r_float);\n end function \"=\";\n\n function \"/=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ne (l, r_float);\n end function \"/=\";\n\n function \">=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ge (l, r_float);\n end function \">=\";\n\n function \"<=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return le (l, r_float);\n end function \"<=\";\n\n function \">\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return gt (l, r_float);\n end function \">\";\n\n function \"<\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return lt (l, r_float);\n end function \"<\";\n\n function \"=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return eq (l_float, r);\n end function \"=\";\n\n function \"/=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ne (l_float, r);\n end function \"/=\";\n\n function \">=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ge (l_float, r);\n end function \">=\";\n\n function \"<=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return le (l_float, r);\n end function \"<=\";\n\n function \">\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return gt (l_float, r);\n end function \">\";\n\n function \"<\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return lt (l_float, r);\n end function \"<\";\n\n function \"=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return eq (l, r_float);\n end function \"=\";\n\n function \"/=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ne (l, r_float);\n end function \"/=\";\n\n function \">=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ge (l, r_float);\n end function \">=\";\n\n function \"<=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return le (l, r_float);\n end function \"<=\";\n\n function \">\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return gt (l, r_float);\n end function \">\";\n\n function \"<\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return lt (l, r_float);\n end function \"<\";\n\n function \"=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return eq (l_float, r);\n end function \"=\";\n\n function \"/=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ne (l_float, r);\n end function \"/=\";\n\n function \">=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ge (l_float, r);\n end function \">=\";\n\n function \"<=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return le (l_float, r);\n end function \"<=\";\n\n function \">\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return gt (l_float, r);\n end function \">\";\n\n function \"<\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return lt (l_float, r);\n end function \"<\";\n\n -- ?= overloads\n function \\?=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?=\\ (l, r_float);\n end function \\?=\\;\n\n function \\?/=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?/=\\ (l, r_float);\n end function \\?/=\\;\n\n function \\?>\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>\\ (l, r_float);\n end function \\?>\\;\n\n function \\?>=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>=\\ (l, r_float);\n end function \\?>=\\;\n\n function \\?<\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<\\ (l, r_float);\n end function \\?<\\;\n\n function \\?<=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<=\\ (l, r_float);\n end function \\?<=\\;\n\n -- real and float\n function \\?=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?=\\ (l_float, r);\n end function \\?=\\;\n\n function \\?/=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?/=\\ (l_float, r);\n end function \\?/=\\;\n\n function \\?>\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>\\ (l_float, r);\n end function \\?>\\;\n\n function \\?>=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>=\\ (l_float, r);\n end function \\?>=\\;\n\n function \\?<\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<\\ (l_float, r);\n end function \\?<\\;\n\n function \\?<=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<=\\ (l_float, r);\n end function \\?<=\\;\n\n -- ?= overloads\n function \\?=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?=\\ (l, r_float);\n end function \\?=\\;\n\n function \\?/=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?/=\\ (l, r_float);\n end function \\?/=\\;\n\n function \\?>\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>\\ (l, r_float);\n end function \\?>\\;\n\n function \\?>=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>=\\ (l, r_float);\n end function \\?>=\\;\n\n function \\?<\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<\\ (l, r_float);\n end function \\?<\\;\n\n function \\?<=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<=\\ (l, r_float);\n end function \\?<=\\;\n\n -- integer and float\n function \\?=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?=\\ (l_float, r);\n end function \\?=\\;\n\n function \\?/=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?/=\\ (l_float, r);\n end function \\?/=\\;\n\n function \\?>\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>\\ (l_float, r);\n end function \\?>\\;\n\n function \\?>=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>=\\ (l_float, r);\n end function \\?>=\\;\n\n function \\?<\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<\\ (l_float, r);\n end function \\?<\\;\n\n function \\?<=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<=\\ (l_float, r);\n end function \\?<=\\;\n\n -- minimum and maximum overloads\n function minimum (l : UNRESOLVED_float; r : REAL)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return minimum (l, r_float);\n end function minimum;\n\n function maximum (l : UNRESOLVED_float; r : REAL)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return maximum (l, r_float);\n end function maximum;\n\n function minimum (l : REAL; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return minimum (l_float, r);\n end function minimum;\n\n function maximum (l : REAL; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return maximum (l_float, r);\n end function maximum;\n\n function minimum (l : UNRESOLVED_float; r : INTEGER)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return minimum (l, r_float);\n end function minimum;\n\n function maximum (l : UNRESOLVED_float; r : INTEGER)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return maximum (l, r_float);\n end function maximum;\n\n function minimum (l : INTEGER; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return minimum (l_float, r);\n end function minimum;\n\n function maximum (l : INTEGER; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return maximum (l_float, r);\n end function maximum;\n\n ----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n function \"not\" (L : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n RESULT := not to_sulv(L);\n return to_float (RESULT, L'high, -L'low);\n end function \"not\";\n\n function \"and\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) and to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"and\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"and\";\n\n function \"or\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) or to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"or\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"or\";\n\n function \"nand\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nand to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"nand\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"nand\";\n\n function \"nor\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nor to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"nor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"nor\";\n\n function \"xor\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xor to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"xor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"xor\";\n\n function \"xnor\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xnor to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"xnor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"xnor\";\n\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L and R(i);\n end loop;\n return result;\n end function \"and\";\n\n function \"and\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) and R;\n end loop;\n return result;\n end function \"and\";\n\n function \"or\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L or R(i);\n end loop;\n return result;\n end function \"or\";\n\n function \"or\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) or R;\n end loop;\n return result;\n end function \"or\";\n\n function \"nand\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L nand R(i);\n end loop;\n return result;\n end function \"nand\";\n\n function \"nand\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nand R;\n end loop;\n return result;\n end function \"nand\";\n\n function \"nor\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L nor R(i);\n end loop;\n return result;\n end function \"nor\";\n\n function \"nor\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nor R;\n end loop;\n return result;\n end function \"nor\";\n\n function \"xor\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L xor R(i);\n end loop;\n return result;\n end function \"xor\";\n\n function \"xor\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xor R;\n end loop;\n return result;\n end function \"xor\";\n\n function \"xnor\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L xnor R(i);\n end loop;\n return result;\n end function \"xnor\";\n\n function \"xnor\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xnor R;\n end loop;\n return result;\n end function \"xnor\";\n\n -- Reduction operator_reduces, same as numeric_std functions\n\n function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return and_reduce (to_sulv(l));\n end function and_reduce;\n\n function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return nand_reduce (to_sulv(l));\n end function nand_reduce;\n\n function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return or_reduce (to_sulv(l));\n end function or_reduce;\n\n function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return nor_reduce (to_sulv(l));\n end function nor_reduce;\n\n function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return xor_reduce (to_sulv(l));\n end function xor_reduce;\n\n function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return xnor_reduce (to_sulv(l));\n end function xnor_reduce;\n\n -----------------------------------------------------------------------------\n -- Recommended Functions from the IEEE 754 Appendix\n -----------------------------------------------------------------------------\n -- returns x with the sign of y.\n function Copysign (\n x, y : UNRESOLVED_float) -- floating point input\n return UNRESOLVED_float is\n begin\n return y(y'high) & x (x'high-1 downto x'low);\n end function Copysign;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : INTEGER; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction\n constant exponent_width : NATURAL := y'high; -- length of FP output exponent\n variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument\n variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp\n variable exp : SIGNED (exponent_width downto 0);\n variable ufract : UNSIGNED (fraction_width downto 0);\n constant expon_base : SIGNED (exponent_width-1 downto 0)\n := gen_expon_base(exponent_width); -- exponent offset\n variable fptype : valid_fpstate;\n begin\n -- This can be done by simply adding N to the exponent.\n arg := to_01 (y, 'X');\n fptype := classfp(arg, check_error);\n classcase : case fptype is\n when isx =>\n result := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n result := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when others =>\n break_number (\n arg => arg,\n fptyp => fptype,\n denormalize => denormalize,\n fract => ufract,\n expon => expon);\n exp := resize (expon, exp'length) + N;\n result := normalize (\n fract => ufract,\n expon => exp,\n sign => to_x01 (arg (arg'high)),\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => 0);\n end case classcase;\n return result;\n end function Scalb;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : SIGNED; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable n_int : INTEGER;\n begin\n n_int := to_integer(N);\n return Scalb (y => y,\n N => n_int,\n round_style => round_style,\n check_error => check_error,\n denormalize => denormalize);\n end function Scalb;\n\n -- returns the unbiased exponent of x\n function Logb (\n x : UNRESOLVED_float) -- floating point input\n return INTEGER is\n constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction\n constant exponent_width : NATURAL := x'high; -- length of FP output exponent\n variable result : INTEGER; -- result\n variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument\n variable expon : SIGNED (exponent_width - 1 downto 0);\n variable fract : UNSIGNED (fraction_width downto 0);\n constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent\n -- offset +1\n variable fptype : valid_fpstate;\n begin\n -- Just return the exponent.\n arg := to_01 (x, 'X');\n fptype := classfp(arg);\n classcase : case fptype is\n when isx | nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n result := 0;\n when pos_denormal | neg_denormal =>\n fract (fraction_width) := '0';\n fract (fraction_width-1 downto 0) :=\n UNSIGNED (to_slv(arg(-1 downto -fraction_width)));\n result := find_leftmost (fract, '1') -- Find the first \"1\"\n - fraction_width; -- subtract the length we want\n result := -expon_base + 1 + result;\n when others =>\n expon := SIGNED(arg (exponent_width - 1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n expon := expon + 1;\n result := to_integer (expon);\n end case classcase;\n return result;\n end function Logb;\n\n -- returns the unbiased exponent of x\n function Logb (\n x : UNRESOLVED_float) -- floating point input\n return SIGNED is\n constant exponent_width : NATURAL := x'high; -- length of FP output exponent\n variable result : SIGNED (exponent_width - 1 downto 0); -- result\n begin\n -- Just return the exponent.\n result := to_signed (Logb (x), exponent_width);\n return result;\n end function Logb;\n\n -- returns the next representable neighbor of x in the direction toward y\n function Nextafter (\n x, y : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction\n constant exponent_width : NATURAL := x'high; -- length of FP output exponent\n function \"=\" (\n l, r : UNRESOLVED_float) -- inputs\n return BOOLEAN is\n begin -- function \"=\"\n return eq (l => l,\n r => r,\n check_error => false);\n end function \"=\";\n function \">\" (\n l, r : UNRESOLVED_float) -- inputs\n return BOOLEAN is\n begin -- function \">\"\n return gt (l => l,\n r => r,\n check_error => false);\n end function \">\";\n variable fract : UNSIGNED (fraction_width-1 downto 0);\n variable expon : UNSIGNED (exponent_width-1 downto 0);\n variable sign : STD_ULOGIC;\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable validfpx, validfpy : valid_fpstate; -- Valid FP state\n begin -- fp_Nextafter\n -- If Y > X, add one to the fraction, otherwise subtract.\n validfpx := classfp (x, check_error);\n validfpy := classfp (y, check_error);\n if validfpx = isx or validfpy = isx then\n result := (others => 'X');\n return result;\n elsif (validfpx = nan or validfpy = nan) then\n return nanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (validfpx = quiet_nan or validfpy = quiet_nan) then\n return qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif x = y then -- Return X\n return x;\n else\n fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction\n expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent\n sign := x(exponent_width); -- sign bit\n if (y > x) then\n -- Increase the number given\n if validfpx = neg_inf then\n -- return most negative number\n expon := (others => '1');\n expon (0) := '0';\n fract := (others => '1');\n elsif validfpx = pos_zero or validfpx = neg_zero then\n -- return smallest denormal number\n sign := '0';\n expon := (others => '0');\n fract := (others => '0');\n fract(0) := '1';\n elsif validfpx = pos_normal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n if and_reduce (expon (exponent_width-1 downto 1)) = '1'\n and expon (0) = '0' then\n -- Exponent is one away from infinity.\n assert NO_WARNING\n report float_pkg'instance_name\n & \"FP_NEXTAFTER: NextAfter overflow\"\n severity warning;\n return pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n expon := expon + 1;\n fract := (others => '0');\n end if;\n else\n fract := fract + 1;\n end if;\n elsif validfpx = pos_denormal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n -- return smallest possible normal number\n expon := (others => '0');\n expon(0) := '1';\n fract := (others => '0');\n else\n fract := fract + 1;\n end if;\n elsif validfpx = neg_normal then\n if or_reduce (fract) = '0' then -- fraction is all \"0\".\n if or_reduce (expon (exponent_width-1 downto 1)) = '0' and\n expon (0) = '1' then -- Smallest exponent\n -- return the largest negative denormal number\n expon := (others => '0');\n fract := (others => '1');\n else\n expon := expon - 1;\n fract := (others => '1');\n end if;\n else\n fract := fract - 1;\n end if;\n elsif validfpx = neg_denormal then\n if or_reduce (fract(fract'high downto 1)) = '0'\n and fract (0) = '1' then -- Smallest possible fraction\n return zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n fract := fract - 1;\n end if;\n end if;\n else\n -- Decrease the number\n if validfpx = pos_inf then\n -- return most positive number\n expon := (others => '1');\n expon (0) := '0';\n fract := (others => '1');\n elsif validfpx = pos_zero\n or classfp (x) = neg_zero then\n -- return smallest negative denormal number\n sign := '1';\n expon := (others => '0');\n fract := (others => '0');\n fract(0) := '1';\n elsif validfpx = neg_normal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n if and_reduce (expon (exponent_width-1 downto 1)) = '1'\n and expon (0) = '0' then\n -- Exponent is one away from infinity.\n assert NO_WARNING\n report float_pkg'instance_name\n & \"FP_NEXTAFTER: NextAfter overflow\"\n severity warning;\n return neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n expon := expon + 1; -- Fraction overflow\n fract := (others => '0');\n end if;\n else\n fract := fract + 1;\n end if;\n elsif validfpx = neg_denormal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n -- return smallest possible normal number\n expon := (others => '0');\n expon(0) := '1';\n fract := (others => '0');\n else\n fract := fract + 1;\n end if;\n elsif validfpx = pos_normal then\n if or_reduce (fract) = '0' then -- fraction is all \"0\".\n if or_reduce (expon (exponent_width-1 downto 1)) = '0' and\n expon (0) = '1' then -- Smallest exponent\n -- return the largest positive denormal number\n expon := (others => '0');\n fract := (others => '1');\n else\n expon := expon - 1;\n fract := (others => '1');\n end if;\n else\n fract := fract - 1;\n end if;\n elsif validfpx = pos_denormal then\n if or_reduce (fract(fract'high downto 1)) = '0'\n and fract (0) = '1' then -- Smallest possible fraction\n return zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n fract := fract - 1;\n end if;\n end if;\n end if;\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);\n result (exponent_width) := sign;\n return result;\n end if;\n end function Nextafter;\n\n -- Returns True if X is unordered with Y.\n function Unordered (\n x, y : UNRESOLVED_float) -- floating point input\n return BOOLEAN is\n variable lfptype, rfptype : valid_fpstate;\n begin\n lfptype := classfp (x);\n rfptype := classfp (y);\n if (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan or\n lfptype = isx or rfptype = isx) then\n return true;\n else\n return false;\n end if;\n end function Unordered;\n\n function Finite (\n x : UNRESOLVED_float)\n return BOOLEAN is\n variable fp_state : valid_fpstate; -- fp state\n begin\n fp_state := Classfp (x);\n if (fp_state = pos_inf) or (fp_state = neg_inf) then\n return true;\n else\n return false;\n end if;\n end function Finite;\n\n function Isnan (\n x : UNRESOLVED_float)\n return BOOLEAN is\n variable fp_state : valid_fpstate; -- fp state\n begin\n fp_state := Classfp (x);\n if (fp_state = nan) or (fp_state = quiet_nan) then\n return true;\n else\n return false;\n end if;\n end function Isnan;\n\n -- Function to return constants.\n function zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n return result;\n end function zerofp;\n\n function nanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width-1 downto 0) := (others => '1');\n -- Exponent all \"1\"\n result (-1) := '1'; -- MSB of Fraction \"1\"\n -- Note: From W. Khan \"IEEE Standard 754 for Binary Floating Point\"\n -- The difference between a signaling NAN and a quiet NAN is that\n -- the MSB of the Fraction is a \"1\" in a Signaling NAN, and is a\n -- \"0\" in a quiet NAN.\n return result;\n end function nanfp;\n\n function qnanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width-1 downto 0) := (others => '1');\n -- Exponent all \"1\"\n result (-fraction_width) := '1'; -- LSB of Fraction \"1\"\n -- (Could have been any bit)\n return result;\n end function qnanfp;\n\n function pos_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all \"1\"\n return result;\n end function pos_inffp;\n\n function neg_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width downto 0) := (others => '1'); -- top bits all \"1\"\n return result;\n end function neg_inffp;\n\n function neg_zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width) := '1';\n return result;\n end function neg_zerofp;\n\n -- size_res versions\n function zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return zerofp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function zerofp;\n\n function nanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return nanfp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function nanfp;\n\n function qnanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return qnanfp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function qnanfp;\n\n function pos_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return pos_inffp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function pos_inffp;\n\n function neg_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return neg_inffp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function neg_inffp;\n\n function neg_zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return neg_zerofp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function neg_zerofp;\n\n-- rtl_synthesis off\n-- pragma synthesis_off\n\n --%%% these functions are copied from std_logic_1164 (VHDL-200X edition)\n -- Textio functions\n -- purpose: writes float into a line (NOTE changed basetype)\n type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);\n type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;\n type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;\n type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;\n\n constant NBSP : CHARACTER := CHARACTER'val(160); -- space character\n constant MVL9_to_char : char_indexed_by_MVL9 := \"UX01ZWLH-\";\n constant char_to_MVL9 : MVL9_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');\n constant char_to_MVL9plus : MVL9plus_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);\n constant NUS : STRING(2 to 1) := (others => ' ');\n\n -- purpose: Skips white space\n procedure skip_whitespace (\n L : inout LINE) is\n variable readOk : BOOLEAN;\n variable c : CHARACTER;\n begin\n while L /= null and L.all'length /= 0 loop\n if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then\n read (l, c, readOk);\n else\n exit;\n end if;\n end loop;\n end procedure skip_whitespace;\n\n-- %%% Replicated textio functions\n function to_ostring (value : STD_LOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+2)/3;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);\n variable result : STRING(1 to ne);\n variable tri : STD_LOGIC_VECTOR(0 to 2);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n tri := To_X01Z(ivalue(3*i to 3*i+2));\n case tri is\n when o\"0\" => result(i+1) := '0';\n when o\"1\" => result(i+1) := '1';\n when o\"2\" => result(i+1) := '2';\n when o\"3\" => result(i+1) := '3';\n when o\"4\" => result(i+1) := '4';\n when o\"5\" => result(i+1) := '5';\n when o\"6\" => result(i+1) := '6';\n when o\"7\" => result(i+1) := '7';\n when \"ZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_ostring;\n ------------------------------------------------------------------- \n function to_hstring (value : STD_LOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+3)/4;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);\n variable result : STRING(1 to ne);\n variable quad : STD_LOGIC_VECTOR(0 to 3);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n quad := To_X01Z(ivalue(4*i to 4*i+3));\n case quad is\n when x\"0\" => result(i+1) := '0';\n when x\"1\" => result(i+1) := '1';\n when x\"2\" => result(i+1) := '2';\n when x\"3\" => result(i+1) := '3';\n when x\"4\" => result(i+1) := '4';\n when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n when x\"7\" => result(i+1) := '7';\n when x\"8\" => result(i+1) := '8';\n when x\"9\" => result(i+1) := '9';\n when x\"A\" => result(i+1) := 'A';\n when x\"B\" => result(i+1) := 'B';\n when x\"C\" => result(i+1) := 'C';\n when x\"D\" => result(i+1) := 'D';\n when x\"E\" => result(i+1) := 'E';\n when x\"F\" => result(i+1) := 'F';\n when \"ZZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_hstring;\n procedure Char2TriBits (C : CHARACTER;\n RESULT : out STD_LOGIC_VECTOR(2 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n when '4' => result := o\"4\"; good := true;\n when '5' => result := o\"5\"; good := true;\n when '6' => result := o\"6\"; good := true;\n when '7' => result := o\"7\"; good := true;\n when 'Z' => result := \"ZZZ\"; good := true;\n when 'X' => result := \"XXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report float_pkg'instance_name\n & \"OREAD Error: Read a '\" & c &\n \"', expected an Octal character (0-7).\"\n severity error;\n result := \"UUU\";\n good := false;\n end case;\n end procedure Char2TriBits;\n\n procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2TriBits(c, sv(3*i to 3*i+2), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- read into a null array\n end if;\n end procedure OREAD;\n\n -- Hex Read and Write procedures for STD_ULOGIC_VECTOR.\n -- Modified from the original to be more forgiving.\n\n procedure Char2QuadBits (C : CHARACTER;\n RESULT : out STD_LOGIC_VECTOR(3 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := x\"0\"; good := true;\n when '1' => result := x\"1\"; good := true;\n when '2' => result := x\"2\"; good := true;\n when '3' => result := x\"3\"; good := true;\n when '4' => result := x\"4\"; good := true;\n when '5' => result := x\"5\"; good := true;\n when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n when 'B' | 'b' => result := x\"B\"; good := true;\n when 'C' | 'c' => result := x\"C\"; good := true;\n when 'D' | 'd' => result := x\"D\"; good := true;\n when 'E' | 'e' => result := x\"E\"; good := true;\n when 'F' | 'f' => result := x\"F\"; good := true;\n when 'Z' => result := \"ZZZZ\"; good := true;\n when 'X' => result := \"XXXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report float_pkg'instance_name\n & \"HREAD Error: Read a '\" & c &\n \"', expected a Hex character (0-F).\"\n severity error;\n result := \"UUUU\";\n good := false;\n end case;\n end procedure Char2QuadBits;\n\n procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- Null input string, skips whitespace\n end if;\n end procedure HREAD;\n\n-- %%% END replicated textio functions\n\n -- purpose: Checks the punctuation in a line\n procedure check_punctuation (\n arg : in STRING;\n colon : out BOOLEAN; -- There was a colon in the line\n dot : out BOOLEAN; -- There was a dot in the line\n good : out BOOLEAN; -- True if enough characters found\n chars : in INTEGER) is\n -- Examples. Legal inputs are \"0000000\", \"0000.000\", \"0:000:000\"\n alias xarg : STRING (1 to arg'length) is arg; -- make it downto range\n variable icolon, idot : BOOLEAN; -- internal\n variable j : INTEGER := 0; -- charters read\n begin\n good := false;\n icolon := false;\n idot := false;\n for i in 1 to arg'length loop\n if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then\n exit;\n elsif xarg(i) = ':' then\n icolon := true;\n elsif xarg(i) = '.' then\n idot := true;\n elsif xarg (i) /= '_' then\n j := j + 1;\n end if;\n end loop;\n if j = chars then\n good := true; -- There are enough charactes to read\n end if;\n colon := icolon;\n if idot and icolon then\n dot := false;\n else\n dot := idot;\n end if;\n end procedure check_punctuation;\n\n -- purpose: Searches a line for a \":\" and replaces it with a \".\".\n procedure fix_colon (\n arg : inout STRING;\n chars : in integer) is\n alias xarg : STRING (1 to arg'length) is arg; -- make it downto range\n variable j : INTEGER := 0; -- charters read\n begin\n for i in 1 to arg'length loop\n if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then\n exit;\n elsif xarg(i) = ':' then\n xarg (i) := '.';\n elsif xarg (i) /= '_' then\n j := j + 1;\n end if;\n end loop;\n end procedure fix_colon;\n\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_float; -- floating point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n variable s : STRING(1 to value'high - value'low +3);\n variable sindx : INTEGER;\n begin -- function write\n s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));\n s(2) := ':';\n sindx := 3;\n for i in VALUE'high-1 downto 0 loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n s(sindx) := ':';\n sindx := sindx + 1;\n for i in -1 downto VALUE'low loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n WRITE (L, s, JUSTIFIED, FIELD);\n end procedure WRITE;\n\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is\n -- Possible data: 0:0000:0000000\n -- 000000000000\n variable c : CHARACTER;\n variable mv : UNRESOLVED_float (VALUE'range);\n variable readOk : BOOLEAN;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable i : INTEGER; -- index variable\n begin -- READ\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n READ (l, c, readOk);\n if VALUE'length > 0 then\n i := value'high;\n readloop : loop\n if readOk = false then -- Bail out if there was a bad read\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Error end of file encountered.\"\n severity error;\n return;\n elsif c = ' ' or c = CR or c = HT then -- reading done.\n if (i /= value'low) then\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Warning: Value truncated.\"\n severity warning;\n return;\n end if;\n elsif c = '_' then\n if i = value'high then -- Begins with an \"_\"\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then -- \"__\" detected\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n elsif c = ':' or c = '.' then -- separator, ignore\n if not (i = -1 or i = value'high-1) then\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Warning: Separator point does not match number format: '\"\n & c & \"' encountered at location \" & INTEGER'image(i) & \".\"\n severity warning;\n end if;\n lastu := false;\n elsif (char_to_MVL9plus(c) = error) then\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Error: Character '\" & c & \"' read, expected STD_ULOGIC literal.\"\n severity error;\n return;\n else\n mv (i) := char_to_MVL9(c);\n i := i - 1;\n if i < value'low then\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n READ (l, c, readOk);\n end loop readloop;\n end if;\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is\n -- Possible data: 0:0000:0000000\n -- 000000000000\n variable c : CHARACTER;\n variable mv : UNRESOLVED_float (VALUE'range);\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable i : INTEGER; -- index variable\n variable readOk : BOOLEAN;\n begin -- READ\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n READ (l, c, readOk);\n if VALUE'length > 0 then\n i := value'high;\n good := false;\n readloop : loop\n if readOk = false then -- Bail out if there was a bad read\n return;\n elsif c = ' ' or c = CR or c = HT then -- reading done\n return;\n elsif c = '_' then\n if i = 0 then -- Begins with an \"_\"\n return;\n elsif lastu then -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n elsif c = ':' or c = '.' then -- separator, ignore\n -- good := (i = -1 or i = value'high-1);\n lastu := false;\n elsif (char_to_MVL9plus(c) = error) then\n return;\n else\n mv (i) := char_to_MVL9(c);\n i := i - 1;\n if i < value'low then\n good := true;\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n READ (l, c, readOk);\n end loop readloop;\n else\n good := true; -- read into a null array\n end if;\n end procedure READ;\n\n procedure OWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0) is -- width of field\n begin\n WRITE (L => L,\n VALUE => to_ostring(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure OWRITE;\n\n procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is\n constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/3);\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"short string encounted: \" & L.all\n & \" needs to have \" & integer'image (ne/3)\n & \" valid octal characters.\"\n severity error;\n return;\n elsif dot then\n OREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n OREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif nybble (2 downto 1) /= \"00\" then\n report float_pkg'instance_name & \"OREAD: \"\n & \"Illegal sign bit STRING encounted \"\n severity error;\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/3); -- replaces the colon with a \".\".\n OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n OREAD (L, slv, ok);\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"Error encounted during read\"\n severity error;\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n report float_pkg'instance_name & \"OREAD: \"\n & \"Vector truncated.\"\n severity error;\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n end if;\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is\n constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n GOOD := false;\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/3);\n if not ok then\n return;\n elsif dot then\n OREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n OREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n return;\n elsif nybble (2 downto 1) /= \"00\" then\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/3); -- replaces the colon with a \".\".\n OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n OREAD (L, slv, ok);\n if not ok then\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n GOOD := true;\n end if;\n end procedure OREAD;\n\n procedure HWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0) is -- width of field\n begin\n WRITE (L => L,\n VALUE => to_hstring(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure HWRITE;\n\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is\n constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/4);\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"short string encounted: \" & L.all\n & \" needs to have \" & integer'image (ne/4)\n & \" valid hex characters.\"\n severity error;\n return;\n elsif dot then\n HREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n HREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif nybble (3 downto 1) /= \"000\" then\n report float_pkg'instance_name & \"HREAD: \"\n & \"Illegal sign bit STRING encounted \"\n severity error;\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/4); -- replaces the colon with a \".\".\n HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n HREAD (L, slv, ok);\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"Error encounted during read\"\n severity error;\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n report float_pkg'instance_name & \"HREAD: \"\n & \"Vector truncated.\"\n severity error;\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n end if;\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is\n constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n GOOD := false;\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/4);\n if not ok then\n return;\n elsif dot then\n HREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n HREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n return;\n elsif nybble (3 downto 1) /= \"000\" then\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/4); -- replaces the colon with a \".\".\n HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n HREAD (L, slv, ok);\n if not ok then\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n GOOD := true;\n end if;\n end procedure HREAD;\n\n function to_string (value : UNRESOLVED_float) return STRING is\n variable s : STRING(1 to value'high - value'low +3);\n variable sindx : INTEGER;\n begin -- function write\n s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));\n s(2) := ':';\n sindx := 3;\n for i in VALUE'high-1 downto 0 loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n s(sindx) := ':';\n sindx := sindx + 1;\n for i in -1 downto VALUE'low loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n return s;\n end function to_string;\n\n function to_hstring (value : UNRESOLVED_float) return STRING is\n variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);\n begin\n floop : for i in slv'range loop\n slv(i) := to_X01Z (value(i + value'low));\n end loop floop;\n return to_hstring (slv);\n end function to_hstring;\n\n function to_ostring (value : UNRESOLVED_float) return STRING is\n variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);\n begin\n floop : for i in slv'range loop\n slv(i) := to_X01Z (value(i + value'low));\n end loop floop;\n return to_ostring (slv);\n end function to_ostring;\n\n function from_string (\n bstring : STRING; -- binary string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(bstring);\n READ (L, result, good);\n deallocate (L);\n assert (good)\n report float_pkg'instance_name\n & \"from_string: Bad string \" & bstring\n severity error;\n return result;\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(ostring);\n OREAD (L, result, good);\n deallocate (L);\n assert (good)\n report float_pkg'instance_name\n & \"from_ostring: Bad string \" & ostring\n severity error;\n return result;\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(hstring);\n HREAD (L, result, good);\n deallocate (L);\n assert (good)\n report float_pkg'instance_name\n & \"from_hstring: Bad string \" & hstring\n severity error;\n return result;\n end function from_hstring;\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float is\n begin\n return from_string (bstring => bstring,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float is\n begin\n return from_ostring (ostring => ostring,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float is\n begin\n return from_hstring (hstring => hstring,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function from_hstring;\n-- rtl_synthesis on\n-- pragma synthesis_on\n function to_float (\n arg : STD_LOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float is\n begin\n return to_float (\n arg => to_stdulogicvector (arg),\n exponent_width => exponent_width,\n fraction_width => fraction_width);\n end function to_float;\n\n function to_float (\n arg : STD_LOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float is\n begin\n return to_float (\n arg => to_stdulogicvector (arg),\n size_res => size_res);\n end function to_float;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_LOGIC_VECTOR is\n variable result : float64; -- 64 bit floating point\n begin\n result := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_slv (result);\n end function realtobits;\n\n function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is\n variable arg64 : float64; -- arg converted to float\n begin\n arg64 := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_real (arg64);\n end function bitstoreal;\n\nend package body float_noround_pkg;\n", "groundtruth": " fpresult := neg_zerofp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when others =>\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/float_pkg_c.vhdl", "left_context": "-- --------------------------------------------------------------------\n-- \"float_pkg\" package contains functions for floating point math.\n-- Please see the documentation for the floating point package.\n-- This package should be compiled into \"ieee_proposed\" and used as follows:\n-- use ieee.std_logic_1164.all;\n-- use ieee.numeric_std.all;\n-- use ieee_proposed.fixed_float_types.all;\n-- use ieee_proposed.fixed_pkg.all;\n-- use ieee_proposed.float_pkg.all;\n--\n-- This verison is designed to work with the VHDL-93 compilers. Please\n-- note the \"%%%\" comments. These are where we diverge from the\n-- VHDL-200X LRM.\n--\n-- --------------------------------------------------------------------\n-- Version : $Revision: 2.2 $\n-- Date : $Date: 2010/09/22 18:26:46 $\n-- --------------------------------------------------------------------\n\nuse STD.TEXTIO.all;\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\nuse IEEE.NUMERIC_STD.all;\nlibrary ieee_proposed;\nuse ieee_proposed.fixed_float_types.all;\nuse ieee_proposed.fixed_pkg.all;\n\npackage float_pkg is\n-- generic (\n -- Defaults for sizing routines, when you do a \"to_float\" this will be\n -- the default size. Example float32 would be 8 and 23 (8 downto -23)\n constant float_exponent_width : NATURAL := 8;\n constant float_fraction_width : NATURAL := 23;\n -- Rounding algorithm, \"round_nearest\" is default, other valid values\n -- are \"round_zero\" (truncation), \"round_inf\" (round up), and\n -- \"round_neginf\" (round down)\n constant float_round_style : round_type := round_nearest;\n -- Denormal numbers (very small numbers near zero) true or false\n constant float_denormalize : BOOLEAN := true;\n -- Turns on NAN processing (invalid numbers and overflow) true of false\n constant float_check_error : BOOLEAN := true;\n -- Guard bits are added to the bottom of every operation for rounding.\n -- any natural number (including 0) are valid.\n constant float_guard_bits : NATURAL := 3;\n -- If TRUE, then turn off warnings on \"X\" propagation\n constant no_warning : BOOLEAN := (false\n );\n\n -- Author David Bishop (dbishop@vhdl.org)\n\n -- Note that the size of the vector is not defined here, but in\n -- the package which calls this one.\n type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type\n subtype U_float is UNRESOLVED_float;\n\n subtype float is UNRESOLVED_float;\n -----------------------------------------------------------------------------\n -- Use the float type to define your own floating point numbers.\n -- There must be a negative index or the packages will error out.\n -- Minimum supported is \"subtype float7 is float (3 downto -3);\"\n -- \"subtype float16 is float (6 downto -9);\" is probably the smallest\n -- practical one to use.\n -----------------------------------------------------------------------------\n\n -- IEEE 754 single precision\n subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);\n alias U_float32 is UNRESOLVED_float32;\n subtype float32 is float (8 downto -23);\n -----------------------------------------------------------------------------\n -- IEEE-754 single precision floating point. This is a \"float\"\n -- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and\n -- the fraction is 23 bits wide. This format can hold roughly 7 decimal\n -- digits. Infinity is 2**127 = 1.7E38 in this number system.\n -- The bit representation is as follows:\n -- 1 09876543 21098765432109876543210\n -- 8 76543210 12345678901234567890123\n -- 0 00000000 00000000000000000000000\n -- 8 7 0 -1 -23\n -- +/- exp. fraction\n -----------------------------------------------------------------------------\n\n -- IEEE 754 double precision\n subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);\n alias U_float64 is UNRESOLVED_float64;\n subtype float64 is float (11 downto -52);\n -----------------------------------------------------------------------------\n -- IEEE-754 double precision floating point. This is a \"double float\"\n -- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and\n -- the fraction is 52 bits wide. This format can hold roughly 15 decimal\n -- digits. Infinity is 2**2047 in this number system.\n -- The bit representation is as follows:\n -- 3 21098765432 1098765432109876543210987654321098765432109876543210\n -- 1 09876543210 1234567890123456789012345678901234567890123456789012\n -- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF\n -- 11 10 0 -1 -52\n -- +/- exponent fraction\n -----------------------------------------------------------------------------\n\n -- IEEE 854 & C extended precision\n subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);\n alias U_float128 is UNRESOLVED_float128;\n subtype float128 is float (15 downto -112);\n -----------------------------------------------------------------------------\n -- The 128 bit floating point number is \"long double\" in C (on\n -- some systems this is a 70 bit floating point number) and FLOAT*32\n -- in Fortran. The exponent is 15 bits wide and the fraction is 112\n -- bits wide. This number can handle approximately 33 decimal digits.\n -- Infinity is 2**32,767 in this number system.\n -----------------------------------------------------------------------------\n\n -- purpose: Checks for a valid floating point number\n type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)\n quiet_nan, -- Quiet NaN (C FP_NAN)\n neg_inf, -- Negative infinity (C FP_INFINITE)\n neg_normal, -- negative normalized nonzero\n neg_denormal, -- negative denormalized (FP_SUBNORMAL)\n neg_zero, -- -0 (C FP_ZERO)\n pos_zero, -- +0 (C FP_ZERO)\n pos_denormal, -- Positive denormalized (FP_SUBNORMAL)\n pos_normal, -- positive normalized nonzero\n pos_inf, -- positive infinity\n isx); -- at least one input is unknown\n\n -- This deferred constant will tell you if the package body is synthesizable\n -- or implemented as real numbers.\n constant fphdlsynth_or_real : BOOLEAN; -- deferred constant\n\n -- Returns the class which X falls into\n function Classfp (\n x : UNRESOLVED_float; -- floating point input\n check_error : BOOLEAN := float_check_error) -- check for errors\n return valid_fpstate;\n\n -- Arithmetic functions, these operators do not require parameters.\n function \"abs\" (arg : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (arg : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- These allows the base math functions to use the default values\n -- of their parameters. Thus they do full IEEE floating point.\n\n function \"+\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"*\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"/\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"rem\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"mod\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- Basic parameter list\n -- round_style - Selects the rounding algorithm to use\n -- guard - extra bits added to the end if the operation to add precision\n -- check_error - When \"false\" turns off NAN and overflow checks\n -- denormalize - When \"false\" turns off denormal number processing\n\n function add (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function subtract (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function multiply (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function divide (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function remainder (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function modulo (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- reciprocal\n function reciprocal (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function dividebyp2 (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- Multiply accumulate result = l*r + c\n function mac (\n l, r, c : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- Square root (all 754 based implementations need this)\n function sqrt (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style;\n constant guard : NATURAL := float_guard_bits;\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float;\n\n function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;\n\n -----------------------------------------------------------------------------\n -- compare functions\n -- =, /=, >=, <=, <, >, maximum, minimum\n\n function eq ( -- equal =\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function ne ( -- not equal /=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function lt ( -- less than <\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function gt ( -- greater than >\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function le ( -- less than or equal to <=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n function ge ( -- greater than or equal to >=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN;\n\n -- Need to overload the default versions of these\n function \"=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \"/=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \">=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \"<=\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \">\" (l, r : UNRESOLVED_float) return BOOLEAN;\n function \"<\" (l, r : UNRESOLVED_float) return BOOLEAN;\n\n function \\?=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?/=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<=\\ (l, r : UNRESOLVED_float) return STD_ULOGIC;\n\n function std_match (l, r : UNRESOLVED_float) return BOOLEAN;\n function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)\n return INTEGER;\n function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)\n return INTEGER;\n function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- conversion functions\n -- Converts one floating point number into another.\n\n function resize (\n arg : UNRESOLVED_float; -- Floating point input\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function resize (\n arg : UNRESOLVED_float; -- Floating point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n function to_float32 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float32;\n\n function to_float64 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float64;\n\n function to_float128 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float128;\n\n -- Converts an fp into an SLV (needed for synthesis)\n function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;\n alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];\n alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];\n\n -- Converts an fp into an std_ulogic_vector (sulv)\n function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;\n alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];\n alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];\n\n -- std_ulogic_vector to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float;\n\n -- Integer to float\n function to_float (\n arg : INTEGER;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- real to float\n function to_float (\n arg : REAL;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- unsigned to float\n function to_float (\n arg : UNSIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- signed to float\n function to_float (\n arg : SIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- unsigned fixed point to float\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n constant exponent_width : NATURAL := float_exponent_width; -- width of exponent\n constant fraction_width : NATURAL := float_fraction_width; -- width of fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float;\n\n -- signed fixed point to float\n function to_float (\n arg : UNRESOLVED_sfixed;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float;\n\n -- size_res functions\n -- Integer to float\n function to_float (\n arg : INTEGER;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- real to float\n function to_float (\n arg : REAL;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- unsigned to float\n function to_float (\n arg : UNSIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- signed to float\n function to_float (\n arg : SIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float;\n\n -- sulv to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float;\n\n -- unsigned fixed point to float\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float;\n\n -- signed fixed point to float\n function to_float (\n arg : UNRESOLVED_sfixed;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float;\n\n -- float to unsigned\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED;\n\n -- float to signed\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED;\n\n -- purpose: Converts a float to unsigned fixed point\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed;\n\n -- float to signed fixed point\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed;\n\n -- size_res versions\n -- float to unsigned\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n size_res : UNSIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED;\n\n -- float to signed\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n size_res : SIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED;\n\n -- purpose: Converts a float to unsigned fixed point\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_ufixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed;\n\n -- float to signed fixed point\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_sfixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed;\n\n -- float to real\n function to_real (\n arg : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return REAL;\n\n -- float to integer\n function to_integer (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return INTEGER;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;\n function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;\n\n -- Maps metalogical values\n function to_01 (\n arg : UNRESOLVED_float; -- floating point input\n XMAP : STD_LOGIC := '0')\n return UNRESOLVED_float;\n\n function Is_X (arg : UNRESOLVED_float) return BOOLEAN;\n function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;\n function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;\n function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- These two procedures were copied out of the body because they proved\n -- very useful for vendor specific algorithm development\n -- Break_number converts a floating point number into it's parts\n -- Exponent is biased by -1\n\n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out UNSIGNED;\n expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!\n sign : out STD_ULOGIC);\n\n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out ufixed; -- a number between 1.0 and 2.0\n expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!\n sign : out STD_ULOGIC);\n\n -- Normalize takes a fraction and and exponent and converts them into\n -- a floating point number. Does the shifting and the rounding.\n -- Exponent is assumed to be biased by -1\n\n function normalize (\n fract : UNSIGNED; -- fraction, unnormalized\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n -- Exponent is assumed to be biased by -1\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n function normalize (\n fract : UNSIGNED; -- unsigned\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n -- Exponent is assumed to be biased by -1\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float;\n\n -- overloaded versions\n function \"+\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"+\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"+\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"+\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"-\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"-\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"-\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"*\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"*\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"*\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"*\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"/\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"/\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"/\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"/\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"rem\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"rem\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"rem\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"rem\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"mod\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function \"mod\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"mod\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function \"mod\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- overloaded compare functions\n function \"=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \">\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;\n function \"=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"/=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \">=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"<=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \">\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"<\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;\n function \"=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"/=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \">=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"<=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \">\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"<\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;\n function \"=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \"/=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \">=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \"<=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \">\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \"<\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;\n function \\?=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;\n function \\?=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?/=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?/=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?>\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?>=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?<\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?<=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;\n function \\?=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?/=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?>=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n function \\?<=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;\n -- minimum and maximum overloads\n function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;\n function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;\n function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;\n function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;\n----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n\n function \"not\" (l : UNRESOLVED_float) return UNRESOLVED_float;\n function \"and\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"or\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"nand\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"nor\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"xor\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n function \"xnor\" (l, r : UNRESOLVED_float) return UNRESOLVED_float;\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"and\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"or\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"or\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"nand\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"nand\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"nor\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"nor\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"xor\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"xor\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n function \"xnor\" (l : STD_ULOGIC; r : UNRESOLVED_float)\n return UNRESOLVED_float;\n function \"xnor\" (l : UNRESOLVED_float; r : STD_ULOGIC)\n return UNRESOLVED_float;\n -- Reduction operators, same as numeric_std functions\n function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;\n\n -- Note: \"sla\", \"sra\", \"sll\", \"slr\", \"rol\" and \"ror\" not implemented.\n\n -----------------------------------------------------------------------------\n -- Recommended Functions from the IEEE 754 Appendix\n -----------------------------------------------------------------------------\n\n -- returns x with the sign of y.\n function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : INTEGER; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : SIGNED; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float;\n\n -- returns the unbiased exponent of x\n function Logb (x : UNRESOLVED_float) return INTEGER;\n function Logb (x : UNRESOLVED_float) return SIGNED;\n\n -- returns the next representable neighbor of x in the direction toward y\n function Nextafter (\n x, y : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float;\n\n -- Returns TRUE if X is unordered with Y.\n function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;\n function Finite (x : UNRESOLVED_float) return BOOLEAN;\n function Isnan (x : UNRESOLVED_float) return BOOLEAN;\n\n -- Function to return constants.\n function zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function nanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function qnanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function pos_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function neg_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n function neg_zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float;\n -- size_res versions\n function zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function nanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function qnanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function pos_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function neg_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n function neg_zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float;\n\n -- ===========================================================================\n -- string and textio Functions\n -- ===========================================================================\n-- rtl_synthesis off\n-- pragma synthesis_off\n -- writes S:EEEE:FFFFFFFF\n procedure WRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0); -- width of field\n\n -- Reads SEEEEFFFFFFFF, \".\" and \":\" are ignored\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;\n GOOD : out BOOLEAN);\n\n alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];\n alias BREAD is READ [LINE, UNRESOLVED_float];\n alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];\n alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];\n alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];\n alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];\n\n procedure OWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0); -- width of field\n\n -- Octal read with padding, no separators used\n procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);\n procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;\n GOOD : out BOOLEAN);\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];\n alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];\n\n -- Hex write with padding, no separators\n procedure HWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0); -- width of field\n\n -- Hex read with padding, no separators used\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;\n GOOD : out BOOLEAN);\n alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];\n alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];\n alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];\n\n -- returns \"S:EEEE:FFFFFFFF\"\n function to_string (value : UNRESOLVED_float) return STRING;\n alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];\n alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];\n\n -- Returns a HEX string, with padding\n function to_hstring (value : UNRESOLVED_float) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];\n\n -- Returns and octal string, with padding\n function to_ostring (value : UNRESOLVED_float) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];\n\n function from_string (\n bstring : STRING; -- binary string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float;\n alias from_bstring is from_string [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n alias from_binary_string is from_string [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n function from_ostring (\n ostring : STRING; -- Octal string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float;\n alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float;\n alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL\n return UNRESOLVED_float];\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float;\n alias from_bstring is from_string [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n alias from_binary_string is from_string [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float;\n alias from_octal_string is from_ostring [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float;\n alias from_hex_string is from_hstring [STRING, UNRESOLVED_float\n return UNRESOLVED_float];\n-- rtl_synthesis on\n-- pragma synthesis_on\n -- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these\n -- extra functions are needed for compatability.\n function to_float (\n arg : STD_LOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float;\n\n function to_float (\n arg : STD_LOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_LOGIC_VECTOR;\n function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;\n\nend package float_pkg;\n-------------------------------------------------------------------------------\n-- Proposed package body for the VHDL-200x-FT float_pkg package\n-- This version is optimized for Synthesis, and not for simulation.\n-- Note that there are functional differences between the synthesis and\n-- simulation packages bodies. The Synthesis version is preferred.\n-- This package body supplies a recommended implementation of these functions\n-- Version : $Revision: 2.2 $\n-- Date : $Date: 2010/09/22 18:26:46 $\n--\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n-------------------------------------------------------------------------------\n\npackage body float_pkg is\n\n -- Author David Bishop (dbishop@vhdl.org)\n -----------------------------------------------------------------------------\n -- type declarations\n -----------------------------------------------------------------------------\n\n -- This deferred constant will tell you if the package body is synthesizable\n -- or implemented as real numbers, set to \"true\" if synthesizable.\n constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant\n\n -- types of boundary conditions\n type boundary_type is (normal, infinity, zero, denormal);\n\n -- null range array constant\n constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');\n constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');\n\n -- %%% Replicated functions\n -- These functions are replicated so that we don't need to reference the new\n -- 2006 package std.standard, std_logic_1164 and numeric_std.\n function maximum (\n l, r : INTEGER) -- inputs\n return INTEGER is\n begin -- function max\n if l > r then return l;\n else return r;\n end if;\n end function maximum;\n\n function minimum (\n l, r : INTEGER) -- inputs\n return INTEGER is\n begin -- function min\n if l > r then return r;\n else return l;\n end if;\n end function minimum;\n\n function or_reduce (arg : STD_ULOGIC_VECTOR)\n return STD_LOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC;\n begin\n if (arg'length < 1) then -- In the case of a NULL range\n Result := '0';\n else\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := or_reduce (BUS_int (BUS_int'left downto Half));\n Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper or Lower;\n end if;\n end if;\n return Result;\n end function or_reduce;\n\n function or_reduce (arg : UNSIGNED)\n return STD_ULOGIC is\n begin\n return or_reduce (STD_ULOGIC_VECTOR (arg));\n end function or_reduce;\n\n function or_reduce (arg : SIGNED)\n return STD_ULOGIC is\n begin\n return or_reduce (STD_ULOGIC_VECTOR (arg));\n end function or_reduce;\n\n function or_reduce (arg : STD_LOGIC_VECTOR)\n return STD_ULOGIC is\n begin\n return or_reduce (STD_ULOGIC_VECTOR (arg));\n end function or_reduce;\n\n -- purpose: AND all of the bits in a vector together\n -- This is a copy of the proposed \"and_reduce\" from 1076.3\n function and_reduce (arg : STD_ULOGIC_VECTOR)\n return STD_LOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC;\n begin\n if (arg'length < 1) then -- In the case of a NULL range\n Result := '1';\n else\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := and_reduce (BUS_int (BUS_int'left downto Half));\n Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper and Lower;\n end if;\n end if;\n return Result;\n end function and_reduce;\n\n function and_reduce (arg : UNSIGNED)\n return STD_ULOGIC is\n begin\n return and_reduce (STD_ULOGIC_VECTOR (arg));\n end function and_reduce;\n\n function and_reduce (arg : SIGNED)\n return STD_ULOGIC is\n begin\n return and_reduce (STD_ULOGIC_VECTOR (arg));\n end function and_reduce;\n\n function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);\n variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range\n begin\n if (arg'length >= 1) then\n BUS_int := to_ux01 (arg);\n if (BUS_int'length = 1) then\n Result := BUS_int (BUS_int'left);\n elsif (BUS_int'length = 2) then\n Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);\n else\n Half := (BUS_int'length + 1) / 2 + BUS_int'right;\n Upper := xor_reduce (BUS_int (BUS_int'left downto Half));\n Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));\n Result := Upper xor Lower;\n end if;\n end if;\n return Result;\n end function xor_reduce;\n\n function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not and_reduce (arg);\n end function nand_reduce;\n\n function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not or_reduce (arg);\n end function nor_reduce;\n\n function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not xor_reduce (arg);\n end function xnor_reduce;\n\n function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)\n return INTEGER is\n begin\n for INDEX in ARG'range loop\n if ARG(INDEX) = Y then\n return INDEX;\n end if;\n end loop;\n return -1;\n end function find_leftmost;\n\n -- Match table, copied form new std_logic_1164\n type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;\n constant match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |\n ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |\n );\n\n\n -------------------------------------------------------------------\n -- ?= functions, Similar to \"std_match\", but returns \"std_ulogic\".\n -------------------------------------------------------------------\n -- %%% FUNCTION \"?=\" ( l, r : std_ulogic ) RETURN std_ulogic IS\n function \\?=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return match_logic_table (l, r);\n end function \\?=\\;\n -- %%% END FUNCTION \"?=\";\n\n -- %%% FUNCTION \"?/=\" ( l, r : std_ulogic ) RETURN std_ulogic is\n function \\?/=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return not match_logic_table (l, r);\n end function \\?/=\\;\n -- %%% END FUNCTION \"?/=\";\n\n function \\?=\\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;\n alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;\n variable result, result1 : STD_ULOGIC;\n begin\n -- Logically identical to an \"=\" operator.\n if ((l'length < 1) and (r'length < 1)) then\n -- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal\n return '1';\n elsif lv'length /= rv'length then\n -- Two arrays of different lengths are false\n return '0';\n else\n result := '1';\n for i in lv'low to lv'high loop\n result1 := match_logic_table(lv(i), rv(i));\n result := result and result1;\n end loop;\n return result;\n end if;\n end function \\?=\\;\n\n function Is_X (s : UNSIGNED) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n\n function Is_X (s : SIGNED) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n-- %%% END replicated functions\n\n -- Special version of \"minimum\" to do some boundary checking\n function mine (L, R : INTEGER)\n return INTEGER is\n begin -- function minimum\n if (L = INTEGER'low or R = INTEGER'low) then\n report float_pkg'instance_name\n & \" Unbounded number passed, was a literal used?\"\n severity error;\n return 0;\n end if;\n return minimum (L, R);\n end function mine;\n\n -- Generates the base number for the exponent normalization offset.\n function gen_expon_base (\n constant exponent_width : NATURAL)\n return SIGNED is\n variable result : SIGNED (exponent_width-1 downto 0);\n begin\n result := (others => '1');\n result (exponent_width-1) := '0';\n return result;\n end function gen_expon_base;\n\n -- Integer version of the \"log2\" command (contributed by Peter Ashenden)\n function log2 (A : NATURAL) return NATURAL is\n variable quotient : NATURAL;\n variable result : NATURAL := 0;\n begin\n quotient := A / 2;\n while quotient > 0 loop\n quotient := quotient / 2;\n result := result + 1;\n end loop;\n return result;\n end function log2;\n\n -- Function similar to the ILOGB function in MATH_REAL\n function log2 (A : REAL) return INTEGER is\n variable Y : REAL;\n variable N : INTEGER := 0;\n begin\n if (A = 1.0 or A = 0.0) then\n return 0;\n end if;\n Y := A;\n if(A > 1.0) then\n while Y >= 2.0 loop\n Y := Y / 2.0;\n N := N + 1;\n end loop;\n return N;\n end if;\n -- O < Y < 1\n while Y < 1.0 loop\n Y := Y * 2.0;\n N := N - 1;\n end loop;\n return N;\n end function log2;\n\n -- purpose: Test the boundary conditions of a Real number\n procedure test_boundary (\n arg : in REAL; -- Input, converted to real\n constant fraction_width : in NATURAL; -- length of FP output fraction\n constant exponent_width : in NATURAL; -- length of FP exponent\n constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP\n variable btype : out boundary_type;\n variable log2i : out INTEGER\n ) is\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n constant exp_min : SIGNED (12 downto 0) :=\n -(resize(expon_base, 13)) + 1; -- Minimum normal exponent\n constant exp_ext_min : SIGNED (12 downto 0) :=\n exp_min - fraction_width; -- Minimum for denormal exponent\n variable log2arg : INTEGER; -- log2 of argument\n begin -- function test_boundary\n -- Check to see if the exponent is big enough\n -- Note that the argument is always an absolute value at this point.\n log2arg := log2(arg);\n if arg = 0.0 then\n btype := zero;\n elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)\n btype := normal;\n else\n if log2arg < to_integer(exp_min) then\n if denormalize then\n if log2arg < to_integer(exp_ext_min) then\n btype := zero;\n else\n btype := denormal;\n end if;\n else\n if log2arg < to_integer(exp_min)-1 then\n btype := zero;\n else\n btype := normal; -- Can still represent this number\n end if;\n end if;\n elsif exponent_width < 11 then\n if log2arg > to_integer(expon_base)+1 then\n btype := infinity;\n else\n btype := normal;\n end if;\n else\n btype := normal;\n end if;\n end if;\n log2i := log2arg;\n end procedure test_boundary;\n\n -- purpose: Rounds depending on the state of the \"round_style\"\n -- Logic taken from\n -- \"What Every Computer Scientist Should Know About Floating Point Arithmetic\"\n -- by David Goldberg (1991)\n function check_round (\n fract_in : STD_ULOGIC; -- input fraction\n sign : STD_ULOGIC; -- sign bit\n remainder : UNSIGNED; -- remainder to round from\n sticky : STD_ULOGIC := '0'; -- Sticky bit\n constant round_style : round_type) -- rounding type\n return BOOLEAN is\n variable result : BOOLEAN;\n variable or_reduced : STD_ULOGIC;\n begin -- function check_round\n result := false;\n if (remainder'length > 0) then -- if remainder in a null array\n or_reduced := or_reduce (remainder & sticky);\n rounding_case : case round_style is\n when round_nearest => -- Round Nearest, default mode\n if remainder(remainder'high) = '1' then -- round\n if (remainder'length > 1) then\n if ((or_reduce (remainder(remainder'high-1\n downto remainder'low)) = '1'\n or sticky = '1')\n or fract_in = '1') then\n -- Make the bottom bit zero if possible if we are at 1/2\n result := true;\n end if;\n else\n result := (fract_in = '1' or sticky = '1');\n end if;\n end if;\n when round_inf => -- round up if positive, else truncate.\n if or_reduced = '1' and sign = '0' then\n result := true;\n end if;\n when round_neginf => -- round down if negative, else truncate.\n if or_reduced = '1' and sign = '1' then\n result := true;\n end if;\n when round_zero => -- round toward 0 Truncate\n null;\n end case rounding_case;\n end if;\n return result;\n end function check_round;\n\n -- purpose: Rounds depending on the state of the \"round_style\"\n -- unsigned version\n procedure fp_round (\n fract_in : in UNSIGNED; -- input fraction\n expon_in : in SIGNED; -- input exponent\n fract_out : out UNSIGNED; -- output fraction\n expon_out : out SIGNED) is -- output exponent\n begin -- procedure fp_round\n if and_reduce (fract_in) = '1' then -- Fraction is all \"1\"\n expon_out := expon_in + 1;\n fract_out := to_unsigned(0, fract_out'high+1);\n else\n expon_out := expon_in;\n fract_out := fract_in + 1;\n end if;\n end procedure fp_round;\n\n -- This version of break_number doesn't call \"classfp\"\n procedure break_number ( -- internal version\n arg : in UNRESOLVED_float;\n fptyp : in valid_fpstate;\n denormalize : in BOOLEAN := true;\n fract : out UNSIGNED;\n expon : out SIGNED) is\n constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction\n constant exponent_width : NATURAL := arg'high; -- length of FP output exponent\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable exp : SIGNED (expon'range);\n begin\n fract (fraction_width-1 downto 0) :=\n UNSIGNED (to_slv(arg(-1 downto -fraction_width)));\n breakcase : case fptyp is\n when pos_zero | neg_zero =>\n fract (fraction_width) := '0';\n exp := -expon_base;\n when pos_denormal | neg_denormal =>\n if denormalize then\n exp := -expon_base;\n fract (fraction_width) := '0';\n else\n exp := -expon_base - 1;\n fract (fraction_width) := '1';\n end if;\n when pos_normal | neg_normal | pos_inf | neg_inf =>\n fract (fraction_width) := '1';\n exp := SIGNED(arg(exponent_width-1 downto 0));\n exp (exponent_width-1) := not exp(exponent_width-1);\n when others =>\n assert NO_WARNING\n report float_pkg'instance_name\n & \"BREAK_NUMBER: \" &\n \"Meta state detected in fp_break_number process\"\n severity warning;\n -- complete the case, if a NAN goes in, a NAN comes out.\n exp := (others => '1');\n fract (fraction_width) := '1';\n end case breakcase;\n expon := exp;\n end procedure break_number;\n\n -- purpose: floating point to UNSIGNED\n -- Used by to_integer, to_unsigned, and to_signed functions\n procedure float_to_unsigned (\n arg : in UNRESOLVED_float; -- floating point input\n variable sign : out STD_ULOGIC; -- sign of output\n variable frac : out UNSIGNED; -- unsigned biased output\n constant denormalize : in BOOLEAN; -- turn on denormalization\n constant bias : in NATURAL; -- bias for fixed point\n constant round_style : in round_type) is -- rounding method\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n variable fract : UNSIGNED (frac'range); -- internal version of frac\n variable isign : STD_ULOGIC; -- internal version of sign\n variable exp : INTEGER; -- Exponent\n variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp\n -- Base to divide fraction by\n variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted\n variable shift : INTEGER;\n variable remainder : UNSIGNED (2 downto 0);\n variable round : STD_ULOGIC; -- round BIT\n begin\n isign := to_x01(arg(arg'high));\n -- exponent /= '0', normal floating point\n expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (expon);\n -- Figure out the fraction\n fract := (others => '0'); -- fill with zero\n fract (fract'high) := '1'; -- Add the \"1.0\".\n shift := (fract'high-1) - exp;\n if fraction_width > fract'high then -- Can only use size-2 bits\n fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto\n -fract'high)));\n else -- can use all bits\n fract (fract'high-1 downto fract'high-fraction_width) :=\n UNSIGNED (to_slv (arg(-1 downto -fraction_width)));\n end if;\n frac_shift := fract & \"000\";\n if shift < 0 then -- Overflow\n fract := (others => '1');\n else\n frac_shift := shift_right (frac_shift, shift);\n fract := frac_shift (frac_shift'high downto 3);\n remainder := frac_shift (2 downto 0);\n -- round (round_zero will bypass this and truncate)\n case round_style is\n when round_nearest =>\n round := remainder(2) and\n (fract (0) or (or_reduce (remainder (1 downto 0))));\n", "right_context": " end if;\n end if;\n frac := fract;\n sign := isign;\n end procedure float_to_unsigned;\n\n -- purpose: returns a part of a vector, this function is here because\n -- or (fractr (to_integer(shiftx) downto 0));\n -- can't be synthesized in some synthesis tools.\n function smallfract (\n arg : UNSIGNED;\n shift : NATURAL)\n return STD_ULOGIC is\n variable orx : STD_ULOGIC;\n begin\n orx := arg(shift);\n for i in arg'range loop\n if i < shift then\n orx := arg(i) or orx;\n end if;\n end loop;\n return orx;\n end function smallfract;\n ---------------------------------------------------------------------------\n -- Visible functions\n ---------------------------------------------------------------------------\n\n -- purpose: converts the negative index to a positive one\n -- negative indices are illegal in 1164 and 1076.3\n function to_sulv (\n arg : UNRESOLVED_float) -- fp vector\n return STD_ULOGIC_VECTOR is\n variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);\n begin -- function to_std_ulogic_vector\n if arg'length < 1 then\n return NSLV;\n end if;\n result := STD_ULOGIC_VECTOR (arg);\n return result;\n end function to_sulv;\n\n -- Converts an fp into an SLV\n function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is\n begin\n return to_stdlogicvector (to_sulv (arg));\n end function to_slv;\n\n -- purpose: normalizes a floating point number\n -- This version assumes an \"unsigned\" input with\n function normalize (\n fract : UNSIGNED; -- fraction, unnormalized\n expon : SIGNED; -- exponent, normalized by -1\n sign : STD_ULOGIC; -- sign BIT\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction\n variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction\n variable exp : SIGNED (exponent_width+1 downto 0); -- exponent\n variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result\n variable shiftr : INTEGER; -- shift amount\n variable stickyx : STD_ULOGIC; -- version of sticky\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable round, zerores, infres : BOOLEAN;\n begin -- function normalize\n zerores := false;\n infres := false;\n round := false;\n shiftr := find_leftmost (to_01(fract), '1') -- Find the first \"1\"\n - fraction_width - nguard; -- subtract the length we want\n exp := resize (expon, exp'length) + shiftr;\n if (or_reduce (fract) = '0') then -- Zero\n zerores := true;\n elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)\n or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then\n if (exp >= -resize(expon_base, exp'length)-fraction_width-1)\n and denormalize then\n exp := -resize(expon_base, exp'length)-1;\n shiftr := -to_integer (expon + expon_base); -- new shift\n else -- return zero\n zerores := true;\n end if;\n elsif (exp > expon_base-1) then -- infinity\n infres := true;\n end if;\n if zerores then\n result := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif infres then\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n sfract := fract srl shiftr; -- shift\n if shiftr > 0 then\n-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));\n stickyx := sticky or smallfract (fract, shiftr-1);\n else\n stickyx := sticky;\n end if;\n if nguard > 0 then\n round := check_round (\n fract_in => sfract (nguard),\n sign => sign,\n remainder => sfract(nguard-1 downto 0),\n sticky => stickyx,\n round_style => round_style);\n end if;\n if round then\n fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),\n expon_in => exp(rexp'range),\n fract_out => rfract,\n expon_out => rexp);\n else\n rfract := sfract (fraction_width-1+nguard downto nguard);\n rexp := exp(rexp'range);\n end if;\n -- result\n rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));\n rexpon (exponent_width-1) := not rexpon(exponent_width-1);\n result (rexpon'range) := UNRESOLVED_float(rexpon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);\n end if;\n result (exponent_width) := sign; -- sign BIT\n return result;\n end function normalize;\n\n -- purpose: normalizes a floating point number\n -- This version assumes a \"ufixed\" input\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent, normalized by -1\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arguns : UNSIGNED (fract'high + fraction_width + nguard\n downto 0) := (others => '0');\n begin -- function normalize\n arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=\n UNSIGNED (to_slv (fract));\n result := normalize (fract => arguns,\n expon => expon,\n sign => sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => nguard);\n return result;\n end function normalize;\n\n -- purpose: normalizes a floating point number\n -- This version assumes a \"ufixed\" input with a \"size_res\" input\n function normalize (\n fract : ufixed; -- unsigned fixed point\n expon : SIGNED; -- exponent, normalized by -1\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -size_res'low;\n constant exponent_width : NATURAL := size_res'high;\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arguns : UNSIGNED (fract'high + fraction_width + nguard\n downto 0) := (others => '0');\n begin -- function normalize\n arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=\n UNSIGNED (to_slv (fract));\n result := normalize (fract => arguns,\n expon => expon,\n sign => sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => nguard);\n return result;\n end function normalize;\n\n -- Regular \"normalize\" function with a \"size_res\" input.\n function normalize (\n fract : UNSIGNED; -- unsigned\n expon : SIGNED; -- exponent - 1, normalized\n sign : STD_ULOGIC; -- sign bit\n sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)\n size_res : UNRESOLVED_float; -- used for sizing only\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant nguard : NATURAL := float_guard_bits) -- guard bits\n return UNRESOLVED_float is\n begin\n return normalize (fract => fract,\n expon => expon,\n sign => sign,\n sticky => sticky,\n fraction_width => -size_res'low,\n exponent_width => size_res'high,\n round_style => round_style,\n denormalize => denormalize,\n nguard => nguard);\n end function normalize;\n\n -- Returns the class which X falls into\n function Classfp (\n x : UNRESOLVED_float; -- floating point input\n check_error : BOOLEAN := float_check_error) -- check for errors\n return valid_fpstate is\n constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction\n constant exponent_width : INTEGER := x'high; -- length of FP output exponent\n variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- classfp\n if (arg'length < 1 or fraction_width < 3 or exponent_width < 3\n or x'left < x'right) then\n report float_pkg'instance_name\n & \"CLASSFP: \" &\n \"Floating point number detected with a bad range\"\n severity error;\n return isx;\n end if;\n -- Check for \"X\".\n arg := to_01 (x, 'X');\n if (arg(0) = 'X') then\n return isx; -- If there is an X in the number\n -- Special cases, check for illegal number\n elsif check_error and\n (and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))\n = '1') then -- Exponent is all \"1\".\n if or_reduce (to_slv (arg (-1 downto -fraction_width)))\n /= '0' then -- Fraction must be all \"0\" or this is not a number.\n if (arg(-1) = '1') then -- From \"W. Khan - IEEE standard\n return nan; -- 754 binary FP Signaling nan (Not a number)\n else\n return quiet_nan;\n end if;\n -- Check for infinity\n elsif arg(exponent_width) = '0' then\n return pos_inf; -- Positive infinity\n else\n return neg_inf; -- Negative infinity\n end if;\n -- check for \"0\"\n elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))\n = '0' then -- Exponent is all \"0\"\n if or_reduce (to_slv (arg (-1 downto -fraction_width)))\n = '0' then -- Fraction is all \"0\"\n if arg(exponent_width) = '0' then\n return pos_zero; -- Zero\n else\n return neg_zero;\n end if;\n else\n if arg(exponent_width) = '0' then\n return pos_denormal; -- Denormal number (ieee extended fp)\n else\n return neg_denormal;\n end if;\n end if;\n else\n if arg(exponent_width) = '0' then\n return pos_normal; -- Normal FP number\n else\n return neg_normal;\n end if;\n end if;\n end function Classfp;\n\n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out UNSIGNED;\n expon : out SIGNED;\n sign : out STD_ULOGIC) is\n constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction\n variable fptyp : valid_fpstate;\n begin\n fptyp := Classfp (arg, check_error);\n sign := to_x01(arg(arg'high));\n break_number (\n arg => arg,\n fptyp => fptyp,\n denormalize => denormalize,\n fract => fract,\n expon => expon);\n end procedure break_number;\n \n procedure break_number (\n arg : in UNRESOLVED_float;\n denormalize : in BOOLEAN := float_denormalize;\n check_error : in BOOLEAN := float_check_error;\n fract : out ufixed; -- 1 downto -fraction_width\n expon : out SIGNED; -- exponent_width-1 downto 0\n sign : out STD_ULOGIC) is\n constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction\n variable fptyp : valid_fpstate;\n variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction\n begin\n fptyp := Classfp (arg, check_error);\n sign := to_x01(arg(arg'high));\n break_number (\n arg => arg,\n fptyp => fptyp,\n denormalize => denormalize,\n fract => ufract,\n expon => expon);\n fract (0 downto -fraction_width) := ufixed (ufract);\n end procedure break_number;\n\n -- Arithmetic functions\n function \"abs\" (\n arg : UNRESOLVED_float) -- floating point input\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range); -- result\n begin\n if (arg'length > 0) then\n result := to_01 (arg, 'X');\n result (arg'high) := '0'; -- set the sign bit to positive \n return result;\n else\n return NAFP;\n end if;\n end function \"abs\";\n\n -- IEEE 754 \"negative\" function\n function \"-\" (\n arg : UNRESOLVED_float) -- floating point input\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range); -- result\n begin\n if (arg'length > 0) then\n result := to_01 (arg, 'X');\n result (arg'high) := not result (arg'high); -- invert sign bit\n return result;\n else\n return NAFP;\n end if;\n end function \"-\";\n\n -- Addition, adds two floating point numbers\n function add (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant addguard : NATURAL := guard; -- add one guard bit\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions\n variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables\n variable urfract, ulfract : UNSIGNED (fraction_width downto 0);\n variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width downto 0); -- result exponent\n variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions\n variable sign : STD_ULOGIC; -- sign of the output\n variable leftright : BOOLEAN; -- left or right used\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable sticky : STD_ULOGIC; -- Holds precision for rounding\n begin -- addition\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan)\n -- Return quiet NAN, IEEE754-1985-7.1,1\n or (lfptype = pos_inf and rfptype = neg_inf)\n or (lfptype = neg_inf and rfptype = pos_inf) then\n -- Return quiet NAN, IEEE754-1985-7.1,2\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf\n fpresult := neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0\n fpresult := neg_zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n fractl := (others => '0');\n fractl (fraction_width+addguard downto addguard) := ulfract;\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n fractr := (others => '0');\n fractr (fraction_width+addguard downto addguard) := urfract;\n shiftx := (exponl(exponent_width-1) & exponl) - exponr;\n if shiftx < -fractl'high then\n rexpon := exponr(exponent_width-1) & exponr;\n fractc := fractr;\n fracts := (others => '0'); -- add zero\n leftright := false;\n sticky := or_reduce (fractl);\n elsif shiftx < 0 then\n shiftx := - shiftx;\n fracts := shift_right (fractl, to_integer(shiftx));\n fractc := fractr;\n rexpon := exponr(exponent_width-1) & exponr;\n leftright := false;\n-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));\n sticky := smallfract (fractl, to_integer(shiftx));\n elsif shiftx = 0 then\n rexpon := exponl(exponent_width-1) & exponl;\n sticky := '0';\n if fractr > fractl then\n fractc := fractr;\n fracts := fractl;\n leftright := false;\n else\n fractc := fractl;\n fracts := fractr;\n leftright := true;\n end if;\n elsif shiftx > fractr'high then\n rexpon := exponl(exponent_width-1) & exponl;\n fracts := (others => '0'); -- add zero\n fractc := fractl;\n leftright := true;\n sticky := or_reduce (fractr);\n elsif shiftx > 0 then\n fracts := shift_right (fractr, to_integer(shiftx));\n fractc := fractl;\n rexpon := exponl(exponent_width-1) & exponl;\n leftright := true;\n-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));\n sticky := smallfract (fractr, to_integer(shiftx));\n end if;\n -- add\n fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB\n if l(l'high) = r(r'high) then\n ufract := fractc + fracts;\n sign := l(l'high);\n else -- signs are different\n ufract := fractc - fracts; -- always positive result\n if leftright then -- Figure out which sign to use\n sign := l(l'high);\n else\n sign := r(r'high);\n end if;\n end if;\n if or_reduce (ufract) = '0' then\n sign := '0'; -- IEEE 854, 6.3, paragraph 2.\n end if;\n -- normalize\n fpresult := normalize (fract => ufract,\n expon => rexpon,\n sign => sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => addguard);\n end if;\n return fpresult;\n end function add;\n\n -- Subtraction, Calls \"add\".\n function subtract (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable negr : UNRESOLVED_float (r'range); -- negative version of r\n begin\n negr := -r;\n return add (l => l,\n r => negr,\n round_style => round_style,\n guard => guard,\n check_error => check_error,\n denormalize => denormalize);\n end function subtract;\n\n -- Floating point multiply\n function multiply (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant multguard : NATURAL := guard; -- guard bits\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions\n variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction\n variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction\n variable shifty : INTEGER; -- denormal shift\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable sticky : STD_ULOGIC; -- Holds precision for rounding\n begin -- multiply\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif ((lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan)) then\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (((lfptype = pos_inf or lfptype = neg_inf) and\n (rfptype = pos_zero or rfptype = neg_zero)) or\n ((rfptype = pos_inf or rfptype = neg_inf) and\n (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf\n -- Return quiet NAN, IEEE754-1985-7.1,3\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = pos_inf or rfptype = pos_inf\n or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n -- figure out the sign\n fp_sign := l(l'high) xor r(r'high); -- figure out the sign\n fpresult (exponent_width) := fp_sign;\n else\n fp_sign := l(l'high) xor r(r'high); -- figure out the sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => fractl,\n expon => exponl);\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => fractr,\n expon => exponr);\n if (rfptype = pos_denormal or rfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractr, '1');\n fractr := shift_left (fractr, shifty);\n elsif (lfptype = pos_denormal or lfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractl, '1');\n fractl := shift_left (fractl, shifty);\n else\n shifty := 0;\n -- Note that a denormal number * a denormal number is always zero.\n end if;\n -- multiply\n -- add the exponents\n rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;\n rfract := fractl * fractr; -- Multiply the fraction\n sfract := rfract (rfract'high downto\n rfract'high - (fraction_width+1+multguard));\n sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)\n downto 0));\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => rexpon,\n sign => fp_sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => multguard);\n end if;\n return fpresult;\n end function multiply;\n\n function short_divide (\n lx, rx : UNSIGNED)\n return UNSIGNED is\n -- This is a special divider for the floating point routines.\n -- For a true unsigned divider, \"stages\" needs to = lx'high\n constant stages : INTEGER := lx'high - rx'high; -- number of stages\n variable partial : UNSIGNED (lx'range);\n variable q : UNSIGNED (stages downto 0);\n variable partial_argl : SIGNED (rx'high + 2 downto 0);\n variable partial_arg : SIGNED (rx'high + 2 downto 0);\n begin\n partial := lx;\n for i in stages downto 0 loop\n partial_argl := resize (\"0\" & SIGNED (partial(lx'high downto i)),\n partial_argl'length);\n partial_arg := partial_argl - SIGNED (\"0\" & rx);\n if (partial_arg (partial_arg'high) = '1') then -- negative\n q(i) := '0';\n else\n q(i) := '1';\n partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=\n UNSIGNED (partial_arg(rx'range));\n end if;\n end loop;\n -- to make the output look like that of the unsigned IEEE divide.\n return resize (q, lx'length);\n end function short_divide;\n\n -- 1/X function. Needed for algorithm development.\n function reciprocal (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : NATURAL := arg'high; -- length of FP output exponent\n constant divguard : NATURAL := guard; -- guard bits\n function onedivy (\n arg : UNSIGNED)\n return UNSIGNED is\n variable q : UNSIGNED((2*arg'high)+1 downto 0);\n variable one : UNSIGNED (q'range);\n begin\n one := (others => '0');\n one(one'high) := '1';\n q := short_divide (one, arg); -- Unsigned divide\n return resize (q, arg'length+1);\n end function onedivy;\n variable fptype : valid_fpstate;\n variable expon : SIGNED (exponent_width-1 downto 0); -- exponents\n variable denorm_offset : NATURAL range 0 to 2;\n variable fract : UNSIGNED (fraction_width downto 0);\n variable fractg : UNSIGNED (fraction_width+divguard downto 0);\n variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- reciprocal\n fptype := classfp(arg, check_error);\n classcase : case fptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf => -- 1/inf, return 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when neg_zero | pos_zero => -- 1/0\n report float_pkg'instance_name\n & \"RECIPROCAL: Floating Point divide by zero\"\n severity error;\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when others =>\n if (fptype = pos_denormal or fptype = neg_denormal)\n and ((arg (-1) or arg(-2)) /= '1') then\n -- 1/denormal = infinity, with the exception of 2**-expon_base\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fpresult (exponent_width) := to_x01 (arg (exponent_width));\n else\n break_number (\n arg => arg,\n fptyp => fptype,\n denormalize => denormalize,\n fract => fract,\n expon => expon);\n fractg := (others => '0');\n if (fptype = pos_denormal or fptype = neg_denormal) then\n -- The reciprocal of a denormal number is typically zero,\n -- except for two special cases which are trapped here.\n if (to_x01(arg (-1)) = '1') then\n fractg (fractg'high downto divguard+1) :=\n fract (fract'high-1 downto 0); -- Shift to not denormal\n denorm_offset := 1; -- add 1 to exponent compensate\n else -- arg(-2) = '1'\n fractg (fractg'high downto divguard+2) :=\n fract (fract'high-2 downto 0); -- Shift to not denormal\n denorm_offset := 2; -- add 2 to exponent compensate\n end if;\n else\n fractg (fractg'high downto divguard) := fract;\n denorm_offset := 0;\n end if;\n expon := - expon - 3 + denorm_offset;\n sfract := onedivy (fractg);\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => expon,\n sign => arg(exponent_width),\n sticky => '1',\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => divguard);\n end if;\n end case classcase;\n return fpresult;\n end function reciprocal;\n\n -- floating point division\n function divide (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant divguard : NATURAL := guard; -- division guard bits\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable ulfract, urfract : UNSIGNED (fraction_width downto 0);\n variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left\n variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right\n variable rfract : UNSIGNED (fractl'range); -- result fraction\n variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable fp_sign, sticky : STD_ULOGIC; -- sign of result\n variable shifty, shiftx : INTEGER; -- denormal number shift\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- divide\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n classcase : case rfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf =>\n if lfptype = pos_inf or lfptype = neg_inf -- inf / inf\n or lfptype = quiet_nan or lfptype = nan then\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else -- x / inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when pos_zero | neg_zero =>\n if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0\n or lfptype = quiet_nan or lfptype = nan then\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n report float_pkg'instance_name\n & \"DIVIDE: Floating Point divide by zero\"\n severity error;\n -- Infinity, define in 754-1985-7.2\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when others =>\n classcase2 : case lfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf => -- inf / x = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult(exponent_width) := fp_sign;\n when pos_zero | neg_zero => -- 0 / X = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult(exponent_width) := fp_sign;\n when others =>\n fp_sign := l(l'high) xor r(r'high); -- sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n -- right side\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n -- Compute the exponent\n rexpon := resize (exponl, rexpon'length) - exponr - 2;\n if (rfptype = pos_denormal or rfptype = neg_denormal) then\n -- Do the shifting here not after. That way we have a smaller\n -- shifter, and need a smaller divider, because the top\n -- bit in the divisor will always be a \"1\".\n shifty := fraction_width - find_leftmost(urfract, '1');\n urfract := shift_left (urfract, shifty);\n rexpon := rexpon + shifty;\n end if;\n fractr := (others => '0');\n fractr (fraction_width+divguard downto divguard) := urfract;\n if (lfptype = pos_denormal or lfptype = neg_denormal) then\n shiftx := fraction_width - find_leftmost(ulfract, '1');\n ulfract := shift_left (ulfract, shiftx);\n rexpon := rexpon - shiftx;\n end if;\n fractl := (others => '0');\n fractl (fractl'high downto fractl'high-fraction_width) := ulfract;\n -- divide\n rfract := short_divide (fractl, fractr); -- unsigned divide\n sfract := rfract (sfract'range); -- lower bits\n sticky := '1';\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => rexpon,\n sign => fp_sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => divguard);\n end case classcase2;\n end case classcase;\n return fpresult;\n end function divide;\n\n -- division by a power of 2\n function dividebyp2 (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable ulfract, urfract : UNSIGNED (fraction_width downto 0);\n variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED(exponent_width downto 0); -- result exponent\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- divisionbyp2\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n classcase : case rfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf =>\n if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else -- x / inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when pos_zero | neg_zero =>\n if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0\n -- Return quiet NAN, IEEE754-1985-7.1,4\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n report float_pkg'instance_name\n & \"DIVIDEBYP2: Floating Point divide by zero\"\n severity error;\n -- Infinity, define in 754-1985-7.2\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (fpresult'high) := fp_sign; -- sign\n end if;\n when others =>\n classcase2 : case lfptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf | neg_inf => -- inf / x = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (exponent_width) := fp_sign; -- sign\n when pos_zero | neg_zero => -- 0 / X = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n fp_sign := l(l'high) xor r(r'high); -- sign\n fpresult (exponent_width) := fp_sign; -- sign\n when others =>\n fp_sign := l(l'high) xor r(r'high); -- sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n -- right side\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')\n report float_pkg'instance_name\n & \"DIVIDEBYP2: \"\n & \"Dividebyp2 called with a non power of two divisor\"\n severity error;\n rexpon := (exponl(exponl'high)&exponl)\n - (exponr(exponr'high)&exponr) - 1;\n -- normalize\n fpresult := normalize (fract => ulfract,\n expon => rexpon,\n sign => fp_sign,\n sticky => '1',\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => 0);\n end case classcase2;\n end case classcase;\n return fpresult;\n end function dividebyp2;\n\n -- Multiply accumulate result = l*r + c\n function mac (\n l, r, c : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL :=\n -mine (mine(l'low, r'low), c'low); -- length of FP output fraction\n constant exponent_width : NATURAL :=\n maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent\n variable lfptype, rfptype, cfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions\n variable fractx : UNSIGNED (fraction_width+guard downto 0);\n variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);\n variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction\n variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction\n variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent\n variable shifty : INTEGER; -- denormal shift\n variable shiftx : SIGNED (rexpon'range); -- shift fractions\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);\n variable leftright : BOOLEAN; -- left or right used\n variable sticky : STD_ULOGIC; -- Holds precision for rounding\n begin -- multiply\n if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n cfptype := classfp (c, check_error);\n end if;\n if (lfptype = isx or rfptype = isx or cfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan or\n cfptype = nan or cfptype = quiet_nan) then\n -- Return quiet NAN, IEEE754-1985-7.1,1\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (((lfptype = pos_inf or lfptype = neg_inf) and\n (rfptype = pos_zero or rfptype = neg_zero)) or\n ((rfptype = pos_inf or rfptype = neg_inf) and\n (lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf\n -- Return quiet NAN, IEEE754-1985-7.1,3\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (lfptype = pos_inf or rfptype = pos_inf\n or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf\n or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf\n fpresult := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n -- figure out the sign\n fpresult (exponent_width) := l(l'high) xor r(r'high);\n else\n fp_sign := l(l'high) xor r(r'high); -- figure out the sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n cresize := resize (arg => to_x01(c),\n exponent_width => exponent_width,\n fraction_width => -cresize'low,\n denormalize_in => denormalize,\n denormalize => denormalize);\n cfptype := classfp (cresize, false); -- errors already checked\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => fractl,\n expon => exponl);\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => fractr,\n expon => exponr);\n break_number (\n arg => cresize,\n fptyp => cfptype,\n denormalize => denormalize,\n fract => fractx,\n expon => exponc);\n if (rfptype = pos_denormal or rfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractr, '1');\n fractr := shift_left (fractr, shifty);\n elsif (lfptype = pos_denormal or lfptype = neg_denormal) then\n shifty := fraction_width - find_leftmost(fractl, '1');\n fractl := shift_left (fractl, shifty);\n else\n shifty := 0;\n -- Note that a denormal number * a denormal number is always zero.\n end if;\n -- multiply\n rfract := fractl * fractr; -- Multiply the fraction\n -- add the exponents\n rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;\n shiftx := rexpon - exponc;\n if shiftx < -fractl'high then\n rexpon2 := resize (exponc, rexpon2'length);\n fractc := \"0\" & fractx;\n fracts := (others => '0');\n sticky := or_reduce (rfract);\n elsif shiftx < 0 then\n shiftx := - shiftx;\n fracts := shift_right (rfract (rfract'high downto rfract'high\n - fracts'length+1),\n to_integer(shiftx));\n fractc := \"0\" & fractx;\n rexpon2 := resize (exponc, rexpon2'length);\n leftright := false;\n sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high\n - fracts'length downto 0));\n elsif shiftx = 0 then\n rexpon2 := resize (exponc, rexpon2'length);\n sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));\n if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx\n then\n fractc := \"0\" & fractx;\n fracts := rfract (rfract'high downto rfract'high\n - fracts'length+1);\n leftright := false;\n else\n fractc := rfract (rfract'high downto rfract'high\n - fractc'length+1);\n fracts := \"0\" & fractx;\n leftright := true;\n end if;\n elsif shiftx > fractx'high then\n rexpon2 := rexpon;\n fracts := (others => '0');\n fractc := rfract (rfract'high downto rfract'high - fractc'length+1);\n leftright := true;\n sticky := or_reduce (fractx & rfract (rfract'high - fractc'length\n downto 0));\n else -- fractx'high > shiftx > 0\n rexpon2 := rexpon;\n fracts := \"0\" & shift_right (fractx, to_integer (shiftx));\n fractc := rfract (rfract'high downto rfract'high - fractc'length+1);\n leftright := true;\n sticky := or_reduce (fractx (to_integer (shiftx) downto 0)\n & rfract (rfract'high - fractc'length downto 0));\n end if;\n fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB\n if fp_sign = to_X01(c(c'high)) then\n ufract := fractc + fracts;\n fp_sign := fp_sign;\n else -- signs are different\n ufract := fractc - fracts; -- always positive result\n if leftright then -- Figure out which sign to use\n fp_sign := fp_sign;\n else\n fp_sign := c(c'high);\n end if;\n end if;\n -- normalize\n fpresult := normalize (fract => ufract,\n expon => rexpon2,\n sign => fp_sign,\n sticky => sticky,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => guard);\n end if;\n return fpresult;\n end function mac;\n\n -- \"rem\" function\n function remainder (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n constant divguard : NATURAL := guard; -- division guard bits\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable ulfract, urfract : UNSIGNED (fraction_width downto 0);\n variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right\n variable rfract : UNSIGNED (fractr'range); -- result fraction\n variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction\n variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents\n variable rexpon : SIGNED (exponent_width downto 0); -- result exponent\n variable fp_sign : STD_ULOGIC; -- sign of result\n variable shifty : INTEGER; -- denormal number shift\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- remainder\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan)\n or (rfptype = nan or rfptype = quiet_nan)\n -- Return quiet NAN, IEEE754-1985-7.1,1\n or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x\n -- Return quiet NAN, IEEE754-1985-7.1,5\n or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0\n -- Return quiet NAN, IEEE754-1985-7.1,5\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (abs(l) < abs(r)) then\n fpresult := l;\n else\n fp_sign := to_X01(l(l'high)); -- sign\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n lfptype := classfp (lresize, false); -- errors already checked\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rfptype := classfp (rresize, false); -- errors already checked\n fractl := (others => '0');\n break_number (\n arg => lresize,\n fptyp => lfptype,\n denormalize => denormalize,\n fract => ulfract,\n expon => exponl);\n fractl (fraction_width+divguard downto divguard) := ulfract;\n -- right side\n fractr := (others => '0');\n break_number (\n arg => rresize,\n fptyp => rfptype,\n denormalize => denormalize,\n fract => urfract,\n expon => exponr);\n fractr (fraction_width+divguard downto divguard) := urfract;\n rexpon := (exponr(exponr'high)&exponr);\n shifty := to_integer(exponl - rexpon);\n if (shifty > 0) then\n fractr := shift_right (fractr, shifty);\n rexpon := rexpon + shifty;\n end if;\n if (fractr /= 0) then\n -- rem\n rfract := fractl rem fractr; -- unsigned rem\n sfract := rfract (sfract'range); -- lower bits\n -- normalize\n fpresult := normalize (fract => sfract,\n expon => rexpon,\n sign => fp_sign,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => divguard);\n else\n -- If we shift \"fractr\" so far that it becomes zero, return zero.\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n end if;\n end if;\n return fpresult;\n end function remainder;\n\n -- \"mod\" function\n function modulo (\n l, r : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant guard : NATURAL := float_guard_bits; -- number of guard bits\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- remainder\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n lfptype := isx;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = isx or rfptype = isx) then\n fpresult := (others => 'X');\n elsif (lfptype = nan or lfptype = quiet_nan)\n or (rfptype = nan or rfptype = quiet_nan)\n -- Return quiet NAN, IEEE754-1985-7.1,1\n or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x\n -- Return quiet NAN, IEEE754-1985-7.1,5\n or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0\n -- Return quiet NAN, IEEE754-1985-7.1,5\n fpresult := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0\n fpresult := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n remres := remainder (l => abs(l),\n r => abs(r),\n round_style => round_style,\n guard => guard,\n check_error => false,\n denormalize => denormalize);\n -- MOD is the same as REM, but you do something different with\n -- negative values\n if (is_negative (l)) then\n remres := - remres;\n end if;\n if (is_negative (l) = is_negative (r) or remres = 0) then\n fpresult := remres;\n else\n fpresult := add (l => remres,\n r => r,\n round_style => round_style,\n guard => guard,\n check_error => false,\n denormalize => denormalize); \n end if;\n end if;\n return fpresult;\n end function modulo;\n\n -- Square root of a floating point number. Done using Newton's Iteration.\n function sqrt (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style;\n constant guard : NATURAL := float_guard_bits;\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction\n constant exponent_width : NATURAL := arg'high; -- length of FP output exponent\n variable sign : STD_ULOGIC;\n variable fpresult : float (arg'range);\n variable fptype : valid_fpstate;\n variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents\n variable expon : SIGNED(exponent_width downto 0); -- exponents\n variable ufact : ufixed (0 downto arg'low);\n variable fact : ufixed (2 downto -fraction_width); -- fraction\n variable resb : ufixed (fact'high+1 downto fact'low);\n begin -- square root\n fptype := Classfp (arg, check_error);\n classcase : case fptype is\n when isx =>\n fpresult := (others => 'X');\n when nan | quiet_nan |\n -- Return quiet NAN, IEEE754-1985-7.1,1\n neg_normal | neg_denormal | neg_inf => -- sqrt (neg)\n -- Return quiet NAN, IEEE754-1985-7.1.6\n fpresult := qnanfp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when pos_inf => -- Sqrt (inf), return infinity\n fpresult := pos_inffp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when pos_zero => -- return 0\n fpresult := zerofp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when neg_zero => -- IEEE754-1985-6.3 return -0\n fpresult := neg_zerofp (fraction_width => fraction_width-guard,\n exponent_width => exponent_width);\n when others =>\n break_number (arg => arg,\n denormalize => denormalize,\n check_error => false,\n fract => ufact,\n expon => iexpon,\n sign => sign);\n expon := resize (iexpon+1, expon'length); -- get exponent\n fact := resize (ufact, fact'high, fact'low);\n if (expon(0) = '1') then\n fact := fact sla 1; -- * 2.0\n end if;\n expon := shift_right (expon, 1); -- exponent/2\n -- Newton's iteration - root := (1 + arg) / 2\n resb := (fact + 1) sra 1;\n for j in 0 to fraction_width/4 loop\n -- root := (root + (arg/root))/2\n resb := resize (arg => (resb + (fact/resb)) sra 1,\n left_index => resb'high,\n right_index => resb'low,\n round_style => fixed_truncate,\n overflow_style => fixed_wrap);\n end loop;\n fpresult := normalize (fract => resb,\n expon => expon-1,\n sign => '0',\n exponent_width => arg'high,\n fraction_width => -arg'low,\n round_style => round_style,\n denormalize => denormalize,\n nguard => guard);\n end case classcase;\n return fpresult;\n end function sqrt;\n\n function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is\n -- Technically -0 should return \"false\", but I'm leaving that case out.\n begin\n return (to_x01(arg(arg'high)) = '1');\n end function Is_Negative;\n\n -- compare functions\n -- =, /=, >=, <=, <, >\n\n function eq ( -- equal =\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable lfptype, rfptype : valid_fpstate;\n variable is_equal, is_unordered : BOOLEAN;\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- equal\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return false;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n end if;\n if (lfptype = neg_zero or lfptype = pos_zero) and\n (rfptype = neg_zero or rfptype = pos_zero) then\n is_equal := true;\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n is_equal := (to_slv(lresize) = to_slv(rresize));\n end if;\n if (check_error) then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return is_equal and not is_unordered;\n end function eq;\n\n function lt ( -- less than <\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable expl, expr : UNSIGNED (exponent_width-1 downto 0);\n variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);\n variable is_less_than, is_unordered : BOOLEAN;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n is_less_than := false;\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits\n expl := UNSIGNED(lresize(exponent_width-1 downto 0));\n expr := UNSIGNED(rresize(exponent_width-1 downto 0));\n if expl = expr then\n fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));\n fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));\n if to_x01(l(l'high)) = '0' then -- positive number\n is_less_than := (fractl < fractr);\n else\n is_less_than := (fractl > fractr); -- negative\n end if;\n else\n if to_x01(l(l'high)) = '0' then -- positive number\n is_less_than := (expl < expr);\n else\n is_less_than := (expl > expr); -- negative\n end if;\n end if;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n if (lfptype = neg_zero and rfptype = pos_zero) then\n is_less_than := false; -- -0 < 0 returns false.\n else\n is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));\n end if;\n end if;\n end if;\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return is_less_than and not is_unordered;\n end function lt;\n\n function gt ( -- greater than >\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable expl, expr : UNSIGNED (exponent_width-1 downto 0);\n variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);\n variable is_greater_than : BOOLEAN;\n variable is_unordered : BOOLEAN;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- greater_than\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n is_greater_than := false;\n else\n lresize := resize (arg => to_x01(l),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n rresize := resize (arg => to_x01(r),\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => denormalize,\n denormalize => denormalize);\n if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits\n expl := UNSIGNED(lresize(exponent_width-1 downto 0));\n expr := UNSIGNED(rresize(exponent_width-1 downto 0));\n if expl = expr then\n fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));\n fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));\n if to_x01(l(l'high)) = '0' then -- positive number\n is_greater_than := fractl > fractr;\n else\n is_greater_than := fractl < fractr; -- negative\n end if;\n else\n if to_x01(l(l'high)) = '0' then -- positive number\n is_greater_than := expl > expr;\n else\n is_greater_than := expl < expr; -- negative\n end if;\n end if;\n else\n lfptype := classfp (l, check_error);\n rfptype := classfp (r, check_error);\n if (lfptype = pos_zero and rfptype = neg_zero) then\n is_greater_than := false; -- 0 > -0 returns false.\n else\n is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));\n end if;\n end if;\n end if;\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return is_greater_than and not is_unordered;\n end function gt;\n\n -- purpose: /= function\n function ne ( -- not equal /=\n l, r : UNRESOLVED_float;\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable is_equal, is_unordered : BOOLEAN;\n begin\n is_equal := eq (l => l,\n r => r,\n check_error => false,\n denormalize => denormalize);\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return not (is_equal and not is_unordered);\n end function ne;\n\n function le ( -- less than or equal to <=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable is_greater_than, is_unordered : BOOLEAN;\n begin\n is_greater_than := gt (l => l,\n r => r,\n check_error => false,\n denormalize => denormalize);\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return not is_greater_than and not is_unordered;\n end function le;\n\n function ge ( -- greater than or equal to >=\n l, r : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize : BOOLEAN := float_denormalize)\n return BOOLEAN is\n variable is_less_than, is_unordered : BOOLEAN;\n begin\n is_less_than := lt (l => l,\n r => r,\n check_error => false,\n denormalize => denormalize);\n if check_error then\n is_unordered := Unordered (x => l,\n y => r);\n else\n is_unordered := false;\n end if;\n return not is_less_than and not is_unordered;\n end function ge;\n\n function \\?=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable is_equal, is_unordered : STD_ULOGIC;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- ?=\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n lfptype := classfp (l, float_check_error);\n rfptype := classfp (r, float_check_error);\n end if;\n if (lfptype = neg_zero or lfptype = pos_zero) and\n (rfptype = neg_zero or rfptype = pos_zero) then\n is_equal := '1';\n else\n lresize := resize (arg => l,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n rresize := resize (arg => r,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n is_equal := \\?=\\ (to_sulv(lresize), to_sulv(rresize));\n end if;\n if (float_check_error) then\n if (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan) then\n is_unordered := '1';\n else\n is_unordered := '0';\n end if;\n else\n is_unordered := '0';\n end if;\n return is_equal and not is_unordered;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lfptype, rfptype : valid_fpstate;\n variable is_equal, is_unordered : STD_ULOGIC;\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- ?/=\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n lfptype := classfp (l, float_check_error);\n rfptype := classfp (r, float_check_error);\n end if;\n if (lfptype = neg_zero or lfptype = pos_zero) and\n (rfptype = neg_zero or rfptype = pos_zero) then\n is_equal := '1';\n else\n lresize := resize (arg => l,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n rresize := resize (arg => r,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n denormalize_in => float_denormalize,\n denormalize => float_denormalize);\n is_equal := \\?=\\ (to_sulv(lresize), to_sulv(rresize));\n end if;\n if (float_check_error) then\n if (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan) then\n is_unordered := '1';\n else\n is_unordered := '0';\n end if;\n else\n is_unordered := '0';\n end if;\n return not (is_equal and not is_unordered);\n end function \\?/=\\;\n\n function \\?>\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l > r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>\\;\n\n function \\?>=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l >= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>=\\;\n\n function \\?<\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l < r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<\\;\n\n function \\?<=\\ (L, R : UNRESOLVED_float) return STD_ULOGIC is\n constant fraction_width : NATURAL := -mine(l'low, r'low);\n variable founddash : BOOLEAN := false;\n begin\n if (fraction_width = 0 or l'length < 7 or r'length < 7) then\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n founddash := true;\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n founddash := true;\n end if;\n end loop;\n if founddash then\n report float_pkg'instance_name\n & \" \"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n elsif is_x(l) or is_x(r) then\n return 'X';\n elsif l <= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<=\\;\n\n function std_match (L, R : UNRESOLVED_float) return BOOLEAN is\n begin\n if (L'high = R'high and L'low = R'low) then\n return std_match(to_sulv(L), to_sulv(R));\n else\n report float_pkg'instance_name\n & \"STD_MATCH: L'RANGE /= R'RANGE, returning FALSE\"\n severity warning;\n return false;\n end if;\n end function std_match;\n\n function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is\n begin\n for_loop : for i in arg'reverse_range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'high+1; -- return out of bounds 'high\n end function find_rightmost;\n\n function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is\n begin\n for_loop : for i in arg'range loop\n if \\?=\\ (arg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return arg'low-1; -- return out of bounds 'low\n end function find_leftmost;\n\n -- These override the defaults for the compare operators.\n function \"=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return eq(l, r);\n end function \"=\";\n\n function \"/=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return ne(l, r);\n end function \"/=\";\n\n function \">=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return ge(l, r);\n end function \">=\";\n\n function \"<=\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return le(l, r);\n end function \"<=\";\n\n function \">\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return gt(l, r);\n end function \">\";\n\n function \"<\" (l, r : UNRESOLVED_float) return BOOLEAN is\n begin\n return lt(l, r);\n end function \"<\";\n\n -- purpose: maximum of two numbers (overrides default)\n function maximum (\n L, R : UNRESOLVED_float)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAFP;\n end if;\n lresize := resize (l, exponent_width, fraction_width);\n rresize := resize (r, exponent_width, fraction_width);\n if lresize > rresize then return lresize;\n else return rresize;\n end if;\n end function maximum;\n\n function minimum (\n L, R : UNRESOLVED_float)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction\n constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent\n variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAFP;\n end if;\n lresize := resize (l, exponent_width, fraction_width);\n rresize := resize (r, exponent_width, fraction_width);\n if lresize > rresize then return rresize;\n else return lresize;\n end if;\n end function minimum;\n\n -----------------------------------------------------------------------------\n -- conversion functions\n -----------------------------------------------------------------------------\n\n -- Converts a floating point number of one format into another format\n function resize (\n arg : UNRESOLVED_float; -- Floating point input\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction\n constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n -- result value\n variable fptype : valid_fpstate;\n variable expon_in : SIGNED (in_exponent_width-1 downto 0);\n variable fract_in : UNSIGNED (in_fraction_width downto 0);\n variable round : BOOLEAN;\n variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract\n variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract\n variable passguard : NATURAL;\n begin\n fptype := classfp(arg, check_error);\n if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in\n and (in_exponent_width < exponent_width\n or in_fraction_width < fraction_width))\n or in_exponent_width > exponent_width\n or in_fraction_width > fraction_width then\n -- size reduction\n classcase : case fptype is\n when isx =>\n result := (others => 'X');\n when nan | quiet_nan =>\n result := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_inf =>\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when neg_inf =>\n result := neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when pos_zero | neg_zero =>\n result := zerofp (fraction_width => fraction_width, -- hate -0\n exponent_width => exponent_width);\n when others =>\n break_number (\n arg => arg,\n fptyp => fptype,\n denormalize => denormalize_in,\n fract => fract_in,\n expon => expon_in);\n if fraction_width > in_fraction_width and denormalize_in then\n -- You only get here if you have a denormal input\n fract_out := (others => '0'); -- pad with zeros\n fract_out (fraction_width downto\n fraction_width - in_fraction_width) := fract_in;\n result := normalize (\n fract => fract_out,\n expon => expon_in,\n sign => arg(arg'high),\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => 0);\n else\n result := normalize (\n fract => fract_in,\n expon => expon_in,\n sign => arg(arg'high),\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => in_fraction_width - fraction_width);\n end if;\n end case classcase;\n else -- size increase or the same size\n if exponent_width > in_exponent_width then\n expon_in := SIGNED(arg (in_exponent_width-1 downto 0));\n if fptype = pos_zero or fptype = neg_zero then\n result (exponent_width-1 downto 0) := (others => '0');\n elsif expon_in = -1 then -- inf or nan (shorts out check_error)\n result (exponent_width-1 downto 0) := (others => '1');\n else\n -- invert top BIT\n expon_in(expon_in'high) := not expon_in(expon_in'high);\n expon_out := resize (expon_in, expon_out'length); -- signed expand\n -- Flip it back.\n expon_out(expon_out'high) := not expon_out(expon_out'high);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);\n end if;\n result (exponent_width) := arg (in_exponent_width); -- sign\n else -- exponent_width = in_exponent_width\n result (exponent_width downto 0) := arg (in_exponent_width downto 0);\n end if;\n if fraction_width > in_fraction_width then\n result (-1 downto -fraction_width) := (others => '0'); -- zeros\n result (-1 downto -in_fraction_width) :=\n arg (-1 downto -in_fraction_width);\n else -- fraction_width = in_fraciton_width\n result (-1 downto -fraction_width) :=\n arg (-1 downto -in_fraction_width);\n end if;\n end if;\n return result;\n end function resize;\n\n function resize (\n arg : UNRESOLVED_float; -- floating point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := resize (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n return result;\n end if;\n end function resize;\n\n function to_float32 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float32 is\n begin\n return resize (arg => arg,\n exponent_width => float32'high,\n fraction_width => -float32'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n end function to_float32;\n\n function to_float64 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float64 is\n begin\n return resize (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n end function to_float64;\n\n function to_float128 (\n arg : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error;\n constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float128 is\n begin\n return resize (arg => arg,\n exponent_width => float128'high,\n fraction_width => -float128'low,\n round_style => round_style,\n check_error => check_error,\n denormalize_in => denormalize_in,\n denormalize => denormalize);\n end function to_float128;\n\n -- to_float (Real)\n -- typically not Synthesizable unless the input is a constant.\n function to_float (\n arg : REAL;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arg_real : REAL; -- Real version of argument\n variable validfp : boundary_type; -- Check for valid results\n variable exp : INTEGER; -- Integer version of exponent\n variable expon : UNSIGNED (exponent_width - 1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable fract : UNSIGNED (fraction_width-1 downto 0);\n variable frac : REAL; -- Real version of fraction\n constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding\n variable round : BOOLEAN; -- to round or not to round\n begin\n result := (others => '0');\n arg_real := arg;\n if arg_real < 0.0 then\n result (exponent_width) := '1';\n arg_real := - arg_real; -- Make it positive.\n else\n result (exponent_width) := '0';\n end if;\n test_boundary (arg => arg_real,\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n denormalize => denormalize,\n btype => validfp,\n log2i => exp);\n if validfp = zero then\n return result; -- Result initialized to \"0\".\n elsif validfp = infinity then\n result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all \"1\"\n -- return infinity.\n return result;\n else\n if validfp = denormal then -- Exponent will default to \"0\".\n expon := (others => '0');\n frac := arg_real * (2.0 ** (to_integer(expon_base)-1));\n else -- Number less than 1. \"normal\" number\n expon := UNSIGNED (to_signed (exp-1, exponent_width));\n expon(exponent_width-1) := not expon(exponent_width-1);\n frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.\n end if;\n for i in 0 to fract'high loop\n if frac >= 2.0 ** (-1 - i) then\n fract (fract'high - i) := '1';\n frac := frac - 2.0 ** (-1 - i);\n else\n fract (fract'high - i) := '0';\n end if;\n end loop;\n round := false;\n case round_style is\n when round_nearest =>\n if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then\n round := true;\n end if;\n when round_inf =>\n if frac /= 0.0 and result(exponent_width) = '0' then\n round := true;\n end if;\n when round_neginf =>\n if frac /= 0.0 and result(exponent_width) = '1' then\n round := true;\n end if;\n when others =>\n null; -- don't round\n end case;\n if (round) then\n if and_reduce (fract) = '1' then -- fraction is all \"1\"\n expon := expon + 1;\n fract := (others => '0');\n else\n fract := fract + 1;\n end if;\n end if;\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n return result;\n end if;\n end function to_float;\n\n -- to_float (Integer)\n function to_float (\n arg : INTEGER;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arg_int : NATURAL; -- Natural version of argument\n variable expon : SIGNED (exponent_width-1 downto 0);\n variable exptmp : SIGNED (exponent_width-1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');\n variable fracttmp : UNSIGNED (fraction_width-1 downto 0);\n variable round : BOOLEAN;\n variable shift : NATURAL;\n variable shiftr : NATURAL;\n variable roundfrac : NATURAL; -- used in rounding\n begin\n if arg < 0 then\n result (exponent_width) := '1';\n arg_int := -arg; -- Make it positive.\n else\n result (exponent_width) := '0';\n arg_int := arg;\n end if;\n if arg_int = 0 then\n result := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n -- If the number is larger than we can represent in this number system\n -- we need to return infinity.\n shift := log2(arg_int);\n if shift > to_integer(expon_base) then\n -- worry about infinity\n if result (exponent_width) = '0' then\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n -- return negative infinity.\n result := neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n end if;\n else -- Normal number (can't be denormal)\n -- Compute Exponent\n expon := to_signed (shift-1, expon'length); -- positive fraction.\n -- Compute Fraction\n arg_int := arg_int - 2**shift; -- Subtract off the 1.0\n shiftr := shift;\n for I in fract'high downto maximum (fract'high - shift + 1, 0) loop\n shiftr := shiftr - 1;\n if (arg_int >= 2**shiftr) then\n arg_int := arg_int - 2**shiftr;\n fract(I) := '1';\n else\n fract(I) := '0';\n end if;\n end loop;\n -- Rounding routine\n round := false;\n if arg_int > 0 then\n roundfrac := 2**(shiftr-1);\n case round_style is\n when round_nearest =>\n if arg_int > roundfrac or\n ((arg_int = roundfrac) and fract(0) = '1') then\n round := true;\n end if;\n when round_inf =>\n if arg_int /= 0 and result (exponent_width) = '0' then\n round := true;\n end if;\n when round_neginf =>\n if arg_int /= 0 and result (exponent_width) = '1' then\n round := true;\n end if;\n when others =>\n null;\n end case;\n end if;\n if round then\n fp_round(fract_in => fract,\n expon_in => expon,\n fract_out => fracttmp,\n expon_out => exptmp);\n fract := fracttmp;\n expon := exptmp;\n end if;\n -- Put the number together and return\n expon(exponent_width-1) := not expon(exponent_width-1);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n end if;\n end if;\n return result;\n end function to_float;\n\n -- to_float (unsigned)\n function to_float (\n arg : UNSIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;\n variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg\n begin\n if arg'length < 1 then\n return NAFP;\n end if;\n sarg (XARG'range) := SIGNED (XARG);\n sarg (sarg'high) := '0';\n result := to_float (arg => sarg,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n round_style => round_style);\n return result;\n end function to_float;\n\n -- to_float (signed)\n function to_float (\n arg : SIGNED;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n constant ARG_LEFT : INTEGER := ARG'length-1;\n alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;\n variable arg_int : UNSIGNED(xarg'range); -- Real version of argument\n variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input\n variable rexp : SIGNED (exponent_width - 1 downto 0);\n variable exp : SIGNED (exponent_width - 1 downto 0);\n -- signed version of exp.\n variable expon : UNSIGNED (exponent_width - 1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable round : BOOLEAN;\n variable fract : UNSIGNED (fraction_width-1 downto 0);\n variable rfract : UNSIGNED (fraction_width-1 downto 0);\n variable sign : STD_ULOGIC; -- sign bit\n begin\n if arg'length < 1 then\n return NAFP;\n end if;\n if Is_X (xarg) then\n result := (others => 'X');\n elsif (xarg = 0) then\n result := zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else -- Normal number (can't be denormal)\n sign := to_X01(xarg (xarg'high));\n arg_int := UNSIGNED(abs (to_01(xarg)));\n -- Compute Exponent\n argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2\n if argb2 > UNSIGNED(expon_base) then\n result := pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n result (exponent_width) := sign;\n else\n exp := SIGNED(resize(argb2, exp'length));\n arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));\n if (arg_int'high > fraction_width) then\n fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));\n round := check_round (\n fract_in => fract (0),\n sign => sign,\n remainder => arg_int((arg_int'high-fraction_width-1)\n downto 0),\n round_style => round_style);\n if round then\n fp_round(fract_in => fract,\n expon_in => exp,\n fract_out => rfract,\n expon_out => rexp);\n else\n rfract := fract;\n rexp := exp;\n end if;\n else\n rexp := exp;\n rfract := (others => '0');\n rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=\n arg_int (arg_int'high-1 downto 0);\n end if;\n result (exponent_width) := sign;\n expon := UNSIGNED (rexp-1);\n expon(exponent_width-1) := not expon(exponent_width-1);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);\n end if;\n end if;\n return result;\n end function to_float;\n\n -- std_logic_vector to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float is\n variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin\n if arg'length < 1 then\n return NAFP;\n end if;\n fpvar := UNRESOLVED_float(arg);\n return fpvar;\n end function to_float;\n\n -- purpose: converts a ufixed to a floating point\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n constant exponent_width : NATURAL := float_exponent_width; -- width of exponent\n constant fraction_width : NATURAL := float_fraction_width; -- width of fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float is\n variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n begin -- function to_float\n if (arg'length < 1) then\n return NAFP;\n end if;\n sarg (arg'range) := sfixed (arg);\n sarg (sarg'high) := '0';\n result := to_float (arg => sarg,\n exponent_width => exponent_width,\n fraction_width => fraction_width,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end function to_float;\n\n function to_float (\n arg : UNRESOLVED_sfixed; -- signed fixed point\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float is\n constant integer_width : INTEGER := arg'high;\n constant in_fraction_width : INTEGER := arg'low;\n variable xresult : sfixed (integer_width downto in_fraction_width);\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable arg_int : UNSIGNED(integer_width - in_fraction_width\n downto 0); -- unsigned version of argument\n variable argx : SIGNED (integer_width - in_fraction_width downto 0);\n variable exp, exptmp : SIGNED (exponent_width + 1 downto 0);\n variable expon : UNSIGNED (exponent_width - 1 downto 0);\n -- Unsigned version of exp.\n constant expon_base : SIGNED (exponent_width-1 downto 0) :=\n gen_expon_base(exponent_width); -- exponent offset\n variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=\n (others => '0');\n variable round : BOOLEAN := false;\n begin\n if (arg'length < 1) then\n return NAFP;\n end if;\n xresult := to_01(arg, 'X');\n argx := SIGNED(to_slv(xresult));\n if (Is_X (arg)) then\n result := (others => 'X');\n elsif (argx = 0) then\n result := (others => '0');\n else\n result := (others => '0'); -- zero out the result\n if argx(argx'left) = '1' then -- toss the sign bit\n result (exponent_width) := '1'; -- Negative number\n arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement\n else\n result (exponent_width) := '0';\n arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned\n end if;\n -- Compute Exponent\n exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2\n if exp + in_fraction_width > expon_base then -- return infinity\n result (-1 downto -fraction_width) := (others => '0');\n result (exponent_width -1 downto 0) := (others => '1');\n return result;\n elsif (denormalize and\n (exp + in_fraction_width <= -resize(expon_base, exp'length))) then\n exp := -resize(expon_base, exp'length);\n -- shift by a constant\n arg_int := shift_left (arg_int,\n (arg_int'high + to_integer(expon_base)\n + in_fraction_width - 1));\n if (arg_int'high > fraction_width) then\n fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));\n round := check_round (\n fract_in => arg_int(arg_int'high-fraction_width),\n sign => result(result'high),\n remainder => arg_int((arg_int'high-fraction_width-1)\n downto 0),\n round_style => round_style);\n if (round) then\n fp_round (fract_in => arg_int (arg_int'high-1 downto\n (arg_int'high-fraction_width)),\n expon_in => exp,\n fract_out => fract,\n expon_out => exptmp);\n exp := exptmp;\n end if;\n else\n fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=\n arg_int (arg_int'high-1 downto 0);\n end if;\n else\n arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));\n exp := exp + in_fraction_width;\n if (arg_int'high > fraction_width) then\n fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));\n round := check_round (\n fract_in => fract(0),\n sign => result(result'high),\n remainder => arg_int((arg_int'high-fraction_width-1)\n downto 0),\n round_style => round_style);\n if (round) then\n fp_round (fract_in => fract,\n expon_in => exp,\n fract_out => fracttmp,\n expon_out => exptmp);\n fract := fracttmp;\n exp := exptmp;\n end if;\n else\n fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=\n arg_int (arg_int'high-1 downto 0);\n end if;\n end if;\n expon := UNSIGNED (resize(exp-1, exponent_width));\n expon(exponent_width-1) := not expon(exponent_width-1);\n result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n end if;\n return result;\n end function to_float;\n\n -- size_res functions\n -- Integer to float\n function to_float (\n arg : INTEGER;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style);\n return result;\n end if;\n end function to_float;\n\n -- real to float\n function to_float (\n arg : REAL;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding option\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end if;\n end function to_float;\n\n -- unsigned to float\n function to_float (\n arg : UNSIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style);\n return result;\n end if;\n end function to_float;\n\n -- signed to float\n function to_float (\n arg : SIGNED;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style) -- rounding\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style);\n return result;\n end if;\n end function to_float;\n\n -- std_ulogic_vector to float\n function to_float (\n arg : STD_ULOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n return result;\n end if;\n end function to_float;\n\n -- unsigned fixed point to float\n function to_float (\n arg : UNRESOLVED_ufixed; -- unsigned fixed point input\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end if;\n end function to_float;\n\n -- signed fixed point to float\n function to_float (\n arg : UNRESOLVED_sfixed;\n size_res : UNRESOLVED_float;\n constant round_style : round_type := float_round_style; -- rounding\n constant denormalize : BOOLEAN := float_denormalize) -- rounding option\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_float (arg => arg,\n exponent_width => size_res'high,\n fraction_width => -size_res'low,\n round_style => round_style,\n denormalize => denormalize);\n return result;\n end if;\n end function to_float;\n\n -- to_integer (float)\n function to_integer (\n arg : UNRESOLVED_float; -- floating point input\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return INTEGER is\n variable validfp : valid_fpstate; -- Valid FP state\n variable frac : UNSIGNED (-arg'low downto 0); -- Fraction\n variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction\n variable expon : SIGNED (arg'high-1 downto 0);\n variable isign : STD_ULOGIC; -- internal version of sign\n variable round : STD_ULOGIC; -- is rounding needed?\n variable result : INTEGER;\n variable base : INTEGER; -- Integer exponent\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>\n result := 0; -- return 0\n when pos_inf =>\n result := INTEGER'high;\n when neg_inf =>\n result := INTEGER'low;\n when others =>\n break_number (\n arg => arg,\n fptyp => validfp,\n denormalize => false,\n fract => frac,\n expon => expon);\n fract (fract'high) := '0'; -- Add extra bit for 0.6 case\n fract (fract'high-1 downto 0) := frac;\n isign := to_x01 (arg (arg'high));\n base := to_integer (expon) + 1;\n if base < -1 then\n result := 0;\n elsif base >= frac'high then\n result := to_integer (fract) * 2**(base - frac'high);\n else -- We need to round\n if base = -1 then -- trap for 0.6 case.\n result := 0;\n else\n result := to_integer (fract (frac'high downto frac'high-base));\n end if;\n -- rounding routine\n case round_style is\n when round_nearest =>\n if frac'high - base > 1 then\n round := fract (frac'high - base - 1) and\n (fract (frac'high - base)\n or (or_reduce (fract (frac'high - base - 2 downto 0))));\n else\n round := fract (frac'high - base - 1) and\n fract (frac'high - base);\n end if;\n when round_inf =>\n round := fract(frac'high - base - 1) and not isign;\n when round_neginf =>\n round := fract(frac'high - base - 1) and isign;\n when others =>\n round := '0';\n end case;\n if round = '1' then\n result := result + 1;\n end if;\n end if;\n if isign = '1' then\n result := - result;\n end if;\n end case classcase;\n return result;\n end function to_integer;\n\n -- to_unsigned (float)\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED is\n variable validfp : valid_fpstate; -- Valid FP state\n variable frac : UNSIGNED (size-1 downto 0); -- Fraction\n variable sign : STD_ULOGIC; -- not used\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n frac := (others => 'X');\n when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>\n frac := (others => '0'); -- return 0\n when pos_inf =>\n frac := (others => '1');\n when others =>\n float_to_unsigned (\n arg => arg,\n frac => frac,\n sign => sign,\n denormalize => false,\n bias => 0,\n round_style => round_style);\n end case classcase;\n return (frac);\n end function to_unsigned;\n\n -- to_signed (float)\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n constant size : NATURAL; -- length of output\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED is\n variable sign : STD_ULOGIC; -- true if negative\n variable validfp : valid_fpstate; -- Valid FP state\n variable frac : UNSIGNED (size-1 downto 0); -- Fraction\n variable result : SIGNED (size-1 downto 0);\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n result := (others => 'X');\n when pos_zero | neg_zero | pos_denormal | neg_denormal =>\n result := (others => '0'); -- return 0\n when pos_inf =>\n result := (others => '1');\n result (result'high) := '0';\n when neg_inf =>\n result := (others => '0');\n result (result'high) := '1';\n when others =>\n float_to_unsigned (\n arg => arg,\n sign => sign,\n frac => frac,\n denormalize => false,\n bias => 0,\n round_style => round_style);\n result (size-1) := '0';\n result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));\n if sign = '1' then\n -- Because the most negative signed number is 1 less than the most\n -- positive signed number, we need this code.\n if frac(frac'high) = '1' then -- return most negative number\n result := (others => '0');\n result (result'high) := '1';\n else\n result := -result;\n end if;\n else\n if frac(frac'high) = '1' then -- return most positive number\n result := (others => '1');\n result (result'high) := '0';\n end if;\n end if;\n end case classcase;\n return result;\n end function to_signed;\n\n -- purpose: Converts a float to ufixed\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed is\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n constant size : INTEGER := left_index - right_index + 4; -- unsigned size\n variable expon_base : INTEGER; -- exponent offset\n variable validfp : valid_fpstate; -- Valid FP state\n variable exp : INTEGER; -- Exponent\n variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent\n -- Base to divide fraction by\n variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction\n variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted\n variable shift : INTEGER;\n variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);\n variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result\n begin -- function to_ufixed\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n frac := (others => 'X');\n when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>\n frac := (others => '0'); -- return 0\n when pos_inf =>\n frac := (others => '1'); -- always saturate\n when others =>\n expon_base := 2**(exponent_width-1) -1; -- exponent offset\n -- Figure out the fraction\n if (validfp = pos_denormal) and denormalize then\n exp := -expon_base +1;\n frac (frac'high) := '0'; -- Remove the \"1.0\".\n else\n -- exponent /= '0', normal floating point\n expon := UNSIGNED(arg (exponent_width-1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (SIGNED(expon)) +1;\n frac (frac'high) := '1'; -- Add the \"1.0\".\n end if;\n shift := (frac'high - 3 + right_index) - exp;\n if fraction_width > frac'high then -- Can only use size-2 bits\n frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto\n -frac'high)));\n else -- can use all bits\n frac (frac'high-1 downto frac'high-fraction_width) :=\n UNSIGNED (to_slv (arg(-1 downto -fraction_width)));\n end if;\n frac_shift := frac srl shift;\n if shift < 0 then -- Overflow\n frac := (others => '1');\n else\n frac := frac_shift;\n end if;\n end case classcase;\n result_big := to_ufixed (\n arg => STD_ULOGIC_VECTOR(frac),\n left_index => left_index,\n right_index => (right_index-3));\n result := resize (arg => result_big,\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n return result;\n end function to_ufixed;\n\n -- purpose: Converts a float to sfixed\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n constant left_index : INTEGER; -- integer part\n constant right_index : INTEGER; -- fraction part\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed is\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n constant size : INTEGER := left_index - right_index + 4; -- unsigned size\n variable expon_base : INTEGER; -- exponent offset\n variable validfp : valid_fpstate; -- Valid FP state\n variable exp : INTEGER; -- Exponent\n variable sign : BOOLEAN; -- true if negative\n variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent\n -- Base to divide fraction by\n variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction\n variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted\n variable shift : INTEGER;\n variable rsigned : SIGNED (size-1 downto 0); -- signed version of result\n variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);\n variable result : UNRESOLVED_sfixed (left_index downto right_index)\n := (others => '0'); -- result\n begin -- function to_sfixed\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | nan | quiet_nan =>\n result := (others => 'X');\n when pos_zero | neg_zero =>\n result := (others => '0'); -- return 0\n when neg_inf =>\n result (left_index) := '1'; -- return smallest negative number\n when pos_inf =>\n result := (others => '1'); -- return largest number\n result (left_index) := '0';\n when others =>\n expon_base := 2**(exponent_width-1) -1; -- exponent offset\n if arg(exponent_width) = '0' then\n sign := false;\n else\n sign := true;\n end if;\n -- Figure out the fraction\n if (validfp = pos_denormal or validfp = neg_denormal)\n and denormalize then\n exp := -expon_base +1;\n frac (frac'high) := '0'; -- Add the \"1.0\".\n else\n -- exponent /= '0', normal floating point\n expon := UNSIGNED(arg (exponent_width-1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (SIGNED(expon)) +1;\n frac (frac'high) := '1'; -- Add the \"1.0\".\n end if;\n shift := (frac'high - 3 + right_index) - exp;\n if fraction_width > frac'high then -- Can only use size-2 bits\n frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto\n -frac'high)));\n else -- can use all bits\n frac (frac'high-1 downto frac'high-fraction_width) :=\n UNSIGNED (to_slv (arg(-1 downto -fraction_width)));\n end if;\n frac_shift := frac srl shift;\n if shift < 0 then -- Overflow\n frac := (others => '1');\n else\n frac := frac_shift;\n end if;\n if not sign then\n rsigned := SIGNED(\"0\" & frac);\n else\n rsigned := -(SIGNED(\"0\" & frac));\n end if;\n result_big := to_sfixed (\n arg => STD_LOGIC_VECTOR(rsigned),\n left_index => left_index,\n right_index => (right_index-3));\n result := resize (arg => result_big,\n left_index => left_index,\n right_index => right_index,\n round_style => round_style,\n overflow_style => overflow_style);\n end case classcase;\n return result;\n end function to_sfixed;\n\n -- size_res versions\n -- float to unsigned\n function to_unsigned (\n arg : UNRESOLVED_float; -- floating point input\n size_res : UNSIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return UNSIGNED is\n variable result : UNSIGNED (size_res'range);\n begin\n if (SIZE_RES'length = 0) then\n return result;\n else\n result := to_unsigned (\n arg => arg,\n size => size_res'length,\n round_style => round_style,\n check_error => check_error);\n return result;\n end if;\n end function to_unsigned;\n\n -- float to signed\n function to_signed (\n arg : UNRESOLVED_float; -- floating point input\n size_res : SIGNED;\n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error) -- check for errors\n return SIGNED is\n variable result : SIGNED (size_res'range);\n begin\n if (SIZE_RES'length = 0) then\n return result;\n else\n result := to_signed (\n arg => arg,\n size => size_res'length,\n round_style => round_style,\n check_error => check_error);\n return result;\n end if;\n end function to_signed;\n\n -- purpose: Converts a float to unsigned fixed point\n function to_ufixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_ufixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_ufixed is\n variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_ufixed (\n arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style,\n check_error => check_error,\n denormalize => denormalize);\n return result;\n end if;\n end function to_ufixed;\n\n -- float to signed fixed point\n function to_sfixed (\n arg : UNRESOLVED_float; -- fp input\n size_res : UNRESOLVED_sfixed;\n constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate\n constant round_style : fixed_round_style_type := fixed_round_style; -- rounding\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_sfixed is\n variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);\n begin\n if (result'length < 1) then\n return result;\n else\n result := to_sfixed (\n arg => arg,\n left_index => size_res'high,\n right_index => size_res'low,\n overflow_style => overflow_style,\n round_style => round_style,\n check_error => check_error,\n denormalize => denormalize);\n return result;\n end if;\n end function to_sfixed;\n\n -- to_real (float)\n -- typically not Synthesizable unless the input is a constant.\n function to_real (\n arg : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return REAL is\n constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction\n constant exponent_width : INTEGER := arg'high; -- length of FP output exponent\n variable sign : REAL; -- Sign, + or - 1\n variable exp : INTEGER; -- Exponent\n variable expon_base : INTEGER; -- exponent offset\n variable frac : REAL := 0.0; -- Fraction\n variable validfp : valid_fpstate; -- Valid FP state\n variable expon : UNSIGNED (exponent_width - 1 downto 0)\n := (others => '1'); -- Vectorized exponent\n begin\n validfp := classfp (arg, check_error);\n classcase : case validfp is\n when isx | pos_zero | neg_zero | nan | quiet_nan =>\n return 0.0;\n when neg_inf =>\n return REAL'low; -- Negative infinity.\n when pos_inf =>\n return REAL'high; -- Positive infinity\n when others =>\n expon_base := 2**(exponent_width-1) -1;\n if to_X01(arg(exponent_width)) = '0' then\n sign := 1.0;\n else\n sign := -1.0;\n end if;\n -- Figure out the fraction\n for i in 0 to fraction_width-1 loop\n if to_X01(arg (-1 - i)) = '1' then\n frac := frac + (2.0 **(-1 - i));\n end if;\n end loop; -- i\n if validfp = pos_normal or validfp = neg_normal or not denormalize then\n -- exponent /= '0', normal floating point\n expon := UNSIGNED(arg (exponent_width-1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n exp := to_integer (SIGNED(expon)) +1;\n sign := sign * (2.0 ** exp) * (1.0 + frac);\n else -- exponent = '0', IEEE extended floating point\n exp := 1 - expon_base;\n sign := sign * (2.0 ** exp) * frac;\n end if;\n return sign;\n end case classcase;\n end function to_real;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is\n variable result : float64; -- 64 bit floating point\n begin\n result := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_sulv (result);\n end function realtobits;\n\n function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is\n variable arg64 : float64; -- arg converted to float\n begin\n arg64 := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_real (arg64);\n end function bitstoreal;\n\n -- purpose: Removes meta-logical values from FP string\n function to_01 (\n arg : UNRESOLVED_float; -- floating point input\n XMAP : STD_LOGIC := '0')\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin -- function to_01\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_01: null detected, returning NULL\"\n severity warning;\n return NAFP;\n end if;\n result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));\n return result;\n end function to_01;\n\n function Is_X\n (arg : UNRESOLVED_float)\n return BOOLEAN is\n begin\n return Is_X (to_slv(arg));\n end function Is_X;\n\n function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_X01: null detected, returning NULL\"\n severity warning;\n return NAFP;\n else\n result := UNRESOLVED_float (to_X01(to_slv(arg)));\n return result;\n end if;\n end function to_X01;\n\n function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_X01Z: null detected, returning NULL\"\n severity warning;\n return NAFP;\n else\n result := UNRESOLVED_float (to_X01Z(to_slv(arg)));\n return result;\n end if;\n end function to_X01Z;\n\n function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is\n variable result : UNRESOLVED_float (arg'range);\n begin\n if (arg'length < 1) then\n assert NO_WARNING\n report float_pkg'instance_name\n & \"TO_UX01: null detected, returning NULL\"\n severity warning;\n return NAFP;\n else\n result := UNRESOLVED_float (to_UX01(to_slv(arg)));\n return result;\n end if;\n end function to_UX01;\n\n -- These allows the base math functions to use the default values\n -- of their parameters. Thus they do full IEEE floating point.\n function \"+\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return add (l, r);\n end function \"+\";\n\n function \"-\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return subtract (l, r);\n end function \"-\";\n\n function \"*\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return multiply (l, r);\n end function \"*\";\n\n function \"/\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return divide (l, r);\n end function \"/\";\n\n function \"rem\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return remainder (l, r);\n end function \"rem\";\n\n function \"mod\" (l, r : UNRESOLVED_float) return UNRESOLVED_float is\n begin\n return modulo (l, r);\n end function \"mod\";\n\n -- overloaded versions\n function \"+\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return add (l, r_float);\n end function \"+\";\n\n function \"+\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return add (l_float, r);\n end function \"+\";\n\n function \"+\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return add (l, r_float);\n end function \"+\";\n\n function \"+\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return add (l_float, r);\n end function \"+\";\n\n function \"-\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return subtract (l, r_float);\n end function \"-\";\n\n function \"-\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return subtract (l_float, r);\n end function \"-\";\n\n function \"-\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return subtract (l, r_float);\n end function \"-\";\n\n function \"-\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return subtract (l_float, r);\n end function \"-\";\n\n function \"*\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return multiply (l, r_float);\n end function \"*\";\n\n function \"*\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return multiply (l_float, r);\n end function \"*\";\n\n function \"*\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return multiply (l, r_float);\n end function \"*\";\n\n function \"*\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return multiply (l_float, r);\n end function \"*\";\n\n function \"/\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return divide (l, r_float);\n end function \"/\";\n\n function \"/\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return divide (l_float, r);\n end function \"/\";\n\n function \"/\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return divide (l, r_float);\n end function \"/\";\n\n function \"/\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return divide (l_float, r);\n end function \"/\";\n\n function \"rem\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return remainder (l, r_float);\n end function \"rem\";\n\n function \"rem\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return remainder (l_float, r);\n end function \"rem\";\n\n function \"rem\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return remainder (l, r_float);\n end function \"rem\";\n\n function \"rem\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return remainder (l_float, r);\n end function \"rem\";\n\n function \"mod\" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return modulo (l, r_float);\n end function \"mod\";\n\n function \"mod\" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return modulo (l_float, r);\n end function \"mod\";\n\n function \"mod\" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return modulo (l, r_float);\n end function \"mod\";\n\n function \"mod\" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return modulo (l_float, r);\n end function \"mod\";\n\n function \"=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return eq (l, r_float);\n end function \"=\";\n\n function \"/=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ne (l, r_float);\n end function \"/=\";\n\n function \">=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ge (l, r_float);\n end function \">=\";\n\n function \"<=\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return le (l, r_float);\n end function \"<=\";\n\n function \">\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return gt (l, r_float);\n end function \">\";\n\n function \"<\" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return lt (l, r_float);\n end function \"<\";\n\n function \"=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return eq (l_float, r);\n end function \"=\";\n\n function \"/=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ne (l_float, r);\n end function \"/=\";\n\n function \">=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ge (l_float, r);\n end function \">=\";\n\n function \"<=\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return le (l_float, r);\n end function \"<=\";\n\n function \">\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return gt (l_float, r);\n end function \">\";\n\n function \"<\" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return lt (l_float, r);\n end function \"<\";\n\n function \"=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return eq (l, r_float);\n end function \"=\";\n\n function \"/=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ne (l, r_float);\n end function \"/=\";\n\n function \">=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return ge (l, r_float);\n end function \">=\";\n\n function \"<=\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return le (l, r_float);\n end function \"<=\";\n\n function \">\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return gt (l, r_float);\n end function \">\";\n\n function \"<\" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return lt (l, r_float);\n end function \"<\";\n\n function \"=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return eq (l_float, r);\n end function \"=\";\n\n function \"/=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ne (l_float, r);\n end function \"/=\";\n\n function \">=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return ge (l_float, r);\n end function \">=\";\n\n function \"<=\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return le (l_float, r);\n end function \"<=\";\n\n function \">\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return gt (l_float, r);\n end function \">\";\n\n function \"<\" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float(l, r'high, -r'low);\n return lt (l_float, r);\n end function \"<\";\n\n -- ?= overloads\n function \\?=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?=\\ (l, r_float);\n end function \\?=\\;\n\n function \\?/=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?/=\\ (l, r_float);\n end function \\?/=\\;\n\n function \\?>\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>\\ (l, r_float);\n end function \\?>\\;\n\n function \\?>=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>=\\ (l, r_float);\n end function \\?>=\\;\n\n function \\?<\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<\\ (l, r_float);\n end function \\?<\\;\n\n function \\?<=\\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<=\\ (l, r_float);\n end function \\?<=\\;\n\n -- real and float\n function \\?=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?=\\ (l_float, r);\n end function \\?=\\;\n\n function \\?/=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?/=\\ (l_float, r);\n end function \\?/=\\;\n\n function \\?>\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>\\ (l_float, r);\n end function \\?>\\;\n\n function \\?>=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>=\\ (l_float, r);\n end function \\?>=\\;\n\n function \\?<\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<\\ (l_float, r);\n end function \\?<\\;\n\n function \\?<=\\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<=\\ (l_float, r);\n end function \\?<=\\;\n\n -- ?= overloads\n function \\?=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?=\\ (l, r_float);\n end function \\?=\\;\n\n function \\?/=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?/=\\ (l, r_float);\n end function \\?/=\\;\n\n function \\?>\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>\\ (l, r_float);\n end function \\?>\\;\n\n function \\?>=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?>=\\ (l, r_float);\n end function \\?>=\\;\n\n function \\?<\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<\\ (l, r_float);\n end function \\?<\\;\n\n function \\?<=\\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return \\?<=\\ (l, r_float);\n end function \\?<=\\;\n\n -- integer and float\n function \\?=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?=\\ (l_float, r);\n end function \\?=\\;\n\n function \\?/=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?/=\\ (l_float, r);\n end function \\?/=\\;\n\n function \\?>\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>\\ (l_float, r);\n end function \\?>\\;\n\n function \\?>=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?>=\\ (l_float, r);\n end function \\?>=\\;\n\n function \\?<\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<\\ (l_float, r);\n end function \\?<\\;\n\n function \\?<=\\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return \\?<=\\ (l_float, r);\n end function \\?<=\\;\n\n -- minimum and maximum overloads\n function minimum (l : UNRESOLVED_float; r : REAL)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return minimum (l, r_float);\n end function minimum;\n\n function maximum (l : UNRESOLVED_float; r : REAL)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return maximum (l, r_float);\n end function maximum;\n\n function minimum (l : REAL; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return minimum (l_float, r);\n end function minimum;\n\n function maximum (l : REAL; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return maximum (l_float, r);\n end function maximum;\n\n function minimum (l : UNRESOLVED_float; r : INTEGER)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return minimum (l, r_float);\n end function minimum;\n\n function maximum (l : UNRESOLVED_float; r : INTEGER)\n return UNRESOLVED_float is\n variable r_float : UNRESOLVED_float (l'range);\n begin\n r_float := to_float (r, l'high, -l'low);\n return maximum (l, r_float);\n end function maximum;\n\n function minimum (l : INTEGER; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return minimum (l_float, r);\n end function minimum;\n\n function maximum (l : INTEGER; r : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable l_float : UNRESOLVED_float (r'range);\n begin\n l_float := to_float (l, r'high, -r'low);\n return maximum (l_float, r);\n end function maximum;\n\n ----------------------------------------------------------------------------\n -- logical functions\n ----------------------------------------------------------------------------\n function \"not\" (L : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n RESULT := not to_sulv(L);\n return to_float (RESULT, L'high, -L'low);\n end function \"not\";\n\n function \"and\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) and to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"and\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"and\";\n\n function \"or\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) or to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"or\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"or\";\n\n function \"nand\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nand to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"nand\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"nand\";\n\n function \"nor\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) nor to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"nor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"nor\";\n\n function \"xor\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xor to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"xor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"xor\";\n\n function \"xnor\" (L, R : UNRESOLVED_float) return UNRESOLVED_float is\n variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto\n begin\n if (L'high = R'high and L'low = R'low) then\n RESULT := to_sulv(L) xnor to_sulv(R);\n else\n assert NO_WARNING\n report float_pkg'instance_name\n & \"\"\"xnor\"\": Range error L'RANGE /= R'RANGE\"\n severity warning;\n RESULT := (others => 'X');\n end if;\n return to_float (RESULT, L'high, -L'low);\n end function \"xnor\";\n\n -- Vector and std_ulogic functions, same as functions in numeric_std\n function \"and\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L and R(i);\n end loop;\n return result;\n end function \"and\";\n\n function \"and\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) and R;\n end loop;\n return result;\n end function \"and\";\n\n function \"or\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L or R(i);\n end loop;\n return result;\n end function \"or\";\n\n function \"or\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) or R;\n end loop;\n return result;\n end function \"or\";\n\n function \"nand\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L nand R(i);\n end loop;\n return result;\n end function \"nand\";\n\n function \"nand\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nand R;\n end loop;\n return result;\n end function \"nand\";\n\n function \"nor\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L nor R(i);\n end loop;\n return result;\n end function \"nor\";\n\n function \"nor\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) nor R;\n end loop;\n return result;\n end function \"nor\";\n\n function \"xor\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L xor R(i);\n end loop;\n return result;\n end function \"xor\";\n\n function \"xor\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xor R;\n end loop;\n return result;\n end function \"xor\";\n\n function \"xnor\" (L : STD_ULOGIC; R : UNRESOLVED_float)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (R'range);\n begin\n for i in result'range loop\n result(i) := L xnor R(i);\n end loop;\n return result;\n end function \"xnor\";\n\n function \"xnor\" (L : UNRESOLVED_float; R : STD_ULOGIC)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (L'range);\n begin\n for i in result'range loop\n result(i) := L(i) xnor R;\n end loop;\n return result;\n end function \"xnor\";\n\n -- Reduction operator_reduces, same as numeric_std functions\n\n function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return and_reduce (to_sulv(l));\n end function and_reduce;\n\n function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return nand_reduce (to_sulv(l));\n end function nand_reduce;\n\n function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return or_reduce (to_sulv(l));\n end function or_reduce;\n\n function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return nor_reduce (to_sulv(l));\n end function nor_reduce;\n\n function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return xor_reduce (to_sulv(l));\n end function xor_reduce;\n\n function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is\n begin\n return xnor_reduce (to_sulv(l));\n end function xnor_reduce;\n\n -----------------------------------------------------------------------------\n -- Recommended Functions from the IEEE 754 Appendix\n -----------------------------------------------------------------------------\n -- returns x with the sign of y.\n function Copysign (\n x, y : UNRESOLVED_float) -- floating point input\n return UNRESOLVED_float is\n begin\n return y(y'high) & x (x'high-1 downto x'low);\n end function Copysign;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : INTEGER; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction\n constant exponent_width : NATURAL := y'high; -- length of FP output exponent\n variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument\n variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp\n variable exp : SIGNED (exponent_width downto 0);\n variable ufract : UNSIGNED (fraction_width downto 0);\n constant expon_base : SIGNED (exponent_width-1 downto 0)\n := gen_expon_base(exponent_width); -- exponent offset\n variable fptype : valid_fpstate;\n begin\n -- This can be done by simply adding N to the exponent.\n arg := to_01 (y, 'X');\n fptype := classfp(arg, check_error);\n classcase : case fptype is\n when isx =>\n result := (others => 'X');\n when nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n result := qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n when others =>\n break_number (\n arg => arg,\n fptyp => fptype,\n denormalize => denormalize,\n fract => ufract,\n expon => expon);\n exp := resize (expon, exp'length) + N;\n result := normalize (\n fract => ufract,\n expon => exp,\n sign => to_x01 (arg (arg'high)),\n fraction_width => fraction_width,\n exponent_width => exponent_width,\n round_style => round_style,\n denormalize => denormalize,\n nguard => 0);\n end case classcase;\n return result;\n end function Scalb;\n\n -- Returns y * 2**n for integral values of N without computing 2**n\n function Scalb (\n y : UNRESOLVED_float; -- floating point input\n N : SIGNED; -- exponent to add \n constant round_style : round_type := float_round_style; -- rounding option\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP\n return UNRESOLVED_float is\n variable n_int : INTEGER;\n begin\n n_int := to_integer(N);\n return Scalb (y => y,\n N => n_int,\n round_style => round_style,\n check_error => check_error,\n denormalize => denormalize);\n end function Scalb;\n\n -- returns the unbiased exponent of x\n function Logb (\n x : UNRESOLVED_float) -- floating point input\n return INTEGER is\n constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction\n constant exponent_width : NATURAL := x'high; -- length of FP output exponent\n variable result : INTEGER; -- result\n variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument\n variable expon : SIGNED (exponent_width - 1 downto 0);\n variable fract : UNSIGNED (fraction_width downto 0);\n constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent\n -- offset +1\n variable fptype : valid_fpstate;\n begin\n -- Just return the exponent.\n arg := to_01 (x, 'X');\n fptype := classfp(arg);\n classcase : case fptype is\n when isx | nan | quiet_nan =>\n -- Return quiet NAN, IEEE754-1985-7.1,1\n result := 0;\n when pos_denormal | neg_denormal =>\n fract (fraction_width) := '0';\n fract (fraction_width-1 downto 0) :=\n UNSIGNED (to_slv(arg(-1 downto -fraction_width)));\n result := find_leftmost (fract, '1') -- Find the first \"1\"\n - fraction_width; -- subtract the length we want\n result := -expon_base + 1 + result;\n when others =>\n expon := SIGNED(arg (exponent_width - 1 downto 0));\n expon(exponent_width-1) := not expon(exponent_width-1);\n expon := expon + 1;\n result := to_integer (expon);\n end case classcase;\n return result;\n end function Logb;\n\n -- returns the unbiased exponent of x\n function Logb (\n x : UNRESOLVED_float) -- floating point input\n return SIGNED is\n constant exponent_width : NATURAL := x'high; -- length of FP output exponent\n variable result : SIGNED (exponent_width - 1 downto 0); -- result\n begin\n -- Just return the exponent.\n result := to_signed (Logb (x), exponent_width);\n return result;\n end function Logb;\n\n -- returns the next representable neighbor of x in the direction toward y\n function Nextafter (\n x, y : UNRESOLVED_float; -- floating point input\n constant check_error : BOOLEAN := float_check_error; -- check for errors\n constant denormalize : BOOLEAN := float_denormalize)\n return UNRESOLVED_float is\n constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction\n constant exponent_width : NATURAL := x'high; -- length of FP output exponent\n function \"=\" (\n l, r : UNRESOLVED_float) -- inputs\n return BOOLEAN is\n begin -- function \"=\"\n return eq (l => l,\n r => r,\n check_error => false);\n end function \"=\";\n function \">\" (\n l, r : UNRESOLVED_float) -- inputs\n return BOOLEAN is\n begin -- function \">\"\n return gt (l => l,\n r => r,\n check_error => false);\n end function \">\";\n variable fract : UNSIGNED (fraction_width-1 downto 0);\n variable expon : UNSIGNED (exponent_width-1 downto 0);\n variable sign : STD_ULOGIC;\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable validfpx, validfpy : valid_fpstate; -- Valid FP state\n begin -- fp_Nextafter\n -- If Y > X, add one to the fraction, otherwise subtract.\n validfpx := classfp (x, check_error);\n validfpy := classfp (y, check_error);\n if validfpx = isx or validfpy = isx then\n result := (others => 'X');\n return result;\n elsif (validfpx = nan or validfpy = nan) then\n return nanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif (validfpx = quiet_nan or validfpy = quiet_nan) then\n return qnanfp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n elsif x = y then -- Return X\n return x;\n else\n fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction\n expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent\n sign := x(exponent_width); -- sign bit\n if (y > x) then\n -- Increase the number given\n if validfpx = neg_inf then\n -- return most negative number\n expon := (others => '1');\n expon (0) := '0';\n fract := (others => '1');\n elsif validfpx = pos_zero or validfpx = neg_zero then\n -- return smallest denormal number\n sign := '0';\n expon := (others => '0');\n fract := (others => '0');\n fract(0) := '1';\n elsif validfpx = pos_normal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n if and_reduce (expon (exponent_width-1 downto 1)) = '1'\n and expon (0) = '0' then\n -- Exponent is one away from infinity.\n assert NO_WARNING\n report float_pkg'instance_name\n & \"FP_NEXTAFTER: NextAfter overflow\"\n severity warning;\n return pos_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n expon := expon + 1;\n fract := (others => '0');\n end if;\n else\n fract := fract + 1;\n end if;\n elsif validfpx = pos_denormal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n -- return smallest possible normal number\n expon := (others => '0');\n expon(0) := '1';\n fract := (others => '0');\n else\n fract := fract + 1;\n end if;\n elsif validfpx = neg_normal then\n if or_reduce (fract) = '0' then -- fraction is all \"0\".\n if or_reduce (expon (exponent_width-1 downto 1)) = '0' and\n expon (0) = '1' then -- Smallest exponent\n -- return the largest negative denormal number\n expon := (others => '0');\n fract := (others => '1');\n else\n expon := expon - 1;\n fract := (others => '1');\n end if;\n else\n fract := fract - 1;\n end if;\n elsif validfpx = neg_denormal then\n if or_reduce (fract(fract'high downto 1)) = '0'\n and fract (0) = '1' then -- Smallest possible fraction\n return zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n fract := fract - 1;\n end if;\n end if;\n else\n -- Decrease the number\n if validfpx = pos_inf then\n -- return most positive number\n expon := (others => '1');\n expon (0) := '0';\n fract := (others => '1');\n elsif validfpx = pos_zero\n or classfp (x) = neg_zero then\n -- return smallest negative denormal number\n sign := '1';\n expon := (others => '0');\n fract := (others => '0');\n fract(0) := '1';\n elsif validfpx = neg_normal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n if and_reduce (expon (exponent_width-1 downto 1)) = '1'\n and expon (0) = '0' then\n -- Exponent is one away from infinity.\n assert NO_WARNING\n report float_pkg'instance_name\n & \"FP_NEXTAFTER: NextAfter overflow\"\n severity warning;\n return neg_inffp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n expon := expon + 1; -- Fraction overflow\n fract := (others => '0');\n end if;\n else\n fract := fract + 1;\n end if;\n elsif validfpx = neg_denormal then\n if and_reduce (fract) = '1' then -- fraction is all \"1\".\n -- return smallest possible normal number\n expon := (others => '0');\n expon(0) := '1';\n fract := (others => '0');\n else\n fract := fract + 1;\n end if;\n elsif validfpx = pos_normal then\n if or_reduce (fract) = '0' then -- fraction is all \"0\".\n if or_reduce (expon (exponent_width-1 downto 1)) = '0' and\n expon (0) = '1' then -- Smallest exponent\n -- return the largest positive denormal number\n expon := (others => '0');\n fract := (others => '1');\n else\n expon := expon - 1;\n fract := (others => '1');\n end if;\n else\n fract := fract - 1;\n end if;\n elsif validfpx = pos_denormal then\n if or_reduce (fract(fract'high downto 1)) = '0'\n and fract (0) = '1' then -- Smallest possible fraction\n return zerofp (fraction_width => fraction_width,\n exponent_width => exponent_width);\n else\n fract := fract - 1;\n end if;\n end if;\n end if;\n result (-1 downto -fraction_width) := UNRESOLVED_float(fract);\n result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);\n result (exponent_width) := sign;\n return result;\n end if;\n end function Nextafter;\n\n -- Returns True if X is unordered with Y.\n function Unordered (\n x, y : UNRESOLVED_float) -- floating point input\n return BOOLEAN is\n variable lfptype, rfptype : valid_fpstate;\n begin\n lfptype := classfp (x);\n rfptype := classfp (y);\n if (lfptype = nan or lfptype = quiet_nan or\n rfptype = nan or rfptype = quiet_nan or\n lfptype = isx or rfptype = isx) then\n return true;\n else\n return false;\n end if;\n end function Unordered;\n\n function Finite (\n x : UNRESOLVED_float)\n return BOOLEAN is\n variable fp_state : valid_fpstate; -- fp state\n begin\n fp_state := Classfp (x);\n if (fp_state = pos_inf) or (fp_state = neg_inf) then\n return true;\n else\n return false;\n end if;\n end function Finite;\n\n function Isnan (\n x : UNRESOLVED_float)\n return BOOLEAN is\n variable fp_state : valid_fpstate; -- fp state\n begin\n fp_state := Classfp (x);\n if (fp_state = nan) or (fp_state = quiet_nan) then\n return true;\n else\n return false;\n end if;\n end function Isnan;\n\n -- Function to return constants.\n function zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n return result;\n end function zerofp;\n\n function nanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width-1 downto 0) := (others => '1');\n -- Exponent all \"1\"\n result (-1) := '1'; -- MSB of Fraction \"1\"\n -- Note: From W. Khan \"IEEE Standard 754 for Binary Floating Point\"\n -- The difference between a signaling NAN and a quiet NAN is that\n -- the MSB of the Fraction is a \"1\" in a Signaling NAN, and is a\n -- \"0\" in a quiet NAN.\n return result;\n end function nanfp;\n\n function qnanfp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width-1 downto 0) := (others => '1');\n -- Exponent all \"1\"\n result (-fraction_width) := '1'; -- LSB of Fraction \"1\"\n -- (Could have been any bit)\n return result;\n end function qnanfp;\n\n function pos_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all \"1\"\n return result;\n end function pos_inffp;\n\n function neg_inffp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width downto 0) := (others => '1'); -- top bits all \"1\"\n return result;\n end function neg_inffp;\n\n function neg_zerofp (\n constant exponent_width : NATURAL := float_exponent_width; -- exponent\n constant fraction_width : NATURAL := float_fraction_width) -- fraction\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=\n (others => '0'); -- zero\n begin\n result (exponent_width) := '1';\n return result;\n end function neg_zerofp;\n\n -- size_res versions\n function zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return zerofp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function zerofp;\n\n function nanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return nanfp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function nanfp;\n\n function qnanfp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return qnanfp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function qnanfp;\n\n function pos_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return pos_inffp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function pos_inffp;\n\n function neg_inffp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return neg_inffp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function neg_inffp;\n\n function neg_zerofp (\n size_res : UNRESOLVED_float) -- variable is only use for sizing\n return UNRESOLVED_float is\n begin\n return neg_zerofp (\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function neg_zerofp;\n\n-- rtl_synthesis off\n-- pragma synthesis_off\n\n --%%% these functions are copied from std_logic_1164 (VHDL-200X edition)\n -- Textio functions\n -- purpose: writes float into a line (NOTE changed basetype)\n type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);\n type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;\n type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;\n type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;\n\n constant NBSP : CHARACTER := CHARACTER'val(160); -- space character\n constant MVL9_to_char : char_indexed_by_MVL9 := \"UX01ZWLH-\";\n constant char_to_MVL9 : MVL9_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');\n constant char_to_MVL9plus : MVL9plus_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);\n constant NUS : STRING(2 to 1) := (others => ' ');\n\n -- purpose: Skips white space\n procedure skip_whitespace (\n L : inout LINE) is\n variable readOk : BOOLEAN;\n variable c : CHARACTER;\n begin\n while L /= null and L.all'length /= 0 loop\n if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then\n read (l, c, readOk);\n else\n exit;\n end if;\n end loop;\n end procedure skip_whitespace;\n\n-- %%% Replicated textio functions\n function to_ostring (value : STD_LOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+2)/3;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);\n variable result : STRING(1 to ne);\n variable tri : STD_LOGIC_VECTOR(0 to 2);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n tri := To_X01Z(ivalue(3*i to 3*i+2));\n case tri is\n when o\"0\" => result(i+1) := '0';\n when o\"1\" => result(i+1) := '1';\n when o\"2\" => result(i+1) := '2';\n when o\"3\" => result(i+1) := '3';\n when o\"4\" => result(i+1) := '4';\n when o\"5\" => result(i+1) := '5';\n when o\"6\" => result(i+1) := '6';\n when o\"7\" => result(i+1) := '7';\n when \"ZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_ostring;\n ------------------------------------------------------------------- \n function to_hstring (value : STD_LOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+3)/4;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);\n variable result : STRING(1 to ne);\n variable quad : STD_LOGIC_VECTOR(0 to 3);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n quad := To_X01Z(ivalue(4*i to 4*i+3));\n case quad is\n when x\"0\" => result(i+1) := '0';\n when x\"1\" => result(i+1) := '1';\n when x\"2\" => result(i+1) := '2';\n when x\"3\" => result(i+1) := '3';\n when x\"4\" => result(i+1) := '4';\n when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n when x\"7\" => result(i+1) := '7';\n when x\"8\" => result(i+1) := '8';\n when x\"9\" => result(i+1) := '9';\n when x\"A\" => result(i+1) := 'A';\n when x\"B\" => result(i+1) := 'B';\n when x\"C\" => result(i+1) := 'C';\n when x\"D\" => result(i+1) := 'D';\n when x\"E\" => result(i+1) := 'E';\n when x\"F\" => result(i+1) := 'F';\n when \"ZZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_hstring;\n procedure Char2TriBits (C : CHARACTER;\n RESULT : out STD_LOGIC_VECTOR(2 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n when '4' => result := o\"4\"; good := true;\n when '5' => result := o\"5\"; good := true;\n when '6' => result := o\"6\"; good := true;\n when '7' => result := o\"7\"; good := true;\n when 'Z' => result := \"ZZZ\"; good := true;\n when 'X' => result := \"XXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report float_pkg'instance_name\n & \"OREAD Error: Read a '\" & c &\n \"', expected an Octal character (0-7).\"\n severity error;\n result := \"UUU\";\n good := false;\n end case;\n end procedure Char2TriBits;\n\n procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2TriBits(c, sv(3*i to 3*i+2), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- read into a null array\n end if;\n end procedure OREAD;\n\n -- Hex Read and Write procedures for STD_ULOGIC_VECTOR.\n -- Modified from the original to be more forgiving.\n\n procedure Char2QuadBits (C : CHARACTER;\n RESULT : out STD_LOGIC_VECTOR(3 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := x\"0\"; good := true;\n when '1' => result := x\"1\"; good := true;\n when '2' => result := x\"2\"; good := true;\n when '3' => result := x\"3\"; good := true;\n when '4' => result := x\"4\"; good := true;\n when '5' => result := x\"5\"; good := true;\n when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n when 'B' | 'b' => result := x\"B\"; good := true;\n when 'C' | 'c' => result := x\"C\"; good := true;\n when 'D' | 'd' => result := x\"D\"; good := true;\n when 'E' | 'e' => result := x\"E\"; good := true;\n when 'F' | 'f' => result := x\"F\"; good := true;\n when 'Z' => result := \"ZZZZ\"; good := true;\n when 'X' => result := \"XXXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report float_pkg'instance_name\n & \"HREAD Error: Read a '\" & c &\n \"', expected a Hex character (0-F).\"\n severity error;\n result := \"UUUU\";\n good := false;\n end case;\n end procedure Char2QuadBits;\n\n procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- Null input string, skips whitespace\n end if;\n end procedure HREAD;\n\n-- %%% END replicated textio functions\n\n -- purpose: Checks the punctuation in a line\n procedure check_punctuation (\n arg : in STRING;\n colon : out BOOLEAN; -- There was a colon in the line\n dot : out BOOLEAN; -- There was a dot in the line\n good : out BOOLEAN; -- True if enough characters found\n chars : in INTEGER) is\n -- Examples. Legal inputs are \"0000000\", \"0000.000\", \"0:000:000\"\n alias xarg : STRING (1 to arg'length) is arg; -- make it downto range\n variable icolon, idot : BOOLEAN; -- internal\n variable j : INTEGER := 0; -- charters read\n begin\n good := false;\n icolon := false;\n idot := false;\n for i in 1 to arg'length loop\n if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then\n exit;\n elsif xarg(i) = ':' then\n icolon := true;\n elsif xarg(i) = '.' then\n idot := true;\n elsif xarg (i) /= '_' then\n j := j + 1;\n end if;\n end loop;\n if j = chars then\n good := true; -- There are enough charactes to read\n end if;\n colon := icolon;\n if idot and icolon then\n dot := false;\n else\n dot := idot;\n end if;\n end procedure check_punctuation;\n\n -- purpose: Searches a line for a \":\" and replaces it with a \".\".\n procedure fix_colon (\n arg : inout STRING;\n chars : in integer) is\n alias xarg : STRING (1 to arg'length) is arg; -- make it downto range\n variable j : INTEGER := 0; -- charters read\n begin\n for i in 1 to arg'length loop\n if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then\n exit;\n elsif xarg(i) = ':' then\n xarg (i) := '.';\n elsif xarg (i) /= '_' then\n j := j + 1;\n end if;\n end loop;\n end procedure fix_colon;\n\n procedure WRITE (\n L : inout LINE; -- input line\n VALUE : in UNRESOLVED_float; -- floating point input\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n variable s : STRING(1 to value'high - value'low +3);\n variable sindx : INTEGER;\n begin -- function write\n s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));\n s(2) := ':';\n sindx := 3;\n for i in VALUE'high-1 downto 0 loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n s(sindx) := ':';\n sindx := sindx + 1;\n for i in -1 downto VALUE'low loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n WRITE (L, s, JUSTIFIED, FIELD);\n end procedure WRITE;\n\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is\n -- Possible data: 0:0000:0000000\n -- 000000000000\n variable c : CHARACTER;\n variable mv : UNRESOLVED_float (VALUE'range);\n variable readOk : BOOLEAN;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable i : INTEGER; -- index variable\n begin -- READ\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n READ (l, c, readOk);\n if VALUE'length > 0 then\n i := value'high;\n readloop : loop\n if readOk = false then -- Bail out if there was a bad read\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Error end of file encountered.\"\n severity error;\n return;\n elsif c = ' ' or c = CR or c = HT then -- reading done.\n if (i /= value'low) then\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Warning: Value truncated.\"\n severity warning;\n return;\n end if;\n elsif c = '_' then\n if i = value'high then -- Begins with an \"_\"\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then -- \"__\" detected\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n elsif c = ':' or c = '.' then -- separator, ignore\n if not (i = -1 or i = value'high-1) then\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Warning: Separator point does not match number format: '\"\n & c & \"' encountered at location \" & INTEGER'image(i) & \".\"\n severity warning;\n end if;\n lastu := false;\n elsif (char_to_MVL9plus(c) = error) then\n report float_pkg'instance_name\n & \"READ(float): \"\n & \"Error: Character '\" & c & \"' read, expected STD_ULOGIC literal.\"\n severity error;\n return;\n else\n mv (i) := char_to_MVL9(c);\n i := i - 1;\n if i < value'low then\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n READ (l, c, readOk);\n end loop readloop;\n end if;\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is\n -- Possible data: 0:0000:0000000\n -- 000000000000\n variable c : CHARACTER;\n variable mv : UNRESOLVED_float (VALUE'range);\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n variable i : INTEGER; -- index variable\n variable readOk : BOOLEAN;\n begin -- READ\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n READ (l, c, readOk);\n if VALUE'length > 0 then\n i := value'high;\n good := false;\n readloop : loop\n if readOk = false then -- Bail out if there was a bad read\n return;\n elsif c = ' ' or c = CR or c = HT then -- reading done\n return;\n elsif c = '_' then\n if i = 0 then -- Begins with an \"_\"\n return;\n elsif lastu then -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n elsif c = ':' or c = '.' then -- separator, ignore\n -- good := (i = -1 or i = value'high-1);\n lastu := false;\n elsif (char_to_MVL9plus(c) = error) then\n return;\n else\n mv (i) := char_to_MVL9(c);\n i := i - 1;\n if i < value'low then\n good := true;\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n READ (l, c, readOk);\n end loop readloop;\n else\n good := true; -- read into a null array\n end if;\n end procedure READ;\n\n procedure OWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0) is -- width of field\n begin\n WRITE (L => L,\n VALUE => to_ostring(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure OWRITE;\n\n procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is\n constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/3);\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"short string encounted: \" & L.all\n & \" needs to have \" & integer'image (ne/3)\n & \" valid octal characters.\"\n severity error;\n return;\n elsif dot then\n OREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n OREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif nybble (2 downto 1) /= \"00\" then\n report float_pkg'instance_name & \"OREAD: \"\n & \"Illegal sign bit STRING encounted \"\n severity error;\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/3); -- replaces the colon with a \".\".\n OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n OREAD (L, slv, ok);\n if not ok then\n report float_pkg'instance_name & \"OREAD: \"\n & \"Error encounted during read\"\n severity error;\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n report float_pkg'instance_name & \"OREAD: \"\n & \"Vector truncated.\"\n severity error;\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n end if;\n end procedure OREAD;\n\n procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is\n constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n GOOD := false;\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/3);\n if not ok then\n return;\n elsif dot then\n OREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n OREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n return;\n elsif nybble (2 downto 1) /= \"00\" then\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/3); -- replaces the colon with a \".\".\n OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n OREAD (L, slv, ok);\n if not ok then\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n GOOD := true;\n end if;\n end procedure OREAD;\n\n procedure HWRITE (\n L : inout LINE; -- access type (pointer)\n VALUE : in UNRESOLVED_float; -- value to write\n JUSTIFIED : in SIDE := right; -- which side to justify text\n FIELD : in WIDTH := 0) is -- width of field\n begin\n WRITE (L => L,\n VALUE => to_hstring(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure HWRITE;\n\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is\n constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/4);\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"short string encounted: \" & L.all\n & \" needs to have \" & integer'image (ne/4)\n & \" valid hex characters.\"\n severity error;\n return;\n elsif dot then\n HREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n HREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif nybble (3 downto 1) /= \"000\" then\n report float_pkg'instance_name & \"HREAD: \"\n & \"Illegal sign bit STRING encounted \"\n severity error;\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/4); -- replaces the colon with a \".\".\n HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"error encounted reading STRING \" & L.all\n severity error;\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n HREAD (L, slv, ok);\n if not ok then\n report float_pkg'instance_name & \"HREAD: \"\n & \"Error encounted during read\"\n severity error;\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n report float_pkg'instance_name & \"HREAD: \"\n & \"Vector truncated.\"\n severity error;\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n end if;\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is\n constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad\n variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv\n variable slvu : ufixed (VALUE'range); -- Unsigned fixed point\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits\n variable colon, dot : BOOLEAN;\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n GOOD := false;\n Skip_whitespace (L);\n if VALUE'length > 0 then\n check_punctuation (arg => L.all,\n colon => colon,\n dot => dot,\n good => ok,\n chars => ne/4);\n if not ok then\n return;\n elsif dot then\n HREAD (L, slvu, ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n VALUE := UNRESOLVED_float (slvu);\n end if;\n elsif colon then\n HREAD (L, nybble, ok); -- read the sign bit\n if not ok then\n return;\n elsif nybble (3 downto 1) /= \"000\" then\n return;\n end if;\n read (l, c, ok); -- read the colon\n fix_colon (L.all, ne/4); -- replaces the colon with a \".\".\n HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number\n if not ok then\n return;\n else\n slvu (slvu'high) := nybble (0);\n VALUE := UNRESOLVED_float (slvu);\n end if;\n else\n HREAD (L, slv, ok);\n if not ok then\n return;\n end if;\n if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then\n return;\n end if;\n VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),\n VALUE'high, -VALUE'low);\n end if;\n GOOD := true;\n end if;\n end procedure HREAD;\n\n function to_string (value : UNRESOLVED_float) return STRING is\n variable s : STRING(1 to value'high - value'low +3);\n variable sindx : INTEGER;\n begin -- function write\n s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));\n s(2) := ':';\n sindx := 3;\n for i in VALUE'high-1 downto 0 loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n s(sindx) := ':';\n sindx := sindx + 1;\n for i in -1 downto VALUE'low loop\n s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));\n sindx := sindx + 1;\n end loop;\n return s;\n end function to_string;\n\n function to_hstring (value : UNRESOLVED_float) return STRING is\n variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);\n begin\n floop : for i in slv'range loop\n slv(i) := to_X01Z (value(i + value'low));\n end loop floop;\n return to_hstring (slv);\n end function to_hstring;\n\n function to_ostring (value : UNRESOLVED_float) return STRING is\n variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);\n begin\n floop : for i in slv'range loop\n slv(i) := to_X01Z (value(i + value'low));\n end loop floop;\n return to_ostring (slv);\n end function to_ostring;\n\n function from_string (\n bstring : STRING; -- binary string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(bstring);\n READ (L, result, good);\n deallocate (L);\n assert (good)\n report float_pkg'instance_name\n & \"from_string: Bad string \" & bstring\n severity error;\n return result;\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(ostring);\n OREAD (L, result, good);\n deallocate (L);\n assert (good)\n report float_pkg'instance_name\n & \"from_ostring: Bad string \" & ostring\n severity error;\n return result;\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n constant exponent_width : NATURAL := float_exponent_width;\n constant fraction_width : NATURAL := float_fraction_width)\n return UNRESOLVED_float is\n variable result : UNRESOLVED_float (exponent_width downto -fraction_width);\n variable L : LINE;\n variable good : BOOLEAN;\n begin\n L := new STRING'(hstring);\n HREAD (L, result, good);\n deallocate (L);\n assert (good)\n report float_pkg'instance_name\n & \"from_hstring: Bad string \" & hstring\n severity error;\n return result;\n end function from_hstring;\n\n function from_string (\n bstring : STRING; -- binary string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float is\n begin\n return from_string (bstring => bstring,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function from_string;\n\n function from_ostring (\n ostring : STRING; -- Octal string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float is\n begin\n return from_ostring (ostring => ostring,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function from_ostring;\n\n function from_hstring (\n hstring : STRING; -- hex string\n size_res : UNRESOLVED_float) -- used for sizing only \n return UNRESOLVED_float is\n begin\n return from_hstring (hstring => hstring,\n exponent_width => size_res'high,\n fraction_width => -size_res'low);\n end function from_hstring;\n-- rtl_synthesis on\n-- pragma synthesis_on\n function to_float (\n arg : STD_LOGIC_VECTOR;\n constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent\n constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction\n return UNRESOLVED_float is\n begin\n return to_float (\n arg => to_stdulogicvector (arg),\n exponent_width => exponent_width,\n fraction_width => fraction_width);\n end function to_float;\n\n function to_float (\n arg : STD_LOGIC_VECTOR;\n size_res : UNRESOLVED_float)\n return UNRESOLVED_float is\n begin\n return to_float (\n arg => to_stdulogicvector (arg),\n size_res => size_res);\n end function to_float;\n\n -- For Verilog compatability\n function realtobits (arg : REAL) return STD_LOGIC_VECTOR is\n variable result : float64; -- 64 bit floating point\n begin\n result := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_slv (result);\n end function realtobits;\n\n function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is\n variable arg64 : float64; -- arg converted to float\n begin\n arg64 := to_float (arg => arg,\n exponent_width => float64'high,\n fraction_width => -float64'low);\n return to_real (arg64);\n end function bitstoreal;\n\nend package body float_pkg;\n", "groundtruth": " when round_inf =>\n round := remainder(2) and not isign;\n when round_neginf =>\n round := remainder(2) and isign;\n when others =>\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/float_synth.vhdl", "left_context": "-------------------------------------------------------------------------------\n-- Synthesis test for the floating point math package\n-- This test is designed to be synthesizable and exercise much of the package.\n-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)\n-- --------------------------------------------------------------------\n-- modification history : Last Modified $Date: 2006-06-08 10:50:32-04 $\n-- Version $Id: float_synth.vhdl,v 1.1 2006-06-08 10:50:32-04 l435385 Exp $\n-------------------------------------------------------------------------------\nlibrary ieee, ieee_proposed;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee_proposed.fixed_float_types.all;\nuse ieee_proposed.fixed_pkg.all;\nuse ieee_proposed.float_pkg.all;\nuse ieee.math_real.all;\nentity float_synth is\n \n port (\n in1, in2 : in std_logic_vector (31 downto 0); -- inputs\n out1 : out std_logic_vector (31 downto 0); -- output\n cmd : in std_logic_vector (3 downto 0);\n clk, rst_n : in std_ulogic); -- clk and reset\n\nend entity float_synth;\n\narchitecture rtl of float_synth is\n subtype fp16 is float (6 downto -9); -- 16 bit\n\n type cmd_type is array (1 to 15) of std_ulogic_vector (cmd'range); -- cmd\n signal cmdarray : cmd_type; -- command pipeline\n type cry_type is array (0 to 15) of float32; -- arrays\n signal outx : cry_type;\n signal in1reg3, in2reg3 : float32; -- register stages\n \nbegin -- architecture rtl\n\n -- purpose: \"0000\" test the \"+\" operator\n cmd0reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n begin -- process cmd0reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(0) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(0) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n outarray(0) := in1reg3 + in2reg3;\n end if;\n\n end process cmd0reg;\n\n -- purpose: \"0001\" test the \"-\" operator\n cmd1reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n begin -- process cmd1reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(1) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(1) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n outarray(0) := in1reg3 - in2reg3;\n end if;\n\n end process cmd1reg;\n\n -- purpose: \"0010\" test the \"*\" operator\n cmd2reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(2) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(2) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n outarray(0) := in1reg3 * in2reg3;\n end if;\n\n end process cmd2reg;\n\n -- purpose: \"0011\" performs test the \"/\" operator\n cmd3reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n begin -- process cmd1reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(3) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(3) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n if (cmdarray(4) = \"0011\") then\n outarray(0) := in1reg3 / in2reg3;\n else\n outarray(0) := (others => '0');\n end if;\n end if;\n end process cmd3reg;\n\n -- purpose: \"0100\" test the \"resize\" function\n cmd4reg: process (clk, rst_n) is\n variable tmpfp161, tmpfp162 : fp16; -- 16 bit fp number\n variable outarray : cry_type; -- array for output\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n begin -- process cmd1reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(4) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(4) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n tmpfp161 := resize ( arg => in1reg3,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low,\n denormalize_in => true,\n denormalize => false,\n round_style => round_zero);\n when \"001\" =>\n tmpfp161 := resize ( arg => in1reg3,\n-- size_res => tmpfp161,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low,\n denormalize_in => false,\n denormalize => false);\n when \"010\" =>\n tmpfp161 := resize ( arg => in1reg3,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low,\n denormalize_in => false,\n denormalize => false);\n when \"011\" =>\n tmpfp161 := resize ( arg => in1reg3,\n-- size_res => tmpfp161,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low,\n denormalize_in => true,\n denormalize => false,\n round_style => round_inf);\n when \"100\" =>\n tmpfp161 := resize ( arg => in1reg3,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low,\n denormalize_in => true,\n denormalize => false,\n round_style => round_neginf);\n when \"101\" =>\n tmpfp161 := resize ( arg => in1reg3,\n-- size_res => tmpfp161,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low,\n denormalize_in => true,\n denormalize => false,\n check_error => false,\n round_style => round_zero);\n when \"110\" =>\n tmpfp161 := resize ( arg => in1reg3,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low);\n when \"111\" =>\n tmpfp161 := resize ( arg => in1reg3,\n exponent_width => tmpfp161'high,\n fraction_width => -tmpfp161'low\n-- size_res => tmpfp161\n );\n when others => null;\n end case;\n outarray(0)(-8 downto -23) := tmpfp161;\n outarray(0)(8 downto 6) := float(tmpcmd);\n outarray(0)(6 downto -7) := (others => '0');\n end if;\n end process cmd4reg;\n\n -- purpose: \"0101\" Conversion function test\n cmd5reg: process (clk, rst_n) is\n variable uns : unsigned (15 downto 0); -- unsigned number\n variable s : signed (15 downto 0); -- signed number\n variable uf : ufixed (8 downto -7); -- unsigned fixed\n variable sf : sfixed (8 downto -7); -- signed fixed point\n variable outarray : cry_type; -- array for output\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n begin -- process cmd1reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(5) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(5) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n uns := to_unsigned (in1reg3, uns'length);\n outarray(0)(-8 downto -23) := float(std_logic_vector(uns));\n when \"001\" =>\n uns := to_unsigned (in1reg3, uns);\n outarray(0)(-8 downto -23) := float(std_logic_vector(uns));\n when \"010\" =>\n s := to_signed (in1reg3, s'length);\n outarray(0)(-8 downto -23) := float(std_logic_vector(s));\n when \"011\" =>\n s := to_signed (in1reg3, s);\n outarray(0)(-8 downto -23) := float(std_logic_vector(s));\n when \"100\" =>\n uf := to_ufixed (in1reg3, uf'high, uf'low);\n outarray(0)(-8 downto -23) := float(to_slv(uf));\n when \"101\" =>\n uf := to_ufixed (in1reg3, uf);\n outarray(0)(-8 downto -23) := float(to_slv(uf));\n when \"110\" =>\n sf := to_sfixed (in1reg3, sf'high, sf'low);\n outarray(0)(-8 downto -23) := float(to_slv(sf));\n when \"111\" =>\n sf := to_sfixed (in1reg3, sf);\n outarray(0)(-8 downto -23) := float(to_slv(sf));\n when others => null;\n end case;\n outarray(0)(8 downto 6) := float(tmpcmd);\n outarray(0)(5 downto -7) := (others => '0');\n end if;\n end process cmd5reg;\n\n -- purpose: \"0110\" to_float()\n cmd6reg: process (clk, rst_n) is\n variable uns : unsigned (15 downto 0); -- unsigned number\n variable s : signed (15 downto 0); -- signed number\n variable uf : ufixed (8 downto -7); -- unsigned fixed\n variable sf : sfixed (8 downto -7); -- signed fixed point\n variable outarray : cry_type; -- array for output\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n begin -- process cmd1reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(6) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(6) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));\n outarray(0) := to_float(uns, 8, 23);\n when \"001\" =>\n uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));\n outarray(0) := to_float(uns, in1reg3);\n when \"010\" =>\n s := SIGNED (to_slv (in1reg3(-8 downto -23)));\n outarray(0) := to_float(s, 8, 23);\n when \"011\" =>\n s := SIGNED (to_slv (in1reg3(-8 downto -23)));\n outarray(0) := to_float(s, in1reg3);\n when \"100\" =>\n uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf'high, uf'low);\n outarray(0) := to_float(uf, 8, 23);\n when \"101\" =>\n uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf);\n outarray(0) := to_float(uf, in1reg3);\n when \"110\" =>\n sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf'high, sf'low);\n outarray(0) := to_float(sf, 8, 23);\n when \"111\" =>\n sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf);\n outarray(0) := to_float(sf, in1reg3);\n when others => null;\n end case;\n end if;\n end process cmd6reg;\n\n -- purpose: \"0111\" mod function\n cmd7reg: process (clk, rst_n) is\n variable tmpuns : unsigned (31 downto 0); -- unsigned number\n variable outarray : cry_type; -- array for output\n begin -- process cmd1reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(7) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(7) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n outarray(0) := in1reg3 mod in2reg3;\n end if;\n end process cmd7reg;\n\n -- purpose: \"1000\" rem function\n cmd8reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(8) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(8) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n outarray(0) := in1reg3 rem in2reg3;\n end if;\n\n end process cmd8reg;\n\n -- purpose: \"1001\" to_float (constants) test\n cmd9reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(9) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(9) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n outarray(0) := to_float(0, 8, 23);\n when \"001\" =>\n outarray(0) := to_float(0.0, 8, 23);\n when \"010\" =>\n outarray(0) := to_float(8, in1reg3);\n when \"011\" =>\n outarray(0) := to_float(8.0, in1reg3);\n when \"100\" =>\n outarray(0) := to_float(-8, 8, 23);\n when \"101\" =>\n outarray(0) := to_float(-8.0, 8, 23);\n when \"110\" =>\n outarray(0) := to_float(27000, in2reg3);\n when \"111\" =>\n-- outarray(0) := \"01000000010010010000111111011011\";\n outarray(0) := to_float(MATH_PI, in2reg3);\n when others => null;\n end case;\n end if;\n\n end process cmd9reg;\n\n -- purpose: \"1010\" data manipulation (+, -, scalb, etc)\n cmd10reg: process (clk, rst_n) is\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n variable s : SIGNED (7 downto 0); -- signed number\n variable outarray : cry_type; -- array for output\n constant posinf : float32 := \"01111111100000000000000000000000\"; -- +inf\n constant neginf : float32 := \"11111111100000000000000000000000\"; -- +inf\n constant onept5 : float32 := \"00111111110000000000000000000000\"; -- 1.5\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(10) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(10) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n outarray(0) := - in1reg3;\n when \"001\" =>\n outarray(0) := abs( in1reg3);\n when \"010\" =>\n if (cmdarray(4) = \"1010\") then\n s := resize (SIGNED (to_slv (in2reg3(8 downto 5))), s'length);\n outarray(0) := Scalb (in1reg3, s);\n else\n outarray(0) := (others => '0');\n end if;\n when \"011\" =>\n if (cmdarray(4) = \"1010\") then\n s := logb (in1reg3);\n outarray(0) := (others => '0');\n outarray(0)(-16 downto -23) := float(std_logic_vector(s));\n else\n outarray(0) := (others => '0');\n end if;\n when \"100\" =>\n outarray(0) := Nextafter ( in1reg3, onept5);\n when \"101\" =>\n outarray(0) := Nextafter ( in1reg3, -onept5);\n when \"110\" =>\n outarray(0) := Nextafter ( x => in1reg3, y => posinf,\n check_error => false,\n denormalize => false);\n when \"111\" =>\n outarray(0) := Nextafter (x => in1reg3, y => neginf,\n check_error => false,\n denormalize => false);\n when others => null;\n end case;\n end if;\n\n end process cmd10reg;\n\n -- purpose \"1011\" copysign\n cmd11reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n begin -- process cmd2reg\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(11) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(11) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n outarray(0) := Copysign (in1reg3, in2reg3);\n end if;\n end process cmd11reg;\n\n -- purpose \"1100\" compare test\n cmd12reg: process (clk, rst_n) is\n variable outarray : cry_type; -- array for output\n constant fifteenpt5 : float32 := \"01000001011110000000000000000000\";-- 15.5\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(12) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(12) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n outarray(0) := (others => '0');\n if (in1reg3 = in2reg3) then\n outarray(0)(outarray(0)'high) := '1';\n else\n outarray(0)(outarray(0)'high) := '0';\n end if;\n if (in1reg3 /= in2reg3) then\n outarray(0)(outarray(0)'high-1) := '1';\n else\n outarray(0)(outarray(0)'high-1) := '0';\n end if;\n if (in1reg3 > in2reg3) then\n outarray(0)(outarray(0)'high-2) := '1';\n else\n outarray(0)(outarray(0)'high-2) := '0';\n end if;\n if (in1reg3 < in2reg3) then\n outarray(0)(outarray(0)'high-3) := '1';\n else\n outarray(0)(outarray(0)'high-3) := '0';\n end if;\n if (in1reg3 >= in2reg3) then\n outarray(0)(outarray(0)'high-4) := '1';\n else\n outarray(0)(outarray(0)'high-4) := '0';\n end if;\n if (in1reg3 <= in2reg3) then\n outarray(0)(outarray(0)'high-5) := '1';\n else\n outarray(0)(outarray(0)'high-5) := '0';\n end if;\n outarray(0)(outarray(0)'high-6) := \\?=\\ (in1reg3, 15);\n outarray(0)(outarray(0)'high-7) := \\?=\\ (in1reg3, 15.5);\n if (Unordered (in1reg3, in2reg3)) then\n outarray(0)(outarray(0)'high-8) := '1';\n else\n outarray(0)(outarray(0)'high-8) := '0'; \n end if;\n if (Finite (in1reg3)) then\n outarray(0)(outarray(0)'high-9) := '1';\n else\n outarray(0)(outarray(0)'high-9) := '0'; \n end if;\n if (Isnan (in1reg3)) then\n outarray(0)(outarray(0)'high-10) := '1';\n else\n outarray(0)(outarray(0)'high-10) := '0'; \n end if;\n end if;\n\n end process cmd12reg;\n\n -- purpose \"1101\" boolean test\n cmd13reg: process (clk, rst_n) is\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n variable outarray : cry_type; -- array for output\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(13) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(13) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n", "right_context": " when \"100\" =>\n outarray(0) := in1reg3 nor in2reg3;\n when \"101\" =>\n outarray(0) := in1reg3 xor in2reg3;\n when \"110\" =>\n outarray(0) := in1reg3 xnor in2reg3;\n when \"111\" =>\n outarray(0) := in1reg3 xor '1';\n when others => null;\n end case;\n end if;\n\n end process cmd13reg;\n\n -- purpose \"1110\" reduce and vector test\n cmd14reg: process (clk, rst_n) is\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n variable outarray : cry_type; -- array for output\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(14) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(14) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n outarray(0) := (others => '0');\n outarray(0)(outarray(0)'high) := and_reduce (in1reg3);\n outarray(0)(outarray(0)'high-1) := nand_reduce (in1reg3);\n outarray(0)(outarray(0)'high-2) := or_reduce (in1reg3);\n outarray(0)(outarray(0)'high-3) := nor_reduce (in1reg3);\n outarray(0)(outarray(0)'high-4) := xor_reduce (in1reg3);\n outarray(0)(outarray(0)'high-5) := xnor_reduce (in1reg3);\n when \"001\" => \n outarray(0) := in1reg3 and in2reg3(in2reg3'high);\n when \"010\" => \n outarray(0) := in1reg3 or in2reg3(in2reg3'high);\n when \"011\" => \n outarray(0) := in1reg3 nand in2reg3(in2reg3'high);\n when \"100\" => \n outarray(0) := in1reg3 nor in2reg3(in2reg3'high);\n when \"101\" => \n outarray(0) := in2reg3(in2reg3'high) xor in1reg3;\n when \"110\" => \n outarray(0) := in2reg3(in2reg3'high) xnor in1reg3;\n when \"111\" => \n outarray(0) := in2reg3(in2reg3'high) and in1reg3;\n when others => null;\n end case;\n end if;\n\n end process cmd14reg;\n\n -- purpose \"1111\" + constant\n cmd15reg: process (clk, rst_n) is\n variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);\n variable outarray : cry_type; -- array for output\n begin -- process cmd2reg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n outx(15) <= ( others => '0'); \n jrloop: for j in 0 to 7 loop\n outarray (j) := (others => '0');\n end loop jrloop;\n elsif rising_edge(clk) then -- rising clock edge\n outx(15) <= outarray(7);\n jcloop: for j in 7 downto 1 loop\n outarray (j) := outarray(j-1);\n end loop jcloop;\n tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));\n case tmpcmd is\n when \"000\" =>\n outarray(0) := in1reg3 + 1;\n when \"001\" =>\n outarray(0) := 1 + in1reg3;\n when \"010\" =>\n outarray(0) := in1reg3 + 1.0;\n when \"011\" =>\n outarray(0) := 1.0 + in1reg3;\n when \"100\" =>\n outarray(0) := in1reg3 * 1;\n when \"101\" =>\n outarray(0) := 1 * in1reg3;\n when \"110\" =>\n outarray(0) := in1reg3 * 1.0;\n when \"111\" =>\n outarray(0) := 1.0 * in1reg3;\n when others => null;\n end case;\n end if;\n\n end process cmd15reg;\n \n -- purpose: multiply floating point\n -- type : sequential\n -- inputs : clk, rst_n, in1, in2\n -- outputs: out1\n cmdreg: process (clk, rst_n) is\n variable outreg : float32; -- register stages\n variable in1reg, in2reg : float32; -- register stages\n variable in1reg2, in2reg2 : float32; -- register stages\n begin -- process mulreg\n\n if rst_n = '0' then -- asynchronous reset (active low)\n in1reg := ( others => '0');\n in2reg := ( others => '0');\n in1reg2 := ( others => '0');\n in2reg2 := ( others => '0');\n in1reg3 <= ( others => '0');\n in2reg3 <= ( others => '0');\n out1 <= ( others => '0');\n outreg := (others => '0');\n rcloop: for i in 1 to 15 loop\n cmdarray (i) <= (others => '0');\n end loop rcloop;\n elsif rising_edge(clk) then -- rising clock edge\n out1 <= to_slv (outreg);\n outregc: case cmdarray (13) is\n when \"0000\" => outreg := outx (0);\n when \"0001\" => outreg := outx (1);\n when \"0010\" => outreg := outx (2);\n when \"0011\" => outreg := outx (3);\n when \"0100\" => outreg := outx (4);\n when \"0101\" => outreg := outx (5);\n when \"0110\" => outreg := outx (6);\n when \"0111\" => outreg := outx (7);\n when \"1000\" => outreg := outx (8);\n when \"1001\" => outreg := outx (9);\n when \"1010\" => outreg := outx (10);\n when \"1011\" => outreg := outx (11);\n when \"1100\" => outreg := outx (12);\n when \"1101\" => outreg := outx (13);\n when \"1110\" => outreg := outx (14);\n when \"1111\" => outreg := outx (15);\n when others => null;\n end case outregc;\n cmdpipe: for i in 15 downto 3 loop\n cmdarray (i) <= cmdarray (i-1);\n end loop cmdpipe;\n cmdarray (2) <= std_ulogic_vector(cmd);\n in1reg3 <= in1reg2;\n in2reg3 <= in2reg2;\n in1reg2 := in1reg;\n in2reg2 := in2reg;\n in1reg := to_float (in1, in1reg);\n in2reg := to_float (in2, in2reg);\n end if;\n\n end process cmdreg;\n\nend architecture rtl;\n", "groundtruth": " outarray(0) := not (in1reg3);\n when \"001\" =>\n outarray(0) := in1reg3 and in2reg3;\n when \"010\" =>\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/numeric_std_additions.vhdl", "left_context": "------------------------------------------------------------------------------\n-- \"numeric_std_additions\" package contains the additions to the standard\n-- \"numeric_std\" package proposed by the VHDL-200X-ft working group.\n-- This package should be compiled into \"ieee_proposed\" and used as follows:\n-- use ieee.std_logic_1164.all;\n-- use ieee.numeric_std.all;\n-- use ieee_proposed.numeric_std_additions.all;\n-- (this package is independant of \"std_logic_1164_additions\")\n-- Last Modified: $Date: 2007/09/27 14:46:32 $\n-- RCS ID: $Id: numeric_std_additions.vhdl,v 1.9 2007/09/27 14:46:32 l435385 Exp $\n--\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n------------------------------------------------------------------------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse std.textio.all;\n\npackage numeric_std_additions is\n -- Make these a subtype of \"signed\" and \"unsigned\" for compatability\n-- type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;\n-- type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;\n\n subtype UNRESOLVED_UNSIGNED is UNSIGNED;\n subtype UNRESOLVED_SIGNED is SIGNED;\n-- alias U_UNSIGNED is UNRESOLVED_UNSIGNED;\n-- alias U_SIGNED is UNRESOLVED_SIGNED;\n subtype U_UNSIGNED is UNSIGNED;\n subtype U_SIGNED is SIGNED; \n\n -- Id: A.3R\n function \"+\"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n -- Result subtype: UNSIGNED(L'RANGE)\n -- Result: Similar to A.3 where R is a one bit UNSIGNED\n\n -- Id: A.3L\n function \"+\"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n -- Result subtype: UNSIGNED(R'RANGE)\n -- Result: Similar to A.3 where L is a one bit UNSIGNED\n\n -- Id: A.4R\n function \"+\"(L : SIGNED; R : STD_ULOGIC) return SIGNED;\n -- Result subtype: SIGNED(L'RANGE)\n -- Result: Similar to A.4 where R is bit 0 of a non-negative\n -- SIGNED\n\n -- Id: A.4L\n function \"+\"(L : STD_ULOGIC; R : SIGNED) return SIGNED;\n -- Result subtype: UNSIGNED(R'RANGE)\n -- Result: Similar to A.4 where L is bit 0 of a non-negative\n -- SIGNED\n -- Id: A.9R\n function \"-\"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n -- Result subtype: UNSIGNED(L'RANGE)\n -- Result: Similar to A.9 where R is a one bit UNSIGNED\n\n -- Id: A.9L\n function \"-\"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n -- Result subtype: UNSIGNED(R'RANGE)\n -- Result: Similar to A.9 where L is a one bit UNSIGNED\n\n -- Id: A.10R\n function \"-\"(L : SIGNED; R : STD_ULOGIC) return SIGNED;\n -- Result subtype: SIGNED(L'RANGE)\n -- Result: Similar to A.10 where R is bit 0 of a non-negative\n -- SIGNED\n\n -- Id: A.10L\n function \"-\"(L : STD_ULOGIC; R : SIGNED) return SIGNED;\n -- Result subtype: UNSIGNED(R'RANGE)\n -- Result: Similar to A.10 where R is bit 0 of a non-negative\n -- SIGNED\n\n -- Id: M.2B\n -- %%% function \"?=\" (L, R : UNSIGNED) return std_ulogic;\n -- %%% function \"?/=\" (L, R : UNSIGNED) return std_ulogic;\n -- %%% function \"?>\" (L, R : UNSIGNED) return std_ulogic;\n -- %%% function \"?>=\" (L, R : UNSIGNED) return std_ulogic;\n -- %%% function \"?<\" (L, R : UNSIGNED) return std_ulogic;\n -- %%% function \"?<=\" (L, R : UNSIGNED) return std_ulogic;\n function \\?=\\ (L, R : UNSIGNED) return STD_ULOGIC;\n function \\?/=\\ (L, R : UNSIGNED) return STD_ULOGIC;\n function \\?>\\ (L, R : UNSIGNED) return STD_ULOGIC;\n function \\?>=\\ (L, R : UNSIGNED) return STD_ULOGIC;\n function \\?<\\ (L, R : UNSIGNED) return STD_ULOGIC;\n function \\?<=\\ (L, R : UNSIGNED) return STD_ULOGIC;\n function \\?=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;\n function \\?/=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;\n function \\?>\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;\n function \\?>=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;\n function \\?<\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;\n function \\?<=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;\n function \\?=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;\n function \\?/=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;\n function \\?>\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;\n function \\?>=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;\n function \\?<\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;\n function \\?<=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: terms compared per STD_LOGIC_1164 intent,\n -- returns an 'X' if a metavalue is passed\n\n -- Id: M.3B\n -- %%% function \"?=\" (L, R : SIGNED) return std_ulogic;\n -- %%% function \"?/=\" (L, R : SIGNED) return std_ulogic;\n -- %%% function \"?>\" (L, R : SIGNED) return std_ulogic;\n -- %%% function \"?>=\" (L, R : SIGNED) return std_ulogic;\n -- %%% function \"?<\" (L, R : SIGNED) return std_ulogic;\n -- %%% function \"?<=\" (L, R : SIGNED) return std_ulogic;\n function \\?=\\ (L, R : SIGNED) return STD_ULOGIC;\n function \\?/=\\ (L, R : SIGNED) return STD_ULOGIC;\n function \\?>\\ (L, R : SIGNED) return STD_ULOGIC;\n function \\?>=\\ (L, R : SIGNED) return STD_ULOGIC;\n function \\?<\\ (L, R : SIGNED) return STD_ULOGIC;\n function \\?<=\\ (L, R : SIGNED) return STD_ULOGIC;\n function \\?=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;\n function \\?/=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;\n function \\?>\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;\n function \\?>=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;\n function \\?<\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;\n function \\?<=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;\n function \\?=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;\n function \\?/=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;\n function \\?>\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;\n function \\?>=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;\n function \\?<\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;\n function \\?<=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC; \n -- Result subtype: std_ulogic\n -- Result: terms compared per STD_LOGIC_1164 intent,\n -- returns an 'X' if a metavalue is passed\n\n -- size_res versions of these functions (Bugzilla 165)\n function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;\n -- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)\n function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;\n -- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)\n function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;\n -- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)\n function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;\n -- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)\n -----------------------------------------------------------------------------\n -- New/updated funcitons for VHDL-200X fast track\n -----------------------------------------------------------------------------\n\n -- Overloaded functions from \"std_logic_1164\"\n function To_X01 (s : UNSIGNED) return UNSIGNED;\n function To_X01 (s : SIGNED) return SIGNED;\n\n function To_X01Z (s : UNSIGNED) return UNSIGNED;\n function To_X01Z (s : SIGNED) return SIGNED;\n\n function To_UX01 (s : UNSIGNED) return UNSIGNED;\n function To_UX01 (s : SIGNED) return SIGNED;\n\n function Is_X (s : UNSIGNED) return BOOLEAN;\n function Is_X (s : SIGNED) return BOOLEAN;\n\n function \"sla\" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;\n function \"sla\" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;\n\n function \"sra\" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;\n function \"sra\" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;\n\n -- Returns the maximum (or minimum) of the two numbers provided.\n -- All types (both inputs and the output) must be the same.\n -- These override the implicit funcitons, using the local \">\" operator\n function maximum (\n l, r : UNSIGNED) -- inputs\n return UNSIGNED;\n\n function maximum (\n l, r : SIGNED) -- inputs\n return SIGNED;\n\n function minimum (\n l, r : UNSIGNED) -- inputs\n return UNSIGNED;\n\n function minimum (\n l, r : SIGNED) -- inputs\n return SIGNED;\n\n function maximum (\n l : UNSIGNED; r : NATURAL) -- inputs\n return UNSIGNED;\n\n function maximum (\n l : SIGNED; r : INTEGER) -- inputs\n return SIGNED;\n\n function minimum (\n l : UNSIGNED; r : NATURAL) -- inputs\n return UNSIGNED;\n\n function minimum (\n l : SIGNED; r : INTEGER) -- inputs\n return SIGNED;\n\n function maximum (\n l : NATURAL; r : UNSIGNED) -- inputs\n return UNSIGNED;\n\n function maximum (\n l : INTEGER; r : SIGNED) -- inputs\n return SIGNED;\n\n function minimum (\n l : NATURAL; r : UNSIGNED) -- inputs\n return UNSIGNED;\n\n function minimum (\n l : INTEGER; r : SIGNED) -- inputs\n return SIGNED;\n -- Finds the first \"Y\" in the input string. Returns an integer index\n -- into that string. If \"Y\" does not exist in the string, then the\n -- \"find_rightmost\" returns arg'low -1, and \"find_leftmost\" returns -1\n function find_rightmost (\n arg : UNSIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER;\n \n function find_rightmost (\n arg : SIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER;\n \n function find_leftmost (\n arg : UNSIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER;\n \n function find_leftmost (\n arg : SIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER;\n\n function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;\n -- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)\n -- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with\n -- the specified SIZE.\n\n alias TO_U_UNSIGNED is\n TO_UNRESOLVED_UNSIGNED[NATURAL, NATURAL return UNRESOLVED_UNSIGNED];\n\n function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;\n -- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)\n -- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.\n\n alias TO_U_SIGNED is\n TO_UNRESOLVED_SIGNED[NATURAL, NATURAL return UNRESOLVED_SIGNED];\n\n -- L.15 \n function \"and\" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n\n-- L.16 \n function \"and\" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n\n-- L.17 \n function \"or\" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n\n-- L.18 \n function \"or\" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n\n-- L.19 \n function \"nand\" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n\n-- L.20 \n function \"nand\" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n\n-- L.21 \n function \"nor\" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n\n-- L.22 \n function \"nor\" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n\n-- L.23 \n function \"xor\" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n\n-- L.24 \n function \"xor\" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n\n-- L.25 \n function \"xnor\" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;\n\n-- L.26 \n function \"xnor\" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;\n\n-- L.27 \n function \"and\" (L : STD_ULOGIC; R : SIGNED) return SIGNED;\n\n-- L.28 \n function \"and\" (L : SIGNED; R : STD_ULOGIC) return SIGNED;\n\n-- L.29 \n function \"or\" (L : STD_ULOGIC; R : SIGNED) return SIGNED;\n\n-- L.30 \n function \"or\" (L : SIGNED; R : STD_ULOGIC) return SIGNED;\n\n-- L.31 \n function \"nand\" (L : STD_ULOGIC; R : SIGNED) return SIGNED;\n\n-- L.32 \n function \"nand\" (L : SIGNED; R : STD_ULOGIC) return SIGNED;\n\n-- L.33 \n function \"nor\" (L : STD_ULOGIC; R : SIGNED) return SIGNED;\n\n-- L.34 \n function \"nor\" (L : SIGNED; R : STD_ULOGIC) return SIGNED;\n\n-- L.35 \n function \"xor\" (L : STD_ULOGIC; R : SIGNED) return SIGNED;\n\n-- L.36 \n function \"xor\" (L : SIGNED; R : STD_ULOGIC) return SIGNED;\n\n-- L.37 \n function \"xnor\" (L : STD_ULOGIC; R : SIGNED) return SIGNED;\n\n-- L.38 \n function \"xnor\" (L : SIGNED; R : STD_ULOGIC) return SIGNED;\n\n -- %%% remove 12 functions (old syntax)\n function and_reduce(l : SIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of and'ing all of the bits of the vector. \n\n function nand_reduce(l : SIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of nand'ing all of the bits of the vector. \n\n function or_reduce(l : SIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of or'ing all of the bits of the vector. \n\n function nor_reduce(l : SIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of nor'ing all of the bits of the vector. \n\n function xor_reduce(l : SIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of xor'ing all of the bits of the vector. \n\n function xnor_reduce(l : SIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of xnor'ing all of the bits of the vector. \n\n function and_reduce(l : UNSIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of and'ing all of the bits of the vector. \n\n function nand_reduce(l : UNSIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of nand'ing all of the bits of the vector. \n\n function or_reduce(l : UNSIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of or'ing all of the bits of the vector. \n\n function nor_reduce(l : UNSIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of nor'ing all of the bits of the vector. \n\n function xor_reduce(l : UNSIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of xor'ing all of the bits of the vector. \n\n function xnor_reduce(l : UNSIGNED) return STD_ULOGIC;\n -- Result subtype: STD_LOGIC. \n -- Result: Result of xnor'ing all of the bits of the vector.\n\n -- %%% Uncomment the following 12 functions (new syntax)\n -- function \"and\" ( l : SIGNED ) RETURN std_ulogic;\n -- function \"nand\" ( l : SIGNED ) RETURN std_ulogic;\n -- function \"or\" ( l : SIGNED ) RETURN std_ulogic;\n -- function \"nor\" ( l : SIGNED ) RETURN std_ulogic;\n -- function \"xor\" ( l : SIGNED ) RETURN std_ulogic;\n -- function \"xnor\" ( l : SIGNED ) RETURN std_ulogic;\n -- function \"and\" ( l : UNSIGNED ) RETURN std_ulogic;\n -- function \"nand\" ( l : UNSIGNED ) RETURN std_ulogic;\n -- function \"or\" ( l : UNSIGNED ) RETURN std_ulogic;\n -- function \"nor\" ( l : UNSIGNED ) RETURN std_ulogic;\n -- function \"xor\" ( l : UNSIGNED ) RETURN std_ulogic;\n -- function \"xnor\" ( l : UNSIGNED ) RETURN std_ulogic;\n\n -- rtl_synthesis off\n-- pragma synthesis_off\n ------------------------------------------------------------------- \n -- string functions\n ------------------------------------------------------------------- \n function to_string (value : UNSIGNED) return STRING;\n function to_string (value : SIGNED) return STRING;\n\n -- explicitly defined operations\n\n alias to_bstring is to_string [UNSIGNED return STRING];\n alias to_bstring is to_string [SIGNED return STRING];\n alias to_binary_string is to_string [UNSIGNED return STRING];\n alias to_binary_string is to_string [SIGNED return STRING];\n\n function to_ostring (value : UNSIGNED) return STRING;\n function to_ostring (value : SIGNED) return STRING;\n alias to_octal_string is to_ostring [UNSIGNED return STRING];\n alias to_octal_string is to_ostring [SIGNED return STRING];\n\n function to_hstring (value : UNSIGNED) return STRING;\n function to_hstring (value : SIGNED) return STRING;\n alias to_hex_string is to_hstring [UNSIGNED return STRING];\n alias to_hex_string is to_hstring [SIGNED return STRING];\n\n procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);\n\n procedure READ(L : inout LINE; VALUE : out UNSIGNED);\n\n procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);\n\n procedure READ(L : inout LINE; VALUE : out SIGNED);\n\n procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n procedure WRITE (L : inout LINE; VALUE : in SIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];\n alias BREAD is READ [LINE, SIGNED, BOOLEAN];\n\n alias BREAD is READ [LINE, UNSIGNED];\n alias BREAD is READ [LINE, SIGNED];\n\n alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];\n alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];\n\n alias BINARY_READ is READ [LINE, UNSIGNED];\n alias BINARY_READ is READ [LINE, SIGNED];\n\n procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);\n procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);\n\n procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);\n procedure OREAD (L : inout LINE; VALUE : out SIGNED);\n\n alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];\n\n alias OCTAL_READ is OREAD [LINE, UNSIGNED];\n alias OCTAL_READ is OREAD [LINE, SIGNED];\n\n procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);\n procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);\n\n procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);\n procedure HREAD (L : inout LINE; VALUE : out SIGNED);\n\n alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];\n alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];\n\n alias HEX_READ is HREAD [LINE, UNSIGNED];\n alias HEX_READ is HREAD [LINE, SIGNED];\n\n alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];\n alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];\n\n alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];\n alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];\n\n procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n procedure OWRITE (L : inout LINE; VALUE : in SIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];\n alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];\n\n procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n procedure HWRITE (L : inout LINE; VALUE : in SIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];\n alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];\n\n -- rtl_synthesis on \n-- pragma synthesis_on\nend package numeric_std_additions;\n\npackage body numeric_std_additions is\n constant NAU : UNSIGNED(0 downto 1) := (others => '0');\n constant NAS : SIGNED(0 downto 1) := (others => '0');\n constant NO_WARNING : BOOLEAN := false; -- default to emit warnings\n function MAX (left, right : INTEGER) return INTEGER is\n begin\n if left > right then return left;\n else return right;\n end if;\n end function MAX;\n\n -- Id: A.3R\n function \"+\"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');\n begin\n XR(0) := R;\n return (L + XR);\n end function \"+\";\n\n -- Id: A.3L\n function \"+\"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');\n begin\n XL(0) := L;\n return (XL + R);\n end function \"+\";\n\n -- Id: A.4R\n function \"+\"(L : SIGNED; R: STD_ULOGIC) return SIGNED is\n variable XR : SIGNED(L'length-1 downto 0) := (others => '0');\n begin\n XR(0) := R;\n return (L + XR);\n end function \"+\";\n\n -- Id: A.4L\n function \"+\"(L : STD_ULOGIC; R: SIGNED) return SIGNED is\n variable XL : SIGNED(R'length-1 downto 0) := (others => '0');\n begin\n XL(0) := L;\n return (XL + R);\n end function \"+\";\n\n -- Id: A.9R\n function \"-\"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');\n begin\n XR(0) := R;\n return (L - XR);\n end function \"-\";\n\n -- Id: A.9L\n function \"-\"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');\n begin\n XL(0) := L;\n return (XL - R);\n end function \"-\";\n\n -- Id: A.10R\n function \"-\"(L : SIGNED; R: STD_ULOGIC) return SIGNED is\n variable XR : SIGNED(L'length-1 downto 0) := (others => '0');\n begin\n XR(0) := R;\n return (L - XR);\n end function \"-\";\n\n -- Id: A.10L\n function \"-\"(L : STD_ULOGIC; R: SIGNED) return SIGNED is\n variable XL : SIGNED(R'length-1 downto 0) := (others => '0');\n begin\n XL(0) := L;\n return (XL - R);\n end function \"-\";\n\n type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;\n constant match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U |\n ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X |\n ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 |\n ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 |\n ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z |\n ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W |\n ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L |\n ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H |\n ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - |\n );\n constant no_match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |\n ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |\n );\n\n-- %%% FUNCTION \"?=\" ( l, r : std_ulogic ) RETURN std_ulogic IS\n function \\?=\\ ( l, r : STD_ULOGIC ) return STD_ULOGIC is\n variable value : STD_ULOGIC;\n begin\n return match_logic_table (l, r);\n end function \\?=\\;\n function \\?/=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return no_match_logic_table (l, r);\n end function \\?/=\\;\n\n -- \"?=\" operator is similar to \"std_match\", but returns a std_ulogic..\n -- Id: M.2B\n function \\?=\\ (L, R: UNSIGNED) return STD_ULOGIC is\n constant L_LEFT : INTEGER := L'length-1;\n constant R_LEFT : INTEGER := R'length-1;\n alias XL : UNSIGNED(L_LEFT downto 0) is L;\n alias XR : UNSIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable LX : UNSIGNED(SIZE-1 downto 0);\n variable RX : UNSIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin\n -- Logically identical to an \"=\" operator.\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '1';\n for i in LX'low to LX'high loop\n result1 := \\?=\\(LX(i), RX(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result and result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?=\\;\n\n -- %%% Replace with the following function\n -- function \"?=\" (L, R: UNSIGNED) return std_ulogic is\n -- end function \"?=\";\n \n -- Id: M.3B\n function \\?=\\ (L, R: SIGNED) return STD_ULOGIC is\n constant L_LEFT : INTEGER := L'length-1;\n constant R_LEFT : INTEGER := R'length-1;\n alias XL : SIGNED(L_LEFT downto 0) is L;\n alias XR : SIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable LX : SIGNED(SIZE-1 downto 0);\n variable RX : SIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin -- ?=\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '1';\n for i in LX'low to LX'high loop\n result1 := \\?=\\ (LX(i), RX(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result and result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?=\\;\n -- %%% Replace with the following function\n-- function \"?=\" (L, R: signed) return std_ulogic is\n-- end function \"?=\";\n\n -- Id: C.75\n function \\?=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is\n begin\n return \\?=\\ (TO_UNSIGNED(L, R'length), R);\n end function \\?=\\;\n\n -- Id: C.76\n function \\?=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is\n begin\n return \\?=\\ (TO_SIGNED(L, R'length), R);\n end function \\?=\\;\n\n -- Id: C.77\n function \\?=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is\n begin\n return \\?=\\ (L, TO_UNSIGNED(R, L'length));\n end function \\?=\\;\n\n -- Id: C.78\n function \\?=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is\n begin\n return \\?=\\ (L, TO_SIGNED(R, L'length));\n end function \\?=\\;\n\n function \\?/=\\ (L, R : UNSIGNED) return STD_ULOGIC is\n constant L_LEFT : INTEGER := L'length-1;\n constant R_LEFT : INTEGER := R'length-1;\n alias XL : UNSIGNED(L_LEFT downto 0) is L;\n alias XR : UNSIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable LX : UNSIGNED(SIZE-1 downto 0);\n variable RX : UNSIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin -- ?=\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '0';\n for i in LX'low to LX'high loop\n result1 := \\?/=\\ (LX(i), RX(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result or result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?/=\\;\n -- %%% function \"?/=\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?/=\";\n function \\?/=\\ (L, R : SIGNED) return STD_ULOGIC is\n constant L_LEFT : INTEGER := L'length-1;\n constant R_LEFT : INTEGER := R'length-1;\n alias XL : SIGNED(L_LEFT downto 0) is L;\n alias XR : SIGNED(R_LEFT downto 0) is R;\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable LX : SIGNED(SIZE-1 downto 0);\n variable RX : SIGNED(SIZE-1 downto 0);\n variable result, result1 : STD_ULOGIC; -- result\n begin -- ?=\n if ((L'length < 1) or (R'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n LX := RESIZE(XL, SIZE);\n RX := RESIZE(XR, SIZE);\n result := '0';\n for i in LX'low to LX'high loop\n result1 := \\?/=\\ (LX(i), RX(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result or result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?/=\\;\n -- %%% function \"?/=\" (L, R : SIGNED) return std_ulogic is\n -- %%% end function \"?/=\";\n\n -- Id: C.75\n function \\?/=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is\n begin\n return \\?/=\\ (TO_UNSIGNED(L, R'length), R);\n end function \\?/=\\;\n\n -- Id: C.76\n function \\?/=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is\n begin\n return \\?/=\\ (TO_SIGNED(L, R'length), R);\n end function \\?/=\\;\n\n -- Id: C.77\n function \\?/=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is\n begin\n return \\?/=\\ (L, TO_UNSIGNED(R, L'length));\n end function \\?/=\\;\n\n -- Id: C.78\n function \\?/=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is\n begin\n return \\?/=\\ (L, TO_SIGNED(R, L'length));\n end function \\?/=\\;\n \n function \\?>\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l > r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>\\;\n -- %%% function \"?>\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?>\"\\;\n function \\?>\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l > r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>\\;\n -- %%% function \"?>\" (L, R : SIGNED) return std_ulogic is\n -- %%% end function \"?>\";\n -- Id: C.57\n function \\?>\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is\n begin\n return \\?>\\ (TO_UNSIGNED(L, R'length), R);\n end function \\?>\\;\n\n -- Id: C.58\n function \\?>\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is\n begin\n return \\?>\\ (TO_SIGNED(L, R'length),R);\n end function \\?>\\;\n\n -- Id: C.59\n function \\?>\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is\n begin\n return \\?>\\ (L, TO_UNSIGNED(R, L'length));\n end function \\?>\\;\n\n -- Id: C.60\n function \\?>\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is\n begin\n return \\?>\\ (L, TO_SIGNED(R, L'length));\n end function \\?>\\;\n \n function \\?>=\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l >= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>=\\;\n -- %%% function \"?>=\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?>=\";\n function \\?>=\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?>=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l >= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>=\\;\n -- %%% function \"?>=\" (L, R : SIGNED) return std_ulogic is\n -- %%% end function \"?>=\";\n\n function \\?>=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is\n begin\n return \\?>=\\ (TO_UNSIGNED(L, R'length), R);\n end function \\?>=\\;\n\n -- Id: C.64\n function \\?>=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is\n begin\n return \\?>=\\ (TO_SIGNED(L, R'length),R);\n end function \\?>=\\;\n\n -- Id: C.65\n function \\?>=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is\n begin\n return \\?>=\\ (L, TO_UNSIGNED(R, L'length));\n end function \\?>=\\;\n\n -- Id: C.66\n function \\?>=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is\n begin\n return \\?>=\\ (L, TO_SIGNED(R, L'length));\n end function \\?>=\\;\n \n function \\?<\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l < r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<\\;\n -- %%% function \"?<\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?<\";\n function \\?<\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l < r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<\\;\n -- %%% function \"?<\" (L, R : SIGNED) return std_ulogic is\n -- %%% end function \"?<\";\n\n -- Id: C.57\n function \\?<\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is\n begin\n return \\?<\\ (TO_UNSIGNED(L, R'length), R);\n end function \\?<\\;\n\n -- Id: C.58\n function \\?<\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is\n begin\n return \\?<\\ (TO_SIGNED(L, R'length),R);\n end function \\?<\\;\n\n -- Id: C.59\n function \\?<\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is\n begin\n return \\?<\\ (L, TO_UNSIGNED(R, L'length));\n end function \\?<\\;\n\n -- Id: C.60\n function \\?<\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is\n begin\n return \\?<\\ (L, TO_SIGNED(R, L'length));\n end function \\?<\\;\n\n function \\?<=\\ (L, R : UNSIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l <= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<=\\;\n -- %%% function \"?<=\" (L, R : UNSIGNED) return std_ulogic is\n -- %%% end function \"?<=\";\n function \\?<=\\ (L, R : SIGNED) return STD_ULOGIC is\n begin\n if ((l'length < 1) or (r'length < 1)) then\n assert NO_WARNING\n report \"NUMERIC_STD.\"\"?<=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n else\n for i in L'range loop\n if L(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n for i in R'range loop\n if R(i) = '-' then\n report \"NUMERIC_STD.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n end if;\n end loop;\n if is_x(l) or is_x(r) then\n return 'X';\n elsif l <= r then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<=\\;\n -- %%% function \"?<=\" (L, R : SIGNED) return std_ulogic is\n -- %%% end function \"?<=\";\n -- Id: C.63\n function \\?<=\\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is\n begin\n return \\?<=\\ (TO_UNSIGNED(L, R'length), R);\n end function \\?<=\\;\n\n -- Id: C.64\n function \\?<=\\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is\n begin\n return \\?<=\\ (TO_SIGNED(L, R'length),R);\n end function \\?<=\\;\n\n -- Id: C.65\n function \\?<=\\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is\n begin\n return \\?<=\\ (L, TO_UNSIGNED(R, L'length));\n end function \\?<=\\;\n\n -- Id: C.66\n function \\?<=\\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is\n begin\n return \\?<=\\ (L, TO_SIGNED(R, L'length));\n end function \\?<=\\;\n\n -- size_res versions of these functions (Bugzilla 165)\n function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)\n return UNSIGNED is\n begin\n return TO_UNSIGNED (ARG => ARG,\n SIZE => SIZE_RES'length);\n end function TO_UNSIGNED;\n\n function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)\n return SIGNED is\n begin\n return TO_SIGNED (ARG => ARG,\n SIZE => SIZE_RES'length);\n end function TO_SIGNED;\n\n function RESIZE (ARG, SIZE_RES : SIGNED)\n return SIGNED is\n begin\n return RESIZE (ARG => ARG,\n NEW_SIZE => SIZE_RES'length);\n end function RESIZE;\n\n function RESIZE (ARG, SIZE_RES : UNSIGNED)\n return UNSIGNED is\n begin\n return RESIZE (ARG => ARG,\n NEW_SIZE => SIZE_RES'length);\n end function RESIZE;\n\n -- Id: S.9\n function \"sll\" (ARG : UNSIGNED; COUNT : INTEGER)\n return UNSIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_LEFT(ARG, COUNT);\n else\n return SHIFT_RIGHT(ARG, -COUNT);\n end if;\n end function \"sll\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.10\n function \"sll\" (ARG : SIGNED; COUNT : INTEGER)\n return SIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_LEFT(ARG, COUNT);\n else\n return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));\n end if;\n end function \"sll\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.11\n function \"srl\" (ARG : UNSIGNED; COUNT : INTEGER)\n return UNSIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_RIGHT(ARG, COUNT);\n else\n return SHIFT_LEFT(ARG, -COUNT);\n end if;\n end function \"srl\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.12\n function \"srl\" (ARG : SIGNED; COUNT : INTEGER)\n return SIGNED is\n begin\n if (COUNT >= 0) then\n return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));\n else\n return SHIFT_LEFT(ARG, -COUNT);\n end if;\n end function \"srl\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.13\n function \"rol\" (ARG : UNSIGNED; COUNT : INTEGER)\n return UNSIGNED is\n begin\n if (COUNT >= 0) then\n return ROTATE_LEFT(ARG, COUNT);\n else\n return ROTATE_RIGHT(ARG, -COUNT);\n end if;\n end function \"rol\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.14\n function \"rol\" (ARG : SIGNED; COUNT : INTEGER)\n return SIGNED is\n begin\n if (COUNT >= 0) then\n return ROTATE_LEFT(ARG, COUNT);\n else\n return ROTATE_RIGHT(ARG, -COUNT);\n end if;\n end function \"rol\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.15\n function \"ror\" (ARG : UNSIGNED; COUNT : INTEGER)\n return UNSIGNED is\n begin\n if (COUNT >= 0) then\n return ROTATE_RIGHT(ARG, COUNT);\n else\n return ROTATE_LEFT(ARG, -COUNT);\n end if;\n end function \"ror\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.16\n function \"ror\" (ARG : SIGNED; COUNT : INTEGER)\n return SIGNED is\n begin\n if (COUNT >= 0) then\n return ROTATE_RIGHT(ARG, COUNT);\n else\n return ROTATE_LEFT(ARG, -COUNT);\n end if;\n end function \"ror\";\n\n-- begin LCS-2006-120\n\n ------------------------------------------------------------------------------\n -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.17\n function \"sla\" (ARG : UNSIGNED; COUNT : INTEGER)\n return UNSIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_LEFT(ARG, COUNT);\n else\n return SHIFT_RIGHT(ARG, -COUNT);\n end if;\n end function \"sla\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.18\n function \"sla\" (ARG : SIGNED; COUNT : INTEGER)\n return SIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_LEFT(ARG, COUNT);\n else\n return SHIFT_RIGHT(ARG, -COUNT);\n end if;\n end function \"sla\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.19\n function \"sra\" (ARG : UNSIGNED; COUNT : INTEGER)\n return UNSIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_RIGHT(ARG, COUNT);\n else\n return SHIFT_LEFT(ARG, -COUNT);\n end if;\n end function \"sra\";\n\n ------------------------------------------------------------------------------\n -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.20\n function \"sra\" (ARG : SIGNED; COUNT : INTEGER)\n return SIGNED is\n begin\n if (COUNT >= 0) then\n return SHIFT_RIGHT(ARG, COUNT);\n else\n return SHIFT_LEFT(ARG, -COUNT);\n end if;\n end function \"sra\";\n\n -- These functions are in std_logic_1164 and are defined for\n -- std_logic_vector. They are overloaded here.\n function To_X01 ( s : UNSIGNED ) return UNSIGNED is\n begin\n return UNSIGNED (To_X01 (STD_LOGIC_VECTOR (s)));\n end function To_X01;\n \n function To_X01 ( s : SIGNED ) return SIGNED is\n begin\n return SIGNED (To_X01 (STD_LOGIC_VECTOR (s)));\n end function To_X01;\n \n function To_X01Z ( s : UNSIGNED ) return UNSIGNED is\n begin\n return UNSIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));\n end function To_X01Z;\n\n function To_X01Z ( s : SIGNED ) return SIGNED is\n begin\n return SIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));\n end function To_X01Z;\n \n function To_UX01 ( s : UNSIGNED ) return UNSIGNED is\n begin\n return UNSIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));\n end function To_UX01;\n \n function To_UX01 ( s : SIGNED ) return SIGNED is\n begin\n return SIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));\n end function To_UX01;\n\n function Is_X ( s : UNSIGNED ) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n \n function Is_X ( s : SIGNED ) return BOOLEAN is\n begin\n return Is_X (STD_LOGIC_VECTOR (s));\n end function Is_X;\n\n -----------------------------------------------------------------------------\n -- New/updated functions for VHDL-200X fast track\n -----------------------------------------------------------------------------\n\n -- Returns the maximum (or minimum) of the two numbers provided.\n -- All types (both inputs and the output) must be the same.\n -- These override the implicit functions, using the local \">\" operator\n -- UNSIGNED output\n function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable L01 : UNSIGNED(SIZE-1 downto 0);\n variable R01 : UNSIGNED(SIZE-1 downto 0);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAU;\n end if;\n L01 := TO_01(RESIZE(L, SIZE), 'X');\n if (L01(L01'left) = 'X') then return L01;\n end if;\n R01 := TO_01(RESIZE(R, SIZE), 'X');\n if (R01(R01'left) = 'X') then return R01;\n end if;\n if L01 < R01 then\n return R01;\n else\n return L01;\n end if;\n end function MAXIMUM;\n\n -- signed output\n function MAXIMUM (L, R : SIGNED) return SIGNED is\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable L01 : SIGNED(SIZE-1 downto 0);\n variable R01 : SIGNED(SIZE-1 downto 0);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAS;\n end if;\n L01 := TO_01(RESIZE(L, SIZE), 'X');\n if (L01(L01'left) = 'X') then return L01;\n end if;\n R01 := TO_01(RESIZE(R, SIZE), 'X');\n if (R01(R01'left) = 'X') then return R01;\n end if;\n if L01 < R01 then\n return R01;\n else\n return L01;\n end if;\n end function MAXIMUM;\n\n -- UNSIGNED output\n function MINIMUM (L, R : UNSIGNED) return UNSIGNED is\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable L01 : UNSIGNED(SIZE-1 downto 0);\n variable R01 : UNSIGNED(SIZE-1 downto 0);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAU;\n end if;\n L01 := TO_01(RESIZE(L, SIZE), 'X');\n if (L01(L01'left) = 'X') then return L01;\n end if;\n R01 := TO_01(RESIZE(R, SIZE), 'X');\n if (R01(R01'left) = 'X') then return R01;\n end if;\n if L01 < R01 then\n return L01;\n else\n return R01;\n end if;\n end function MINIMUM;\n\n\n -- signed output\n function MINIMUM (L, R : SIGNED) return SIGNED is\n constant SIZE : NATURAL := MAX(L'length, R'length);\n variable L01 : SIGNED(SIZE-1 downto 0);\n variable R01 : SIGNED(SIZE-1 downto 0);\n begin\n if ((L'length < 1) or (R'length < 1)) then return NAS;\n end if;\n L01 := TO_01(RESIZE(L, SIZE), 'X');\n if (L01(L01'left) = 'X') then return L01;\n end if;\n R01 := TO_01(RESIZE(R, SIZE), 'X');\n if (R01(R01'left) = 'X') then return R01;\n end if;\n if L01 < R01 then\n return L01;\n else\n return R01;\n end if;\n end function MINIMUM;\n\n -- Id: C.39\n function MINIMUM (L : NATURAL; R : UNSIGNED)\n return UNSIGNED is\n begin\n return MINIMUM(TO_UNSIGNED(L, R'length), R);\n end function MINIMUM;\n\n -- Id: C.40\n function MINIMUM (L : INTEGER; R : SIGNED)\n return SIGNED is\n begin\n return MINIMUM(TO_SIGNED(L, R'length), R);\n end function MINIMUM;\n\n -- Id: C.41\n function MINIMUM (L : UNSIGNED; R : NATURAL)\n return UNSIGNED is\n begin\n return MINIMUM(L, TO_UNSIGNED(R, L'length));\n end function MINIMUM;\n\n -- Id: C.42\n function MINIMUM (L : SIGNED; R : INTEGER)\n return SIGNED is\n begin\n return MINIMUM(L, TO_SIGNED(R, L'length));\n end function MINIMUM;\n \n -- Id: C.45\n function MAXIMUM (L : NATURAL; R : UNSIGNED)\n return UNSIGNED is\n begin\n return MAXIMUM(TO_UNSIGNED(L, R'length), R);\n end function MAXIMUM;\n\n -- Id: C.46\n function MAXIMUM (L : INTEGER; R : SIGNED)\n return SIGNED is\n begin\n return MAXIMUM(TO_SIGNED(L, R'length), R);\n end function MAXIMUM;\n\n -- Id: C.47\n function MAXIMUM (L : UNSIGNED; R : NATURAL)\n return UNSIGNED is\n begin\n return MAXIMUM(L, TO_UNSIGNED(R, L'length));\n end function MAXIMUM;\n\n -- Id: C.48\n function MAXIMUM (L : SIGNED; R : INTEGER)\n return SIGNED is\n begin\n return MAXIMUM(L, TO_SIGNED(R, L'length));\n end function MAXIMUM;\n\n function find_rightmost (\n arg : UNSIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER is\n alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;\n begin\n for_loop: for i in xarg'reverse_range loop\n if \\?=\\ (xarg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return -1;\n end function find_rightmost;\n\n function find_rightmost (\n arg : SIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER is\n alias xarg : SIGNED(arg'length-1 downto 0) is arg;\n begin\n for_loop: for i in xarg'reverse_range loop\n if \\?=\\ (xarg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return -1;\n end function find_rightmost;\n\n function find_leftmost (\n arg : UNSIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER is\n alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;\n begin\n for_loop: for i in xarg'range loop\n if \\?=\\ (xarg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return -1;\n end function find_leftmost;\n\n function find_leftmost (\n arg : SIGNED; -- vector argument\n y : STD_ULOGIC) -- look for this bit\n return INTEGER is\n alias xarg : SIGNED(arg'length-1 downto 0) is arg;\n begin\n for_loop: for i in xarg'range loop\n if \\?=\\ (xarg(i), y) = '1' then\n return i;\n end if;\n end loop;\n return -1;\n end function find_leftmost;\n\n function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL)\n return UNRESOLVED_UNSIGNED is\n begin\n return UNRESOLVED_UNSIGNED(to_unsigned (arg, size));\n end function TO_UNRESOLVED_UNSIGNED;\n -- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)\n -- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with\n -- the specified SIZE.\n\n\n function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL)\n return UNRESOLVED_SIGNED is\n begin\n return UNRESOLVED_SIGNED(to_signed (arg, size));\n end function TO_UNRESOLVED_SIGNED;\n -- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)\n -- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.\n\n -- Performs the boolean operation on every bit in the vector\n-- L.15 \n function \"and\" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n alias rv : UNSIGNED ( 1 to r'length ) is r;\n variable result : UNSIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"and\" (l, rv(i));\n end loop;\n return result;\n end function \"and\";\n\n-- L.16 \n function \"and\" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n alias lv : UNSIGNED ( 1 to l'length ) is l;\n variable result : UNSIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"and\" (lv(i), r);\n end loop;\n return result;\n end function \"and\";\n\n-- L.17 \n function \"or\" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n alias rv : UNSIGNED ( 1 to r'length ) is r;\n variable result : UNSIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"or\" (l, rv(i));\n end loop;\n return result;\n end function \"or\";\n\n-- L.18 \n function \"or\" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n alias lv : UNSIGNED ( 1 to l'length ) is l;\n variable result : UNSIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"or\" (lv(i), r);\n end loop;\n return result;\n end function \"or\";\n\n-- L.19 \n function \"nand\" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n alias rv : UNSIGNED ( 1 to r'length ) is r;\n variable result : UNSIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (l, rv(i)));\n end loop;\n return result;\n end function \"nand\";\n\n-- L.20 \n function \"nand\" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n alias lv : UNSIGNED ( 1 to l'length ) is l;\n variable result : UNSIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (lv(i), r));\n end loop;\n return result;\n end function \"nand\";\n\n-- L.21 \n function \"nor\" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n alias rv : UNSIGNED ( 1 to r'length ) is r;\n variable result : UNSIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (l, rv(i)));\n end loop;\n return result;\n end function \"nor\";\n\n-- L.22 \n function \"nor\" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n alias lv : UNSIGNED ( 1 to l'length ) is l;\n variable result : UNSIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (lv(i), r));\n end loop;\n return result;\n end function \"nor\";\n\n-- L.23 \n function \"xor\" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n alias rv : UNSIGNED ( 1 to r'length ) is r;\n variable result : UNSIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"xor\" (l, rv(i));\n end loop;\n return result;\n end function \"xor\";\n\n-- L.24 \n function \"xor\" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n alias lv : UNSIGNED ( 1 to l'length ) is l;\n variable result : UNSIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"xor\" (lv(i), r);\n end loop;\n return result;\n end function \"xor\";\n\n-- L.25 \n function \"xnor\" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is\n alias rv : UNSIGNED ( 1 to r'length ) is r;\n variable result : UNSIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (l, rv(i)));\n end loop;\n return result;\n end function \"xnor\";\n\n-- L.26 \n function \"xnor\" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is\n alias lv : UNSIGNED ( 1 to l'length ) is l;\n variable result : UNSIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (lv(i), r));\n end loop;\n return result;\n end function \"xnor\";\n\n-- L.27 \n function \"and\" (L: STD_ULOGIC; R: SIGNED) return SIGNED is\n alias rv : SIGNED ( 1 to r'length ) is r;\n variable result : SIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"and\" (l, rv(i));\n end loop;\n return result;\n end function \"and\";\n\n-- L.28 \n function \"and\" (L: SIGNED; R: STD_ULOGIC) return SIGNED is\n alias lv : SIGNED ( 1 to l'length ) is l;\n variable result : SIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"and\" (lv(i), r);\n end loop;\n return result;\n end function \"and\";\n\n-- L.29 \n function \"or\" (L: STD_ULOGIC; R: SIGNED) return SIGNED is\n alias rv : SIGNED ( 1 to r'length ) is r;\n variable result : SIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"or\" (l, rv(i));\n end loop;\n return result;\n end function \"or\";\n\n-- L.30 \n function \"or\" (L: SIGNED; R: STD_ULOGIC) return SIGNED is\n alias lv : SIGNED ( 1 to l'length ) is l;\n variable result : SIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"or\" (lv(i), r);\n end loop;\n return result;\n end function \"or\";\n\n-- L.31 \n function \"nand\" (L: STD_ULOGIC; R: SIGNED) return SIGNED is\n alias rv : SIGNED ( 1 to r'length ) is r;\n variable result : SIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (l, rv(i)));\n end loop;\n return result;\n end function \"nand\";\n\n-- L.32 \n function \"nand\" (L: SIGNED; R: STD_ULOGIC) return SIGNED is\n alias lv : SIGNED ( 1 to l'length ) is l;\n variable result : SIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (lv(i), r));\n end loop;\n return result;\n end function \"nand\";\n\n-- L.33 \n function \"nor\" (L: STD_ULOGIC; R: SIGNED) return SIGNED is\n alias rv : SIGNED ( 1 to r'length ) is r;\n variable result : SIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (l, rv(i)));\n end loop;\n return result;\n end function \"nor\";\n\n-- L.34 \n function \"nor\" (L: SIGNED; R: STD_ULOGIC) return SIGNED is\n alias lv : SIGNED ( 1 to l'length ) is l;\n variable result : SIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (lv(i), r));\n end loop;\n return result;\n end function \"nor\";\n\n-- L.35 \n function \"xor\" (L: STD_ULOGIC; R: SIGNED) return SIGNED is\n alias rv : SIGNED ( 1 to r'length ) is r;\n variable result : SIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"xor\" (l, rv(i));\n end loop;\n return result;\n end function \"xor\";\n\n-- L.36 \n function \"xor\" (L: SIGNED; R: STD_ULOGIC) return SIGNED is\n alias lv : SIGNED ( 1 to l'length ) is l;\n variable result : SIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"xor\" (lv(i), r);\n end loop;\n return result;\n end function \"xor\";\n\n-- L.37 \n function \"xnor\" (L: STD_ULOGIC; R: SIGNED) return SIGNED is\n alias rv : SIGNED ( 1 to r'length ) is r;\n variable result : SIGNED ( 1 to r'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (l, rv(i)));\n end loop;\n return result;\n end function \"xnor\";\n\n-- L.38 \n function \"xnor\" (L: SIGNED; R: STD_ULOGIC) return SIGNED is\n alias lv : SIGNED ( 1 to l'length ) is l;\n variable result : SIGNED ( 1 to l'length );\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (lv(i), r));\n end loop;\n return result;\n end function \"xnor\";\n \n --------------------------------------------------------------------------\n -- Reduction operations\n --------------------------------------------------------------------------\n -- %%% Remove the following 12 funcitons (old syntax)\n function and_reduce (l : SIGNED ) return STD_ULOGIC is\n begin\n return and_reduce (UNSIGNED ( l ));\n end function and_reduce;\n\n function and_reduce ( l : UNSIGNED ) return STD_ULOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );\n variable Result : STD_ULOGIC := '1'; -- In the case of a NULL range\n begin\n if (l'length >= 1) then\n BUS_int := to_ux01 (l);\n if ( BUS_int'length = 1 ) then\n Result := BUS_int ( BUS_int'left );\n elsif ( BUS_int'length = 2 ) then\n Result := \"and\" (BUS_int(BUS_int'right),BUS_int(BUS_int'left));\n else\n Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;\n Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));\n Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));\n Result := \"and\" (Upper, Lower);\n end if;\n end if;\n return Result;\n end function and_reduce;\n\n function nand_reduce (l : SIGNED ) return STD_ULOGIC is\n begin\n return \"not\" (and_reduce ( l ));\n end function nand_reduce;\n\n function nand_reduce (l : UNSIGNED ) return STD_ULOGIC is\n begin\n return \"not\" (and_reduce (l ));\n end function nand_reduce;\n \n function or_reduce (l : SIGNED ) return STD_ULOGIC is\n begin\n return or_reduce (UNSIGNED ( l ));\n end function or_reduce;\n\n function or_reduce (l : UNSIGNED ) return STD_ULOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );\n variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range\n begin\n if (l'length >= 1) then\n BUS_int := to_ux01 (l);\n if ( BUS_int'length = 1 ) then\n Result := BUS_int ( BUS_int'left );\n elsif ( BUS_int'length = 2 ) then\n Result := \"or\" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));\n else\n Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;\n Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));\n Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));\n Result := \"or\" (Upper, Lower);\n end if;\n end if;\n return Result;\n end function or_reduce;\n\n function nor_reduce (l : SIGNED ) return STD_ULOGIC is\n begin\n return \"not\"(or_reduce(l));\n end function nor_reduce;\n\n function nor_reduce (l : UNSIGNED ) return STD_ULOGIC is\n begin\n return \"not\"(or_reduce(l));\n end function nor_reduce;\n\n function xor_reduce (l : SIGNED ) return STD_ULOGIC is\n begin\n return xor_reduce (UNSIGNED ( l ));\n end function xor_reduce;\n\n function xor_reduce (l : UNSIGNED ) return STD_ULOGIC is\n variable Upper, Lower : STD_ULOGIC;\n variable Half : INTEGER;\n variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );\n variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range\n begin\n if (l'length >= 1) then\n BUS_int := to_ux01 (l);\n if ( BUS_int'length = 1 ) then\n Result := BUS_int ( BUS_int'left );\n elsif ( BUS_int'length = 2 ) then\n Result := \"xor\" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));\n else\n Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;\n Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));\n Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));\n Result := \"xor\" (Upper, Lower);\n end if;\n end if;\n return Result;\n end function xor_reduce;\n\n function xnor_reduce (l : SIGNED ) return STD_ULOGIC is\n begin\n return \"not\"(xor_reduce(l));\n end function xnor_reduce;\n\n function xnor_reduce (l : UNSIGNED ) return STD_ULOGIC is\n begin\n return \"not\"(xor_reduce(l));\n end function xnor_reduce;\n\n -- %%% Replace the above with the following 12 functions (New syntax)\n-- function \"and\" ( l : SIGNED ) return std_ulogic is\n-- begin\n-- return and (std_logic_vector ( l ));\n-- end function \"and\";\n\n-- function \"and\" ( l : UNSIGNED ) return std_ulogic is\n-- begin\n-- return and (std_logic_vector ( l ));\n-- end function \"and\";\n\n-- function \"nand\" ( l : SIGNED ) return std_ulogic is\n-- begin\n-- return nand (std_logic_vector ( l ));\n-- end function \"nand\";\n\n-- function \"nand\" ( l : UNSIGNED ) return std_ulogic is\n-- begin\n-- return nand (std_logic_vector ( l ));\n-- end function \"nand\";\n \n-- function \"or\" ( l : SIGNED ) return std_ulogic is\n-- begin\n-- return or (std_logic_vector ( l ));\n-- end function \"or\";\n\n-- function \"or\" ( l : UNSIGNED ) return std_ulogic is\n-- begin\n-- return or (std_logic_vector ( l ));\n-- end function \"or\";\n\n-- function \"nor\" ( l : SIGNED ) return std_ulogic is\n-- begin\n-- return nor (std_logic_vector ( l ));\n-- end function \"nor\";\n\n-- function \"nor\" ( l : UNSIGNED ) return std_ulogic is\n-- begin\n-- return nor (std_logic_vector ( l ));\n-- end function \"nor\";\n\n-- function \"xor\" ( l : SIGNED ) return std_ulogic is\n-- begin\n-- return xor (std_logic_vector ( l ));\n-- end function \"xor\";\n\n-- function \"xor\" ( l : UNSIGNED ) return std_ulogic is\n-- begin\n-- return xor (std_logic_vector ( l ));\n-- end function \"xor\";\n\n-- function \"xnor\" ( l : SIGNED ) return std_ulogic is\n-- begin\n-- return xnor (std_logic_vector ( l ));\n-- end function \"xnor\";\n\n-- function \"xnor\" ( l : UNSIGNED ) return std_ulogic is\n-- begin\n-- return xnor (std_logic_vector ( l ));\n-- end function \"xnor\";\n \n -- rtl_synthesis off\n-- pragma synthesis_off\n ------------------------------------------------------------------- \n -- TO_STRING\n -------------------------------------------------------------------\n -- Type and constant definitions used to map STD_ULOGIC values \n -- into/from character values.\n type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);\n type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;\n type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;\n type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;\n constant MVL9_to_char : char_indexed_by_MVL9 := \"UX01ZWLH-\";\n constant char_to_MVL9 : MVL9_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');\n constant char_to_MVL9plus : MVL9plus_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);\n\n constant NBSP : CHARACTER := CHARACTER'val(160); -- space character\n constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array\n \n function to_string (value : UNSIGNED) return STRING is\n alias ivalue : UNSIGNED(1 to value'length) is value;\n variable result : STRING(1 to value'length);\n begin\n if value'length < 1 then\n return NUS;\n else\n for i in ivalue'range loop\n result(i) := MVL9_to_char( iValue(i) );\n end loop;\n return result;\n end if;\n end function to_string;\n\n function to_string (value : SIGNED) return STRING is\n alias ivalue : SIGNED(1 to value'length) is value;\n variable result : STRING(1 to value'length);\n begin\n if value'length < 1 then\n return NUS;\n else\n for i in ivalue'range loop\n result(i) := MVL9_to_char( iValue(i) );\n end loop;\n return result;\n end if;\n end function to_string;\n \n function to_hstring (value : SIGNED) return STRING is\n constant ne : INTEGER := (value'length+3)/4;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);\n variable result : STRING(1 to ne);\n variable quad : STD_LOGIC_VECTOR(0 to 3);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => value(value'high)); -- Extend sign bit\n end if;\n ivalue := pad & STD_LOGIC_VECTOR (value);\n for i in 0 to ne-1 loop\n quad := To_X01Z(ivalue(4*i to 4*i+3));\n case quad is\n when x\"0\" => result(i+1) := '0';\n when x\"1\" => result(i+1) := '1';\n when x\"2\" => result(i+1) := '2';\n when x\"3\" => result(i+1) := '3';\n when x\"4\" => result(i+1) := '4';\n", "right_context": " when x\"8\" => result(i+1) := '8';\n when x\"9\" => result(i+1) := '9';\n when x\"A\" => result(i+1) := 'A';\n when x\"B\" => result(i+1) := 'B';\n when x\"C\" => result(i+1) := 'C';\n when x\"D\" => result(i+1) := 'D';\n when x\"E\" => result(i+1) := 'E';\n when x\"F\" => result(i+1) := 'F';\n when \"ZZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_hstring;\n\n function to_ostring (value : SIGNED) return STRING is\n constant ne : INTEGER := (value'length+2)/3;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);\n variable result : STRING(1 to ne);\n variable tri : STD_LOGIC_VECTOR(0 to 2);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => value (value'high)); -- Extend sign bit\n end if;\n ivalue := pad & STD_LOGIC_VECTOR (value);\n for i in 0 to ne-1 loop\n tri := To_X01Z(ivalue(3*i to 3*i+2));\n case tri is\n when o\"0\" => result(i+1) := '0';\n when o\"1\" => result(i+1) := '1';\n when o\"2\" => result(i+1) := '2';\n when o\"3\" => result(i+1) := '3';\n when o\"4\" => result(i+1) := '4';\n when o\"5\" => result(i+1) := '5';\n when o\"6\" => result(i+1) := '6';\n when o\"7\" => result(i+1) := '7';\n when \"ZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_ostring;\n \n function to_hstring (value : UNSIGNED) return STRING is\n constant ne : INTEGER := (value'length+3)/4;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);\n variable result : STRING(1 to ne);\n variable quad : STD_LOGIC_VECTOR(0 to 3);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & STD_LOGIC_VECTOR (value);\n for i in 0 to ne-1 loop\n quad := To_X01Z(ivalue(4*i to 4*i+3));\n case quad is\n when x\"0\" => result(i+1) := '0';\n when x\"1\" => result(i+1) := '1';\n when x\"2\" => result(i+1) := '2';\n when x\"3\" => result(i+1) := '3';\n when x\"4\" => result(i+1) := '4';\n when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n when x\"7\" => result(i+1) := '7';\n when x\"8\" => result(i+1) := '8';\n when x\"9\" => result(i+1) := '9';\n when x\"A\" => result(i+1) := 'A';\n when x\"B\" => result(i+1) := 'B';\n when x\"C\" => result(i+1) := 'C';\n when x\"D\" => result(i+1) := 'D';\n when x\"E\" => result(i+1) := 'E';\n when x\"F\" => result(i+1) := 'F';\n when \"ZZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_hstring;\n\n function to_ostring (value : UNSIGNED) return STRING is\n constant ne : INTEGER := (value'length+2)/3;\n variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);\n variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);\n variable result : STRING(1 to ne);\n variable tri : STD_LOGIC_VECTOR(0 to 2);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & STD_LOGIC_VECTOR (value);\n for i in 0 to ne-1 loop\n tri := To_X01Z(ivalue(3*i to 3*i+2));\n case tri is\n when o\"0\" => result(i+1) := '0';\n when o\"1\" => result(i+1) := '1';\n when o\"2\" => result(i+1) := '2';\n when o\"3\" => result(i+1) := '3';\n when o\"4\" => result(i+1) := '4';\n when o\"5\" => result(i+1) := '5';\n when o\"6\" => result(i+1) := '6';\n when o\"7\" => result(i+1) := '7';\n when \"ZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_ostring;\n\n -----------------------------------------------------------------------------\n -- Read and Write routines\n -----------------------------------------------------------------------------\n\n -- Routines copied from the \"std_logic_1164_additions\" package\n -- purpose: Skips white space\n procedure skip_whitespace (\n L : inout LINE) is\n variable readOk : BOOLEAN;\n variable c : CHARACTER;\n begin\n while L /= null and L.all'length /= 0 loop\n if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then\n read (l, c, readOk);\n else\n exit;\n end if;\n end loop;\n end procedure skip_whitespace;\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable m : STD_ULOGIC;\n variable c : CHARACTER;\n variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);\n variable readOk : BOOLEAN;\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, readOk);\n i := 0;\n good := true;\n while i < VALUE'length loop\n if not readOk then -- Bail out if there was a bad read\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n elsif (char_to_MVL9plus(c) = error) then\n good := false; -- Illegal character\n return;\n else\n mv(i) := char_to_MVL9(c);\n i := i + 1;\n if i > mv'high then -- reading done\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n read(L, c, readOk);\n end loop;\n else\n good := true; -- read into a null array\n end if;\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is\n variable m : STD_ULOGIC;\n variable c : CHARACTER;\n variable readOk : BOOLEAN;\n variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then -- non Null input string\n read (l, c, readOk);\n i := 0;\n while i < VALUE'length loop\n if readOk = false then -- Bail out if there was a bad read\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif c = '_' then\n if i = 0 then\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n elsif char_to_MVL9plus(c) = error then\n report\n \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '\" &\n c & \"' read, expected STD_ULOGIC literal.\"\n severity error;\n return;\n else\n mv(i) := char_to_MVL9(c);\n i := i + 1;\n if i > mv'high then\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n read(L, c, readOk);\n end loop;\n end if;\n end procedure READ;\n\n -- purpose: or reduction\n function or_reduce (\n arg : STD_ULOGIC_VECTOR)\n return STD_ULOGIC is\n variable uarg : UNSIGNED (arg'range);\n begin\n uarg := unsigned(arg);\n return or_reduce (uarg);\n end function or_reduce;\n\n procedure Char2QuadBits (C : CHARACTER;\n RESULT : out STD_ULOGIC_VECTOR(3 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := x\"0\"; good := true;\n when '1' => result := x\"1\"; good := true;\n when '2' => result := x\"2\"; good := true;\n when '3' => result := x\"3\"; good := true;\n when '4' => result := x\"4\"; good := true;\n when '5' => result := x\"5\"; good := true;\n when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n when 'B' | 'b' => result := x\"B\"; good := true;\n when 'C' | 'c' => result := x\"C\"; good := true;\n when 'D' | 'd' => result := x\"D\"; good := true;\n when 'E' | 'e' => result := x\"E\"; good := true;\n when 'F' | 'f' => result := x\"F\"; good := true;\n when 'Z' => result := \"ZZZZ\"; good := true;\n when 'X' => result := \"XXXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report\n \"STD_LOGIC_1164.HREAD Read a '\" & c &\n \"', expected a Hex character (0-F).\"\n severity error;\n good := false;\n end case;\n end procedure Char2QuadBits;\n\n procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- Null input string, skips whitespace\n end if;\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then -- non Null input string\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n report \"STD_LOGIC_1164.HREAD \"\n & \"End of string encountered\"\n severity error;\n return;\n end if;\n if c = '_' then\n if i = 0 then\n report \"STD_LOGIC_1164.HREAD \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report \"STD_LOGIC_1164.HREAD \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n else\n Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);\n if not ok then\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n report \"STD_LOGIC_1164.HREAD Vector truncated\"\n severity error;\n else\n VALUE := sv (pad to sv'high);\n end if;\n end if;\n end procedure HREAD;\n\n -- Octal Read and Write procedures for STD_ULOGIC_VECTOR.\n -- Modified from the original to be more forgiving.\n\n procedure Char2TriBits (C : CHARACTER;\n RESULT : out STD_ULOGIC_VECTOR(2 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n when '4' => result := o\"4\"; good := true;\n when '5' => result := o\"5\"; good := true;\n when '6' => result := o\"6\"; good := true;\n when '7' => result := o\"7\"; good := true;\n when 'Z' => result := \"ZZZ\"; good := true;\n when 'X' => result := \"XXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report\n \"STD_LOGIC_1164.OREAD Error: Read a '\" & c &\n \"', expected an Octal character (0-7).\"\n severity error;\n good := false;\n end case;\n end procedure Char2TriBits;\n\n procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2TriBits(c, sv(3*i to 3*i+2), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- read into a null array\n end if;\n end procedure OREAD;\n\n procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n report \"STD_LOGIC_1164.OREAD \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif c = '_' then\n if i = 0 then\n report \"STD_LOGIC_1164.OREAD \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report \"STD_LOGIC_1164.OREAD \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n else\n Char2TriBits(c, sv(3*i to 3*i+2), ok, true);\n if not ok then\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n report \"STD_LOGIC_1164.OREAD Vector truncated\"\n severity error;\n else\n VALUE := sv (pad to sv'high);\n end if;\n end if;\n end procedure OREAD;\n -- End copied code.\n\n procedure READ (L : inout LINE; VALUE : out UNSIGNED;\n GOOD : out BOOLEAN) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n READ (L => L,\n VALUE => ivalue,\n GOOD => GOOD);\n VALUE := UNSIGNED(ivalue);\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out UNSIGNED) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n READ (L => L,\n VALUE => ivalue);\n VALUE := UNSIGNED (ivalue);\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out SIGNED;\n GOOD : out BOOLEAN) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n READ (L => L,\n VALUE => ivalue,\n GOOD => GOOD);\n VALUE := SIGNED(ivalue);\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out SIGNED) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n READ (L => L,\n VALUE => ivalue);\n VALUE := SIGNED (ivalue);\n end procedure READ;\n\n procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_string(VALUE), JUSTIFIED, FIELD);\n end procedure WRITE;\n\n procedure WRITE (L : inout LINE; VALUE : in SIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_string(VALUE), JUSTIFIED, FIELD);\n end procedure WRITE;\n\n procedure OREAD (L : inout LINE; VALUE : out UNSIGNED;\n GOOD : out BOOLEAN) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n OREAD (L => L,\n VALUE => ivalue,\n GOOD => GOOD);\n VALUE := UNSIGNED(ivalue);\n end procedure OREAD;\n\n procedure OREAD (L : inout LINE; VALUE : out SIGNED;\n GOOD : out BOOLEAN) is\n constant ne : INTEGER := (value'length+2)/3;\n constant pad : INTEGER := ne*3 - value'length;\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);\n variable ok : BOOLEAN;\n variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);\n begin\n OREAD (L => L,\n VALUE => ivalue, -- Read padded STRING\n GOOD => ok);\n -- Bail out if there was a bad read\n if not ok then\n GOOD := false;\n return;\n end if;\n expected_padding := (others => ivalue(pad));\n if ivalue(0 to pad-1) /= expected_padding then\n GOOD := false;\n else\n GOOD := true;\n VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));\n end if;\n end procedure OREAD;\n\n procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n OREAD (L => L,\n VALUE => ivalue);\n VALUE := UNSIGNED (ivalue);\n end procedure OREAD;\n\n procedure OREAD (L : inout LINE; VALUE : out SIGNED) is\n constant ne : INTEGER := (value'length+2)/3;\n constant pad : INTEGER := ne*3 - value'length;\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);\n variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);\n begin\n OREAD (L => L,\n VALUE => ivalue); -- Read padded string\n expected_padding := (others => ivalue(pad));\n if ivalue(0 to pad-1) /= expected_padding then\n assert false\n report \"NUMERIC_STD.OREAD Error: Signed vector truncated\"\n severity error;\n else\n VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));\n end if;\n end procedure OREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out UNSIGNED;\n GOOD : out BOOLEAN) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n HREAD (L => L,\n VALUE => ivalue,\n GOOD => GOOD);\n VALUE := UNSIGNED(ivalue);\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out SIGNED;\n GOOD : out BOOLEAN) is\n constant ne : INTEGER := (value'length+3)/4;\n constant pad : INTEGER := ne*4 - value'length;\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);\n variable ok : BOOLEAN;\n variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);\n begin\n HREAD (L => L,\n VALUE => ivalue, -- Read padded STRING\n GOOD => ok);\n if not ok then\n GOOD := false;\n return;\n end if;\n expected_padding := (others => ivalue(pad));\n if ivalue(0 to pad-1) /= expected_padding then\n GOOD := false;\n else\n GOOD := true;\n VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));\n end if;\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is\n variable ivalue : STD_ULOGIC_VECTOR(value'range);\n begin\n HREAD (L => L,\n VALUE => ivalue);\n VALUE := UNSIGNED (ivalue);\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out SIGNED) is\n constant ne : INTEGER := (value'length+3)/4;\n constant pad : INTEGER := ne*4 - value'length;\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);\n variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);\n begin\n HREAD (L => L,\n VALUE => ivalue); -- Read padded string\n expected_padding := (others => ivalue(pad));\n if ivalue(0 to pad-1) /= expected_padding then\n assert false\n report \"NUMERIC_STD.HREAD Error: Signed vector truncated\"\n severity error;\n else\n VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));\n end if;\n end procedure HREAD;\n\n procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_ostring(VALUE), JUSTIFIED, FIELD);\n end procedure OWRITE;\n\n procedure OWRITE (L : inout LINE; VALUE : in SIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_ostring(VALUE), JUSTIFIED, FIELD);\n end procedure OWRITE;\n\n procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_hstring (VALUE), JUSTIFIED, FIELD);\n end procedure HWRITE;\n\n procedure HWRITE (L : inout LINE; VALUE : in SIGNED;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_hstring (VALUE), JUSTIFIED, FIELD);\n end procedure HWRITE;\n\n -- rtl_synthesis on\n-- pragma synthesis_on\nend package body numeric_std_additions;\n", "groundtruth": " when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/numeric_std_unsigned_c.vhdl", "left_context": "-- --------------------------------------------------------------------\n-- Title : Standard VHDL Synthesis Packages (1076.3, NUMERIC_STD_UNSIGNED)\n--\n-- This package overloaded the arithmetic operaters for\n-- \"STD_ULOGIC_VECTOR\", and treats this vector like an\n-- \"UNSIGNED\" from \"numeric_std\".\n--\n-- This is the updated (proposed) new package to be\n-- balloted in January.\n--\n-- New subprograms are at the end of the package header\n-- and the package body. These are to be revised, ID's\n-- assigned, and voted into the ballot version.\n-- \n-- Other changes will be noted here.\n--\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n------------------------------------------------------------------------------\n\nlibrary IEEE;\nuse IEEE.STD_LOGIC_1164.all;\npackage NUMERIC_STD_UNSIGNED is\n\n-- begin LCS-2006-141\n -- Replace all subsequent occurrences of STD_LOGIC_VECTOR\n -- with STD_ULOGIC_ECTOR.\n-- end LCS-2006-141\n -- Id: A.3\n function \"+\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).\n -- Result: Adds two UNSIGNED vectors that may be of different lengths.\n\n -- Id: A.3R\n function \"+\"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR\n\n -- Id: A.3L\n function \"+\"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Similar to A.3 where L is a one bit UNSIGNED\n\n -- Id: A.5\n function \"+\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).\n -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.\n\n -- Id: A.6\n function \"+\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).\n -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.\n\n --============================================================================\n\n -- Id: A.9\n function \"-\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).\n -- Result: Subtracts two UNSIGNED vectors that may be of different lengths.\n\n -- Id: A.9R\n function \"-\"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Similar to A.9 where R is a one bit UNSIGNED\n\n -- Id: A.9L\n function \"-\"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Similar to A.9 where L is a one bit UNSIGNED\n\n -- Id: A.11\n function \"-\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).\n -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.\n\n -- Id: A.12\n function \"-\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).\n -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.\n\n --============================================================================\n\n -- Id: A.15\n function \"*\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).\n -- Result: Performs the multiplication operation on two UNSIGNED vectors\n -- that may possibly be of different lengths.\n\n -- Id: A.17\n function \"*\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).\n -- Result: Multiplies an UNSIGNED vector, L, with a non-negative\n -- INTEGER, R. R is converted to an UNSIGNED vector of\n -- SIZE L'LENGTH before multiplication.\n\n -- Id: A.18\n function \"*\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).\n -- Result: Multiplies an UNSIGNED vector, R, with a non-negative\n -- INTEGER, L. L is converted to an UNSIGNED vector of\n -- SIZE R'LENGTH before multiplication.\n\n --============================================================================\n --\n -- NOTE: If second argument is zero for \"/\" operator, a severity level\n -- of ERROR is issued.\n\n -- Id: A.21\n function \"/\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.\n\n -- Id: A.23\n function \"/\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.\n -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.\n\n -- Id: A.24\n function \"/\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.\n -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.\n\n --============================================================================\n --\n -- NOTE: If second argument is zero for \"rem\" operator, a severity level\n -- of ERROR is issued.\n\n -- Id: A.27\n function \"rem\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L rem R\" where L and R are UNSIGNED vectors.\n\n -- Id: A.29\n function \"rem\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Computes \"L rem R\" where L is an UNSIGNED vector and R is a\n -- non-negative INTEGER.\n -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.\n\n -- Id: A.30\n function \"rem\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L rem R\" where R is an UNSIGNED vector and L is a\n -- non-negative INTEGER.\n -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.\n\n --============================================================================\n --\n -- NOTE: If second argument is zero for \"mod\" operator, a severity level\n -- of ERROR is issued.\n\n -- Id: A.33\n function \"mod\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L mod R\" where L and R are UNSIGNED vectors.\n\n -- Id: A.35\n function \"mod\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Computes \"L mod R\" where L is an UNSIGNED vector and R\n -- is a non-negative INTEGER.\n -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.\n\n -- Id: A.36\n function \"mod\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L mod R\" where R is an UNSIGNED vector and L\n -- is a non-negative INTEGER.\n -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.\n\n-- begin LCS-2006-129\n --============================================================================\n -- Id: A.39\n function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;\n -- Result subtype: INTEGER\n -- Result: Finds the leftmost occurrence of the value of Y in ARG.\n -- Returns the index of the occurrence if it exists, or -1 otherwise.\n\n -- Id: A.41\n function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;\n -- Result subtype: INTEGER\n -- Result: Finds the leftmost occurrence of the value of Y in ARG.\n -- Returns the index of the occurrence if it exists, or -1 otherwise.\n\n-- end LCS-2006-129\n --============================================================================\n -- Comparison Operators\n --============================================================================\n\n -- Id: C.1\n function \">\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L > R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.3\n function \">\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L > R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.5\n function \">\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L > R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.7\n function \"<\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L < R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.9\n function \"<\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L < R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.11\n function \"<\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L < R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.13\n function \"<=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L <= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.15\n function \"<=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L <= R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.17\n function \"<=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L <= R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.19\n function \">=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L >= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.21\n function \">=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L >= R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.23\n function \">=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L >= R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.25\n function \"=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L = R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.27\n function \"=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L = R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.29\n function \"=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L = R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.31\n function \"/=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L /= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.33\n function \"/=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L /= R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.35\n function \"/=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L /= R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.37\n function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR\n -- Result: Returns the lesser of two UNSIGNED vectors that may be\n -- of different lengths.\n\n -- Id: C.39\n function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR\n -- Result: Returns the lesser of a nonnegative INTEGER, L, and\n -- an UNSIGNED vector, R.\n\n -- Id: C.41\n function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR\n -- Result: Returns the lesser of an UNSIGNED vector, L, and\n -- a nonnegative INTEGER, R.\n\n --============================================================================\n\n -- Id: C.43\n function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR\n -- Result: Returns the greater of two UNSIGNED vectors that may be\n -- of different lengths.\n\n -- Id: C.45\n function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR\n -- Result: Returns the greater of a nonnegative INTEGER, L, and\n -- an UNSIGNED vector, R.\n\n -- Id: C.47\n function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR\n -- Result: Returns the greater of an UNSIGNED vector, L, and\n -- a nonnegative INTEGER, R.\n\n --============================================================================\n -- Id: C.49\n function \\?>\\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L > R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.51\n function \\?>\\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L > R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.53\n function \\?>\\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L > R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.55\n function \\?<\\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L < R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.57\n function \\?<\\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L < R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.59\n function \\?<\\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L < R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.61\n function \\?<=\\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L <= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.63\n function \\?<=\\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L <= R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.65\n function \\?<=\\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L <= R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.67\n function \\?>=\\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L >= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.69\n function \\?>=\\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L >= R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.71\n function \\?>=\\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L >= R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.73\n function \\?=\\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L = R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.75\n function \\?=\\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L = R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.77\n function \\?=\\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L = R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.79\n function \\?/=\\ (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L /= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.81\n function \\?/=\\ (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L /= R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.83\n function \\?/=\\ (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L /= R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n -- Shift and Rotate Functions\n --============================================================================\n\n -- Id: S.1\n function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)\n return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.\n -- The vacated positions are filled with '0'.\n -- The COUNT leftmost elements are lost.\n\n -- Id: S.2\n function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)\n return STD_ULOGIC_VECTOR;\n -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)\n -- Result: Performs a shift-right on an UNSIGNED vector COUNT times.\n -- The vacated positions are filled with '0'.\n -- The COUNT rightmost elements are lost.\n --============================================================================\n\n -- Id: S.5\n function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)\n return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.\n\n -- Id: S.6\n function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)\n return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.\n\n ------------------------------------------------------------------------------\n -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.17\n function \"sla\" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: SHIFT_LEFT(ARG, COUNT)\n\n ------------------------------------------------------------------------------\n -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.19\n function \"sra\" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: SHIFT_RIGHT(ARG, COUNT)\n\n\n --============================================================================\n -- RESIZE Functions\n --============================================================================\n\n -- Id: R.2\n function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)\n return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)\n -- Result: Resizes the UNSIGNED vector ARG to the specified size.\n -- To create a larger vector, the new [leftmost] bit positions\n -- are filled with '0'. When truncating, the leftmost bits\n -- are dropped.\n\n -- size_res versions of these functions (Bugzilla 165)\n function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)\n --============================================================================\n -- Conversion Functions\n --============================================================================\n\n -- Id: D.1\n function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;\n -- Result subtype: NATURAL. Value cannot be negative since parameter is an\n -- UNSIGNED vector.\n -- Result: Converts the UNSIGNED vector to an INTEGER.\n\n -- Id: D.3\n function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)\n -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with\n -- the specified SIZE.\n\n-- begin LCS-2006-130\n alias To_Std_Logic_Vector is\n To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];\n alias To_SLV is\n To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];\n -- size_res versions of these functions (Bugzilla 165)\n function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)\n-- end LCS-2006-130\n -- Id: D.5\n function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)\n -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with\n -- the specified SIZE.\n -- size_res versions of these functions (Bugzilla 165)\n function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)\n-- begin LCS-2006-130\n alias To_Std_ULogic_Vector is\n To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];\n alias To_SULV is\n To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];\n alias To_Std_ULogic_Vector is\n To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];\n alias To_SULV is\n To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];\n\n-- end LCS-2006-130\n --============================================================================\n -- Translation Functions\n --============================================================================\n\n -- Id: T.1\n function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')\n return STD_ULOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR(S'RANGE)\n -- Result: Termwise, 'H' is translated to '1', and 'L' is translated\n -- to '0'. If a value other than '0'|'1'|'H'|'L' is found,\n -- the array is set to (others => XMAP), and a warning is\n -- issued.\n-- begin LCS-2006-141\n -- Replace all subsequent occurrences of STD_LOGIC_VECTOR\n -- with STD_ULOGIC_ECTOR.\n-- end LCS-2006-141\n -- Id: A.3\n function \"+\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).\n -- Result: Adds two UNSIGNED vectors that may be of different lengths.\n\n -- Id: A.3R\n function \"+\"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Similar to A.3 where R is a one bit STD_LOGIC_VECTOR\n\n -- Id: A.3L\n function \"+\"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Similar to A.3 where L is a one bit UNSIGNED\n\n -- Id: A.5\n function \"+\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).\n -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.\n\n -- Id: A.6\n function \"+\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).\n -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.\n\n --============================================================================\n\n -- Id: A.9\n function \"-\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).\n -- Result: Subtracts two UNSIGNED vectors that may be of different lengths.\n\n -- Id: A.9R\n function \"-\"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Similar to A.9 where R is a one bit UNSIGNED\n\n -- Id: A.9L\n function \"-\"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Similar to A.9 where L is a one bit UNSIGNED\n\n -- Id: A.11\n function \"-\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).\n -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.\n\n -- Id: A.12\n function \"-\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).\n -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.\n\n --============================================================================\n\n -- Id: A.15\n function \"*\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).\n -- Result: Performs the multiplication operation on two UNSIGNED vectors\n -- that may possibly be of different lengths.\n\n -- Id: A.17\n function \"*\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).\n -- Result: Multiplies an UNSIGNED vector, L, with a non-negative\n -- INTEGER, R. R is converted to an UNSIGNED vector of\n -- SIZE L'LENGTH before multiplication.\n\n -- Id: A.18\n function \"*\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).\n -- Result: Multiplies an UNSIGNED vector, R, with a non-negative\n -- INTEGER, L. L is converted to an UNSIGNED vector of\n -- SIZE R'LENGTH before multiplication.\n\n --============================================================================\n --\n -- NOTE: If second argument is zero for \"/\" operator, a severity level\n -- of ERROR is issued.\n\n -- Id: A.21\n function \"/\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.\n\n -- Id: A.23\n function \"/\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.\n -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.\n\n -- Id: A.24\n function \"/\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.\n -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.\n\n --============================================================================\n --\n -- NOTE: If second argument is zero for \"rem\" operator, a severity level\n -- of ERROR is issued.\n\n -- Id: A.27\n function \"rem\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L rem R\" where L and R are UNSIGNED vectors.\n\n -- Id: A.29\n function \"rem\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Computes \"L rem R\" where L is an UNSIGNED vector and R is a\n -- non-negative INTEGER.\n -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.\n\n -- Id: A.30\n function \"rem\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L rem R\" where R is an UNSIGNED vector and L is a\n -- non-negative INTEGER.\n -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.\n\n --============================================================================\n --\n -- NOTE: If second argument is zero for \"mod\" operator, a severity level\n -- of ERROR is issued.\n\n -- Id: A.33\n function \"mod\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L mod R\" where L and R are UNSIGNED vectors.\n\n -- Id: A.35\n function \"mod\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0)\n -- Result: Computes \"L mod R\" where L is an UNSIGNED vector and R\n -- is a non-negative INTEGER.\n -- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.\n\n -- Id: A.36\n function \"mod\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0)\n -- Result: Computes \"L mod R\" where R is an UNSIGNED vector and L\n -- is a non-negative INTEGER.\n -- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.\n\n-- begin LCS-2006-129\n --============================================================================\n -- Id: A.39\n function find_leftmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;\n -- Result subtype: INTEGER\n -- Result: Finds the leftmost occurrence of the value of Y in ARG.\n -- Returns the index of the occurrence if it exists, or -1 otherwise.\n\n -- Id: A.41\n function find_rightmost (ARG : STD_LOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;\n -- Result subtype: INTEGER\n -- Result: Finds the leftmost occurrence of the value of Y in ARG.\n -- Returns the index of the occurrence if it exists, or -1 otherwise.\n\n-- end LCS-2006-129\n --============================================================================\n -- Comparison Operators\n --============================================================================\n\n -- Id: C.1\n function \">\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L > R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.3\n function \">\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L > R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.5\n function \">\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L > R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.7\n function \"<\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L < R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.9\n function \"<\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L < R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.11\n function \"<\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L < R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.13\n function \"<=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L <= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.15\n function \"<=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L <= R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.17\n function \"<=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L <= R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.19\n function \">=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L >= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.21\n function \">=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L >= R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.23\n function \">=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L >= R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.25\n function \"=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L = R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.27\n function \"=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L = R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.29\n function \"=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L = R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.31\n function \"/=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L /= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.33\n function \"/=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L /= R\" where L is a non-negative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.35\n function \"/=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN;\n -- Result subtype: BOOLEAN\n -- Result: Computes \"L /= R\" where L is an UNSIGNED vector and\n -- R is a non-negative INTEGER.\n\n --============================================================================\n\n -- Id: C.37\n function MINIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR\n -- Result: Returns the lesser of two UNSIGNED vectors that may be\n -- of different lengths.\n\n -- Id: C.39\n function MINIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR\n -- Result: Returns the lesser of a nonnegative INTEGER, L, and\n -- an UNSIGNED vector, R.\n\n -- Id: C.41\n function MINIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR\n -- Result: Returns the lesser of an UNSIGNED vector, L, and\n -- a nonnegative INTEGER, R.\n\n --============================================================================\n\n -- Id: C.43\n function MAXIMUM (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR\n -- Result: Returns the greater of two UNSIGNED vectors that may be\n -- of different lengths.\n\n -- Id: C.45\n function MAXIMUM (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR\n -- Result: Returns the greater of a nonnegative INTEGER, L, and\n -- an UNSIGNED vector, R.\n\n -- Id: C.47\n function MAXIMUM (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR\n -- Result: Returns the greater of an UNSIGNED vector, L, and\n -- a nonnegative INTEGER, R.\n\n --============================================================================\n -- Id: C.49\n function \\?>\\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L > R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.51\n function \\?>\\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L > R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.53\n function \\?>\\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L > R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.55\n function \\?<\\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L < R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.57\n function \\?<\\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L < R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.59\n function \\?<\\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L < R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.61\n function \\?<=\\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L <= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.63\n function \\?<=\\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L <= R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.65\n function \\?<=\\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L <= R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.67\n function \\?>=\\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L >= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.69\n function \\?>=\\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L >= R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.71\n function \\?>=\\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L >= R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.73\n function \\?=\\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L = R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.75\n function \\?=\\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L = R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.77\n function \\?=\\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L = R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n\n -- Id: C.79\n function \\?/=\\ (L, R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L /= R\" where L and R are UNSIGNED vectors possibly\n -- of different lengths.\n\n -- Id: C.81\n function \\?/=\\ (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L /= R\" where L is a nonnegative INTEGER and\n -- R is an UNSIGNED vector.\n\n -- Id: C.83\n function \\?/=\\ (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;\n -- Result subtype: STD_ULOGIC\n -- Result: Computes \"L /= R\" where L is an UNSIGNED vector and\n -- R is a nonnegative INTEGER.\n\n --============================================================================\n -- Shift and Rotate Functions\n --============================================================================\n\n -- Id: S.1\n function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)\n return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.\n -- The vacated positions are filled with '0'.\n -- The COUNT leftmost elements are lost.\n\n -- Id: S.2\n function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)\n return STD_LOGIC_VECTOR;\n -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)\n -- Result: Performs a shift-right on an UNSIGNED vector COUNT times.\n -- The vacated positions are filled with '0'.\n -- The COUNT rightmost elements are lost.\n --============================================================================\n\n -- Id: S.5\n function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)\n return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.\n\n -- Id: S.6\n function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL)\n return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.\n\n ------------------------------------------------------------------------------\n -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.17\n function \"sla\" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: SHIFT_LEFT(ARG, COUNT)\n\n ------------------------------------------------------------------------------\n -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment\n -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.\n ------------------------------------------------------------------------------\n -- Id: S.19\n function \"sra\" (ARG : STD_LOGIC_VECTOR; COUNT : INTEGER) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(ARG'LENGTH-1 downto 0)\n -- Result: SHIFT_RIGHT(ARG, COUNT)\n\n\n --============================================================================\n -- RESIZE Functions\n --============================================================================\n\n -- Id: R.2\n function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)\n return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(NEW_SIZE-1 downto 0)\n -- Result: Resizes the UNSIGNED vector ARG to the specified size.\n -- To create a larger vector, the new [leftmost] bit positions\n -- are filled with '0'. When truncating, the leftmost bits\n -- are dropped.\n\n -- size_res versions of these functions (Bugzilla 165)\n function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n -- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)\n --============================================================================\n -- Conversion Functions\n --============================================================================\n\n -- Id: D.1\n function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL;\n -- Result subtype: NATURAL. Value cannot be negative since parameter is an\n -- UNSIGNED vector.\n -- Result: Converts the UNSIGNED vector to an INTEGER.\n\n-- end LCS-2006-130\n \n --============================================================================\n -- Translation Functions\n --============================================================================\n\n -- Id: T.1\n function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')\n return STD_LOGIC_VECTOR;\n -- Result subtype: STD_LOGIC_VECTOR(S'RANGE)\n -- Result: Termwise, 'H' is translated to '1', and 'L' is translated\n -- to '0'. If a value other than '0'|'1'|'H'|'L' is found,\n -- the array is set to (others => XMAP), and a warning is\n -- issued.\nend package NUMERIC_STD_UNSIGNED;\n-------------------------------------------------------------------------------\n-- Proposed package body for the VHDL-200x-FT NUMERIC_STD_UNSIGNED package\n-- This package body supplies a recommended implementation of these functions\n-- Version: $Revision: 1.4 $\n-- Date: $Date: 2009/08/26 19:56:30 $\n--\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n-------------------------------------------------------------------------------\nlibrary ieee;\nuse ieee.numeric_std.all;\nuse work.numeric_std_additions.all;\n\npackage body NUMERIC_STD_UNSIGNED is\n\n -- Id: A.3\n function \"+\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));\n end function \"+\";\n\n -- Id: A.3R\n function \"+\"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);\n end function \"+\";\n\n -- Id: A.3L\n function \"+\"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L + UNSIGNED(R));\n end function \"+\";\n\n -- Id: A.5\n function \"+\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);\n end function \"+\";\n\n -- Id: A.6\n function \"+\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L + UNSIGNED(R));\n end function \"+\";\n\n --============================================================================\n\n -- Id: A.9\n function \"-\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));\n end function \"-\";\n\n -- Id: A.9R\n function \"-\"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);\n end function \"-\";\n\n -- Id: A.9L\n function \"-\"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L - UNSIGNED(R));\n end function \"-\";\n\n -- Id: A.11\n function \"-\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);\n end function \"-\";\n\n -- Id: A.12\n function \"-\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L - UNSIGNED(R));\n end function \"-\";\n\n --============================================================================\n\n -- Id: A.15\n function \"*\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));\n end function \"*\";\n\n -- Id: A.17\n function \"*\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);\n end function \"*\";\n\n -- Id: A.18\n function \"*\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L * UNSIGNED(R));\n end function \"*\";\n\n --============================================================================\n\n -- Id: A.21\n function \"/\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));\n end function \"/\";\n\n -- Id: A.23\n function \"/\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);\n end function \"/\";\n\n -- Id: A.24\n function \"/\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L / UNSIGNED(R));\n end function \"/\";\n\n --============================================================================\n\n -- Id: A.27\n function \"rem\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));\n end function \"rem\";\n\n -- Id: A.29\n function \"rem\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);\n end function \"rem\";\n\n -- Id: A.30\n function \"rem\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));\n end function \"rem\";\n\n --============================================================================\n\n -- Id: A.33\n function \"mod\" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));\n end function \"mod\";\n\n -- Id: A.35\n function \"mod\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);\n end function \"mod\";\n\n -- Id: A.36\n function \"mod\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));\n end function \"mod\";\n\n-- begin LCS-2006-129\n --============================================================================\n -- Id: A.39\n function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is\n begin\n return find_leftmost(UNSIGNED(ARG), Y);\n end function find_leftmost;\n\n -- Id: A.41\n function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is\n begin\n return find_rightmost(UNSIGNED(ARG), Y);\n end function find_rightmost;\n\n-- end LCS-2006-129\n --============================================================================\n\n -- Id: C.1\n function \">\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) > UNSIGNED(R);\n end function \">\";\n\n -- Id: C.3\n function \">\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return L > UNSIGNED(R);\n end function \">\";\n\n -- Id: C.5\n function \">\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) > R;\n end function \">\";\n\n --============================================================================\n\n -- Id: C.7\n function \"<\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) < UNSIGNED(R);\n end function \"<\";\n\n -- Id: C.9\n function \"<\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return L < UNSIGNED(R);\n end function \"<\";\n\n -- Id: C.11\n function \"<\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) < R;\n end function \"<\";\n\n --============================================================================\n\n -- Id: C.13\n function \"<=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) <= UNSIGNED(R);\n end function \"<=\";\n\n -- Id: C.15\n function \"<=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return L <= UNSIGNED(R);\n end function \"<=\";\n\n -- Id: C.17\n function \"<=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) <= R;\n end function \"<=\";\n\n --============================================================================\n\n -- Id: C.19\n function \">=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) >= UNSIGNED(R);\n end function \">=\";\n\n -- Id: C.21\n function \">=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return L >= UNSIGNED(R);\n end function \">=\";\n\n -- Id: C.23\n function \">=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) >= R;\n end function \">=\";\n\n --============================================================================\n\n -- Id: C.25\n function \"=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) = UNSIGNED(R);\n end function \"=\";\n\n -- Id: C.27\n function \"=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return L = UNSIGNED(R);\n end function \"=\";\n\n -- Id: C.29\n function \"=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) = R;\n end function \"=\";\n\n --============================================================================\n\n -- Id: C.31\n function \"/=\" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) /= UNSIGNED(R);\n end function \"/=\";\n\n -- Id: C.33\n function \"/=\" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is\n begin\n return L /= UNSIGNED(R);\n end function \"/=\";\n\n -- Id: C.35\n function \"/=\" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) /= R;\n end function \"/=\";\n\n --============================================================================\n\n -- Id: C.37\n function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));\n end function MINIMUM;\n\n -- Id: C.39\n function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));\n end function MINIMUM;\n\n -- Id: C.41\n function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));\n end function MINIMUM;\n\n --============================================================================\n -- Id: C.43\n function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));\n end function MAXIMUM;\n\n -- Id: C.45\n function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));\n end function MAXIMUM;\n\n -- Id: C.47\n function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));\n end function MAXIMUM;\n\n --============================================================================\n\n -- Id: C.49\n function \\?>\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?>\\;\n\n -- Id: C.51\n function \\?>\\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>\\ (L, UNSIGNED(R));\n end function \\?>\\;\n\n -- Id: C.53\n function \\?>\\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?>\\ (UNSIGNED(L), R);\n end function \\?>\\;\n\n --============================================================================\n\n -- Id: C.55\n", "right_context": " begin\n return \\?<\\ (L, UNSIGNED(R));\n end function \\?<\\;\n\n -- Id: C.59\n function \\?<\\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?<\\ (UNSIGNED(L), R);\n end function \\?<\\;\n\n --============================================================================\n\n -- Id: C.61\n function \\?<=\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?<=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?<=\\;\n\n -- Id: C.63\n function \\?<=\\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?<=\\ (L, UNSIGNED(R));\n end function \\?<=\\;\n\n -- Id: C.65\n function \\?<=\\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?<=\\ (UNSIGNED(L), R);\n end function \\?<=\\;\n\n --============================================================================\n\n -- Id: C.67\n function \\?>=\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?>=\\;\n\n -- Id: C.69\n function \\?>=\\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>=\\ (L, UNSIGNED(R));\n end function \\?>=\\;\n\n -- Id: C.71\n function \\?>=\\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?>=\\ (UNSIGNED(L), R);\n end function \\?>=\\;\n\n --============================================================================\n\n -- Id: C.73\n function \\?=\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?=\\;\n\n -- Id: C.75\n function \\?=\\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?=\\ (L, UNSIGNED(R));\n end function \\?=\\;\n\n -- Id: C.77\n function \\?=\\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?=\\ (UNSIGNED(L), R);\n end function \\?=\\;\n\n --============================================================================\n\n -- Id: C.79\n function \\?/=\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?/=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?/=\\;\n\n -- Id: C.81\n function \\?/=\\ (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?/=\\ (L, UNSIGNED(R));\n end function \\?/=\\;\n\n -- Id: C.83\n function \\?/=\\ (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?/=\\ (UNSIGNED(L), R);\n end function \\?/=\\;\n\n --============================================================================\n\n -- Id: S.1\n function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return std_ulogic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));\n end function SHIFT_LEFT;\n\n -- Id: S.2\n function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return std_ulogic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));\n end function SHIFT_RIGHT;\n\n --============================================================================\n\n -- Id: S.5\n function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return std_ulogic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));\n end function ROTATE_LEFT;\n\n -- Id: S.6\n function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return std_ulogic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));\n end function ROTATE_RIGHT;\n\n --============================================================================\n\n -- Id: S.17\n function \"sla\" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);\n end function \"sla\";\n\n -- Id: S.19\n function \"sra\" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);\n end function \"sra\";\n\n --============================================================================\n\n -- Id: R.2\n function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)\n return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (\n RESIZE (ARG => UNSIGNED(ARG),\n NEW_SIZE => NEW_SIZE));\n end function RESIZE;\n\n function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)\n return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (\n RESIZE (ARG => UNSIGNED(ARG),\n NEW_SIZE => SIZE_RES'length));\n end function RESIZE;\n --============================================================================\n\n -- Id: D.1\n function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is\n begin\n return TO_INTEGER(UNSIGNED(ARG));\n end function TO_INTEGER;\n\n -- Id: D.3\n function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,\n SIZE => SIZE));\n end function To_StdLogicVector;\n\n function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,\n SIZE => SIZE_RES'length));\n end function To_StdLogicVector;\n -- Id: D.5\n function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,\n SIZE => SIZE));\n end function To_StdULogicVector;\n\n function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,\n SIZE => SIZE_RES'length));\n end function To_StdULogicVector;\n --============================================================================\n\n -- function TO_01 is used to convert vectors to the\n -- correct form for exported functions,\n -- and to report if there is an element which\n -- is not in (0, 1, H, L).\n\n -- Id: T.1\n function TO_01 (S : STD_ULOGIC_VECTOR; XMAP : STD_ULOGIC := '0')\n return STD_ULOGIC_VECTOR is\n begin\n return STD_ULOGIC_VECTOR (\n TO_01 (S => UNSIGNED(S),\n XMAP => XMAP));\n end function TO_01;\n\n -- Id: A.3\n function \"+\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));\n end function \"+\";\n\n -- Id: A.3R\n function \"+\"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) + R);\n end function \"+\";\n\n -- Id: A.3L\n function \"+\"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L + UNSIGNED(R));\n end function \"+\";\n\n -- Id: A.5\n function \"+\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) + R);\n end function \"+\";\n\n -- Id: A.6\n function \"+\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L + UNSIGNED(R));\n end function \"+\";\n\n --============================================================================\n\n -- Id: A.9\n function \"-\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));\n end function \"-\";\n\n -- Id: A.9R\n function \"-\"(L : STD_LOGIC_VECTOR; R : STD_ULOGIC) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) - R);\n end function \"-\";\n\n -- Id: A.9L\n function \"-\"(L : STD_ULOGIC; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L - UNSIGNED(R));\n end function \"-\";\n\n -- Id: A.11\n function \"-\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) - R);\n end function \"-\";\n\n -- Id: A.12\n function \"-\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L - UNSIGNED(R));\n end function \"-\";\n\n --============================================================================\n\n -- Id: A.15\n function \"*\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));\n end function \"*\";\n\n -- Id: A.17\n function \"*\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) * R);\n end function \"*\";\n\n -- Id: A.18\n function \"*\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L * UNSIGNED(R));\n end function \"*\";\n\n --============================================================================\n\n -- Id: A.21\n function \"/\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));\n end function \"/\";\n\n -- Id: A.23\n function \"/\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) / R);\n end function \"/\";\n\n -- Id: A.24\n function \"/\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L / UNSIGNED(R));\n end function \"/\";\n\n --============================================================================\n\n -- Id: A.27\n function \"rem\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));\n end function \"rem\";\n\n -- Id: A.29\n function \"rem\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) rem R);\n end function \"rem\";\n\n -- Id: A.30\n function \"rem\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L rem UNSIGNED(R));\n end function \"rem\";\n\n --============================================================================\n\n -- Id: A.33\n function \"mod\" (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));\n end function \"mod\";\n\n -- Id: A.35\n function \"mod\" (L : STD_LOGIC_VECTOR; R : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(L) mod R);\n end function \"mod\";\n\n -- Id: A.36\n function \"mod\" (L : NATURAL; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (L mod UNSIGNED(R));\n end function \"mod\";\n\n-- begin LCS-2006-129\n --============================================================================\n -- Id: A.39\n function find_leftmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is\n begin\n return find_leftmost(UNSIGNED(ARG), Y);\n end function find_leftmost;\n\n -- Id: A.41\n function find_rightmost (ARG: STD_LOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is\n begin\n return find_rightmost(UNSIGNED(ARG), Y);\n end function find_rightmost;\n\n-- end LCS-2006-129\n --============================================================================\n\n -- Id: C.1\n function \">\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) > UNSIGNED(R);\n end function \">\";\n\n -- Id: C.3\n function \">\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return L > UNSIGNED(R);\n end function \">\";\n\n -- Id: C.5\n function \">\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) > R;\n end function \">\";\n\n --============================================================================\n\n -- Id: C.7\n function \"<\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) < UNSIGNED(R);\n end function \"<\";\n\n -- Id: C.9\n function \"<\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return L < UNSIGNED(R);\n end function \"<\";\n\n -- Id: C.11\n function \"<\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) < R;\n end function \"<\";\n\n --============================================================================\n\n -- Id: C.13\n function \"<=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) <= UNSIGNED(R);\n end function \"<=\";\n\n -- Id: C.15\n function \"<=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return L <= UNSIGNED(R);\n end function \"<=\";\n\n -- Id: C.17\n function \"<=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) <= R;\n end function \"<=\";\n\n --============================================================================\n\n -- Id: C.19\n function \">=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) >= UNSIGNED(R);\n end function \">=\";\n\n -- Id: C.21\n function \">=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return L >= UNSIGNED(R);\n end function \">=\";\n\n -- Id: C.23\n function \">=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) >= R;\n end function \">=\";\n\n --============================================================================\n\n -- Id: C.25\n function \"=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) = UNSIGNED(R);\n end function \"=\";\n\n -- Id: C.27\n function \"=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return L = UNSIGNED(R);\n end function \"=\";\n\n -- Id: C.29\n function \"=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) = R;\n end function \"=\";\n\n --============================================================================\n\n -- Id: C.31\n function \"/=\" (L, R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return UNSIGNED(L) /= UNSIGNED(R);\n end function \"/=\";\n\n -- Id: C.33\n function \"/=\" (L : NATURAL; R : STD_LOGIC_VECTOR) return BOOLEAN is\n begin\n return L /= UNSIGNED(R);\n end function \"/=\";\n\n -- Id: C.35\n function \"/=\" (L : STD_LOGIC_VECTOR; R : NATURAL) return BOOLEAN is\n begin\n return UNSIGNED(L) /= R;\n end function \"/=\";\n\n --============================================================================\n\n -- Id: C.37\n function MINIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));\n end function MINIMUM;\n\n -- Id: C.39\n function MINIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));\n end function MINIMUM;\n\n -- Id: C.41\n function MINIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));\n end function MINIMUM;\n\n --============================================================================\n -- Id: C.43\n function MAXIMUM (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));\n end function MAXIMUM;\n\n -- Id: C.45\n function MAXIMUM (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));\n end function MAXIMUM;\n\n -- Id: C.47\n function MAXIMUM (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));\n end function MAXIMUM;\n\n --============================================================================\n\n -- Id: C.49\n function \\?>\\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?>\\;\n\n -- Id: C.51\n function \\?>\\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>\\ (L, UNSIGNED(R));\n end function \\?>\\;\n\n -- Id: C.53\n function \\?>\\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?>\\ (UNSIGNED(L), R);\n end function \\?>\\;\n\n --============================================================================\n\n -- Id: C.55\n function \\?<\\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?<\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?<\\;\n\n -- Id: C.57\n function \\?<\\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?<\\ (L, UNSIGNED(R));\n end function \\?<\\;\n\n -- Id: C.59\n function \\?<\\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?<\\ (UNSIGNED(L), R);\n end function \\?<\\;\n\n --============================================================================\n\n -- Id: C.61\n function \\?<=\\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?<=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?<=\\;\n\n -- Id: C.63\n function \\?<=\\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?<=\\ (L, UNSIGNED(R));\n end function \\?<=\\;\n\n -- Id: C.65\n function \\?<=\\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?<=\\ (UNSIGNED(L), R);\n end function \\?<=\\;\n\n --============================================================================\n\n -- Id: C.67\n function \\?>=\\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?>=\\;\n\n -- Id: C.69\n function \\?>=\\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?>=\\ (L, UNSIGNED(R));\n end function \\?>=\\;\n\n -- Id: C.71\n function \\?>=\\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?>=\\ (UNSIGNED(L), R);\n end function \\?>=\\;\n\n --============================================================================\n\n -- Id: C.73\n function \\?=\\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?=\\;\n\n -- Id: C.75\n function \\?=\\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?=\\ (L, UNSIGNED(R));\n end function \\?=\\;\n\n -- Id: C.77\n function \\?=\\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?=\\ (UNSIGNED(L), R);\n end function \\?=\\;\n\n --============================================================================\n\n -- Id: C.79\n function \\?/=\\ (L, R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?/=\\ (UNSIGNED(L), UNSIGNED(R));\n end function \\?/=\\;\n\n -- Id: C.81\n function \\?/=\\ (L: NATURAL; R: STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \\?/=\\ (L, UNSIGNED(R));\n end function \\?/=\\;\n\n -- Id: C.83\n function \\?/=\\ (L: STD_LOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is\n begin\n return \\?/=\\ (UNSIGNED(L), R);\n end function \\?/=\\;\n\n --============================================================================\n\n -- Id: S.1\n function SHIFT_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (SHIFT_LEFT(unsigned(ARG), COUNT));\n end function SHIFT_LEFT;\n\n -- Id: S.2\n function SHIFT_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (SHIFT_RIGHT(unsigned(ARG), COUNT));\n end function SHIFT_RIGHT;\n\n --============================================================================\n\n -- Id: S.5\n function ROTATE_LEFT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (ROTATE_LEFT(unsigned(ARG), COUNT));\n end function ROTATE_LEFT;\n\n -- Id: S.6\n function ROTATE_RIGHT (ARG : STD_LOGIC_VECTOR; COUNT : NATURAL) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (ROTATE_RIGHT(unsigned(ARG), COUNT));\n end function ROTATE_RIGHT;\n\n --============================================================================\n\n -- Id: S.17\n function \"sla\" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);\n end function \"sla\";\n\n -- Id: S.19\n function \"sra\" (ARG: STD_LOGIC_VECTOR; COUNT: INTEGER) return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);\n end function \"sra\";\n\n --============================================================================\n\n -- Id: R.2\n function RESIZE (ARG : STD_LOGIC_VECTOR; NEW_SIZE : NATURAL)\n return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (\n RESIZE (ARG => UNSIGNED(ARG),\n NEW_SIZE => NEW_SIZE));\n end function RESIZE;\n\n function RESIZE (ARG, SIZE_RES : STD_LOGIC_VECTOR)\n return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (\n RESIZE (ARG => UNSIGNED(ARG),\n NEW_SIZE => SIZE_RES'length));\n end function RESIZE;\n --============================================================================\n\n -- Id: D.1\n function TO_INTEGER (ARG : STD_LOGIC_VECTOR) return NATURAL is\n begin\n return TO_INTEGER(UNSIGNED(ARG));\n end function TO_INTEGER;\n\n --============================================================================\n\n -- function TO_01 is used to convert vectors to the\n -- correct form for exported functions,\n -- and to report if there is an element which\n -- is not in (0, 1, H, L).\n\n -- Id: T.1\n function TO_01 (S : STD_LOGIC_VECTOR; XMAP : STD_ULOGIC := '0')\n return STD_LOGIC_VECTOR is\n begin\n return STD_LOGIC_VECTOR (\n TO_01 (S => UNSIGNED(S),\n XMAP => XMAP));\n end function TO_01;\n\nend package body NUMERIC_STD_UNSIGNED;\n", "groundtruth": " function \\?<\\ (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is\r\n begin\r\n return \\?<\\ (UNSIGNED(L), UNSIGNED(R));\r\n end function \\?<\\;\r\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/standard_additions_c.vhdl", "left_context": "------------------------------------------------------------------------------\n-- \"standard_additions\" package contains the additions to the built in\n-- \"standard.std\" package. In the final version this package will be implicit.\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n------------------------------------------------------------------------------\npackage standard_additions is\n\n function \\?=\\ (L, R : BOOLEAN) return BOOLEAN;\n function \\?/=\\ (L, R : BOOLEAN) return BOOLEAN;\n function \\?<\\ (L, R : BOOLEAN) return BOOLEAN;\n function \\?<=\\ (L, R : BOOLEAN) return BOOLEAN;\n function \\?>\\ (L, R : BOOLEAN) return BOOLEAN;\n function \\?>=\\ (L, R : BOOLEAN) return BOOLEAN;\n\n function MINIMUM (L, R : BOOLEAN) return BOOLEAN;\n function MAXIMUM (L, R : BOOLEAN) return BOOLEAN;\n\n function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN;\n function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN;\n\n function \\?=\\ (L, R : BIT) return BIT;\n function \\?/=\\ (L, R : BIT) return BIT;\n function \\?<\\ (L, R : BIT) return BIT;\n function \\?<=\\ (L, R : BIT) return BIT;\n function \\?>\\ (L, R : BIT) return BIT;\n function \\?>=\\ (L, R : BIT) return BIT;\n\n function MINIMUM (L, R : BIT) return BIT;\n function MAXIMUM (L, R : BIT) return BIT;\n\n function \\??\\ (L : BIT) return BOOLEAN;\n\n function RISING_EDGE (signal S : BIT) return BOOLEAN;\n function FALLING_EDGE (signal S : BIT) return BOOLEAN;\n\n function MINIMUM (L, R : CHARACTER) return CHARACTER;\n function MAXIMUM (L, R : CHARACTER) return CHARACTER;\n\n function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;\n function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL;\n\n function MINIMUM (L, R : INTEGER) return INTEGER;\n function MAXIMUM (L, R : INTEGER) return INTEGER;\n\n function MINIMUM (L, R : REAL) return REAL;\n function MAXIMUM (L, R : REAL) return REAL;\n\n function \"mod\" (L, R : TIME) return TIME;\n function \"rem\" (L, R : TIME) return TIME;\n\n function MINIMUM (L, R : TIME) return TIME;\n function MAXIMUM (L, R : TIME) return TIME;\n\n function MINIMUM (L, R : STRING) return STRING;\n function MAXIMUM (L, R : STRING) return STRING;\n\n function MINIMUM (L : STRING) return CHARACTER;\n function MAXIMUM (L : STRING) return CHARACTER;\n\n type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;\n\n -- The predefined operations for this type are as follows:\n\n function \"and\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n function \"or\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n function \"nand\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n function \"nor\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n function \"xor\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n function \"xnor\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n\n function \"not\" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n\n function \"and\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR;\n function \"and\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR;\n function \"or\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR;\n function \"or\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR;\n function \"nand\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR;\n function \"nand\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR;\n function \"nor\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR;\n function \"nor\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR;\n function \"xor\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR;\n function \"xor\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR;\n function \"xnor\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR;\n function \"xnor\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR;\n\n function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;\n function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;\n function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;\n function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;\n function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;\n function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN;\n\n function \"sll\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR;\n function \"srl\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR;\n function \"sla\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR;\n function \"sra\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR;\n function \"rol\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR;\n function \"ror\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR;\n\n-- function \"=\" (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n-- function \"/=\" (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n-- function \"<\" (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n-- function \"<=\" (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n-- function \">\" (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n-- function \">=\" (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n\n function \\?=\\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n function \\?/=\\ (L, R : BOOLEAN_VECTOR) return BOOLEAN;\n\n-- function \"&\" (L : BOOLEAN_VECTOR; R : BOOLEAN_VECTOR)\n -- return BOOLEAN_VECTOR;\n-- function \"&\" (L : BOOLEAN_VECTOR; R : BOOLEAN) -- return BOOLEAN_VECTOR;\n-- function \"&\" (L : BOOLEAN; R : BOOLEAN_VECTOR) -- return BOOLEAN_VECTOR;\n-- function \"&\" (L : BOOLEAN; R : BOOLEAN) -- return BOOLEAN_VECTOR;\n\n function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n\n function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;\n function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN;\n\n function \"and\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;\n function \"and\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;\n function \"or\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;\n function \"or\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;\n function \"nand\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;\n function \"nand\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;\n function \"nor\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;\n function \"nor\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;\n function \"xor\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;\n function \"xor\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;\n function \"xnor\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR;\n function \"xnor\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR;\n\n function and_reduce (L : BIT_VECTOR) return BIT;\n function or_reduce (L : BIT_VECTOR) return BIT;\n function nand_reduce (L : BIT_VECTOR) return BIT;\n function nor_reduce (L : BIT_VECTOR) return BIT;\n function xor_reduce (L : BIT_VECTOR) return BIT;\n function xnor_reduce (L : BIT_VECTOR) return BIT;\n\n function \\?=\\ (L, R : BIT_VECTOR) return BIT;\n function \\?/=\\ (L, R : BIT_VECTOR) return BIT;\n\n function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;\n function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;\n\n function MINIMUM (L : BIT_VECTOR) return BIT;\n function MAXIMUM (L : BIT_VECTOR) return BIT;\n\n function TO_STRING (VALUE : BIT_VECTOR) return STRING;\n\n alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];\n alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];\n function TO_OSTRING (VALUE : BIT_VECTOR) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];\n function TO_HSTRING (VALUE : BIT_VECTOR) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];\n\n type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;\n\n -- The predefined operations for this type are as follows:\n function \"=\" (L, R : INTEGER_VECTOR) return BOOLEAN;\n function \"/=\" (L, R : INTEGER_VECTOR) return BOOLEAN;\n function \"<\" (L, R : INTEGER_VECTOR) return BOOLEAN;\n function \"<=\" (L, R : INTEGER_VECTOR) return BOOLEAN;\n function \">\" (L, R : INTEGER_VECTOR) return BOOLEAN;\n function \">=\" (L, R : INTEGER_VECTOR) return BOOLEAN;\n\n-- function \"&\" (L : INTEGER_VECTOR; R : INTEGER_VECTOR)\n-- return INTEGER_VECTOR;\n-- function \"&\" (L : INTEGER_VECTOR; R : INTEGER) return INTEGER_VECTOR;\n-- function \"&\" (L : INTEGER; R : INTEGER_VECTOR) return INTEGER_VECTOR;\n-- function \"&\" (L : INTEGER; R : INTEGER) return INTEGER_VECTOR;\n\n function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;\n function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR;\n\n function MINIMUM (L : INTEGER_VECTOR) return INTEGER;\n function MAXIMUM (L : INTEGER_VECTOR) return INTEGER;\n\n type REAL_VECTOR is array (NATURAL range <>) of REAL;\n\n -- The predefined operations for this type are as follows:\n function \"=\" (L, R : REAL_VECTOR) return BOOLEAN;\n function \"/=\" (L, R : REAL_VECTOR) return BOOLEAN;\n function \"<\" (L, R : REAL_VECTOR) return BOOLEAN;\n function \"<=\" (L, R : REAL_VECTOR) return BOOLEAN;\n function \">\" (L, R : REAL_VECTOR) return BOOLEAN;\n function \">=\" (L, R : REAL_VECTOR) return BOOLEAN;\n\n-- function \"&\" (L : REAL_VECTOR; R : REAL_VECTOR)\n-- return REAL_VECTOR;\n-- function \"&\" (L : REAL_VECTOR; R : REAL) return REAL_VECTOR;\n-- function \"&\" (L : REAL; R : REAL_VECTOR) return REAL_VECTOR;\n-- function \"&\" (L : REAL; R : REAL) return REAL_VECTOR;\n\n function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;\n function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR;\n\n function MINIMUM (L : REAL_VECTOR) return REAL;\n function MAXIMUM (L : REAL_VECTOR) return REAL;\n\n type TIME_VECTOR is array (NATURAL range <>) of TIME;\n\n -- The predefined operations for this type are as follows:\n function \"=\" (L, R : TIME_VECTOR) return BOOLEAN;\n function \"/=\" (L, R : TIME_VECTOR) return BOOLEAN;\n function \"<\" (L, R : TIME_VECTOR) return BOOLEAN;\n function \"<=\" (L, R : TIME_VECTOR) return BOOLEAN;\n function \">\" (L, R : TIME_VECTOR) return BOOLEAN;\n function \">=\" (L, R : TIME_VECTOR) return BOOLEAN;\n\n-- function \"&\" (L : TIME_VECTOR; R : TIME_VECTOR)\n-- return TIME_VECTOR;\n-- function \"&\" (L : TIME_VECTOR; R : TIME) return TIME_VECTOR;\n-- function \"&\" (L : TIME; R : TIME_VECTOR) return TIME_VECTOR;\n-- function \"&\" (L : TIME; R : TIME) return TIME_VECTOR;\n\n function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;\n function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR;\n\n function MINIMUM (L : TIME_VECTOR) return TIME;\n function MAXIMUM (L : TIME_VECTOR) return TIME;\n\n function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;\n function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND;\n\n function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;\n function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS;\n\n -- predefined TO_STRING operations on scalar types\n function TO_STRING (VALUE : BOOLEAN) return STRING;\n function TO_STRING (VALUE : BIT) return STRING;\n function TO_STRING (VALUE : CHARACTER) return STRING;\n function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING;\n function TO_STRING (VALUE : INTEGER) return STRING;\n function TO_STRING (VALUE : REAL) return STRING;\n function TO_STRING (VALUE : TIME) return STRING;\n function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING;\n function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING;\n\n -- predefined overloaded TO_STRING operations\n function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING;\n function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING;\n function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING;\nend package standard_additions;\n\n------------------------------------------------------------------------------\n-- \"standard_additions\" package contains the additions to the built in\n-- \"standard.std\" package. In the final version this package will be implicit.\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n------------------------------------------------------------------------------\nuse std.textio.all;\npackage body standard_additions is\n\n function \\?=\\ (L, R : BOOLEAN) return BOOLEAN is\n begin\n return L = R;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : BOOLEAN) return BOOLEAN is\n begin\n return L /= R;\n end function \\?/=\\;\n\n function \\?<\\ (L, R : BOOLEAN) return BOOLEAN is\n begin\n return L < R;\n end function \\?<\\;\n\n function \\?<=\\ (L, R : BOOLEAN) return BOOLEAN is\n begin\n return L <= R;\n end function \\?<=\\;\n\n function \\?>\\ (L, R : BOOLEAN) return BOOLEAN is\n begin\n return L > R;\n end function \\?>\\;\n\n function \\?>=\\ (L, R : BOOLEAN) return BOOLEAN is\n begin\n return L >= R;\n end function \\?>=\\;\n\n function MINIMUM (L, R : BOOLEAN) return BOOLEAN is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n function MAXIMUM (L, R : BOOLEAN) return BOOLEAN is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : BOOLEAN) return STRING is\n begin\n return BOOLEAN'image(VALUE);\n end function TO_STRING;\n\n function RISING_EDGE (signal S : BOOLEAN) return BOOLEAN is\n begin\n return (s'event and (s = true) and (s'last_value = false));\n end function rising_edge;\n\n function FALLING_EDGE (signal S : BOOLEAN) return BOOLEAN is\n begin\n return (s'event and (s = false) and (s'last_value = true));\n end function falling_edge;\n\n function \\?=\\ (L, R : BIT) return BIT is\n begin\n if L = R then\n return '1';\n else\n return '0';\n end if;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : BIT) return BIT is\n begin\n if L /= R then\n return '1';\n else\n return '0';\n end if;\n end function \\?/=\\;\n\n function \\?<\\ (L, R : BIT) return BIT is\n begin\n if L < R then\n return '1';\n else\n return '0';\n end if;\n end function \\?<\\;\n\n function \\?<=\\ (L, R : BIT) return BIT is\n begin\n if L <= R then\n return '1';\n else\n return '0';\n end if;\n end function \\?<=\\;\n\n function \\?>\\ (L, R : BIT) return BIT is\n begin\n if L > R then\n return '1';\n else\n return '0';\n end if;\n end function \\?>\\;\n\n function \\?>=\\ (L, R : BIT) return BIT is\n begin\n if L >= R then\n return '1';\n else\n return '0';\n end if;\n end function \\?>=\\;\n\n function MINIMUM (L, R : BIT) return BIT is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : BIT) return BIT is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : BIT) return STRING is\n begin\n if VALUE = '1' then\n return \"1\";\n else\n return \"0\";\n end if;\n end function TO_STRING;\n\n function \\??\\ (L : BIT) return BOOLEAN is\n begin\n return L = '1';\n end function \\??\\;\n\n function RISING_EDGE (signal S : BIT) return BOOLEAN is\n begin\n return (s'event and (s = '1') and (s'last_value = '0'));\n end function rising_edge;\n\n function FALLING_EDGE (signal S : BIT) return BOOLEAN is\n begin\n return (s'event and (s = '0') and (s'last_value = '1'));\n end function falling_edge;\n\n function MINIMUM (L, R : CHARACTER) return CHARACTER is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : CHARACTER) return CHARACTER is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : CHARACTER) return STRING is\n variable result : STRING (1 to 1);\n begin\n result (1) := VALUE;\n return result;\n end function TO_STRING;\n\n function MINIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : SEVERITY_LEVEL) return SEVERITY_LEVEL is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : SEVERITY_LEVEL) return STRING is\n begin\n return SEVERITY_LEVEL'image(VALUE);\n end function TO_STRING;\n\n function MINIMUM (L, R : INTEGER) return INTEGER is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : INTEGER) return INTEGER is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : INTEGER) return STRING is\n begin\n return INTEGER'image(VALUE);\n end function TO_STRING;\n\n function MINIMUM (L, R : REAL) return REAL is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : REAL) return REAL is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : REAL) return STRING is\n begin\n return REAL'image (VALUE);\n end function TO_STRING;\n\n function TO_STRING (VALUE : REAL; DIGITS : NATURAL) return STRING is\n begin\n return to_string (VALUE, \"%1.\" & INTEGER'image(DIGITS) & \"f\");\n end function TO_STRING;\n\n function \"mod\" (L, R : TIME) return TIME is\n variable lint, rint : INTEGER;\n begin\n lint := L / 1.0 ns;\n rint := R / 1.0 ns;\n return (lint mod rint) * 1.0 ns;\n end function \"mod\";\n\n function \"rem\" (L, R : TIME) return TIME is\n variable lint, rint : INTEGER;\n begin\n lint := L / 1.0 ns;\n rint := R / 1.0 ns;\n return (lint rem rint) * 1.0 ns;\n end function \"rem\";\n\n function MINIMUM (L, R : TIME) return TIME is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : TIME) return TIME is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : TIME) return STRING is\n begin\n return TIME'image (VALUE);\n end function TO_STRING;\n\n function MINIMUM (L, R : STRING) return STRING is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : STRING) return STRING is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function MINIMUM (L : STRING) return CHARACTER is\n variable result : CHARACTER := CHARACTER'high;\n begin\n for i in l'range loop\n result := minimum (l(i), result);\n end loop;\n return result;\n end function MINIMUM;\n\n function MAXIMUM (L : STRING) return CHARACTER is\n variable result : CHARACTER := CHARACTER'low;\n begin\n for i in l'range loop\n result := maximum (l(i), result);\n end loop;\n return result;\n end function MAXIMUM;\n\n -- type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;\n -- The predefined operations for this type are as follows:\n function \"and\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if (l'length /= r'length) then\n assert false\n report \"STD.\"\"and\"\": \"\n & \"arguments of overloaded 'and' operator are not of the same length\"\n severity failure;\n else\n for i in result'range loop\n result(i) := (lv(i) and rv(i));\n end loop;\n end if;\n return result;\n end function \"and\";\n\n function \"or\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if (l'length /= r'length) then\n assert false\n report \"STD.\"\"or\"\": \"\n & \"arguments of overloaded 'or' operator are not of the same length\"\n severity failure;\n else\n for i in result'range loop\n result(i) := (lv(i) or rv(i));\n end loop;\n end if;\n return result;\n end function \"or\";\n\n function \"nand\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if (l'length /= r'length) then\n assert false\n report \"STD.\"\"nand\"\": \"\n & \"arguments of overloaded 'nand' operator are not of the same length\"\n severity failure;\n else\n for i in result'range loop\n result(i) := (lv(i) nand rv(i));\n end loop;\n end if;\n return result;\n end function \"nand\";\n\n function \"nor\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if (l'length /= r'length) then\n assert false\n report \"STD.\"\"nor\"\": \"\n & \"arguments of overloaded 'nor' operator are not of the same length\"\n severity failure;\n else\n for i in result'range loop\n result(i) := (lv(i) nor rv(i));\n end loop;\n end if;\n return result;\n end function \"nor\";\n\n function \"xor\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if (l'length /= r'length) then\n assert false\n report \"STD.\"\"xor\"\": \"\n & \"arguments of overloaded 'xor' operator are not of the same length\"\n severity failure;\n else\n for i in result'range loop\n result(i) := (lv(i) xor rv(i));\n end loop;\n end if;\n return result;\n end function \"xor\";\n\n function \"xnor\" (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if (l'length /= r'length) then\n assert false\n report \"STD.\"\"xnor\"\": \"\n & \"arguments of overloaded 'xnor' operator are not of the same length\"\n severity failure;\n else\n for i in result'range loop\n result(i) := (lv(i) xnor rv(i));\n end loop;\n end if;\n return result;\n end function \"xnor\";\n\n function \"not\" (L : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := not (lv(i));\n end loop;\n return result;\n end function \"not\";\n\n function \"and\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) and r;\n end loop;\n return result;\n end function \"and\";\n\n function \"and\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR is\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l and rv(i);\n end loop;\n return result;\n end function \"and\";\n\n function \"or\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) or r;\n end loop;\n return result;\n end function \"or\";\n\n function \"or\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR is\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l or rv(i);\n end loop;\n return result;\n end function \"or\";\n\n function \"nand\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) nand r;\n end loop;\n return result;\n end function \"nand\";\n\n function \"nand\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR is\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l nand rv(i);\n end loop;\n return result;\n end function \"nand\";\n\n function \"nor\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) nor r;\n end loop;\n return result;\n end function \"nor\";\n\n function \"nor\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR is\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l nor rv(i);\n end loop;\n return result;\n end function \"nor\";\n\n function \"xor\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) xor r;\n end loop;\n return result;\n end function \"xor\";\n\n function \"xor\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR is\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l xor rv(i);\n end loop;\n return result;\n end function \"xor\";\n\n function \"xnor\" (L : BOOLEAN_VECTOR; R : BOOLEAN)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) xnor r;\n end loop;\n return result;\n end function \"xnor\";\n\n function \"xnor\" (L : BOOLEAN; R : BOOLEAN_VECTOR)\n return BOOLEAN_VECTOR is\n alias rv : BOOLEAN_VECTOR (1 to r'length) is r;\n variable result : BOOLEAN_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l xnor rv(i);\n end loop;\n return result;\n end function \"xnor\";\n\n function and_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := true;\n begin\n for i in l'reverse_range loop\n result := l(i) and result;\n end loop;\n return result;\n end function and_reduce;\n\n function or_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := false;\n begin\n for i in l'reverse_range loop\n result := l(i) or result;\n end loop;\n return result;\n end function or_reduce;\n\n function nand_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := true;\n begin\n for i in l'reverse_range loop\n result := l(i) and result;\n end loop;\n return not result;\n end function nand_reduce;\n\n function nor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := false;\n begin\n for i in l'reverse_range loop\n result := l(i) or result;\n end loop;\n return not result;\n end function nor_reduce;\n\n function xor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := false;\n begin\n for i in l'reverse_range loop\n result := l(i) xor result;\n end loop;\n return result;\n end function xor_reduce;\n\n function xnor_reduce (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := false;\n begin\n for i in l'reverse_range loop\n result := l(i) xor result;\n end loop;\n return not result;\n end function xnor_reduce;\n\n function \"sll\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if r >= 0 then\n result(1 to l'length - r) := lv(r + 1 to l'length);\n else\n result := l srl -r;\n end if;\n return result;\n end function \"sll\";\n\n function \"srl\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n if r >= 0 then\n result(r + 1 to l'length) := lv(1 to l'length - r);\n else\n result := l sll -r;\n end if;\n return result;\n end function \"srl\";\n\n function \"sla\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in L'range loop\n result (i) := L(L'high);\n end loop;\n if r >= 0 then\n result(1 to l'length - r) := lv(r + 1 to l'length);\n else\n result := l sra -r;\n end if;\n return result;\n end function \"sla\";\n\n function \"sra\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n begin\n for i in L'range loop\n result (i) := L(L'low);\n end loop;\n if r >= 0 then\n result(1 to l'length - r) := lv(r + 1 to l'length);\n else\n result := l sra -r;\n end if;\n return result;\n end function \"sra\";\n\n function \"rol\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n constant rm : INTEGER := r mod l'length;\n begin\n if r >= 0 then\n result(1 to l'length - rm) := lv(rm + 1 to l'length);\n result(l'length - rm + 1 to l'length) := lv(1 to rm);\n else\n result := l ror -r;\n end if;\n return result;\n end function \"rol\";\n\n function \"ror\" (L : BOOLEAN_VECTOR; R : INTEGER)\n return BOOLEAN_VECTOR is\n alias lv : BOOLEAN_VECTOR (1 to l'length) is l;\n variable result : BOOLEAN_VECTOR (1 to l'length);\n constant rm : INTEGER := r mod l'length;\n begin\n if r >= 0 then\n result(rm + 1 to l'length) := lv(1 to l'length - rm);\n result(1 to rm) := lv(l'length - rm + 1 to l'length);\n else\n result := l rol -r;\n end if;\n return result;\n end function \"ror\";\n-- function \"=\" (L, R: BOOLEAN_VECTOR) return BOOLEAN;\n-- function \"/=\" (L, R: BOOLEAN_VECTOR) return BOOLEAN;\n-- function \"<\" (L, R: BOOLEAN_VECTOR) return BOOLEAN;\n-- function \"<=\" (L, R: BOOLEAN_VECTOR) return BOOLEAN;\n-- function \">\" (L, R: BOOLEAN_VECTOR) return BOOLEAN;\n-- function \">=\" (L, R: BOOLEAN_VECTOR) return BOOLEAN;\n\n function \\?=\\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is\n begin\n return L = R;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : BOOLEAN_VECTOR) return BOOLEAN is\n begin\n return L /= R;\n end function \\?/=\\;\n-- function \"&\" (L: BOOLEAN_VECTOR; R: BOOLEAN_VECTOR)\n-- return BOOLEAN_VECTOR;\n-- function \"&\" (L: BOOLEAN_VECTOR; R: BOOLEAN) return BOOLEAN_VECTOR;\n-- function \"&\" (L: BOOLEAN; R: BOOLEAN_VECTOR) return BOOLEAN_VECTOR;\n-- function \"&\" (L: BOOLEAN; R: BOOLEAN) return BOOLEAN_VECTOR;\n\n function MINIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : BOOLEAN_VECTOR) return BOOLEAN_VECTOR is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function MINIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := BOOLEAN'high;\n begin\n for i in l'range loop\n result := minimum (l(i), result);\n end loop;\n return result;\n end function MINIMUM;\n\n function MAXIMUM (L : BOOLEAN_VECTOR) return BOOLEAN is\n variable result : BOOLEAN := BOOLEAN'low;\n begin\n for i in l'range loop\n result := maximum (l(i), result);\n end loop;\n return result;\n end function MAXIMUM;\n\n function \"and\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is\n alias lv : BIT_VECTOR (1 to l'length) is l;\n variable result : BIT_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) and r;\n end loop;\n return result;\n end function \"and\";\n\n function \"and\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is\n alias rv : BIT_VECTOR (1 to r'length) is r;\n variable result : BIT_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l and rv(i);\n end loop;\n return result;\n end function \"and\";\n\n function \"or\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is\n alias lv : BIT_VECTOR (1 to l'length) is l;\n variable result : BIT_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) or r;\n end loop;\n return result;\n end function \"or\";\n\n function \"or\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is\n alias rv : BIT_VECTOR (1 to r'length) is r;\n variable result : BIT_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l or rv(i);\n end loop;\n return result;\n end function \"or\";\n\n function \"nand\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is\n alias lv : BIT_VECTOR (1 to l'length) is l;\n variable result : BIT_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) and r;\n end loop;\n return not result;\n end function \"nand\";\n\n function \"nand\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is\n alias rv : BIT_VECTOR (1 to r'length) is r;\n variable result : BIT_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l and rv(i);\n end loop;\n return not result;\n end function \"nand\";\n\n function \"nor\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is\n alias lv : BIT_VECTOR (1 to l'length) is l;\n variable result : BIT_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) or r;\n end loop;\n return not result;\n end function \"nor\";\n\n function \"nor\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is\n alias rv : BIT_VECTOR (1 to r'length) is r;\n variable result : BIT_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l or rv(i);\n end loop;\n return not result;\n end function \"nor\";\n\n function \"xor\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is\n alias lv : BIT_VECTOR (1 to l'length) is l;\n variable result : BIT_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) xor r;\n end loop;\n return result;\n end function \"xor\";\n\n function \"xor\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is\n alias rv : BIT_VECTOR (1 to r'length) is r;\n variable result : BIT_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l xor rv(i);\n end loop;\n return result;\n end function \"xor\";\n\n function \"xnor\" (L : BIT_VECTOR; R : BIT) return BIT_VECTOR is\n alias lv : BIT_VECTOR (1 to l'length) is l;\n variable result : BIT_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := lv(i) xor r;\n end loop;\n return not result;\n end function \"xnor\";\n\n function \"xnor\" (L : BIT; R : BIT_VECTOR) return BIT_VECTOR is\n alias rv : BIT_VECTOR (1 to r'length) is r;\n variable result : BIT_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := l xor rv(i);\n end loop;\n return not result;\n end function \"xnor\";\n\n function and_reduce (L : BIT_VECTOR) return BIT is\n variable result : BIT := '1';\n begin\n for i in l'reverse_range loop\n result := l(i) and result;\n end loop;\n return result;\n end function and_reduce;\n\n function or_reduce (L : BIT_VECTOR) return BIT is\n variable result : BIT := '0';\n begin\n for i in l'reverse_range loop\n result := l(i) or result;\n end loop;\n return result;\n end function or_reduce;\n\n function nand_reduce (L : BIT_VECTOR) return BIT is\n variable result : BIT := '1';\n begin\n for i in l'reverse_range loop\n result := l(i) and result;\n end loop;\n return not result;\n end function nand_reduce;\n\n function nor_reduce (L : BIT_VECTOR) return BIT is\n variable result : BIT := '0';\n begin\n for i in l'reverse_range loop\n result := l(i) or result;\n end loop;\n return not result;\n end function nor_reduce;\n\n function xor_reduce (L : BIT_VECTOR) return BIT is\n variable result : BIT := '0';\n begin\n for i in l'reverse_range loop\n result := l(i) xor result;\n end loop;\n return result;\n end function xor_reduce;\n\n function xnor_reduce (L : BIT_VECTOR) return BIT is\n variable result : BIT := '0';\n begin\n for i in l'reverse_range loop\n result := l(i) xor result;\n end loop;\n return not result;\n end function xnor_reduce;\n\n function \\?=\\ (L, R : BIT_VECTOR) return BIT is\n begin\n if L = R then\n return '1';\n else\n return '0';\n end if;\n end function \\?=\\;\n\n function \\?/=\\ (L, R : BIT_VECTOR) return BIT is\n begin\n if L /= R then\n return '1';\n else\n return '0';\n end if;\n end function \\?/=\\;\n\n function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function MINIMUM (L : BIT_VECTOR) return BIT is\n variable result : BIT := BIT'high;\n begin\n for i in l'range loop\n result := minimum (l(i), result);\n end loop;\n return result;\n end function MINIMUM;\n\n function MAXIMUM (L : BIT_VECTOR) return BIT is\n variable result : BIT := BIT'low;\n begin\n for i in l'range loop\n result := maximum (l(i), result);\n end loop;\n return result;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : BIT_VECTOR) return STRING is\n alias ivalue : BIT_VECTOR(1 to value'length) is value;\n variable result : STRING(1 to value'length);\n begin\n if value'length < 1 then\n return \"\";\n else\n for i in ivalue'range loop\n if iValue(i) = '0' then\n result(i) := '0';\n else\n result(i) := '1';\n end if;\n end loop;\n return result;\n end if;\n end function to_string;\n\n-- alias TO_BSTRING is TO_STRING [BIT_VECTOR return STRING];\n-- alias TO_BINARY_STRING is TO_STRING [BIT_VECTOR return STRING];\n\n function TO_OSTRING (VALUE : BIT_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+2)/3;\n constant pad : BIT_VECTOR(0 to (ne*3 - value'length) - 1) := (others => '0');\n variable ivalue : BIT_VECTOR(0 to ne*3 - 1);\n variable result : STRING(1 to ne);\n variable tri : BIT_VECTOR(0 to 2);\n begin\n if value'length < 1 then\n return \"\";\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n tri := ivalue(3*i to 3*i+2);\n case tri is\n when o\"0\" => result(i+1) := '0';\n when o\"1\" => result(i+1) := '1';\n when o\"2\" => result(i+1) := '2';\n when o\"3\" => result(i+1) := '3';\n when o\"4\" => result(i+1) := '4';\n when o\"5\" => result(i+1) := '5';\n when o\"6\" => result(i+1) := '6';\n when o\"7\" => result(i+1) := '7';\n end case;\n end loop;\n return result;\n end function to_ostring;\n-- alias TO_OCTAL_STRING is TO_OSTRING [BIT_VECTOR return STRING];\n\n function TO_HSTRING (VALUE : BIT_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+3)/4;\n constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1) := (others => '0');\n variable ivalue : BIT_VECTOR(0 to ne*4 - 1);\n variable result : STRING(1 to ne);\n variable quad : BIT_VECTOR(0 to 3);\n begin\n if value'length < 1 then\n return \"\";\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n quad := ivalue(4*i to 4*i+3);\n case quad is\n when x\"0\" => result(i+1) := '0';\n when x\"1\" => result(i+1) := '1';\n when x\"2\" => result(i+1) := '2';\n when x\"3\" => result(i+1) := '3';\n when x\"4\" => result(i+1) := '4';\n when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n when x\"7\" => result(i+1) := '7';\n when x\"8\" => result(i+1) := '8';\n when x\"9\" => result(i+1) := '9';\n when x\"A\" => result(i+1) := 'A';\n when x\"B\" => result(i+1) := 'B';\n when x\"C\" => result(i+1) := 'C';\n when x\"D\" => result(i+1) := 'D';\n when x\"E\" => result(i+1) := 'E';\n when x\"F\" => result(i+1) := 'F';\n end case;\n end loop;\n return result;\n end function to_hstring;\n-- alias TO_HEX_STRING is TO_HSTRING [BIT_VECTOR return STRING];\n\n-- type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;\n -- The predefined operations for this type are as follows:\n\n function \"=\" (L, R : INTEGER_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length or L'length < 1 or R'length < 1 then\n return false;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n return false;\n end if;\n end loop;\n return true;\n end if;\n end function \"=\";\n\n function \"/=\" (L, R : INTEGER_VECTOR) return BOOLEAN is\n begin\n return not (L = R);\n end function \"/=\";\n\n function \"<\" (L, R : INTEGER_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length < R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) < R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return false;\n end if;\n end function \"<\";\n\n function \"<=\" (L, R : INTEGER_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length < R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) < R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return true;\n end if;\n end function \"<=\";\n\n function \">\" (L, R : INTEGER_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length > R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) > R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return false;\n end if;\n end function \">\";\n\n function \">=\" (L, R : INTEGER_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length > R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) > R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return true;\n end if;\n end function \">=\";\n-- function \"&\" (L: INTEGER_VECTOR; R: INTEGER_VECTOR)\n-- return INTEGER_VECTOR;\n-- function \"&\" (L: INTEGER_VECTOR; R: INTEGER) return INTEGER_VECTOR;\n-- function \"&\" (L: INTEGER; R: INTEGER_VECTOR) return INTEGER_VECTOR;\n-- function \"&\" (L: INTEGER; R: INTEGER) return INTEGER_VECTOR;\n\n function MINIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : INTEGER_VECTOR) return INTEGER_VECTOR is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function MINIMUM (L : INTEGER_VECTOR) return INTEGER is\n variable result : INTEGER := INTEGER'high;\n begin\n for i in l'range loop\n result := minimum (l(i), result);\n end loop;\n return result;\n end function MINIMUM;\n\n function MAXIMUM (L : INTEGER_VECTOR) return INTEGER is\n variable result : INTEGER := INTEGER'low;\n begin\n for i in l'range loop\n result := maximum (l(i), result);\n end loop;\n return result;\n end function MAXIMUM;\n\n -- type REAL_VECTOR is array (NATURAL range <>) of REAL;\n -- The predefined operations for this type are as follows:\n function \"=\" (L, R : REAL_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length or L'length < 1 or R'length < 1 then\n return false;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n return false;\n end if;\n end loop;\n return true;\n end if;\n end function \"=\";\n\n function \"/=\" (L, R : REAL_VECTOR) return BOOLEAN is\n begin\n return not (L = R);\n end function \"/=\";\n\n function \"<\" (L, R : REAL_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length < R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) < R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return false;\n end if;\n end function \"<\";\n\n function \"<=\" (L, R : REAL_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length < R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) < R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return true;\n end if;\n end function \"<=\";\n\n function \">\" (L, R : REAL_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length > R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) > R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return false;\n end if;\n end function \">\";\n\n function \">=\" (L, R : REAL_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length > R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) > R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return true;\n end if;\n end function \">=\";\n-- function \"&\" (L: REAL_VECTOR; R: REAL_VECTOR)\n-- return REAL_VECTOR;\n-- function \"&\" (L: REAL_VECTOR; R: REAL) return REAL_VECTOR;\n-- function \"&\" (L: REAL; R: REAL_VECTOR) return REAL_VECTOR;\n-- function \"&\" (L: REAL; R: REAL) return REAL_VECTOR;\n\n function MINIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : REAL_VECTOR) return REAL_VECTOR is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function MINIMUM (L : REAL_VECTOR) return REAL is\n variable result : REAL := REAL'high;\n begin\n for i in l'range loop\n result := minimum (l(i), result);\n end loop;\n return result;\n end function MINIMUM;\n\n function MAXIMUM (L : REAL_VECTOR) return REAL is\n variable result : REAL := REAL'low;\n begin\n for i in l'range loop\n result := maximum (l(i), result);\n end loop;\n return result;\n end function MAXIMUM;\n\n -- type TIME_VECTOR is array (NATURAL range <>) of TIME;\n -- The predefined implicit operations for this type are as follows:\n function \"=\" (L, R : TIME_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length or L'length < 1 or R'length < 1 then\n return false;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n return false;\n end if;\n end loop;\n return true;\n end if;\n end function \"=\";\n\n function \"/=\" (L, R : TIME_VECTOR) return BOOLEAN is\n begin\n return not (L = R);\n end function \"/=\";\n\n function \"<\" (L, R : TIME_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length < R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) < R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return false;\n end if;\n end function \"<\";\n\n function \"<=\" (L, R : TIME_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length < R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) < R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return true;\n end if;\n end function \"<=\";\n\n function \">\" (L, R : TIME_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length > R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) > R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return false;\n end if;\n end function \">\";\n\n function \">=\" (L, R : TIME_VECTOR) return BOOLEAN is\n begin\n if L'length /= R'length then\n return L'length > R'length;\n else\n for i in l'range loop\n if L(i) /= R(i) then\n if L(i) > R(i) then\n return true;\n else\n return false;\n end if;\n end if;\n end loop;\n return true;\n end if;\n end function \">=\";\n-- function \"&\" (L: TIME_VECTOR; R: TIME_VECTOR)\n-- return TIME_VECTOR;\n-- function \"&\" (L: TIME_VECTOR; R: TIME) return TIME_VECTOR;\n-- function \"&\" (L: TIME; R: TIME_VECTOR) return TIME_VECTOR;\n-- function \"&\" (L: TIME; R: TIME) return TIME_VECTOR;\n\n function MINIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : TIME_VECTOR) return TIME_VECTOR is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function MINIMUM (L : TIME_VECTOR) return TIME is\n variable result : TIME := TIME'high;\n begin\n for i in l'range loop\n result := minimum (l(i), result);\n end loop;\n return result;\n end function MINIMUM;\n\n function MAXIMUM (L : TIME_VECTOR) return TIME is\n variable result : TIME := TIME'low;\n begin\n for i in l'range loop\n result := maximum (l(i), result);\n end loop;\n return result;\n end function MAXIMUM;\n\n function MINIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : FILE_OPEN_KIND) return FILE_OPEN_KIND is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : FILE_OPEN_KIND) return STRING is\n begin\n return FILE_OPEN_KIND'image(VALUE);\n end function TO_STRING;\n\n function MINIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function MINIMUM;\n\n function MAXIMUM (L, R : FILE_OPEN_STATUS) return FILE_OPEN_STATUS is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function MAXIMUM;\n\n function TO_STRING (VALUE : FILE_OPEN_STATUS) return STRING is\n begin\n return FILE_OPEN_STATUS'image(VALUE);\n end function TO_STRING;\n\n -- USED INTERNALLY!\n function justify (\n value : in STRING;\n justified : in SIDE := right;\n field : in width := 0)\n return STRING is\n constant VAL_LEN : INTEGER := value'length;\n variable result : STRING (1 to field) := (others => ' ');\n begin -- function justify\n -- return value if field is too small\n if VAL_LEN >= field then\n return value;\n end if;\n if justified = left then\n result(1 to VAL_LEN) := value;\n elsif justified = right then\n result(field - VAL_LEN + 1 to field) := value;\n end if;\n return result;\n end function justify;\n\n function TO_STRING (VALUE : TIME; UNIT : TIME) return STRING is\n variable L : LINE; -- pointer\n begin\n deallocate (L);\n write (L => L,\n VALUE => VALUE,\n UNIT => UNIT);\n return L.all;\n end function to_string;\n\n function TO_STRING (VALUE : REAL; FORMAT : STRING) return STRING is\n constant czero : CHARACTER := '0'; -- zero\n constant half : REAL := 0.4999999999; -- almost 0.5\n -- Log10 funciton\n function log10 (arg : REAL) return INTEGER is\n variable i : INTEGER := 1;\n begin\n if ((arg = 0.0)) then\n return 0;\n elsif arg >= 1.0 then\n while arg >= 10.0**i loop\n i := i + 1;\n end loop;\n return (i-1);\n else\n while arg < 10.0**i loop\n i := i - 1;\n end loop;\n return i;\n end if;\n end function log10;\n -- purpose: writes a fractional real number into a line\n procedure writefrc (\n variable L : inout LINE; -- LINE\n variable cdes : in CHARACTER;\n variable precision : in INTEGER; -- number of decimal places\n variable value : in REAL) is -- real value\n variable rvar : REAL; -- temp variable\n variable xint : INTEGER;\n variable xreal : REAL;\n begin\n xreal := (10.0**(-precision));\n write (L, '.');\n rvar := value;\n for i in 1 to precision loop\n rvar := rvar * 10.0;\n xint := INTEGER(rvar-0.49999999999); -- round\n write (L, xint);\n rvar := rvar - REAL(xint);\n xreal := xreal * 10.0;\n if (cdes = 'g') and (rvar < xreal) then\n exit;\n end if;\n end loop;\n end procedure writefrc;\n -- purpose: replace the \".\" with a \"@\", and \"e\" with \"j\" to get around\n -- read (\"6.\") and read (\"2e\") issues.\n function subdot (\n constant format : STRING)\n return STRING is\n variable result : STRING (format'range);\n begin\n for i in format'range loop\n if (format(i) = '.') then\n result(i) := '@'; -- Because the parser reads 6.2 as REAL\n elsif (format(i) = 'e') then\n result(i) := 'j'; -- Because the parser read 2e as REAL\n elsif (format(i) = 'E') then\n result(i) := 'J'; -- Because the parser reads 2E as REAL\n else\n result(i) := format(i);\n end if;\n end loop;\n return result;\n end function subdot;\n -- purpose: find a . in a STRING\n function isdot (\n constant format : STRING)\n return BOOLEAN is\n begin\n for i in format'range loop\n if (format(i) = '@') then\n return true;\n end if;\n end loop;\n return false;\n end function isdot;\n variable exp : INTEGER; -- integer version of baseexp\n variable bvalue : REAL; -- base value\n variable roundvar, tvar : REAL; -- Rounding values\n variable frcptr : INTEGER; -- integer version of number\n variable fwidth, dwidth : INTEGER; -- field width and decimal width\n variable dash, dot : BOOLEAN := false;\n variable cdes, ddes : CHARACTER := ' ';\n variable L : LINE; -- line type\n begin\n -- Perform the same function that \"printf\" does\n -- examples \"%6.2f\" \"%-7e\" \"%g\"\n if not (format(format'left) = '%') then\n report \"to_string: Illegal format string \"\"\" & format & '\"'\n severity error;\n return \"\";\n end if;\n L := new STRING'(subdot(format));\n read (L, ddes); -- toss the '%'\n case L.all(1) is\n when '-' => dash := true;\n when '@' => dash := true; -- in FP, a \"-\" and a \".\" are the same\n when 'f' => cdes := 'f';\n when 'F' => cdes := 'F';\n when 'g' => cdes := 'g';\n when 'G' => cdes := 'G';\n when 'j' => cdes := 'e'; -- parser reads 5e as real, thus we sub j\n when 'J' => cdes := 'E';\n when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|'8'|'9' => null;\n when others =>\n report \"to_string: Illegal format string \"\"\" & format & '\"'\n severity error;\n return \"\";\n end case;\n if (dash or (cdes /= ' ')) then\n read (L, ddes); -- toss the next character\n end if;\n if (cdes = ' ') then\n if (isdot(L.all)) then -- if you see a . two numbers\n read (L, fwidth); -- read field width\n read (L, ddes); -- toss the next character .\n read (L, dwidth); -- read decimal width \n else\n read (L, fwidth); -- read field width\n dwidth := 6; -- the default decimal width is 6\n end if;\n read (L, cdes);\n if (cdes = 'j') then\n cdes := 'e'; -- because 2e reads as \"REAL\".\n elsif (cdes = 'J') then\n cdes := 'E';\n end if;\n else\n if (cdes = 'E' or cdes = 'e') then\n fwidth := 10; -- default for e and E is %10.6e\n else\n fwidth := 0; -- default for f and g is %0.6f\n end if;\n dwidth := 6;\n end if;\n deallocate (L); -- reclame the pointer L.\n-- assert (not debug) report \"Format: \" & format & \" \"\n-- & INTEGER'image(fwidth) & \".\" & INTEGER'image(dwidth) & cdes\n-- severity note;\n if (not (cdes = 'f' or cdes = 'F' or cdes = 'g' or cdes = 'G'\n or cdes = 'e' or cdes = 'E')) then\n report \"to_string: Illegal format \"\"\" & format & '\"' severity error; \n return \"\";\n end if;\n if (VALUE < 0.0) then\n bvalue := -value;\n write (L, '-');\n else\n bvalue := value;\n end if;\n case cdes is\n when 'e' | 'E' => -- 7.000E+01\n exp := log10(bvalue);\n roundvar := half*(10.0**(exp-dwidth));\n bvalue := bvalue + roundvar; -- round\n exp := log10(bvalue); -- because we CAN overflow\n bvalue := bvalue * (10.0**(-exp)); -- result is D.XXXXXX\n frcptr := INTEGER(bvalue-half); -- Write a single digit.\n write (L, frcptr);\n bvalue := bvalue - REAL(frcptr);\n writefrc (-- Write out the fraction\n L => L,\n cdes => cdes,\n precision => dwidth,\n value => bvalue);\n write (L, cdes); -- e or E\n if (exp < 0) then\n write (L, '-');\n else\n write (L, '+');\n end if;\n exp := abs(exp);\n if (exp < 10) then -- we need another \"0\".\n write (L, czero);\n end if;\n write (L, exp);\n when 'f' | 'F' => -- 70.0\n exp := log10(bvalue);\n roundvar := half*(10.0**(-dwidth));\n bvalue := bvalue + roundvar; -- round\n exp := log10(bvalue); -- because we CAN overflow\n if (exp < 0) then -- 0.X case\n write (L, czero);\n else -- loop because real'high > integer'high\n while (exp >= 0) loop\n frcptr := INTEGER(bvalue * (10.0**(-exp)) - half);\n write (L, frcptr);\n bvalue := bvalue - (REAL(frcptr) * (10.0**exp));\n exp := exp-1;\n end loop;\n end if;\n writefrc (\n L => L,\n cdes => cdes,\n precision => dwidth,\n value => bvalue);\n when 'g' | 'G' => -- 70\n exp := log10(bvalue);\n roundvar := half*(10.0**(exp-dwidth)); -- small number\n bvalue := bvalue + roundvar; -- round\n exp := log10(bvalue); -- because we CAN overflow\n frcptr := INTEGER(bvalue-half);\n tvar := bvalue-roundvar - REAL(frcptr); -- even smaller number\n if (exp < dwidth)\n", "right_context": " if (bvalue > (10.0**(1-dwidth))) then\n dwidth := dwidth - 1;\n writefrc (\n L => L,\n cdes => cdes,\n precision => dwidth,\n value => bvalue);\n end if;\n if (cdes = 'G') then\n write (L, 'E');\n else\n write (L, 'e');\n end if;\n if (exp < 0) then\n write (L, '-');\n else\n write (L, '+');\n end if;\n exp := abs(exp);\n if (exp < 10) then\n write (L, czero);\n end if;\n write (L, exp);\n else\n -- in \"f\" format (modified)\n if (exp < 0) then\n write (L, czero);\n dwidth := maximum (dwidth, 4); -- if exp < -4 or > precision.\n bvalue := bvalue - roundvar; -- recalculate rounding\n roundvar := half*(10.0**(-dwidth));\n bvalue := bvalue + roundvar;\n else\n write (L, frcptr); -- integer part (always small)\n bvalue := bvalue - (REAL(frcptr));\n dwidth := dwidth - exp - 1;\n end if;\n if (bvalue > roundvar) then\n writefrc (\n L => L,\n cdes => cdes,\n precision => dwidth,\n value => bvalue);\n end if;\n end if;\n when others => return \"\";\n end case;\n -- You don't truncate real numbers.\n-- if (dot) then -- truncate\n-- if (L.all'length > fwidth) then\n-- return justify (value => L.all (1 to fwidth),\n-- justified => RIGHT,\n-- field => fwidth); \n-- else\n-- return justify (value => L.all,\n-- justified => RIGHT,\n-- field => fwidth); \n-- end if;\n if (dash) then -- fill to fwidth\n return justify (value => L.all,\n justified => left,\n field => fwidth);\n else\n return justify (value => L.all,\n justified => right,\n field => fwidth);\n end if;\n end function to_string;\n\nend package body standard_additions;\n", "groundtruth": " and (tvar < roundvar and tvar > -roundvar) then\n-- and ((bvalue-roundvar) = real(frcptr)) then\n write (L, frcptr); -- Just a short integer, write it.\n elsif (exp >= dwidth) or (exp < -4) then\n -- in \"e\" format (modified)\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/standard_textio_additions_c.vhdl", "left_context": "------------------------------------------------------------------------------\n-- \"standard_textio_additions\" package contains the additions to the built in\n-- \"standard.textio\" package.\n-- This package should be compiled into \"ieee_proposed\" and used as follows:\n-- use ieee_proposed.standard_textio_additions.all;\n-- Last Modified: $Date: 2007-03-13 14:25:58-04 $\n-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007-03-13 14:25:58-04 l435385 Exp $\n--\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n------------------------------------------------------------------------------\nuse std.textio.all;\npackage standard_textio_additions is\n\n-- procedure DEALLOCATE (P : inout LINE);\n\n procedure FLUSH (file F : TEXT);\n\n function MINIMUM (L, R : SIDE) return SIDE;\n function MAXIMUM (L, R : SIDE) return SIDE;\n\n function TO_STRING (VALUE : SIDE) return STRING;\n\n function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;\n\n procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);\n alias STRING_READ is SREAD [LINE, STRING, NATURAL];\n alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];\n alias BREAD is READ [LINE, BIT_VECTOR];\n alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];\n alias BINARY_READ is READ [LINE, BIT_VECTOR];\n procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);\n procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);\n alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];\n procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);\n procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);\n alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];\n alias HEX_READ is HREAD [LINE, BIT_VECTOR];\n procedure TEE (file F : TEXT; L : inout LINE);\n procedure WRITE (L : inout LINE; VALUE : in REAL;\n FORMAT : in STRING);\n alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];\n alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];\n alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];\n alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];\n procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];\n procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];\n\nend package standard_textio_additions;\n\nlibrary ieee_proposed;\nuse ieee_proposed.standard_additions.all;\n\npackage body standard_textio_additions is\n-- pragma synthesis_off\n constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array\n constant NBSP : CHARACTER := CHARACTER'val(160); -- space character\n\n -- Writes L to a file without modifying the contents of the line\n procedure TEE (file F : TEXT; L : inout LINE) is\n begin\n write (OUTPUT, L.all & LF);\n writeline(F, L);\n end procedure TEE;\n\n procedure FLUSH (file F: TEXT) is -- Implicit\n begin\n file_close (F);\n end procedure FLUSH;\n\n -- Read and Write procedure for strings\n procedure SREAD (L : inout LINE;\n VALUE : out STRING;\n STRLEN : out natural) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n -- Result is padded with space characters\n variable result : STRING (1 to VALUE'length) := (others => ' ');\n begin\n VALUE := result;\n loop -- skip white space\n read(L, c, ok);\n exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));\n end loop;\n -- Bail out if there was a bad read\n if not ok then\n STRLEN := 0;\n return;\n end if;\n result (1) := c;\n STRLEN := 1;\n for i in 2 to VALUE'length loop\n read(L, c, ok);\n if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then\n exit;\n else\n result (i) := c;\n end if;\n STRLEN := i;\n end loop;\n VALUE := result;\n end procedure SREAD;\n\n -- Hex Read and Write procedures for bit_vector.\n -- Procedure only visible internally.\n procedure Char2QuadBits (C : CHARACTER;\n RESULT : out BIT_VECTOR(3 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := x\"0\"; good := true;\n when '1' => result := x\"1\"; good := true;\n when '2' => result := x\"2\"; good := true;\n when '3' => result := x\"3\"; good := true;\n when '4' => result := x\"4\"; good := true;\n when '5' => result := x\"5\"; good := true;\n", "right_context": " when 'F' | 'f' => result := x\"F\"; good := true;\n when others =>\n assert not ISSUE_ERROR report\n \"TEXTIO.HREAD Error: Read a '\" & c &\n \"', expected a Hex character (0-F).\" severity error;\n GOOD := false;\n end case;\n end procedure Char2QuadBits;\n\n procedure HREAD (L : inout LINE;\n VALUE : out BIT_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');\n variable s : STRING(1 to ne-1);\n begin\n VALUE := (VALUE'range => '0');\n loop -- skip white space\n read(l, c, ok);\n exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));\n end loop;\n -- Bail out if there was a bad read\n if not ok then\n GOOD := false;\n return;\n end if;\n Char2QuadBits(c, sv(0 to 3), ok, false);\n if not ok then\n GOOD := false;\n return;\n end if;\n read(L, s, ok);\n if not ok then\n GOOD := false;\n return;\n end if;\n for i in 1 to ne-1 loop\n Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);\n if not ok then\n GOOD := false;\n return;\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then\n GOOD := false; -- vector was truncated.\n else\n GOOD := true;\n VALUE := sv (pad to sv'high);\n end if;\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE;\n VALUE : out BIT_VECTOR) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');\n variable s : STRING(1 to ne-1);\n begin\n VALUE := (VALUE'range => '0');\n loop -- skip white space\n read(l, c, ok);\n exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));\n end loop;\n -- Bail out if there was a bad read\n if not ok then\n report \"TEXTIO.HREAD Error: Failed skipping white space\"\n severity error;\n return;\n end if;\n Char2QuadBits(c, sv(0 to 3), ok, true);\n if not ok then\n return;\n end if;\n read(L, s, ok);\n if not ok then\n report \"TEXTIO.HREAD Error: Failed to read the STRING\"\n severity error;\n return;\n end if;\n for i in 1 to ne-1 loop\n Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);\n if not ok then\n return;\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then\n report \"TEXTIO.HREAD Error: Vector truncated\"\n severity error;\n else\n VALUE := sv (pad to sv'high);\n end if;\n end procedure HREAD;\n\n procedure HWRITE (L : inout LINE;\n VALUE : in BIT_VECTOR;\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n begin\n write (L => L,\n VALUE => to_hstring(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure HWRITE;\n\n -- Procedure only visible internally.\n procedure Char2TriBits (C : CHARACTER;\n RESULT : out BIT_VECTOR(2 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n when '4' => result := o\"4\"; good := true;\n when '5' => result := o\"5\"; good := true;\n when '6' => result := o\"6\"; good := true;\n when '7' => result := o\"7\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report\n \"TEXTIO.OREAD Error: Read a '\" & c &\n \"', expected an Octal character (0-7).\"\n severity error;\n GOOD := false;\n end case;\n end procedure Char2TriBits;\n\n -- Read and Write procedures for Octal values\n procedure OREAD (L : inout LINE;\n VALUE : out BIT_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');\n variable s : STRING(1 to ne-1);\n begin\n VALUE := (VALUE'range => '0');\n loop -- skip white space\n read(l, c, ok);\n exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));\n end loop;\n -- Bail out if there was a bad read\n if not ok then\n GOOD := false;\n return;\n end if;\n Char2TriBits(c, sv(0 to 2), ok, false);\n if not ok then\n GOOD := false;\n return;\n end if;\n read(L, s, ok);\n if not ok then\n GOOD := false;\n return;\n end if;\n for i in 1 to ne-1 loop\n Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);\n if not ok then\n GOOD := false;\n return;\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then\n GOOD := false; -- vector was truncated.\n else\n GOOD := true;\n VALUE := sv (pad to sv'high);\n end if;\n end procedure OREAD;\n\n procedure OREAD (L : inout LINE;\n VALUE : out BIT_VECTOR) is\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');\n variable s : STRING(1 to ne-1);\n begin\n VALUE := (VALUE'range => '0');\n loop -- skip white space\n read(l, c, ok);\n exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));\n end loop;\n -- Bail out if there was a bad read\n if not ok then\n report \"TEXTIO.OREAD Error: Failed skipping white space\"\n severity error;\n return;\n end if;\n Char2TriBits(c, sv(0 to 2), ok, true);\n if not ok then\n return;\n end if;\n read(L, s, ok);\n if not ok then\n report \"TEXTIO.OREAD Error: Failed to read the STRING\"\n severity error;\n return;\n end if;\n for i in 1 to ne-1 loop\n Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);\n if not ok then\n return;\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then\n report \"TEXTIO.OREAD Error: Vector truncated\"\n severity error;\n else\n VALUE := sv (pad to sv'high);\n end if;\n end procedure OREAD;\n\n procedure OWRITE (L : inout LINE;\n VALUE : in BIT_VECTOR;\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n begin\n write (L => L,\n VALUE => to_ostring(VALUE),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n end procedure OWRITE;\n\n -- read and write for vector versions\n -- These versions produce \"value1, value2, value3 ....\"\n procedure read (L : inout LINE;\n VALUE : out boolean_vector;\n GOOD : out BOOLEAN) is\n variable dummy : CHARACTER;\n variable igood : BOOLEAN := true;\n begin\n for i in VALUE'range loop\n read (L => L,\n VALUE => VALUE(i),\n GOOD => igood);\n if (igood) and (i /= value'right) then\n read (L => L,\n VALUE => dummy, -- Toss the comma or seperator\n good => igood);\n end if;\n if (not igood) then\n good := false;\n return;\n end if;\n end loop;\n good := true;\n end procedure read;\n\n procedure read (L : inout LINE;\n VALUE : out boolean_vector) is\n variable dummy : CHARACTER;\n variable igood : BOOLEAN;\n begin\n for i in VALUE'range loop\n read (L => L,\n VALUE => VALUE(i),\n good => igood);\n if (igood) and (i /= value'right) then\n read (L => L,\n VALUE => dummy, -- Toss the comma or seperator\n good => igood);\n end if;\n if (not igood) then\n report \"STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) \"\n & \"Read error ecounted during vector read\" severity error;\n return;\n end if;\n end loop;\n end procedure read;\n\n procedure write (L : inout LINE;\n VALUE : in boolean_vector;\n JUSTIFIED : in SIDE := right;\n FIELD : in WIDTH := 0) is\n begin\n for i in VALUE'range loop\n write (L => L,\n VALUE => VALUE(i),\n JUSTIFIED => JUSTIFIED,\n FIELD => FIELD);\n if (i /= value'right) then\n swrite (L, \", \");\n end if;\n end loop;\n end procedure write;\n\n procedure WRITE (L: inout LINE; VALUE: in REAL;\n FORMAT: in STRING) is\n begin\n swrite ( L => L,\n VALUE => to_string (VALUE, FORMAT));\n end procedure WRITE;\n\n function justify (\n value : STRING;\n justified : SIDE := right;\n field : width := 0)\n return STRING is\n constant VAL_LEN : INTEGER := value'length;\n variable result : STRING (1 to field) := (others => ' ');\n begin -- function justify\n -- return value if field is too small\n if VAL_LEN >= field then\n return value;\n end if;\n if justified = left then\n result(1 to VAL_LEN) := value;\n elsif justified = right then\n result(field - VAL_LEN + 1 to field) := value;\n end if;\n return result;\n end function justify;\n\n function to_string (\n VALUE : SIDE) return STRING is\n begin\n return SIDE'image(VALUE);\n end function to_string;\n\n -- pragma synthesis_on\n -- Will be implicit\n function minimum (L, R : SIDE) return SIDE is\n begin\n if L > R then return R;\n else return L;\n end if;\n end function minimum;\n\n function maximum (L, R : SIDE) return SIDE is\n begin\n if L > R then return L;\n else return R;\n end if;\n end function maximum;\n\nend package body standard_textio_additions;\n", "groundtruth": " when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/std_logic_1164_additions.vhdl", "left_context": "------------------------------------------------------------------------------\n-- \"std_logic_1164_additions\" package contains the additions to the standard\n-- \"std_logic_1164\" package proposed by the VHDL-200X-ft working group.\n-- This package should be compiled into \"ieee_proposed\" and used as follows:\n-- use ieee.std_logic_1164.all;\n-- use ieee_proposed.std_logic_1164_additions.all;\n-- Last Modified: $Date: 2007-09-11 14:52:13-04 $\n-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.12 2007-09-11 14:52:13-04 l435385 Exp $\n--\n-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)\n------------------------------------------------------------------------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse std.textio.all;\npackage std_logic_1164_additions is\n\n -- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved\n -- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which\n -- take inputs in STD_LOGIC_VECTOR.\n -- For compatability with VHDL-2002, I have replicated all of these funcitons\n -- here for STD_LOGIC_VECTOR.\n -- new aliases\n alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];\n alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];\n alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];\n alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];\n alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];\n alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];\n alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];\n alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];\n alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];\n alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];\n alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];\n alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];\n\n function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC_VECTOR;\n function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC;\n function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC_VECTOR;\n function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC;\n\n ------------------------------------------------------------------- \n -- overloaded shift operators\n ------------------------------------------------------------------- \n\n function \"sll\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;\n function \"sll\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;\n\n function \"srl\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;\n function \"srl\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;\n\n function \"rol\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;\n function \"rol\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;\n\n function \"ror\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;\n function \"ror\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;\n -------------------------------------------------------------------\n -- vector/scalar overloaded logical operators\n -------------------------------------------------------------------\n function \"and\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;\n function \"and\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n function \"and\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function \"and\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n function \"nand\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;\n function \"nand\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n function \"nand\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function \"nand\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n function \"or\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;\n function \"or\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n function \"or\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function \"or\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n function \"nor\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;\n function \"nor\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n function \"nor\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function \"nor\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n function \"xor\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;\n function \"xor\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n function \"xor\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function \"xor\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n function \"xnor\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;\n function \"xnor\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;\n function \"xnor\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function \"xnor\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n\n -------------------------------------------------------------------\n -- vector-reduction functions.\n -- \"and\" functions default to \"1\", or defaults to \"0\"\n -------------------------------------------------------------------\n -----------------------------------------------------------------------------\n -- %%% Replace the \"_reduce\" functions with the ones commented out below.\n -----------------------------------------------------------------------------\n -- function \"and\" ( l : std_logic_vector ) RETURN std_ulogic;\n -- function \"and\" ( l : std_ulogic_vector ) RETURN std_ulogic; \n -- function \"nand\" ( l : std_logic_vector ) RETURN std_ulogic;\n -- function \"nand\" ( l : std_ulogic_vector ) RETURN std_ulogic;\n -- function \"or\" ( l : std_logic_vector ) RETURN std_ulogic;\n -- function \"or\" ( l : std_ulogic_vector ) RETURN std_ulogic;\n -- function \"nor\" ( l : std_logic_vector ) RETURN std_ulogic;\n -- function \"nor\" ( l : std_ulogic_vector ) RETURN std_ulogic;\n -- function \"xor\" ( l : std_logic_vector ) RETURN std_ulogic;\n -- function \"xor\" ( l : std_ulogic_vector ) RETURN std_ulogic;\n -- function \"xnor\" ( l : std_logic_vector ) RETURN std_ulogic;\n -- function \"xnor\" ( l : std_ulogic_vector ) RETURN std_ulogic;\n function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n -------------------------------------------------------------------\n -- ?= operators, same functionality as 1076.3 1994 std_match\n -------------------------------------------------------------------\n-- FUNCTION \"?=\" ( l, r : std_ulogic ) RETURN std_ulogic;\n-- FUNCTION \"?=\" ( l, r : std_logic_vector ) RETURN std_ulogic;\n-- FUNCTION \"?=\" ( l, r : std_ulogic_vector ) RETURN std_ulogic;\n-- FUNCTION \"?/=\" ( l, r : std_ulogic ) RETURN std_ulogic;\n-- FUNCTION \"?/=\" ( l, r : std_logic_vector ) RETURN std_ulogic;\n-- FUNCTION \"?/=\" ( l, r : std_ulogic_vector ) RETURN std_ulogic;\n-- FUNCTION \"?>\" ( l, r : std_ulogic ) RETURN std_ulogic;\n-- FUNCTION \"?>=\" ( l, r : std_ulogic ) RETURN std_ulogic;\n-- FUNCTION \"?<\" ( l, r : std_ulogic ) RETURN std_ulogic;\n-- FUNCTION \"?<=\" ( l, r : std_ulogic ) RETURN std_ulogic;\n\n function \\?=\\ (l, r : STD_ULOGIC) return STD_ULOGIC;\n function \\?=\\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function \\?=\\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n function \\?/=\\ (l, r : STD_ULOGIC) return STD_ULOGIC;\n function \\?/=\\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;\n function \\?/=\\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;\n function \\?>\\ (l, r : STD_ULOGIC) return STD_ULOGIC;\n function \\?>=\\ (l, r : STD_ULOGIC) return STD_ULOGIC;\n function \\?<\\ (l, r : STD_ULOGIC) return STD_ULOGIC;\n function \\?<=\\ (l, r : STD_ULOGIC) return STD_ULOGIC;\n\n\n -- \"??\" operator, converts a std_ulogic to a boolean.\n --%%% Uncomment the following operators\n -- FUNCTION \"??\" (S : STD_ULOGIC) RETURN BOOLEAN;\n --%%% REMOVE the following funciton (for testing only)\n function \\??\\ (S : STD_ULOGIC) return BOOLEAN;\n\n -- rtl_synthesis off\n-- pragma synthesis_off\n function to_string (value : STD_ULOGIC) return STRING;\n function to_string (value : STD_ULOGIC_VECTOR) return STRING;\n function to_string (value : STD_LOGIC_VECTOR) return STRING;\n\n -- explicitly defined operations\n\n alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];\n alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];\n function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];\n function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];\n\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);\n\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);\n\n procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];\n alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];\n alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];\n alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];\n\n procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);\n procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);\n alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];\n\n procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);\n procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);\n alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];\n alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];\n\n alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];\n alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];\n \n procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];\n \n procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];\n\n alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];\n alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];\n function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;\n alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];\n function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;\n alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];\n\n procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);\n procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);\n\n procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n\n alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];\n alias BREAD is READ [LINE, STD_LOGIC_VECTOR];\n alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];\n alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];\n\n procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);\n procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);\n alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];\n alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];\n\n procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);\n procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);\n alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];\n alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];\n\n alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];\n alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];\n \n procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];\n \n procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);\n alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];\n -- rtl_synthesis on\n-- pragma synthesis_on\n function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;\n function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;\n function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;\n function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;\nend package std_logic_1164_additions;\n\npackage body std_logic_1164_additions is\n type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;\n -----------------------------------------------------------------------------\n -- New/updated funcitons for VHDL-200X fast track\n -----------------------------------------------------------------------------\n -- to_01\n ------------------------------------------------------------------- \n function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC_VECTOR is\n variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);\n variable BAD_ELEMENT : BOOLEAN := false;\n alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;\n begin\n for I in RESULT'range loop\n case XS(I) is\n when '0' | 'L' => RESULT(I) := '0';\n when '1' | 'H' => RESULT(I) := '1';\n when others => BAD_ELEMENT := true;\n end case;\n end loop;\n if BAD_ELEMENT then\n for I in RESULT'range loop\n RESULT(I) := XMAP; -- standard fixup\n end loop;\n end if;\n return RESULT;\n end function TO_01;\n ------------------------------------------------------------------- \n function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC is\n begin\n case s is\n when '0' | 'L' => RETURN '0';\n when '1' | 'H' => RETURN '1';\n when others => return xmap;\n end case;\n end function TO_01;\n ------------------------------------------------------------------- \n function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC_VECTOR is\n variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);\n alias XS : BIT_VECTOR(s'length-1 downto 0) is s;\n begin\n for I in RESULT'range loop\n case XS(I) is\n when '0' => RESULT(I) := '0';\n when '1' => RESULT(I) := '1';\n end case;\n end loop;\n return RESULT;\n end function TO_01;\n ------------------------------------------------------------------- \n function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')\n return STD_ULOGIC is\n begin\n case s is\n when '0' => RETURN '0';\n when '1' => RETURN '1';\n end case;\n end function TO_01;\n-- end Bugzilla issue #148\n ------------------------------------------------------------------- \n\n ------------------------------------------------------------------- \n -- overloaded shift operators\n ------------------------------------------------------------------- \n\n ------------------------------------------------------------------- \n -- sll\n ------------------------------------------------------------------- \n function \"sll\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');\n begin\n if r >= 0 then\n result(1 to l'length - r) := lv(r + 1 to l'length);\n else\n result := l srl -r;\n end if;\n return result;\n end function \"sll\";\n ------------------------------------------------------------------- \n function \"sll\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');\n begin\n if r >= 0 then\n result(1 to l'length - r) := lv(r + 1 to l'length);\n else\n result := l srl -r;\n end if;\n return result;\n end function \"sll\";\n\n ------------------------------------------------------------------- \n -- srl\n ------------------------------------------------------------------- \n function \"srl\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');\n begin\n if r >= 0 then\n result(r + 1 to l'length) := lv(1 to l'length - r);\n else\n result := l sll -r;\n end if;\n return result;\n end function \"srl\";\n ------------------------------------------------------------------- \n function \"srl\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');\n begin\n if r >= 0 then\n result(r + 1 to l'length) := lv(1 to l'length - r);\n else\n result := l sll -r;\n end if;\n return result;\n end function \"srl\";\n\n ------------------------------------------------------------------- \n -- rol\n ------------------------------------------------------------------- \n function \"rol\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length);\n constant rm : INTEGER := r mod l'length;\n begin\n if r >= 0 then\n result(1 to l'length - rm) := lv(rm + 1 to l'length);\n result(l'length - rm + 1 to l'length) := lv(1 to rm);\n else\n result := l ror -r;\n end if;\n return result;\n end function \"rol\";\n ------------------------------------------------------------------- \n function \"rol\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length);\n constant rm : INTEGER := r mod l'length;\n begin\n if r >= 0 then\n result(1 to l'length - rm) := lv(rm + 1 to l'length);\n result(l'length - rm + 1 to l'length) := lv(1 to rm);\n else\n result := l ror -r;\n end if;\n return result;\n end function \"rol\";\n\n ------------------------------------------------------------------- \n -- ror\n ------------------------------------------------------------------- \n function \"ror\" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');\n constant rm : INTEGER := r mod l'length;\n begin\n if r >= 0 then\n result(rm + 1 to l'length) := lv(1 to l'length - rm);\n result(1 to rm) := lv(l'length - rm + 1 to l'length);\n else\n result := l rol -r;\n end if;\n return result;\n end function \"ror\";\n ------------------------------------------------------------------- \n function \"ror\" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');\n constant rm : INTEGER := r mod l'length;\n begin\n if r >= 0 then\n result(rm + 1 to l'length) := lv(1 to l'length - rm);\n result(1 to rm) := lv(l'length - rm + 1 to l'length);\n else\n result := l rol -r;\n end if;\n return result;\n end function \"ror\";\n -------------------------------------------------------------------\n -- vector/scalar overloaded logical operators\n -------------------------------------------------------------------\n\n -------------------------------------------------------------------\n -- and\n -------------------------------------------------------------------\n function \"and\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"and\" (lv(i), r);\n end loop;\n return result;\n end function \"and\";\n -------------------------------------------------------------------\n function \"and\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"and\" (lv(i), r);\n end loop;\n return result;\n end function \"and\";\n -------------------------------------------------------------------\n function \"and\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_LOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"and\" (l, rv(i));\n end loop;\n return result;\n end function \"and\";\n -------------------------------------------------------------------\n function \"and\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_ULOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"and\" (l, rv(i));\n end loop;\n return result;\n end function \"and\";\n\n -------------------------------------------------------------------\n -- nand\n -------------------------------------------------------------------\n function \"nand\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (lv(i), r));\n end loop;\n return result;\n end function \"nand\";\n -------------------------------------------------------------------\n function \"nand\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (lv(i), r));\n end loop;\n return result;\n end function \"nand\";\n -------------------------------------------------------------------\n function \"nand\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_LOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (l, rv(i)));\n end loop;\n return result;\n end function \"nand\";\n -------------------------------------------------------------------\n function \"nand\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_ULOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"and\" (l, rv(i)));\n end loop;\n return result;\n end function \"nand\";\n\n -------------------------------------------------------------------\n -- or\n -------------------------------------------------------------------\n function \"or\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"or\" (lv(i), r);\n end loop;\n return result;\n end function \"or\";\n -------------------------------------------------------------------\n function \"or\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"or\" (lv(i), r);\n end loop;\n return result;\n end function \"or\";\n -------------------------------------------------------------------\n function \"or\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_LOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"or\" (l, rv(i));\n end loop;\n return result;\n end function \"or\";\n -------------------------------------------------------------------\n function \"or\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_ULOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"or\" (l, rv(i));\n end loop;\n return result;\n end function \"or\";\n\n -------------------------------------------------------------------\n -- nor\n -------------------------------------------------------------------\n function \"nor\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (lv(i), r));\n end loop;\n return result;\n end function \"nor\";\n -------------------------------------------------------------------\n function \"nor\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (lv(i), r));\n end loop;\n return result;\n end function \"nor\";\n -------------------------------------------------------------------\n function \"nor\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_LOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (l, rv(i)));\n end loop;\n return result;\n end function \"nor\";\n -------------------------------------------------------------------\n function \"nor\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_ULOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"or\" (l, rv(i)));\n end loop;\n return result;\n end function \"nor\";\n\n -------------------------------------------------------------------\n -- xor\n -------------------------------------------------------------------\n function \"xor\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"xor\" (lv(i), r);\n end loop;\n return result;\n end function \"xor\";\n -------------------------------------------------------------------\n function \"xor\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"xor\" (lv(i), r);\n end loop;\n return result;\n end function \"xor\";\n -------------------------------------------------------------------\n function \"xor\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_LOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"xor\" (l, rv(i));\n end loop;\n return result;\n end function \"xor\";\n -------------------------------------------------------------------\n function \"xor\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_ULOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"xor\" (l, rv(i));\n end loop;\n return result;\n end function \"xor\";\n\n -------------------------------------------------------------------\n -- xnor\n -------------------------------------------------------------------\n function \"xnor\" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is\n alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_LOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (lv(i), r));\n end loop;\n return result;\n end function \"xnor\";\n -------------------------------------------------------------------\n function \"xnor\" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is\n alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;\n variable result : STD_ULOGIC_VECTOR (1 to l'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (lv(i), r));\n end loop;\n return result;\n end function \"xnor\";\n -------------------------------------------------------------------\n function \"xnor\" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_LOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (l, rv(i)));\n end loop;\n return result;\n end function \"xnor\";\n -------------------------------------------------------------------\n function \"xnor\" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;\n variable result : STD_ULOGIC_VECTOR (1 to r'length);\n begin\n for i in result'range loop\n result(i) := \"not\"(\"xor\" (l, rv(i)));\n end loop;\n return result;\n end function \"xnor\";\n\n -------------------------------------------------------------------\n -- vector-reduction functions\n -------------------------------------------------------------------\n\n -------------------------------------------------------------------\n -- and\n -------------------------------------------------------------------\n function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return and_reduce (to_StdULogicVector (l));\n end function and_reduce;\n -------------------------------------------------------------------\n function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n variable result : STD_ULOGIC := '1';\n begin\n for i in l'reverse_range loop\n result := (l(i) and result);\n end loop;\n return result;\n end function and_reduce;\n\n -------------------------------------------------------------------\n -- nand\n -------------------------------------------------------------------\n function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not (and_reduce(to_StdULogicVector(l)));\n end function nand_reduce;\n -------------------------------------------------------------------\n function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return not (and_reduce(l));\n end function nand_reduce;\n\n -------------------------------------------------------------------\n -- or\n -------------------------------------------------------------------\n function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return or_reduce (to_StdULogicVector (l));\n end function or_reduce;\n -------------------------------------------------------------------\n function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n variable result : STD_ULOGIC := '0';\n begin\n for i in l'reverse_range loop\n result := (l(i) or result);\n end loop;\n return result;\n end function or_reduce;\n\n -------------------------------------------------------------------\n -- nor\n -------------------------------------------------------------------\n function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \"not\"(or_reduce(To_StdULogicVector(l)));\n end function nor_reduce;\n -------------------------------------------------------------------\n function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \"not\"(or_reduce(l));\n end function nor_reduce;\n\n -------------------------------------------------------------------\n -- xor\n -------------------------------------------------------------------\n function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return xor_reduce (to_StdULogicVector (l));\n end function xor_reduce;\n -------------------------------------------------------------------\n function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n variable result : STD_ULOGIC := '0';\n begin\n for i in l'reverse_range loop\n result := (l(i) xor result);\n end loop;\n return result;\n end function xor_reduce;\n\n -------------------------------------------------------------------\n -- xnor\n -------------------------------------------------------------------\n function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \"not\"(xor_reduce(To_StdULogicVector(l)));\n end function xnor_reduce;\n -------------------------------------------------------------------\n function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n begin\n return \"not\"(xor_reduce(l));\n end function xnor_reduce;\n -- %%% End \"remove the following functions\"\n\n\n -- The following functions are implicity in 1076-2006\n -- truth table for \"?=\" function\n constant match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |\n ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |\n );\n\n constant no_match_logic_table : stdlogic_table := (\n -----------------------------------------------------\n -- U X 0 1 Z W L H - | | \n -----------------------------------------------------\n ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |\n ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |\n ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |\n ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |\n ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |\n );\n\n -------------------------------------------------------------------\n -- ?= functions, Similar to \"std_match\", but returns \"std_ulogic\".\n -------------------------------------------------------------------\n -- %%% FUNCTION \"?=\" ( l, r : std_ulogic ) RETURN std_ulogic IS\n function \\?=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return match_logic_table (l, r);\n end function \\?=\\;\n -- %%% END FUNCTION \"?=\";\n -------------------------------------------------------------------\n -- %%% FUNCTION \"?=\" ( l, r : std_logic_vector ) RETURN std_ulogic IS\n function \\?=\\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is\n alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;\n alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;\n variable result, result1 : STD_ULOGIC; -- result\n begin\n -- Logically identical to an \"=\" operator.\n if ((l'length < 1) or (r'length < 1)) then\n report \"STD_LOGIC_1164.\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n end if;\n if lv'length /= rv'length then\n report \"STD_LOGIC_1164.\"\"?=\"\": L'LENGTH /= R'LENGTH, returning X\"\n severity warning;\n return 'X';\n else\n result := '1';\n for i in lv'low to lv'high loop\n result1 := match_logic_table(lv(i), rv(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result and result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?=\\;\n -- %%% END FUNCTION \"?=\";\n -------------------------------------------------------------------\n -- %%% FUNCTION \"?=\" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS\n function \\?=\\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;\n alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;\n variable result, result1 : STD_ULOGIC;\n begin\n if ((l'length < 1) or (r'length < 1)) then\n report \"STD_LOGIC_1164.\"\"?=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n end if;\n if lv'length /= rv'length then\n report \"STD_LOGIC_1164.\"\"?=\"\": L'LENGTH /= R'LENGTH, returning X\"\n severity warning;\n return 'X';\n else\n result := '1';\n for i in lv'low to lv'high loop\n result1 := match_logic_table(lv(i), rv(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result and result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?=\\;\n -- %%% END FUNCTION \"?=\";\n -- %%% FUNCTION \"?/=\" ( l, r : std_ulogic ) RETURN std_ulogic is\n function \\?/=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n begin\n return no_match_logic_table (l, r);\n end function \\?/=\\;\n -- %%% END FUNCTION \"?/=\";\n -- %%% FUNCTION \"?/=\" ( l, r : std_logic_vector ) RETURN std_ulogic is\n function \\?/=\\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is\n alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;\n alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;\n variable result, result1 : STD_ULOGIC; -- result\n begin\n if ((l'length < 1) or (r'length < 1)) then\n report \"STD_LOGIC_1164.\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n end if;\n if lv'length /= rv'length then\n report \"STD_LOGIC_1164.\"\"?/=\"\": L'LENGTH /= R'LENGTH, returning X\"\n severity warning;\n return 'X';\n else\n result := '0';\n for i in lv'low to lv'high loop\n result1 := no_match_logic_table(lv(i), rv(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result or result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?/=\\;\n -- %%% END FUNCTION \"?/=\";\n -- %%% FUNCTION \"?/=\" ( l, r : std_ulogic_vector ) RETURN std_ulogic is\n function \\?/=\\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is\n alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;\n alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;\n variable result, result1 : STD_ULOGIC;\n begin\n if ((l'length < 1) or (r'length < 1)) then\n report \"STD_LOGIC_1164.\"\"?/=\"\": null detected, returning X\"\n severity warning;\n return 'X';\n end if;\n if lv'length /= rv'length then\n report \"STD_LOGIC_1164.\"\"?/=\"\": L'LENGTH /= R'LENGTH, returning X\"\n severity warning;\n return 'X';\n else\n result := '0';\n for i in lv'low to lv'high loop\n result1 := no_match_logic_table(lv(i), rv(i));\n if result1 = 'U' then\n return 'U';\n elsif result1 = 'X' or result = 'X' then\n result := 'X';\n else\n result := result or result1;\n end if;\n end loop;\n return result;\n end if;\n end function \\?/=\\;\n -- %%% END FUNCTION \"?/=\";\n -- %%% FUNCTION \"?>\" ( l, r : std_ulogic ) RETURN std_ulogic is\n function \\?>\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n variable lx, rx : STD_ULOGIC;\n begin\n if (l = '-') or (r = '-') then\n report \"STD_LOGIC_1164.\"\"?>\"\": '-' found in compare string\"\n severity error;\n return 'X';\n else\n lx := to_x01 (l);\n rx := to_x01 (r);\n if lx = 'X' or rx = 'X' then\n return 'X';\n elsif lx > rx then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>\\;\n -- %%% END FUNCTION \"?>\";\n\n -- %%% FUNCTION \"?>=\" ( l, r : std_ulogic ) RETURN std_ulogic is\n function \\?>=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n variable lx, rx : STD_ULOGIC;\n begin\n if (l = '-') or (r = '-') then\n report \"STD_LOGIC_1164.\"\"?>=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n else\n lx := to_x01 (l);\n rx := to_x01 (r);\n if lx = 'X' or rx = 'X' then\n return 'X';\n elsif lx >= rx then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?>=\\;\n -- %%% END FUNCTION \"?/>=\";\n\n -- %%% FUNCTION \"?<\" ( l, r : std_ulogic ) RETURN std_ulogic is\n function \\?<\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n variable lx, rx : STD_ULOGIC;\n begin\n if (l = '-') or (r = '-') then\n report \"STD_LOGIC_1164.\"\"?<\"\": '-' found in compare string\"\n severity error;\n return 'X';\n else\n lx := to_x01 (l);\n rx := to_x01 (r);\n if lx = 'X' or rx = 'X' then\n return 'X';\n elsif lx < rx then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<\\;\n -- %%% END FUNCTION \"?/<\";\n\n -- %%% FUNCTION \"?<=\" ( l, r : std_ulogic ) RETURN std_ulogic is\n function \\?<=\\ (l, r : STD_ULOGIC) return STD_ULOGIC is\n variable lx, rx : STD_ULOGIC;\n begin\n if (l = '-') or (r = '-') then\n report \"STD_LOGIC_1164.\"\"?<=\"\": '-' found in compare string\"\n severity error;\n return 'X';\n else\n lx := to_x01 (l);\n rx := to_x01 (r);\n if lx = 'X' or rx = 'X' then\n return 'X';\n elsif lx <= rx then\n return '1';\n else\n return '0';\n end if;\n end if;\n end function \\?<=\\;\n -- %%% END FUNCTION \"?/<=\";\n\n -- \"??\" operator, converts a std_ulogic to a boolean.\n-- %%% FUNCTION \"??\"\n function \\??\\ (S : STD_ULOGIC) return BOOLEAN is\n begin\n return S = '1' or S = 'H';\n end function \\??\\;\n-- %%% END FUNCTION \"??\";\n\n -- rtl_synthesis off\n-- pragma synthesis_off\n -----------------------------------------------------------------------------\n -- This section copied from \"std_logic_textio\"\n -----------------------------------------------------------------------------\n -- Type and constant definitions used to map STD_ULOGIC values \n -- into/from character values.\n type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);\n type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;\n type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;\n type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;\n constant MVL9_to_char : char_indexed_by_MVL9 := \"UX01ZWLH-\";\n constant char_to_MVL9 : MVL9_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');\n constant char_to_MVL9plus : MVL9plus_indexed_by_char :=\n ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',\n 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);\n\n constant NBSP : CHARACTER := CHARACTER'val(160); -- space character\n constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING\n\n -- purpose: Skips white space\n procedure skip_whitespace (\n L : inout LINE) is\n variable readOk : BOOLEAN;\n variable c : CHARACTER;\n begin\n while L /= null and L.all'length /= 0 loop\n if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then\n read (l, c, readOk);\n else\n exit;\n end if;\n end loop;\n end procedure skip_whitespace;\n\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;\n GOOD : out BOOLEAN) is\n variable c : CHARACTER;\n variable readOk : BOOLEAN;\n begin\n VALUE := 'U'; -- initialize to a \"U\"\n Skip_whitespace (L);\n read (l, c, readOk);\n if not readOk then\n good := false;\n else\n if char_to_MVL9plus(c) = error then\n good := false;\n else\n VALUE := char_to_MVL9(c);\n good := true;\n end if;\n end if;\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable m : STD_ULOGIC;\n variable c : CHARACTER;\n variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);\n variable readOk : BOOLEAN;\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, readOk);\n i := 0;\n good := false;\n while i < VALUE'length loop\n if not readOk then -- Bail out if there was a bad read\n return;\n elsif c = '_' then\n if i = 0 then -- Begins with an \"_\"\n return;\n elsif lastu then -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n elsif (char_to_MVL9plus(c) = error) then -- Illegal character\n return;\n else\n mv(i) := char_to_MVL9(c);\n i := i + 1;\n if i > mv'high then -- reading done\n good := true;\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n read(L, c, readOk);\n end loop;\n else\n good := true; -- read into a null array\n end if;\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is\n variable c : CHARACTER;\n variable readOk : BOOLEAN;\n begin\n VALUE := 'U'; -- initialize to a \"U\"\n Skip_whitespace (L);\n read (l, c, readOk);\n if not readOk then\n report \"STD_LOGIC_1164.READ(STD_ULOGIC) \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif char_to_MVL9plus(c) = error then\n report\n \"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '\" &\n c & \"' read, expected STD_ULOGIC literal.\"\n severity error;\n else\n VALUE := char_to_MVL9(c);\n end if;\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is\n variable m : STD_ULOGIC;\n variable c : CHARACTER;\n variable readOk : BOOLEAN;\n variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then -- non Null input string\n read (l, c, readOk);\n i := 0;\n while i < VALUE'length loop\n if readOk = false then -- Bail out if there was a bad read\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif c = '_' then\n if i = 0 then\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n elsif c = ' ' or c = NBSP or c = HT then -- reading done.\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"Short read, Space encounted in input string\"\n severity error;\n return;\n elsif char_to_MVL9plus(c) = error then\n report \"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) \"\n & \"Error: Character '\" &\n c & \"' read, expected STD_ULOGIC literal.\"\n severity error;\n return;\n else\n mv(i) := char_to_MVL9(c);\n i := i + 1;\n if i > mv'high then\n VALUE := mv;\n return;\n end if;\n lastu := false;\n end if;\n read(L, c, readOk);\n end loop;\n end if;\n end procedure READ;\n\n procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write(l, MVL9_to_char(VALUE), justified, field);\n end procedure WRITE;\n\n procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n variable s : STRING(1 to VALUE'length);\n variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;\n begin\n for i in 1 to VALUE'length loop\n s(i) := MVL9_to_char(m(i));\n end loop;\n write(l, s, justified, field);\n end procedure WRITE;\n\n -- Read and Write procedures for STD_LOGIC_VECTOR\n\n procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);\n begin\n READ (L => L, VALUE => ivalue, GOOD => GOOD);\n VALUE := to_stdlogicvector (ivalue);\n end procedure READ;\n\n procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is\n variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);\n begin\n READ (L => L, VALUE => ivalue);\n VALUE := to_stdlogicvector (ivalue);\n end procedure READ;\n\n procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n variable s : STRING(1 to VALUE'length);\n variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;\n begin\n for i in 1 to VALUE'length loop\n s(i) := MVL9_to_char(m(i));\n end loop;\n write(L, s, justified, field);\n end procedure WRITE;\n\n -----------------------------------------------------------------------\n -- Alias for bread and bwrite are provided with call out the read and\n -- write functions.\n -----------------------------------------------------------------------\n\n -- Hex Read and Write procedures for STD_ULOGIC_VECTOR.\n -- Modified from the original to be more forgiving.\n\n procedure Char2QuadBits (C : CHARACTER;\n RESULT : out STD_ULOGIC_VECTOR(3 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n when '0' => result := x\"0\"; good := true;\n when '1' => result := x\"1\"; good := true;\n when '2' => result := x\"2\"; good := true;\n when '3' => result := x\"3\"; good := true;\n when '4' => result := x\"4\"; good := true;\n when '5' => result := x\"5\"; good := true;\n when '6' => result := x\"6\"; good := true;\n when '7' => result := x\"7\"; good := true;\n when '8' => result := x\"8\"; good := true;\n when '9' => result := x\"9\"; good := true;\n when 'A' | 'a' => result := x\"A\"; good := true;\n when 'B' | 'b' => result := x\"B\"; good := true;\n when 'C' | 'c' => result := x\"C\"; good := true;\n when 'D' | 'd' => result := x\"D\"; good := true;\n when 'E' | 'e' => result := x\"E\"; good := true;\n when 'F' | 'f' => result := x\"F\"; good := true;\n when 'Z' => result := \"ZZZZ\"; good := true;\n when 'X' => result := \"XXXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report\n \"STD_LOGIC_1164.HREAD Read a '\" & c &\n \"', expected a Hex character (0-F).\"\n severity error;\n good := false;\n end case;\n end procedure Char2QuadBits;\n\n procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- Null input string, skips whitespace\n end if;\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+3)/4;\n constant pad : INTEGER := ne*4 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then -- non Null input string\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n report \"STD_LOGIC_1164.HREAD \"\n & \"End of string encountered\"\n severity error;\n return;\n end if;\n if c = '_' then\n if i = 0 then\n report \"STD_LOGIC_1164.HREAD \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report \"STD_LOGIC_1164.HREAD \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n else\n Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);\n if not ok then\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n report \"STD_LOGIC_1164.HREAD Vector truncated\"\n severity error;\n else\n VALUE := sv (pad to sv'high);\n end if;\n end if;\n end procedure HREAD;\n\n procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_hstring (VALUE), JUSTIFIED, FIELD);\n end procedure HWRITE;\n\n\n -- Octal Read and Write procedures for STD_ULOGIC_VECTOR.\n -- Modified from the original to be more forgiving.\n\n procedure Char2TriBits (C : CHARACTER;\n RESULT : out STD_ULOGIC_VECTOR(2 downto 0);\n GOOD : out BOOLEAN;\n ISSUE_ERROR : in BOOLEAN) is\n begin\n case c is\n", "right_context": " when '7' => result := o\"7\"; good := true;\n when 'Z' => result := \"ZZZ\"; good := true;\n when 'X' => result := \"XXX\"; good := true;\n when others =>\n assert not ISSUE_ERROR\n report\n \"STD_LOGIC_1164.OREAD Error: Read a '\" & c &\n \"', expected an Octal character (0-7).\"\n severity error;\n good := false;\n end case;\n end procedure Char2TriBits;\n\n procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ok : BOOLEAN;\n variable c : CHARACTER;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n good := false;\n return;\n elsif c = '_' then\n if i = 0 then\n good := false; -- Begins with an \"_\"\n return;\n elsif lastu then\n good := false; -- \"__\" detected\n return;\n else\n lastu := true;\n end if;\n else\n Char2TriBits(c, sv(3*i to 3*i+2), ok, false);\n if not ok then\n good := false;\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n good := false; -- vector was truncated.\n else\n good := true;\n VALUE := sv (pad to sv'high);\n end if;\n else\n good := true; -- read into a null array\n end if;\n end procedure OREAD;\n\n procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is\n variable c : CHARACTER;\n variable ok : BOOLEAN;\n constant ne : INTEGER := (VALUE'length+2)/3;\n constant pad : INTEGER := ne*3 - VALUE'length;\n variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);\n variable i : INTEGER;\n variable lastu : BOOLEAN := false; -- last character was an \"_\"\n begin\n VALUE := (VALUE'range => 'U'); -- initialize to a \"U\"\n Skip_whitespace (L);\n if VALUE'length > 0 then\n read (l, c, ok);\n i := 0;\n while i < ne loop\n -- Bail out if there was a bad read\n if not ok then\n report \"STD_LOGIC_1164.OREAD \"\n & \"End of string encountered\"\n severity error;\n return;\n elsif c = '_' then\n if i = 0 then\n report \"STD_LOGIC_1164.OREAD \"\n & \"String begins with an \"\"_\"\"\" severity error;\n return;\n elsif lastu then\n report \"STD_LOGIC_1164.OREAD \"\n & \"Two underscores detected in input string \"\"__\"\"\"\n severity error;\n return;\n else\n lastu := true;\n end if;\n else\n Char2TriBits(c, sv(3*i to 3*i+2), ok, true);\n if not ok then\n return;\n end if;\n i := i + 1;\n lastu := false;\n end if;\n if i < ne then\n read(L, c, ok);\n end if;\n end loop;\n if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with \"or\"\n report \"STD_LOGIC_1164.OREAD Vector truncated\"\n severity error;\n else\n VALUE := sv (pad to sv'high);\n end if;\n end if;\n end procedure OREAD;\n\n procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_ostring(VALUE), JUSTIFIED, FIELD);\n end procedure OWRITE;\n\n -- Hex Read and Write procedures for STD_LOGIC_VECTOR\n\n procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);\n begin\n HREAD (L => L, VALUE => ivalue, GOOD => GOOD);\n VALUE := to_stdlogicvector (ivalue);\n end procedure HREAD;\n\n procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is\n variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);\n begin\n HREAD (L => L, VALUE => ivalue);\n VALUE := to_stdlogicvector (ivalue);\n end procedure HREAD;\n\n procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_hstring(VALUE), JUSTIFIED, FIELD);\n end procedure HWRITE;\n\n -- Octal Read and Write procedures for STD_LOGIC_VECTOR\n\n procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;\n GOOD : out BOOLEAN) is\n variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);\n begin\n OREAD (L => L, VALUE => ivalue, GOOD => GOOD);\n VALUE := to_stdlogicvector (ivalue);\n end procedure OREAD;\n\n procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is\n variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);\n begin\n OREAD (L => L, VALUE => ivalue);\n VALUE := to_stdlogicvector (ivalue);\n end procedure OREAD;\n\n procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;\n JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is\n begin\n write (L, to_ostring(VALUE), JUSTIFIED, FIELD);\n end procedure OWRITE;\n\n -----------------------------------------------------------------------------\n -- New string functions for vhdl-200x fast track\n -----------------------------------------------------------------------------\n function to_string (value : STD_ULOGIC) return STRING is\n variable result : STRING (1 to 1);\n begin\n result (1) := MVL9_to_char (value);\n return result;\n end function to_string;\n ------------------------------------------------------------------- \n -- TO_STRING (an alias called \"to_bstring\" is provide)\n ------------------------------------------------------------------- \n function to_string (value : STD_ULOGIC_VECTOR) return STRING is\n alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;\n variable result : STRING(1 to value'length);\n begin\n if value'length < 1 then\n return NUS;\n else\n for i in ivalue'range loop\n result(i) := MVL9_to_char(iValue(i));\n end loop;\n return result;\n end if;\n end function to_string;\n\n ------------------------------------------------------------------- \n -- TO_HSTRING\n ------------------------------------------------------------------- \n function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+3)/4;\n variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);\n variable result : STRING(1 to ne);\n variable quad : STD_ULOGIC_VECTOR(0 to 3);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n quad := To_X01Z(ivalue(4*i to 4*i+3));\n case quad is\n when x\"0\" => result(i+1) := '0';\n when x\"1\" => result(i+1) := '1';\n when x\"2\" => result(i+1) := '2';\n when x\"3\" => result(i+1) := '3';\n when x\"4\" => result(i+1) := '4';\n when x\"5\" => result(i+1) := '5';\n when x\"6\" => result(i+1) := '6';\n when x\"7\" => result(i+1) := '7';\n when x\"8\" => result(i+1) := '8';\n when x\"9\" => result(i+1) := '9';\n when x\"A\" => result(i+1) := 'A';\n when x\"B\" => result(i+1) := 'B';\n when x\"C\" => result(i+1) := 'C';\n when x\"D\" => result(i+1) := 'D';\n when x\"E\" => result(i+1) := 'E';\n when x\"F\" => result(i+1) := 'F';\n when \"ZZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_hstring;\n\n ------------------------------------------------------------------- \n -- TO_OSTRING\n ------------------------------------------------------------------- \n function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is\n constant ne : INTEGER := (value'length+2)/3;\n variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);\n variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);\n variable result : STRING(1 to ne);\n variable tri : STD_ULOGIC_VECTOR(0 to 2);\n begin\n if value'length < 1 then\n return NUS;\n else\n if value (value'left) = 'Z' then\n pad := (others => 'Z');\n else\n pad := (others => '0');\n end if;\n ivalue := pad & value;\n for i in 0 to ne-1 loop\n tri := To_X01Z(ivalue(3*i to 3*i+2));\n case tri is\n when o\"0\" => result(i+1) := '0';\n when o\"1\" => result(i+1) := '1';\n when o\"2\" => result(i+1) := '2';\n when o\"3\" => result(i+1) := '3';\n when o\"4\" => result(i+1) := '4';\n when o\"5\" => result(i+1) := '5';\n when o\"6\" => result(i+1) := '6';\n when o\"7\" => result(i+1) := '7';\n when \"ZZZ\" => result(i+1) := 'Z';\n when others => result(i+1) := 'X';\n end case;\n end loop;\n return result;\n end if;\n end function to_ostring;\n\n function to_string (value : STD_LOGIC_VECTOR) return STRING is\n begin\n return to_string (to_stdulogicvector (value));\n end function to_string;\n\n function to_hstring (value : STD_LOGIC_VECTOR) return STRING is\n begin\n return to_hstring (to_stdulogicvector (value));\n end function to_hstring;\n\n function to_ostring (value : STD_LOGIC_VECTOR) return STRING is\n begin\n return to_ostring (to_stdulogicvector (value));\n end function to_ostring;\n\n -- rtl_synthesis on\n-- pragma synthesis_on\n function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin -- function maximum\n if L > R then return L;\n else return R;\n end if;\n end function maximum;\n\n -- std_logic_vector output\n function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is\n begin -- function minimum\n if L > R then return R;\n else return L;\n end if;\n end function minimum;\n\n function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin -- function maximum\n if L > R then return L;\n else return R;\n end if;\n end function maximum;\n\n -- std_logic_vector output\n function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is\n begin -- function minimum\n if L > R then return R;\n else return L;\n end if;\n end function minimum;\n\n function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is\n begin -- function maximum\n if L > R then return L;\n else return R;\n end if;\n end function maximum;\n\n -- std_logic_vector output\n function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is\n begin -- function minimum\n if L > R then return R;\n else return L;\n end if;\n end function minimum;\nend package body std_logic_1164_additions;\n", "groundtruth": " when '0' => result := o\"0\"; good := true;\n when '1' => result := o\"1\"; good := true;\n when '2' => result := o\"2\"; good := true;\n when '3' => result := o\"3\"; good := true;\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/test_fixed_synth.vhdl", "left_context": "-- Test vectors for the synthesis test for the fixed point math package\n-- This test is designed to test fixed_synth and exercise much of the entity.\n-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)\n-- --------------------------------------------------------------------\n-- modification history : Last Modified $Date: 2006-06-08 10:55:54-04 $\n-- Version $Id: test_fixed_synth.vhdl,v 1.1 2006-06-08 10:55:54-04 l435385 Exp $\n-- --------------------------------------------------------------------\n\n", "right_context": "use ieee.numeric_std.all;\nuse ieee_proposed.fixed_pkg.all;\narchitecture testbench of test_fixed_synth is\n\n procedure report_error (\n constant errmes : in string; -- error message\n actual : in sfixed; -- data from algorithm\n constant expected : in sfixed) is -- reference data\n begin -- function report_error\n assert actual = expected\n report errmes & CR\n & \"Actual: \" & to_string(actual)\n & \" (\" & real'image(to_real(actual)) & \")\" & CR\n & \" /= \" & to_string(expected)\n & \" (\" & real'image(to_real(expected)) & \")\"\n severity error;\n return;\n end procedure report_error;\n \n -- Device under test. Note that all inputs and outputs are std_logic_vector.\n -- This entity can be use both pre and post synthesis.\n component fixed_synth is\n port (\n in1, in2 : in std_logic_vector (15 downto 0); -- inputs\n out1 : out std_logic_vector (15 downto 0); -- output\n cmd : in std_logic_vector (3 downto 0);\n clk, rst_n : in std_ulogic); -- clk and reset\n end component fixed_synth;\n constant clock_period : time := 500 ns; -- clock period\n subtype sfixed7 is sfixed (3 downto -3); -- 7 bit\n subtype sfixed16 is sfixed (7 downto -8); -- 16 bit\n signal stop_clock : boolean := false; -- stop the clock\n signal clk, rst_n : std_ulogic; -- clk and reset\n signal in1slv, in2slv, out1slv : std_logic_vector(15 downto 0);\n signal in1, in2 : sfixed16; -- inputs\n signal out1 : sfixed16; -- output\n signal cmd : std_logic_vector (3 downto 0); -- command string\nbegin -- architecture testbench\n\n -- From fixed point to Std_logic_vector\n in1slv <= to_slv(in1);\n in2slv <= to_slv(in2);\n -- Std_logic_vector to fixed point.\n out1 <= to_sfixed(out1slv, out1'high, out1'low);\n DUT: fixed_synth\n port map (\n in1 => in1slv, -- [in std_logic_vector (15 downto 0)] inputs\n in2 => in2slv, -- [in std_logic_vector (15 downto 0)] inputs\n out1 => out1slv, -- [out std_logic_vector (15 downto 0)] output\n cmd => cmd, -- [in std_logic_vector (2 downto 0)]\n clk => clk, -- [in std_ulogic] clk and reset\n rst_n => rst_n); -- [in std_ulogic] clk and reset\n \n -- purpose: clock driver\n clkprc: process is\n begin -- process clkprc\n if (not stop_clock) then\n clk <= '0';\n wait for clock_period/2.0;\n clk <= '1';\n wait for clock_period/2.0;\n else\n wait;\n end if;\n end process clkprc;\n\n -- purpose: reset driver\n reset_proc: process is\n begin -- process reset_proc\n rst_n <= '0';\n wait for clock_period * 2.0;\n rst_n <= '1';\n wait;\n end process reset_proc;\n\n -- purpose: main test loop\n tester: process is\n begin -- process tester\n cmd <= \"0000\"; -- add mode\n in1 <= (others => '0');\n in2 <= (others => '0');\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n in1 <= \"0000011010000000\"; -- 6.5\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0001\"; -- subtract mode\n in1 <= \"0000011010000000\"; -- 6.5\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0010\"; -- multiply mode\n in1 <= \"0000011010000000\"; -- 6.5\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0000\"; -- add mode\n in1 <= \"0000000010000000\"; -- 0.5\n in2 <= \"0000000010000000\"; -- 0.5\n wait for clock_period;\n in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0011\"; -- divide\n in1 <= \"0000000010000000\"; -- 0.5\n in2 <= \"0000000010000000\"; -- 0.5\n wait for clock_period;\n in1 <= to_sfixed (-0.5, sfixed16'high, sfixed16'low); -- -0.5\n in2 <= \"0000000010000000\"; -- 0.5\n wait for clock_period;\n cmd <= \"0100\"; -- unsigned add\n in1 <= \"0000011010000000\"; -- 6.5\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0101\"; -- subtract mode\n in1 <= \"0000011010000000\"; -- 6.5\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0110\"; -- multiply mode\n in1 <= \"0000011010000000\"; -- 6.5\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0100\"; -- add mode\n in1 <= \"0000000010000000\"; -- 0.5\n in2 <= \"0000000010000000\"; -- 0.5\n wait for clock_period;\n in1 <= to_sfixed (3.14, sfixed16'high, sfixed16'low);\n in2 <= \"0000001100000000\"; -- 3\n wait for clock_period;\n cmd <= \"0111\"; -- divide\n in1 <= \"0000000010000000\"; -- 0.5\n in2 <= \"0000000010000000\"; -- 0.5\n wait for clock_period;\n in1 <= to_sfixed (6.5, sfixed16'high, sfixed16'low); -- 6.5\n in2 <= \"0000000010000000\"; -- 0.5\n wait for clock_period;\n -- resize\n cmd <= \"1000\";\n in1 <= to_sfixed (5.25, in1);\n in2 <= to_sfixed (-5.25, in2);\n wait for clock_period;\n in1 <= to_sfixed (21.125, in1);\n in2 <= to_sfixed (21.125, in2);\n wait for clock_period;\n in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');\n cmd <= \"1001\"; -- SIGNED\n in1 <= to_sfixed (6.25, in1);\n wait for clock_period;\n in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');\n cmd <= \"1001\"; -- UNSIGNED\n in1 <= to_sfixed (7.25, in1);\n wait for clock_period;\n in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');\n cmd <= \"1001\"; -- SIGNED\n in1 <= to_sfixed (6.25, in1);\n wait for clock_period;\n in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');\n cmd <= \"1001\"; -- UNSIGNED\n in1 <= to_sfixed (7.25, in1);\n wait for clock_period;\n cmd <= \"1010\";\n in2 <= (in2'high => '0', in2'high-1 => '0', others => '0');\n in1 <= to_sfixed (3, in1);\n wait for clock_period;\n cmd <= \"1010\";\n in2 <= (in2'high => '0', in2'high-1 => '1', others => '0');\n in1 <= to_sfixed (5, in1);\n wait for clock_period;\n cmd <= \"1010\";\n in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');\n in1 <= to_sfixed (-5.5, in1);\n wait for clock_period;\n cmd <= \"1010\";\n in2 <= (in2'high => '1', in2'high-1 => '1', others => '0');\n in1 <= to_sfixed (7.25, in1); \n wait for clock_period;\n cmd <= \"1010\"; -- abs (mod)\n in2 <= (in2'high => '1', in2'high-1 => '0', others => '0');\n in1 <= to_sfixed (-42, in1);\n wait for clock_period;\n cmd <= \"1011\"; -- mod\n in1 <= to_sfixed (6.25, in1);\n in2 <= to_sfixed (6, in2);\n wait for clock_period;\n cmd <= \"1100\"; -- REM\n in1 <= to_sfixed (6.25, in1);\n in2 <= to_sfixed (6, in2);\n wait for clock_period;\n cmd <= \"1101\"; -- srl\n in1 <= to_sfixed (5.25, in1);\n in2 <= to_sfixed (-1, in2);\n wait for clock_period;\n cmd <= \"1110\"; -- sra\n in1 <= to_sfixed (-7.25, in1);\n in2 <= to_sfixed (1, in2);\n wait for clock_period;\n cmd <= \"1111\"; -- compare\n in1 <= to_sfixed (42, in1);\n in2 <= to_sfixed (42, in1);\n wait for clock_period;\n in1 <= to_sfixed (45, in1);\n in2 <= to_sfixed (90, in1);\n wait for clock_period;\n in1 <= to_sfixed (3.125, in1);\n in2 <= (others => '0');\n wait for clock_period;\n in1 <= \"0110111110101111\";\n in2 <= \"1111111111111111\";\n wait for clock_period;\n in1 <= (others => '0');\n in2 <= (others => '0');\n wait for clock_period;\n in1 <= \"0000111000000000\";\n in2 <= \"0000111000000000\";\n wait for clock_period;\n in1 <= (others => '1');\n in2 <= (others => '1');\n wait for clock_period;\n wait for clock_period;\n\n wait for clock_period;\n cmd <= \"0000\"; -- add mode\n in1 <= (others => '0');\n in2 <= (others => '0');\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait;\n end process tester;\n\n -- purpose: check the output of the tester\n -- type : combinational\n -- inputs : \n -- outputs: \n checktest: process is\n constant fxzero : sfixed16 := (others => '0'); -- zero\n variable chks16 : sfixed16; -- variable\n variable sm1, sm2 : sfixed7; -- small fixed point\n begin -- process checktest\n wait for clock_period/2.0;\n wait for clock_period;\n wait for clock_period;\n waitloop: while (out1 = fxzero) loop\n wait for clock_period;\n end loop waitloop;\n chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);\n report_error ( \"3.0 + 6.5 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);\n report_error ( \"6.5 - 3.0 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);\n report_error ( \"6.5 * 3.0 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);\n report_error ( \"0.5 + 0.5 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);\n report_error ( \"3.14 + 3 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := \"0000000100000000\";\n report_error ( \"0.5/0.5 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed (-1, sfixed16'high, sfixed16'low);\n report_error ( \"-0.5/0.5 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed ((3.0+6.5), sfixed16'high, sfixed16'low);\n report_error ( \"3.0 + 6.5 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed ((6.5 - 3.0), sfixed16'high, sfixed16'low);\n report_error ( \"6.5 - 3.0 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed ((6.5 * 3.0), sfixed16'high, sfixed16'low);\n report_error ( \"6.5 * 3.0 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed (1, sfixed16'high, sfixed16'low);\n report_error ( \"0.5 + 0.5 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed (6.14, sfixed16'high, sfixed16'low);\n report_error ( \"3.14 + 3 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := \"0000000100000000\";\n report_error ( \"0.5/0.5 error\",\n out1,\n chks16);\n wait for clock_period;\n chks16 := to_sfixed (13, sfixed16'high, sfixed16'low);\n report_error ( \"6.5/0.5 error\",\n out1,\n chks16);\n wait for clock_period;\n -- resize test\n sm1 := out1 (7 downto 1);\n sm2 := to_sfixed (5.25, sm2);\n report_error ( \"resize 1 error\", sm1, sm2);\n sm1 := out1 (-1 downto -7);\n sm2 := to_sfixed (-5.25, sm2);\n report_error ( \"resize 2 error\", sm1, sm2);\n wait for clock_period;\n sm1 := out1 (7 downto 1);\n sm2 := \"0101001\"; -- wrapped\n-- sm2 := to_sfixed (21.125, sm2, 0, false, false); -- wrap, no round\n report_error ( \"resize 1 error\", sm1, sm2);\n sm1 := out1 (-1 downto -7);\n sm2 := \"0111111\"; -- saturate\n report_error ( \"resize 2 error\", sm1, sm2);\n wait for clock_period;\n -- to_signed and back\n report_error (\"to_signed(6.25)\", out1, to_sfixed (6, out1));\n wait for clock_period;\n -- to_unsigned and back\n report_error (\"to_unsigned(7.25)\", out1, to_sfixed (7, out1));\n wait for clock_period;\n -- to_integer and back\n report_error (\"to_signed(6.25)\", out1, to_sfixed (6, out1));\n wait for clock_period;\n -- to_integer(ufixed) and back\n report_error (\"to_unsigned(7.25)\", out1, to_sfixed (7, out1));\n wait for clock_period;\n report_error (\"1/3\", out1, to_sfixed (1.0/3.0, out1'high, -7));\n wait for clock_period;\n report_error (\"unsigned 1/5\", out1, to_sfixed (1.0/5.0, out1));\n wait for clock_period;\n report_error (\"abs (-5.5)\", out1, to_sfixed (5.5, out1));\n wait for clock_period;\n report_error (\"-7.25\", out1, to_sfixed (-7.25, out1));\n wait for clock_period;\n report_error (\"abs(-42)\", out1, to_sfixed (42, out1));\n wait for clock_period;\n report_error (\"6.25 mod 6\", out1, to_sfixed (0.25, out1));\n wait for clock_period;\n report_error (\"6.25 rem 6\", out1, to_sfixed (0.25, out1));\n wait for clock_period;\n chks16 := \"0000101010000000\";\n report_error (\"5.25 srl -1\", out1, chks16);\n wait for clock_period;\n chks16 := \"1111110001100000\";\n report_error (\"-7.25 sra 1\", out1, chks16);\n wait for clock_period;\n -- 7654321012345678\n chks16 := \"0111000000110001\";\n assert (std_match (out1, chks16))\n report \"42=42 compare \" & CR\n & \"Actual \" & to_string(out1) & CR\n & \"Expected \" & to_string(chks16) severity error;\n wait for clock_period;\n chks16 := \"------0001010110\";\n assert (std_match (out1, chks16))\n report \"45=90 compare \" & CR\n & \"Actual \" & to_string(out1) & CR\n & \"Expected \" & to_string(chks16) severity error;\n wait for clock_period;\n chks16 := \"------1010101010\";\n assert (std_match (out1, chks16))\n report \"3.125=0 compare \" & CR\n & \"Actual \" & to_string(out1) & CR\n & \"Expected \" & to_string(chks16) severity error;\n wait for clock_period;\n -- 7654321012345678\n chks16 := \"0--1010000101010\";\n assert (std_match (out1, chks16))\n report \"pattern1 compare \" & CR\n & \"Actual \" & to_string(out1) & CR\n & \"Expected \" & to_string(chks16) severity error;\n wait for clock_period;\n -- 7654321012345678\n chks16 := \"0001100000110001\";\n assert (std_match (out1, chks16))\n report \"zero = zero \" & CR\n & \"Actual \" & to_string(out1) & CR\n & \"Expected \" & to_string(chks16) severity error;\n wait for clock_period;\n -- 7654321012345678\n chks16 := \"1111000000110001\";\n assert (std_match (out1, chks16))\n report \"pattern2 compare \" & CR\n & \"Actual \" & to_string(out1) & CR\n & \"Expected \" & to_string(chks16) severity error;\n wait for clock_period;\n -- 7654321012345678\n chks16 := \"0111000000110001\";\n assert (std_match (out1, chks16))\n report \"-1 = -1 \" & CR\n & \"Actual \" & to_string(out1) & CR\n & \"Expected \" & to_string(chks16) severity error;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n assert (false) report \"Testing complete\" severity note;\n stop_clock <= true;\n wait; \n end process checktest;\nend architecture testbench;\n", "groundtruth": "entity test_fixed_synth is\n generic (\n quiet : boolean := false); -- make the simulation quiet\nend entity test_fixed_synth;\n", "crossfile_context": ""} {"task_id": "fphdl", "path": "fphdl/test_float_synth.vhdl", "left_context": "-------------------------------------------------------------------------------\n-- test routine for the post synthesis 32 bit multiply\n-------------------------------------------------------------------------------\n\nentity test_float_synth is\n generic (\n quiet : BOOLEAN := false);\nend entity test_float_synth;\n\nuse std.textio.all;\nlibrary ieee, ieee_proposed;\nuse ieee.math_real.all;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee_proposed.fixed_float_types.all;\nuse ieee_proposed.fixed_pkg.all;\nuse ieee_proposed.float_pkg.all;\n\n--library modelsim_lib;\n--use modelsim_lib.util.all;\n\narchitecture testbench of test_float_synth is\n subtype fp16 is float (6 downto -9); -- 16 bit\n function reverse (\n inpvec : STD_LOGIC_VECTOR (0 to 31))\n return float32 is\n variable result : float32;\n begin\n for i in 0 to 31 loop\n result (i-23) := inpvec(i);\n end loop; -- i\n return result;\n end function reverse;\n\n -- purpose: converts an float32 into a std_logic_vector\n-- function to_slv (\n-- input : float32) -- float32 input\n-- return std_logic_vector is\n-- variable result : std_logic_vector (31 downto 0); -- result\n-- begin -- function to_slv\n-- floop: for i in float32'range loop\n-- result (i + fp_fraction_width) := input (i);\n-- end loop floop;\n-- return result;\n-- end function to_slv;\n\n -- purpose: converts a std_logic_vector to an float32\n function to_float32x (\n signal input : STD_LOGIC_VECTOR (31 downto 0))\n return float32 is\n variable result : float32;\n begin -- function to_float32x\n return to_float (input, float32'high, -float32'low);\n end function to_float32x;\n\n procedure report_error (\n constant errmes : STRING; -- error message\n actual : in float32; -- data from algorithm\n constant expected : float32) is -- reference data\n begin -- function report_error\n assert actual = expected\n report errmes & \" miscompare\" & CR &\n \"Actual \" & to_string (actual) & \" (\"\n & REAL'image(to_real(actual))& \") /= \" & CR &\n \"Expected \" & to_string (expected) & \" (\"\n & REAL'image(to_real(expected))& \")\"\n severity error;\n return;\n end procedure report_error;\n procedure report_error16 (\n constant errmes : STRING; -- error message\n actual : in fp16; -- data from algorithm\n constant expected : fp16) is -- reference data\n begin -- function report_error\n assert actual = expected\n report errmes & \" miscompare\" & CR &\n \"Actual \" & to_string (actual) & \" (\"\n & REAL'image(to_real(actual))& \") /= \" & CR &\n \"Expected \" & to_string (expected) & \" (\"\n & REAL'image(to_real(expected))& \")\"\n severity error;\n return;\n end procedure report_error16;\n\n component float_synth is\n port (\n in1, in2 : in STD_LOGIC_VECTOR(31 downto 0); -- inputs\n out1 : out STD_LOGIC_VECTOR(31 downto 0); -- output\n cmd : in STD_LOGIC_VECTOR (3 downto 0);\n clk, rst_n : in STD_ULOGIC); -- clk and reset\n end component float_synth;\n for all : float_synth\n use entity work.float_synth(rtl);\n constant clock_period : TIME := 500 ns; -- clock period\n signal stop_clock : BOOLEAN := false; -- stop the clock\n signal out1real : REAL; -- real version\n signal in1, in2 : float32; -- inputs\n signal out1 : float32; -- output\n constant zero0 : float32 := (others => '0'); -- zero\n signal cmd : STD_LOGIC_VECTOR (3 downto 0); -- command\n signal clk, rst_n : STD_ULOGIC; -- clk and reset\n signal in1slv, in2slv, out1slv : STD_LOGIC_VECTOR(31 downto 0);\n signal indelay : float32; -- spied signal\nbegin -- architecture testbench\n out1real <= to_real (out1);\n in1slv <= to_slv(in1);\n in2slv <= to_slv(in2);\n out1 <= to_float32x(out1slv);\n DUT : float_synth\n port map (\n in1 => in1slv, -- [in float32] inputs\n in2 => in2slv, -- [in float32] inputs\n out1 => out1slv, -- [out float32] output\n cmd => cmd,\n clk => clk, -- [in std_ulogic] clk and reset\n rst_n => rst_n); -- [in std_ulogic] clk and reset\n\n-- spy_process : process\n-- begin\n-- signal_force (\"/DUT/in2reg3\", \"00000000000000000000000000000000\",\n-- 500 ns, freeze, 5000 ns, 1);\n-- wait;\n-- end process spy_process;\n\n -- purpose: clock driver\n -- type : combinational\n -- inputs : \n -- outputs: \n clkprc : process is\n\n begin -- process clkprc\n", "right_context": " clk <= '0';\n wait for clock_period/2.0;\n clk <= '1';\n wait for clock_period/2.0;\n else\n wait;\n end if;\n end process clkprc;\n\n -- purpose: reset driver\n -- type : combinational\n -- inputs : \n -- outputs: \n reset_proc : process is\n\n begin -- process reset_proc\n\n rst_n <= '0';\n wait for clock_period * 2.0;\n rst_n <= '1';\n wait;\n end process reset_proc;\n\n -- purpose: main test loop\n -- type : combinational\n -- inputs : \n -- outputs: \n tester : process is\n\n begin -- process tester\n cmd <= \"0110\"; -- 16 bit to float32 mode\n in1 <= \"10000000000000000000001000101111\"; -- 4.33 ufixed\n in2 <= \"00000000000000000000000000000100\"; -- 4\n floop1: for i in 1 to 100 loop\n wait for clock_period;\n end loop floop1;\n cmd <= \"0110\"; -- 16 bit to float32 mode\n in1 <= \"10000000000000000000001000101011\"; -- 4.33 ufixed\n in2 <= \"00000000000000000000000000000100\"; -- 4\n floop2: for i in 1 to 100 loop\n wait for clock_period;\n end loop floop2;\n cmd <= \"0010\";\n in1 <= reverse(\"00000000000000000000101100000010\"); -- 6.5\n in2 <= reverse(\"00000000000000000001010001000010\"); -- 42\n wait for clock_period;\n in1 <= reverse(\"00000000000000000001010001000010\"); -- 42\n in2 <= reverse(\"00000000000000000000101100000010\"); -- 6.5\n wait for clock_period;\n in1 <= reverse(\"00000000000000000000101100000010\"); -- 6.5\n in2 <= reverse(\"00000000000000000000101100000010\"); -- 6.5\n wait for clock_period;\n in1 <= reverse(\"00000000000000000001010001000010\"); -- 42\n in2 <= \"01000000000000000000000000000000\"; -- 2\n wait for clock_period;\n in1 <= \"00111110101010101010101010101011\"; -- 1/3\n in2 <= \"01000000000000000000000000000000\"; -- 2\n wait for clock_period;\n in1 <= reverse(\"00000000000000000001010001000010\"); -- 42\n in2 <= reverse(\"00000000000000000000101100000011\"); -- -6.5\n wait for clock_period;\n in1 <= reverse(\"10000000000000000000000000000000\"); -- 2**-149\n in2 <= \"11000000000000000000000000000000\"; -- -2.0\n wait for clock_period;\n in1 <= reverse(\"00000000000000000000001000000000\"); -- 2**-127\n in2 <= \"00111110100000000000000000000000\"; -- 0.25\n wait for clock_period;\n in1 <= reverse(\"00000000000000000001010001000010\"); -- 42\n in2 <= reverse(\"00000000000000000000101100000010\"); -- 6.5\n wait for clock_period;\n cmd <= \"0001\"; -- subtract mode\n in2 <= \"01001011111001110011000110011011\"; -- 30303030\n in1 <= \"01001011111001110011000110011100\"; -- 30303033\n wait for clock_period;\n in1 <= reverse(\"00000000000000000000101100000010\"); -- 6.5\n in2 <= \"01000000100000000000000000000000\"; -- 4\n wait for clock_period;\n in2 <= reverse(\"00000000000000000000101100000010\"); -- 6.5\n in1 <= \"01000000100000000000000000000000\"; -- 4\n wait for clock_period;\n in1 <= \"01000000100010101010101010101011\"; -- 4.333333\n in2 <= \"00111110101010101010101010101011\"; -- 1/3\n wait for clock_period;\n cmd <= \"0000\"; -- add mode\n in1 <= \"00111110101010101010101010101011\"; -- 1/3\n in2 <= \"01000000000000000000000000000000\"; -- 2\n wait for clock_period;\n in2 <= \"00111110101010101010101010101011\"; -- 1/3\n in1 <= \"01000000000000000000000000000000\"; -- 2\n wait for clock_period;\n in1 <= \"00000000100000000000000000000001\"; -- 2**-126\n in2 <= \"01000000100000000000000000000001\"; -- 4+\n wait for clock_period;\n cmd <= \"0011\"; -- divide mode\n in1 <= \"00111111100000000000000000000000\"; -- 1.0\n in2 <= \"01000000010000000000000000000000\"; -- 3.0\n wait for clock_period;\n in1 <= \"01001100000011001011110001001111\"; -- 36892987\n in2 <= \"00000000010000000000000000000000\"; -- 2**-127\n wait for clock_period;\n in1 <= \"10111110101010101010101010101011\"; -- -1/3\n in2 <= \"01000000000000000000000000000000\"; -- 2\n wait for clock_period;\n cmd <= \"0100\"; -- 32 to 16 conversion mode\n in1 <= \"00111111100000000000000000000000\"; -- 1.0\n in2 <= (others => '0');\n wait for clock_period;\n in1 <= \"10111110101010101010101010101011\"; -- -1/3, no round\n wait for clock_period;\n in1 <= \"10111110101010101010101010101011\"; -- -1/3\n in2 <= \"00000000000000000000000000000001\"; -- opcode 1\n wait for clock_period;\n cmd <= \"0101\"; -- conversion mode\n in1 <= \"00111111100000000000000000000000\"; -- 1.0\n in2 <= \"01000000000000000000000000000000\"; -- opcode zero\n wait for clock_period;\n in1 <= \"01000010001010000000000000000000\"; -- 42.0\n in2 <= \"00000000000000000000000000000001\"; -- opcode 1\n wait for clock_period;\n in1 <= \"10111111100000000000000000000000\"; -- -1.0\n in2 <= \"00000000000000000000000000000010\"; -- 2\n wait for clock_period;\n in1 <= \"00111111100000000000000000000000\"; -- 1.0\n in2 <= \"00000000000000000000000000000011\"; -- 3\n wait for clock_period;\n in1 <= \"01000000100010101010101010101011\"; -- 4.333333\n in2 <= \"00000000000000000000000000000100\"; -- 4\n wait for clock_period;\n in1 <= \"00111111100000000000000000000000\"; -- 1.0\n in2 <= \"00000000000000000000000000000101\"; -- 5\n wait for clock_period;\n in1 <= \"11000000100010101010101010101011\"; -- -4.333333\n in2 <= \"00000000000000000000000000000110\"; -- 6 to_sfixed\n wait for clock_period;\n in1 <= \"00111111100000000000000000000000\"; -- 1.0\n in2 <= \"00000000000000000000000000000111\"; -- 7 to_sfixed\n wait for clock_period;\n cmd <= \"0110\"; -- 16 bit to float32 mode\n in1 <= \"00000000000000000000000000000011\"; -- 3\n in2 <= \"01000000000000000000000000000000\"; -- mode 0\n wait for clock_period;\n in1 <= \"00000000000000000000000000000100\"; -- 4\n in2 <= \"01000000000000000000000000000001\"; -- 1\n wait for clock_period;\n in1 <= \"00000000000000001111111111111110\"; -- -2\n in2 <= \"01000000000000000000000000000010\"; -- 2 to_float(signed)\n wait for clock_period;\n in1 <= \"00000000000000000000000000000100\"; -- 4\n in2 <= \"01000000000000000000000000000011\"; -- mode 3\n wait for clock_period;\n in1 <= \"10000000000000000000001000101011\"; -- 4.33 ufixed\n in2 <= \"00000000000000000000000000000100\"; -- 4\n wait for clock_period;\n in1 <= \"10100000000000000000000010000000\"; -- 1.0 ufixed\n in2 <= \"00000000000000000000000000000101\"; -- 5\n wait for clock_period;\n in1 <= \"11000000000000001111110111010101\"; -- -4.333 sfixed\n in2 <= \"00000000000000000000000000000110\"; -- 6\n wait for clock_period;\n in1 <= \"10100000000000000000000010000000\"; -- 1.0 sfixed\n in2 <= \"00000000000000000000000000000111\"; -- 7\n wait for clock_period;\n cmd <= \"0111\"; -- Mod\n in1 <= \"00000000000000000000000000000011\"; -- \n in2 <= \"00000000000000000000000000000011\"; -- \n wait for clock_period;\n in1 <= \"00000010001100101111000100111011\"; -- 36892987\n in2 <= \"00000010001100101111000100111011\"; -- 36892987\n wait for clock_period;\n in1 <= \"11000000100010101010101010101011\"; -- -4.333333\n in2 <= \"01000000100000000000000000000000\"; -- 4\n wait for clock_period;\n cmd <= \"1000\"; -- rem\n in1 <= \"00000000000000000000000000000011\"; -- \n in2 <= \"00000000000000000000000000000011\"; -- \n wait for clock_period;\n in1 <= \"00000010001100101111000100111011\"; -- 36892987\n in2 <= \"00000010001100101111000100111011\"; -- 36892987\n wait for clock_period;\n in1 <= \"11000000100010101010101010101011\"; -- -4.333333\n in2 <= \"01000000100000000000000000000000\"; -- 4\n wait for clock_period;\n cmd <= \"1001\"; -- constants conversion\n in2 <= \"11000000000000000000000000000000\"; -- command 0\n wait for clock_period;\n in2 <= \"11000000000000000000000000000001\"; -- command 1\n wait for clock_period;\n in2 <= \"11000000000000000000000000000010\"; -- command 2\n wait for clock_period;\n in2 <= \"11000000000000000000000000000011\"; -- command 3\n wait for clock_period;\n in2 <= \"11000000000000000000000000000100\"; -- command 4\n wait for clock_period;\n in2 <= \"11000000000000000000000000000101\"; -- command 5\n wait for clock_period;\n in2 <= \"11000000000000000000000000000110\"; -- command 6\n wait for clock_period;\n in2 <= \"11000000000000000000000000000111\"; -- command 7\n wait for clock_period;\n cmd <= \"1010\"; -- conversions\n in1 <= to_float (1, in1);\n in2 <= \"11000000000000000000000000000000\"; -- command 0\n wait for clock_period;\n in1 <= to_float (-2, in1);\n wait for clock_period;\n in2 <= \"11000000000000000000000000000001\"; -- command 1\n wait for clock_period;\n in1 <= to_float (1, in1);\n wait for clock_period;\n in2 <= \"00010000000000000000000000000010\"; -- command 2 scalb\n in1 <= to_float (1, in1);\n wait for clock_period;\n in2 <= \"11110000000000000000000000000010\"; -- command 2 scalb\n in1 <= to_float (1, in1);\n wait for clock_period;\n in2 <= \"11000000000000000000000000000011\"; -- command 3 logb\n in1 <= to_float (1, in1);\n wait for clock_period;\n in2 <= \"11000000000000000000000000000011\"; -- command 3 logb\n in1 <= to_float (0.25, in1);\n wait for clock_period;\n in2 <= \"11000000000000000000000000000100\"; -- 4 nextafter\n in1 <= to_float (1, in1);\n wait for clock_period;\n in1 <= to_float (4, in1);\n wait for clock_period;\n in2 <= \"11000000000000000000000000000101\"; -- 5 nextafter\n in1 <= to_float (1, in1);\n wait for clock_period;\n in1 <= to_float (-4, in1);\n wait for clock_period;\n in2 <= \"11000000000000000000000000000110\"; -- 6 nextafter\n in1 <= to_float (1, in1);\n wait for clock_period;\n in1 <= to_float (4, in1);\n wait for clock_period;\n in2 <= \"11000000000000000000000000000111\"; -- 7 nextafter\n in1 <= to_float (1, in1);\n wait for clock_period;\n in1 <= to_float (-4, in1);\n wait for clock_period;\n cmd <= \"1011\"; -- copy sign\n in1 <= to_float (2, in1);\n in2 <= to_float (2, in1);\n wait for clock_period;\n in1 <= to_float (-3, in1);\n in2 <= to_float (3, in1);\n wait for clock_period;\n in1 <= to_float (4, in1);\n in2 <= to_float (-4, in1);\n wait for clock_period;\n in1 <= to_float (-5, in1);\n in2 <= to_float (-5, in1);\n wait for clock_period;\n cmd <= \"1100\"; -- compare test\n in1 <= to_float (15, in1);\n in2 <= to_float (15, in1);\n wait for clock_period;\n in1 <= to_float (15.5, in1);\n in2 <= to_float (-2, in1);\n wait for clock_period;\n in1 <= to_float (-2, in1);\n in2 <= to_float (2, in1);\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= to_float (-2, in1);\n wait for clock_period;\n in1 <= \"01111111100000000000000000000001\"; -- NAN\n in2 <= to_float (-2, in1);\n wait for clock_period;\n cmd <= \"1101\"; -- boolean test\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000000\"; -- command 0 , not\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000001\"; -- command 1, and\n wait for clock_period;\n in1 <= \"01111111000000000000000000000000\"; -- + inf\n in2 <= \"00111111000000000000000000000010\"; -- command 2, or\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000011\"; -- command 3, nand\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000100\"; -- command 4, nor\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000101\"; -- command 5, xor\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000110\"; -- command 6, xnor\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000111\"; -- command 7, xor '1'\n wait for clock_period;\n cmd <= \"1110\"; -- reduce and vector test test\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000000\"; -- command 0, \n wait for clock_period;\n in1 <= \"11111111111111111111111111111111\"; -- all 1\n wait for clock_period;\n in1 <= \"10000000000000000000000000000000\"; -- -0\n wait for clock_period;\n in1 <= \"00000000000000000000000000000000\"; -- 0\n wait for clock_period;\n in1 <= \"01111111100000000000000000000000\"; -- + inf\n in2 <= \"00111111100000000000000000000001\"; -- command 1, and '0'\n wait for clock_period;\n in2 <= \"10111111100000000000000000000001\"; -- command 1, and '1'\n wait for clock_period;\n in2 <= \"00111111100000000000000000000010\"; -- command 2, or '0'\n wait for clock_period;\n in2 <= \"10111111100000000000000000000010\"; -- command 2, or '1'\n wait for clock_period;\n in2 <= \"00111111100000000000000000000011\"; -- command 3, nand '0'\n wait for clock_period;\n in2 <= \"10111111100000000000000000000011\"; -- command 3, nand '1'\n wait for clock_period;\n in2 <= \"00111111100000000000000000000100\"; -- command 4, nor '0'\n wait for clock_period;\n in2 <= \"10111111100000000000000000000100\"; -- command 4, nor '1'\n wait for clock_period;\n in2 <= \"00111111100000000000000000000101\"; -- command 5, xor '0'\n wait for clock_period;\n in2 <= \"10111111100000000000000000000101\"; -- command 5, xor '1'\n wait for clock_period;\n in2 <= \"00111111100000000000000000000110\"; -- command 6, xnor '0'\n wait for clock_period;\n in2 <= \"10111111100000000000000000000110\"; -- command 6, xnor '1'\n wait for clock_period;\n in2 <= \"00111111100000000000000000000111\"; -- command 7, and '0'\n wait for clock_period;\n in2 <= \"10111111100000000000000000000111\"; -- command 7, and '1'\n wait for clock_period;\n cmd <= \"1111\"; -- add and mult by constant\n in2 <= \"10111111100000000000000000000000\"; -- command 0, + 1\n in1 <= to_float (2, in1);\n wait for clock_period;\n in2 <= \"10111111100000000000000000000001\"; -- command 1, 1 +\n wait for clock_period;\n in2 <= \"10111111100000000000000000000010\"; -- command 2, + 1.0\n wait for clock_period;\n in2 <= \"10111111100000000000000000000011\"; -- command 3, 1.0 +\n wait for clock_period;\n in2 <= \"10111111100000000000000000000100\"; -- command 4, * 1\n wait for clock_period;\n in2 <= \"10111111100000000000000000000101\"; -- command 5, 1 *\n wait for clock_period;\n in2 <= \"10111111100000000000000000000110\"; -- command 6, * 1.0\n wait for clock_period;\n in2 <= \"10111111100000000000000000000111\"; -- command 7, 1.0 *\n wait for clock_period;\n\n\n wait for clock_period;\n cmd <= \"0000\"; -- add mode\n in1 <= (others => '0');\n in2 <= (others => '0');\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait for clock_period;\n wait;\n end process tester;\n\n -- purpose: check the output of the tester\n -- type : combinational\n -- inputs : \n -- outputs: \n checktest : process is\n variable out16, out16t : fp16; -- 16 bit fp variables\n variable out1t, out2t : float32; -- 32 bit float\n variable s16, s16t : SIGNED(7 downto 0); -- 7 bit SIGNED\n variable latency : INTEGER := 0;\n begin -- process checktest\n wait for clock_period/2.0;\n floop3: for i in 1 to 100 loop\n wait for clock_period;\n end loop floop3;\n latency := 0;\n out2t := \"01000000100010101100000000000000\";\n wl1: while out1 /= out2t loop\n wait for clock_period;\n latency := latency + 1;\n assert latency /= 100 report \"After 100 loops, pattern never found\"\n severity failure;\n end loop wl1;\n report \"Latency was \" & INTEGER'image(latency) severity note;\n floop4: for i in 1 to 100 loop\n wait for clock_period;\n end loop floop4;\n report_error (\"42 * 6.5 error\",\n out1,\n to_float (273, out1));\n wait for clock_period;\n report_error (\"6.5 * 42 error\",\n out1,\n to_float (273, out1'high, -out1'low));\n wait for clock_period;\n report_error (\"Multiply 42.25 miscompare\",\n out1,\n \"01000010001010010000000000000000\"); -- 42.25\n wait for clock_period;\n report_error (\"Multiply 84 miscompare\",\n out1,\n \"01000010101010000000000000000000\"); -- 84\n wait for clock_period;\n report_error (\"Multiply 2/3 miscompare\",\n out1,\n \"00111111001010101010101010101011\"); -- 2/3\n wait for clock_period;\n report_error (\"Multiply -273 miscompare\",\n out1,\n \"11000011100010001000000000000000\"); -- -273\n wait for clock_period;\n report_error (\"mult 2**-148 test miscompare\",\n out1,\n reverse(\"01000000000000000000000000000001\")); -- -2*-148\n wait for clock_period;\n report_error (\"Multiply 2**-129 miscompare\",\n out1,\n reverse(\"00000000000000000000100000000000\")); -- 2**-129\n wait for clock_period;\n report_error (\"6.5 * 42 error\",\n out1,\n to_float (273, out1));\n wait for clock_period;\n report_error (\"Subtract 30303033 - 30303030 miscompare\",\n out1,\n \"01000000000000000000000000000000\"); -- 2 (not 3, rounding)\n wait for clock_period;\n report_error (\"Subtract 6.5 - 4 miscompare\",\n out1,\n \"01000000001000000000000000000000\"); -- 2.5\n wait for clock_period;\n report_error (\"Subtract 4 - 6.5 miscompare\",\n out1,\n \"11000000001000000000000000000000\"); -- -2.5\n wait for clock_period;\n report_error (\"Subtract 4.333 - 1/3 miscompare\",\n out1,\n \"01000000100000000000000000000000\"); -- 4\n wait for clock_period;\n report_error (\"Add 2.333 miscompare\",\n out1,\n \"01000000000101010101010101010101\"); -- 2.333333\n wait for clock_period;\n report_error (\"Add 2.333 rev miscompare\",\n out1,\n \"01000000000101010101010101010101\"); -- 2.333333\n wait for clock_period;\n report_error (\"Add 4 + miscompare\",\n out1,\n \"01000000100000000000000000000001\"); -- 4\n wait for clock_period;\n report_error (\"div 1/3 test miscompare\",\n out1,\n \"00111110101010101010101010101011\"); -- 1/3\n wait for clock_period;\n report_error (\"div 369297/2**-126 test miscompare\",\n out1,\n \"01111111100000000000000000000000\");\n wait for clock_period;\n report_error (\"-1/6 test miscompare\",\n out1, \"10111110001010101010101010101011\"); -- -1/6\n wait for clock_period;\n -- resize function\n out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);\n out16t := to_float (1, out16t);\n report_error16 (\"1.0 fp16 converserion\",\n out16, out16t);\n wait for clock_period;\n out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);\n out16t := to_float (arg => -1.0/3.0, size_res => out16t,\n round_style => round_zero);\n report_error16 (\"-1/3 not rounded fp16 converserion\",\n out16, out16t);\n wait for clock_period;\n out16 := to_float (to_slv (out1(-8 downto -23)), 6, 9);\n out16t := to_float (-1.0/3.0, out16t);\n report_error16 (\"-1/3 fp16 converserion\",\n out16, out16t);\n -- conversion test\n wait for clock_period;\n report_error (\"1.0 to unsigned miscompare\",\n out1, \"00000000000000000000000000000001\");\n wait for clock_period;\n report_error (\"42 to unsigned miscompare\",\n out1, \"00100000000000000000000000101010\");\n wait for clock_period;\n report_error (\"-1.0 to signed miscompare\",\n out1, \"01000000000000001111111111111111\");\n wait for clock_period;\n report_error (\"1.0 to signed miscompare\",\n out1, \"01100000000000000000000000000001\");\n wait for clock_period;\n report_error (\"4.33 to ufixed miscompare\",\n out1, \"10000000000000000000001000101011\");\n wait for clock_period;\n report_error (\"1.0 to ufixed miscompare\",\n out1, \"10100000000000000000000010000000\");\n wait for clock_period;\n report_error (\"4.333 to sfixed miscompare\",\n out1, \"11000000000000001111110111010101\");\n wait for clock_period;\n report_error (\"1.0 to sfixed miscompare\",\n out1, \"11100000000000000000000010000000\");\n wait for clock_period;\n report_error (\"unsigned 3 to float miscompare\",\n out1, to_float(3, out1));\n wait for clock_period;\n report_error (\"unsigned 4 to float miscompare\",\n out1, to_float(4, out1));\n wait for clock_period;\n report_error (\"signed -2 to float miscompare\",\n out1, to_float(-2, out1));\n wait for clock_period;\n report_error (\"signed 4 to float miscompare\",\n out1, to_float(4, out1));\n wait for clock_period;\n report_error (\"ufixed 4.333 to float miscompare\",\n out1, \"01000000100010101100000000000000\"); -- 4.333333 \n wait for clock_period;\n report_error (\"ufixed 1.0 to float miscompare\",\n out1, \"00111111100000000000000000000000\"); -- 1.0 \n wait for clock_period;\n report_error (\"sfixed -4.333 to float miscompare\",\n out1, \"11000000100010101100000000000000\"); -- -4.333333\n wait for clock_period;\n report_error (\"sfixed 1.0 to float miscompare\",\n out1, \"00111111100000000000000000000000\"); -- 1.0\n wait for clock_period;\n report_error (\"denormal mod denormal miscompare\",\n out1, zero0);\n wait for clock_period;\n report_error (\"large mod large miscompare\",\n out1, zero0);\n wait for clock_period;\n report_error (\"-4.333 mod 4 miscompare\",\n out1,\n from_string (\"01000000011010101010101010101010\", out1));\n wait for clock_period;\n report_error (\"denormal rem denormal miscompare\",\n out1, zero0);\n wait for clock_period;\n report_error (\"large rem large miscompare\",\n out1, zero0);\n wait for clock_period;\n out1t := \"10111110101010101010101010110000\";\n report_error (\"-4.333 rem 4 miscompare\",\n out1, out1t);\n wait for clock_period;\n report_error (\"to_float(0) miscompare\",\n out1, zero0);\n wait for clock_period;\n report_error (\"to_float(0.0) miscompare\",\n out1, zero0);\n wait for clock_period;\n report_error (\"to_float(8) miscompare\",\n out1, to_float(8.0, out1));\n wait for clock_period;\n report_error (\"to_float(8.0) miscompare\",\n out1, to_float(8, out1)); \n wait for clock_period;\n report_error (\"to_float(-8) miscompare\",\n out1, to_float(-8.0, out1));\n wait for clock_period;\n report_error (\"to_float(-8.0) miscompare\",\n out1, to_float(-8, out1)); \n wait for clock_period;\n report_error (\"to_float(27000) miscompare\",\n out1, to_float(27000.0, out1));\n wait for clock_period;\n report_error (\"to_float(PI) miscompare\",\n out1, to_float(3.141592653589, out1));\n -- Conversion test\n wait for clock_period;\n report_error (\"-1 miscompare\",\n out1, to_float(-1, out1));\n wait for clock_period;\n report_error (\"-(-2) miscompare\",\n out1, to_float(2, out1));\n wait for clock_period;\n report_error (\"abs(-2) miscompare\",\n out1, to_float(2, out1));\n wait for clock_period;\n report_error (\"abs(1) miscompare\",\n out1, to_float(1, out1));\n wait for clock_period;\n report_error (\"scalb (1, 1) miscompare\",\n out1, to_float(2, out1));\n wait for clock_period;\n report_error (\"scalb (1, -1) miscompare\",\n out1, to_float(0.5, out1));\n wait for clock_period;\n s16 := SIGNED (to_slv (out1(-16 downto -23)));\n assert (s16 = 0) report \"logb (1) returned \"\n & to_string(to_sfixed(s16)) severity error;\n wait for clock_period;\n s16 := SIGNED (to_slv (out1(-16 downto -23)));\n assert (s16 = -2) report \"logb (0.25) returned \"\n & to_string(to_sfixed(s16)) severity error;\n wait for clock_period;\n out1t := \"00111111100000000000000000000001\";\n report_error (\"nextafter (1, 1.5)\", out1, out1t);\n wait for clock_period;\n out1t := \"01000000011111111111111111111111\";\n report_error (\"nextafter (4, 1.5)\", out1, out1t);\n wait for clock_period;\n out1t := \"00111111011111111111111111111111\";\n report_error (\"nextafter (1, -1.5)\", out1, out1t);\n wait for clock_period;\n out1t := \"11000000011111111111111111111111\";\n report_error (\"nextafter (-4, -1.5)\", out1, out1t);\n wait for clock_period;\n out1t := \"00111111100000000000000000000001\";\n report_error (\"nextafter (1, inf)\", out1, out1t);\n wait for clock_period;\n out1t := \"01000000100000000000000000000001\";\n report_error (\"nextafter (4, inf)\", out1, out1t);\n wait for clock_period;\n out1t := \"00111111011111111111111111111111\";\n report_error (\"nextafter (1, neginf)\", out1, out1t);\n wait for clock_period;\n out1t := \"11000000100000000000000000000001\";\n report_error (\"nextafter (-4, neginf)\", out1, out1t);\n wait for clock_period;\n report_error (\"Copysign (2,2)\", out1, to_float(2, out1));\n wait for clock_period;\n report_error (\"Copysign (-3,3)\", out1, to_float(3, out1));\n wait for clock_period;\n report_error (\"Copysign (4,-4)\", out1, to_float(-4, out1));\n wait for clock_period;\n report_error (\"Copysign (-5,-5)\", out1, to_float(-5, out1));\n wait for clock_period;\n out1t := \"10001110000000000000000000000000\";\n report_error (\"compare test 15, 15\", out1, out1t);\n wait for clock_period;\n out1t := \"01101001000000000000000000000000\";\n report_error (\"compare test 15.5, -2\", out1, out1t);\n wait for clock_period;\n out1t := \"01010100000000000000000000000000\";\n report_error (\"compare test -2, 2\", out1, out1t);\n wait for clock_period;\n out1t := \"01101000010000000000000000000000\";\n report_error (\"compare test inf, -2\", out1, out1t);\n wait for clock_period;\n out1t := \"01000000101000000000000000000000\";\n report_error (\"compare test NAN, -2\", out1, out1t);\n wait for clock_period;\n out1t := \"10000000011111111111111111111111\"; -- not + inf\n report_error (\"not +inf\", out1, out1t);\n wait for clock_period;\n out1t := \"00111111100000000000000000000000\"; -- and\n report_error (\"and +inf\", out1, out1t);\n wait for clock_period;\n out1t := \"01111111000000000000000000000010\"; -- or\n report_error (\"or +inf\", out1, out1t);\n wait for clock_period;\n out1t := \"11000000011111111111111111111111\"; -- nand\n report_error (\"nand +inf\", out1, out1t);\n wait for clock_period;\n out1t := \"10000000011111111111111111111011\"; -- nor\n report_error (\"nor +inf\", out1, out1t);\n wait for clock_period;\n out1t := \"01000000000000000000000000000101\"; -- xor\n report_error (\"xor +inf\", out1, out1t);\n wait for clock_period;\n out1t := \"10111111111111111111111111111001\"; -- xnor\n report_error (\"xnor +inf\", out1, out1t);\n wait for clock_period;\n out1t := \"10000000011111111111111111111111\"; -- xnor '1'\n report_error (\"+inf xor '1'\", out1, out1t);\n wait for clock_period;\n out1t := \"01100100000000000000000000000000\"; -- reduce test\n report_error (\"_reduce test\", out1, out1t);\n wait for clock_period;\n out1t := \"10100100000000000000000000000000\"; -- reduce test\n report_error (\"_reduce all 1 test\", out1, out1t);\n wait for clock_period;\n out1t := \"01101000000000000000000000000000\"; -- reduce test\n report_error (\"_reduce -0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"01010100000000000000000000000000\"; -- reduce test\n report_error (\"_reduce 0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"00000000000000000000000000000000\"; -- 0\n report_error (\"and 0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"01111111100000000000000000000000\"; -- + inf\n report_error (\"and 1 test\", out1, out1t);\n wait for clock_period;\n out1t := \"01111111100000000000000000000000\"; -- + inf\n report_error (\"or 0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"11111111111111111111111111111111\"; -- all 1\n assert (to_slv (out1) = to_slv (out1t))\n report \"or 1 test error \" & to_string (out1) & \" /= \"\n & to_string (out1t) severity error;\n wait for clock_period;\n out1t := \"11111111111111111111111111111111\"; -- all 1\n assert (to_slv (out1) = to_slv (out1t))\n report \"nand 0 test error \" & to_string (out1) & \" /= \"\n & to_string (out1t) severity error;\n wait for clock_period;\n out1t := \"10000000011111111111111111111111\"; -- - denormal\n report_error (\"nand 1 test\", out1, out1t);\n wait for clock_period;\n out1t := \"10000000011111111111111111111111\"; -- - denormal\n report_error (\"nor 0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"00000000000000000000000000000000\"; -- 0\n report_error (\"nor 1 test\", out1, out1t);\n wait for clock_period;\n out1t := \"01111111100000000000000000000000\"; -- + inf\n report_error (\"xor 0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"10000000011111111111111111111111\"; -- - denormal\n report_error (\"xor 1 test\", out1, out1t);\n wait for clock_period;\n out1t := \"10000000011111111111111111111111\"; -- - denormal\n report_error (\"xnor 0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"01111111100000000000000000000000\"; -- + inf\n report_error (\"xnor 1 test\", out1, out1t);\n wait for clock_period;\n out1t := \"00000000000000000000000000000000\"; -- 0\n report_error (\"and 0 test\", out1, out1t);\n wait for clock_period;\n out1t := \"01111111100000000000000000000000\"; -- + inf\n report_error (\"and 1 test\", out1, out1t);\n wait for clock_period;\n out1t := to_float(3, out1t);\n report_error (\"2 + 1 test\", out1, out1t);\n wait for clock_period;\n report_error (\"1 + 2 test\", out1, out1t);\n wait for clock_period;\n report_error (\"2 + 1.0 test\", out1, out1t);\n wait for clock_period;\n report_error (\"1.0 + 2 test\", out1, out1t);\n wait for clock_period;\n out1t := to_float(2, out1t);\n report_error (\"2 * 1 test\", out1, out1t);\n wait for clock_period;\n report_error (\"1 * 2 test\", out1, out1t);\n wait for clock_period;\n report_error (\"2 * 1.0 test\", out1, out1t);\n wait for clock_period;\n report_error (\"1.0 * 2 test\", out1, out1t);\n\n wait for clock_period;\n assert (false) report \"Testing complete\" severity note;\n stop_clock <= true;\n wait;\n end process checktest;\nend architecture testbench;\n", "groundtruth": " if (not stop_clock) then\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/ConvLayer.vhd", "left_context": "------------------------------------------------------------------------------\n-- Title : convElement\n-- Project : Haddoc2\n------------------------------------------------------------------------------\n-- File : convElement.vhd\n-- Author : K. Abdelouahab\n-- Company : Institut Pascal\n-- Last update: 2018-08-23\n------------------------------------------------------------------------------\n-- Description: A fully pipelined implementation of CNN layers that is able to process\n-- one pixel/clock cycle. Each actors of a CNN graph are directly mapped\n-- on the hardware following the principals of DHM and DataFlow processing\n-- ______\n-- | |\n-- | |-- output_streams-->\n-- input_streams---->| conv |-- output_streams-->\n-- input_streams---->| Layer |-- output_streams-->\n-- input_streams---->| |-- output_streams-->\n-- input_streams---->| |-- output_streams-->\n-- | |-- output_streams-->\n-- ______\n-----------------------------------------------------------------------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_signed.all;\nuse ieee.math_real.all;\nlibrary work;\nuse work.cnn_types.all;\n\n\nentity ConvLayer is\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n SUM_WIDTH : integer;\n KERNEL_SIZE : integer;\n NB_IN_FLOWS : integer;\n NB_OUT_FLOWS : integer;\n KERNEL_VALUE : pixel_matrix;\n BIAS_VALUE : pixel_array\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array(0 to NB_IN_FLOWS - 1);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out pixel_array(0 to NB_OUT_FLOWS - 1);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend entity;\n\narchitecture STRUCTURAL of ConvLayer is\n --------------------------------------------------------------------------------\n -- COMPONENTS\n --------------------------------------------------------------------------------\n component TensorExtractor\n generic (\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer;\n NB_IN_FLOWS : integer\n );\n port (\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array (0 to NB_IN_FLOWS - 1);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out pixel_array (0 to NB_IN_FLOWS * KERNEL_SIZE * KERNEL_SIZE- 1);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\n end component TensorExtractor;\n\n component DotProduct\n generic (\n BITWIDTH : integer;\n SUM_WIDTH : integer;\n DOT_PRODUCT_SIZE : integer;\n KERNEL_VALUE : pixel_array;\n BIAS_VALUE : std_logic_vector\n );\n port (\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array (0 to DOT_PRODUCT_SIZE - 1);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (SUM_WIDTH-1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\n end component DotProduct;\n\n\n component TanhLayer\n generic (\n BITWIDTH : integer;\n SUM_WIDTH : integer\n );\n port (\n in_data : in std_logic_vector (SUM_WIDTH-1 downto 0);\n out_data : out std_logic_vector (BITWIDTH-1 downto 0)\n );\n end component TanhLayer;\n ------------------------------------------------------------------------------------------\n signal neighborhood_data : pixel_array (0 to NB_IN_FLOWS * KERNEL_SIZE * KERNEL_SIZE- 1);\n signal neighborhood_dv : std_logic;\n signal neighborhood_fv : std_logic;\n signal dp_data : sum_array (0 to NB_OUT_FLOWS-1);\n signal dp_dv : std_logic;\n signal dp_fv : std_logic;\n-----------------------------------------------------------------------------------------\nbegin\n\n TensorExtractor_i : TensorExtractor\n", "right_context": " enable => enable,\n in_data => in_data,\n in_dv => in_dv,\n in_fv => in_fv,\n out_data => neighborhood_data,\n out_dv => neighborhood_dv,\n out_fv => neighborhood_fv\n );\n\n DotProduct_loop : for n in 0 to NB_OUT_FLOWS- 1 generate\n DotProduct_i : DotProduct\n generic map (\n BITWIDTH => BITWIDTH,\n SUM_WIDTH => SUM_WIDTH,\n DOT_PRODUCT_SIZE => NB_IN_FLOWS * KERNEL_SIZE * KERNEL_SIZE,\n BIAS_VALUE => BIAS_VALUE(n),\n KERNEL_VALUE => extractRow(n,\n NB_OUT_FLOWS, -- N\n NB_IN_FLOWS * KERNEL_SIZE * KERNEL_SIZE, -- CJK\n KERNEL_VALUE) --Theta(n)\n )\n port map (\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => neighborhood_data,\n in_dv => neighborhood_dv,\n in_fv => neighborhood_fv,\n out_data => dp_data(n),\n out_dv => open,\n out_fv => open\n );\n\n -- Dummy Activation\n TanhLayer_i : TanhLayer\n generic map (\n BITWIDTH => BITWIDTH,\n SUM_WIDTH => SUM_WIDTH\n )\n port map (\n in_data => dp_data(n),\n out_data => out_data(n)\n );\n\n out_dv <= in_dv;\n out_fv <= in_fv;\n end generate;\n\n\n\nend architecture;\n", "groundtruth": " generic map (\n BITWIDTH => BITWIDTH,\n IMAGE_WIDTH => IMAGE_WIDTH,\n KERNEL_SIZE => KERNEL_SIZE,\n NB_IN_FLOWS => NB_IN_FLOWS\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/DisplayLayer.vhd", "left_context": "------------------------------------------------------------------------------\n-- Title : DisplayLayer\n-- Project : Haddoc2\n------------------------------------------------------------------------------\n-- File : display_mux.vhd\n-- Author : K. Abdelouahab\n-- Company : Institut Pascal\n-- Last update: 2018-08-23\n------------------------------------------------------------------------------\n-- Description: A design of a multiplexer to be used at the end of a CNN. Can\n-- be used for display puposes\n------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\n\nlibrary work;\nuse work.cnn_types.all;\n\nentity DisplayLayer is\n generic(\n BITWIDTH : integer;\n NB_IN_FLOWS : integer\n );\n port(\n in_data : in pixel_array (0 to NB_IN_FLOWS-1);\n in_dv : in std_logic;\n in_fv : in std_logic;\n sel : in std_logic_vector(31 downto 0);\n out_data : out std_logic_vector(BITWIDTH-1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend entity;\n\narchitecture bhv of DisplayLayer is\n", "right_context": "", "groundtruth": "begin\n out_data <= in_data(to_integer(unsigned(sel)));\n out_dv <= in_dv;\n out_fv <= in_fv;\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/DotProduct.vhd", "left_context": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_signed.all;\nuse ieee.math_real.all;\nlibrary work;\nuse work.cnn_types.all;\n\nentity DotProduct is\n generic(\n BITWIDTH : integer;\n SUM_WIDTH : integer;\n DOT_PRODUCT_SIZE : integer;\n KERNEL_VALUE : pixel_array;\n BIAS_VALUE : std_logic_vector\n );\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array (0 to DOT_PRODUCT_SIZE - 1);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (SUM_WIDTH-1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend DotProduct;\n\narchitecture rtl of DotProduct is\n --------------------------------------------------------------\n ---- Implementation with the multiplier and adder components\n --------------------------------------------------------------\n component MCM\n generic (\n BITWIDTH : integer;\n DOT_PRODUCT_SIZE : integer;\n KERNEL_VALUE : pixel_array\n );\n port (\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array (0 to DOT_PRODUCT_SIZE - 1);\n in_valid : in std_logic;\n out_data : out prod_array (0 to DOT_PRODUCT_SIZE - 1);\n out_valid : out std_logic\n );\n end component MCM;\n --\n component MOA\n generic (\n BITWIDTH : integer;\n SUM_WIDTH : integer;\n NUM_OPERANDS : integer;\n BIAS_VALUE : std_logic_vector\n );\n port (\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in prod_array (0 to NUM_OPERANDS - 1);\n in_valid : in std_logic;\n out_data : out std_logic_vector (SUM_WIDTH-1 downto 0);\n out_valid : out std_logic\n );\n end component MOA;\n --\n signal p_prod_data : prod_array (0 to DOT_PRODUCT_SIZE - 1);\n signal p_prod_valid : std_logic;\n signal s_out_valid : std_logic;\n begin\n MCM_i : MCM\n generic map (\n BITWIDTH => BITWIDTH,\n DOT_PRODUCT_SIZE => DOT_PRODUCT_SIZE,\n KERNEL_VALUE => KERNEL_VALUE\n )\n port map (\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => in_data,\n in_valid => (in_dv and in_fv),\n out_data => p_prod_data,\n out_valid => p_prod_valid\n );\n MOA_i : MOA\n generic map (\n BITWIDTH => BITWIDTH,\n SUM_WIDTH => SUM_WIDTH,\n NUM_OPERANDS => DOT_PRODUCT_SIZE,\n BIAS_VALUE => BIAS_VALUE\n )\n port map (\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => p_prod_data,\n in_valid => p_prod_valid,\n out_data => out_data,\n", "right_context": "-- begin\n-- process(clk)\n-- begin\n-- if (reset_n = '0') then\n-- pip_acc <= (others => (others => '0'));\n-- out_dv <= '0';\n-- out_fv <= '0';\n--\n-- elsif(rising_edge(clk)) then\n-- if (enable = '1') then\n-- if (in_dv = '1' and in_fv = '1') then\n-- pip_acc(0)(2*BITWIDTH-1 downto 0) <= in_data(0) * KERNEL_VALUE(0);\n-- acc_loop : for i in 1 to DOT_PRODUCT_SIZE-1 loop\n-- pip_acc(i) <= pip_acc(i-1) + (in_data(i) * KERNEL_VALUE(i));\n-- end loop acc_loop;\n-- end if;\n-- out_dv <= in_dv;\n-- out_fv <= in_fv;\n-- end if;\n-- end if;\n-- end process;\n-- out_data <= pip_acc(DOT_PRODUCT_SIZE-1) + BIAS_VALUE;\nend architecture;\n", "groundtruth": " out_valid => s_out_valid\n );\n out_dv <= s_out_valid;\n out_fv <= s_out_valid;\n\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/InputLayer.vhd", "left_context": "-- Converts the camera output to signals usable by Haddoc layers\n-- TODO : Support a variable PIXEL_BIT_WIDTH\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_signed.all;\n\nlibrary work;\nuse work.cnn_types.all;\n\nentity InputLayer is\n generic(\n BITWIDTH : integer; -- Bit-width of the activations and FMs\n INPUT_BIT_WIDTH : integer; -- Bit-width of the input pixel\n NB_OUT_FLOWS : integer -- Number of channels in input\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector(INPUT_BIT_WIDTH-1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out pixel_array(0 to NB_OUT_FLOWS-1);\n out_dv : out std_logic;\n out_fv : out std_logic\n\n );\nend entity;\n\narchitecture bhv of InputLayer is\nbegin\n MONOCHROME_INPUT : if NB_OUT_FLOWS = 1 generate\n -- Grayscale input\n process(clk)\n begin\n if (reset_n = '0') then\n out_data <= (others => (others => '0'));\n else\n if (enable = '1') then\n out_data(0) <= '0' & in_data(INPUT_BIT_WIDTH-1 downto INPUT_BIT_WIDTH-BITWIDTH+1);\n end if;\n out_dv <= in_dv;\n", "right_context": " end if;\n end process;\n end generate MONOCHROME_INPUT;\n\n COLOR_INPUT : if NB_OUT_FLOWS = 3 generate\n -- RGB 8 bits color depth\n process(clk)\n begin\n if (reset_n = '0') then\n out_data <= (others => (others => '0'));\n else\n if (enable = '1') then\n -- MSBs of each channel\n out_data(0) <= '0' & in_data(INPUT_BIT_WIDTH/1-1 downto INPUT_BIT_WIDTH/1-BITWIDTH+1);\n out_data(1) <= '0' & in_data(INPUT_BIT_WIDTH/2-1 downto INPUT_BIT_WIDTH/2-BITWIDTH+1);\n out_data(2) <= '0' & in_data(INPUT_BIT_WIDTH/3-1 downto INPUT_BIT_WIDTH/3-BITWIDTH+1);\n end if;\n out_dv <= in_dv;\n out_fv <= in_fv;\n end if;\n end process;\n end generate COLOR_INPUT;\nend bhv;\n", "groundtruth": " out_fv <= in_fv;\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/MCM.vhd", "left_context": "-- Implementation of a Multiple-Constant-Multiplier:\n-- This IP multiplies an input array with CONSTANT coefficients (3D convolution kernels)\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_signed.all;\nuse ieee.math_real.all;\nlibrary work;\nuse work.cnn_types.all;\n\nentity MCM is\n generic(\n BITWIDTH : integer;\n DOT_PRODUCT_SIZE : integer;\n KERNEL_VALUE : pixel_array\n );\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array (0 to DOT_PRODUCT_SIZE - 1);\n in_valid : in std_logic;\n out_data : out prod_array (0 to DOT_PRODUCT_SIZE - 1);\n out_valid : out std_logic\n );\nend MCM;\n\narchitecture rtl of MCM is\n -- Generate DOT_PRODUCT_SIZE Multipliers\n signal mult : prod_array (0 to DOT_PRODUCT_SIZE - 1);\n\nbegin\n ---------------------------------\n -- Assynchronous implmentation --\n ---------------------------------\n -- mcm_loop : for i in 0 to DOT_PRODUCT_SIZE - 1 generate\n -- out_data(i) <= KERNEL_VALUE(i) * in_data(i);\n -- end generate mcm_loop;\n -- out_valid <= in_valid;\n\n ---------------------------------\n -- synchronous implmentation --\n ---------------------------------\n\n process(clk)\n begin\n if(reset_n = '0') then\n out_data <= (others => (others => '0'));\n out_valid <= '0';\n elsif (rising_edge(clk) and enable = '1') then\n", "right_context": " out_valid <= in_valid;\n end if;\n end process;\n\nend architecture;\n", "groundtruth": " if (in_valid = '1') then\n mcm_loop : for i in 0 to DOT_PRODUCT_SIZE - 1 loop\n out_data(i) <= KERNEL_VALUE(i) * in_data(i);\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/MOA.vhd", "left_context": "-- Design of a Multi-Operand-Adder block\n-- This is a naive implementation with binary adder trees\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_signed.all;\nlibrary work;\nuse work.cnn_types.all;\n\nentity MOA is\n generic(\n BITWIDTH : integer;\n SUM_WIDTH : integer;\n NUM_OPERANDS : integer;\n BIAS_VALUE : std_logic_vector\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in prod_array (0 to NUM_OPERANDS - 1);\n in_valid : in std_logic;\n out_data : out std_logic_vector (SUM_WIDTH-1 downto 0);\n out_valid : out std_logic\n );\nend MOA;\n\n\narchitecture rtl of MOA is\n-- Implementation of Multi Operand Adder with Adder trees\n\n-----------------------------------\n-- Removing MOA to Evaluate FMax --\n-----------------------------------\n-- begin\n-- out_valid <= in_valid;\n-- out_data <= \"00000000\" & in_data(0);\n-- end architecture;\n\n\n---------------------------------\n-- Assynchronous implmentation --\n---------------------------------\n--signal s_acc : std_logic_vector (SUM_WIDTH-1 downto 0);\n--signal pip_acc : prod_array (0 to NUM_OPERANDS - 1);\n--begin\n-- add_process : process(clk)\n-- variable v_acc : std_logic_vector (SUM_WIDTH-1 downto 0) := (others => '0');\n-- begin\n-- if (reset_n = '0') then\n-- v_acc := (others => '0');\n-- out_valid <= '0';\n--\n-- elsif (rising_edge(clk)) then\n-- if (enable = '1') then\n-- if (in_valid = '1') then\n-- acc_loop : for i in 0 to NUM_OPERANDS-1 loop\n-- v_acc := v_acc + in_data(i);\n-- end loop acc_loop;\n-- v_acc := v_acc + BIAS_VALUE;\n-- end if;\n-- end if;\n-- s_acc <= v_acc;\n-- v_acc := (others => '0');\n-- out_valid <= in_valid;\n-- end if;\n-- end process;\n-- out_data <= s_acc;\n\n-----------------------------\n-- Pipelined implmentation --\n-----------------------------\n signal pip_acc : sum_array (0 to NUM_OPERANDS - 1) := (others => (others => '0'));\n begin\n process(clk)\n begin\n if (reset_n = '0') then\n pip_acc <= (others => (others => '0'));\n out_valid <= '0';\n", "right_context": " acc_loop : for i in 1 to NUM_OPERANDS-1 loop\n pip_acc(i) <= pip_acc(i-1) + in_data(i);\n end loop acc_loop;\n else\n pip_acc <= (others => (others => '0'));\n end if;\n out_data <= pip_acc(NUM_OPERANDS-1) + BIAS_VALUE;\n out_valid <= in_valid;\n end if;\n end if;\n end process;\n\n\nend architecture;\n", "groundtruth": "\n elsif(rising_edge(clk)) then\n if (enable = '1') then\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/NeighExtractor.vhd", "left_context": "------------------------------------------------------------------------------\n-- Title : neighExtractor\n-- Project : Haddoc2\n------------------------------------------------------------------------------------------------------------\n-- File : neighExtractor.vhd\n-- Author : K. Abdelouahab\n-- Company : Institut Pascal\n-- Last update: 2018-08-23\n-------------------------------------------------------------------------------------------------------------\n-- Description: Extracts a generic neighborhood from serial in_data\n--\n-- ------------------\n-- reset_n --->| |\n-- clk --->| |\n-- enable --->| |\n-- | |---> out_data (pixel_array of size KERNEL_SIZEĀ²)\n-- | neighExtractor |---> out_dv\n-- | |---> out_fv\n-- in_data --->| |---> out_valid\n-- in_dv --->| |\n-- in_fv --->| |\n-- | |\n-- ------------------\n\n--------------------------------------------------------------------------------------------------------------\n\n-- out_data(0) out_data(1) out_data(2)\n-- ^ ^ ^\n-- | | |\n-- ------- | ------- | ------- | ---------------------------\n-- | | | | | | | | | | |\n-- in_data --->| p22 |---|--> | p21 |---|--> | p20 |---|-->| BUFFER |-> to_P1\n-- | | | | | | | |\n-- ------- ------- ------- ---------------------------\n-- out_data(3) out_data(4) out_data(5)\n-- ^ ^ ^\n-- | | |\n-- ------- | ------- | ------- | ---------------------------\n-- | | | | | | | | | | |\n-- P1 --->| p12 |---|--> | p11 |---|--> | p10 |---|-->| BUFFER |-> to_P2\n-- | | | | | | | |\n-- ------- ------- ------- ---------------------------\n-- out_data(6) out_data(7) out_data(8)\n-- ^ ^ ^\n-- | | |\n-- ------- | ------- | ------- |\n-- | | | | | | | | |\n-- P2 --->| p02 |---|--> | p01 |---|--> | p00 |---|\n-- | | | | | |\n-- ------- ------- -------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\nlibrary work;\nuse work.cnn_types.all;\n\nentity neighExtractor is\n\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n", "right_context": " out_dv : out std_logic;\n out_fv : out std_logic\n );\nend neighExtractor;\n\narchitecture rtl of neighExtractor is\n\n -- signals\n signal pixel_out : pixel_array(0 to KERNEL_SIZE-1);\n signal tmp_data : pixel_array (0 to (KERNEL_SIZE * KERNEL_SIZE)- 1);\n signal all_valid : std_logic;\n signal s_valid : std_logic;\n signal buffer_fv : std_logic_vector(KERNEL_SIZE-1 downto 0);\n signal tmp_dv : std_logic;\n signal tmp_fv : std_logic;\n signal delay_dv : std_logic;\n signal delay_fv : std_logic;\n\n -- components\n component taps\n generic (\n BITWIDTH : integer;\n TAPS_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n\n port (\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector (BITWIDTH-1 downto 0);\n taps_data : out pixel_array (0 to KERNEL_SIZE -1);\n out_data : out std_logic_vector (BITWIDTH-1 downto 0)\n );\n end component;\n\n\n component bit_taps\n generic (\n TAPS_WIDTH : integer\n );\n\n port (\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic;\n out_data : out std_logic\n );\n end component;\n\n\nbegin\n\n -- All valid : Logic and\n all_valid <= in_dv and in_fv;\n s_valid <= all_valid and enable;\n ----------------------------------------------------\n -- Instantiates taps\n ----------------------------------------------------\n\n\n taps_inst : for i in 0 to KERNEL_SIZE-1 generate\n -- First line\n gen_1 : if i = 0 generate\n gen1_inst : taps\n generic map(\n BITWIDTH => BITWIDTH,\n TAPS_WIDTH => IMAGE_WIDTH-1,\n KERNEL_SIZE => KERNEL_SIZE\n )\n port map(\n clk => clk,\n reset_n => reset_n,\n enable => s_valid,\n in_data => in_data,\n taps_data => tmp_data(0 to KERNEL_SIZE-1),\n out_data => pixel_out(0)\n );\n end generate gen_1;\n\n -- line i\n gen_i : if i > 0 and i < KERNEL_SIZE-1 generate\n geni_inst : taps\n generic map(\n BITWIDTH => BITWIDTH,\n TAPS_WIDTH => IMAGE_WIDTH-1,\n KERNEL_SIZE => KERNEL_SIZE\n )\n port map(\n clk => clk,\n reset_n => reset_n,\n enable => s_valid,\n in_data => pixel_out(i-1),\n taps_data => tmp_data(i * KERNEL_SIZE to KERNEL_SIZE*(i+1)-1),\n out_data => pixel_out(i)\n );\n end generate gen_i;\n\n -- Last line\n gen_last : if i = (KERNEL_SIZE-1) generate\n gen_last_inst : taps\n generic map(\n BITWIDTH => BITWIDTH,\n TAPS_WIDTH => KERNEL_SIZE,\n KERNEL_SIZE => KERNEL_SIZE\n )\n port map(\n clk => clk,\n reset_n => reset_n,\n enable => s_valid,\n in_data => pixel_out(i-1),\n taps_data => tmp_data((KERNEL_SIZE-1) * KERNEL_SIZE to KERNEL_SIZE*KERNEL_SIZE - 1),\n out_data => open\n );\n end generate gen_last;\n end generate taps_inst;\n\n\n --------------------------------------------------------------------------\n -- Manage out_dv and out_fv\n --------------------------------------------------------------------------\n -- Embrace your self : Managing the image borders is quite a pain\n\n dv_proc : process(clk)\n\n constant NBITS_DELAY : integer := integer(ceil(log2(real(IMAGE_WIDTH))));\n variable x_cmp : unsigned (NBITS_DELAY-1 downto 0) := (others => '0');\n variable y_cmp : unsigned (NBITS_DELAY-1 downto 0) := (others => '0');\n\n begin\n if (reset_n = '0') then\n x_cmp := (others => '0');\n tmp_dv <= '0';\n tmp_fv <= '0';\n\n elsif (rising_edge(clk)) then\n\n out_data <= tmp_data;\n delay_fv <= in_fv;\n\n if(enable = '1') then\n if (in_fv = '1') then\n if(in_dv = '1') then\n---------------------------------------------------------------------------------------------------------------------------------------------------------\n if (y_cmp = to_unsigned (IMAGE_WIDTH - 1, NBITS_DELAY)) then\n if (x_cmp = to_unsigned (IMAGE_WIDTH, NBITS_DELAY)) then\n tmp_dv <= '0';\n x_cmp := (others => '0');\n y_cmp := (others => '0');\n -- elsif(x_cmp< to_unsigned (KERNEL_SIZE - 1, NBITS_DELAY)) then\n -- tmp_dv <='0';\n -- x_cmp := x_cmp + to_unsigned(1,NBITS_DELAY);\n else\n tmp_dv <= '1';\n x_cmp := x_cmp + to_unsigned(1, NBITS_DELAY);\n end if;\n\n\n elsif (y_cmp < to_unsigned (KERNEL_SIZE-1, NBITS_DELAY)) then\n tmp_fv <= '0';\n tmp_dv <= '0';\n\n if (x_cmp = to_unsigned (IMAGE_WIDTH, NBITS_DELAY)) then\n x_cmp := (others => '0');\n y_cmp := y_cmp + to_unsigned(1, NBITS_DELAY);\n else\n x_cmp := x_cmp + to_unsigned(1, NBITS_DELAY);\n end if;\n\n else\n -- Start of frame\n if (x_cmp = to_unsigned (IMAGE_WIDTH-1, NBITS_DELAY)) then\n tmp_dv <= '1';\n x_cmp := (others => '0');\n y_cmp := y_cmp + to_unsigned(1, NBITS_DELAY);\n elsif (x_cmp < to_unsigned (KERNEL_SIZE - 1, NBITS_DELAY)) then\n tmp_dv <= '0';\n x_cmp := x_cmp + to_unsigned(1, NBITS_DELAY);\n else\n tmp_fv <= '1';\n tmp_dv <= '1';\n x_cmp := x_cmp + to_unsigned(1, NBITS_DELAY);\n end if;\n\n end if;\n---------------------------------------------------------------------------------------------------------------------------------------------------------\n else\n tmp_dv <= '0';\n end if;\n\n else\n x_cmp := (others => '0');\n y_cmp := (others => '0');\n tmp_dv <= '0';\n tmp_fv <= '0';\n end if;\n\n -- When enable = 0\n else\n x_cmp := (others => '0');\n y_cmp := (others => '0');\n tmp_dv <= '0';\n tmp_fv <= '0';\n end if;\n end if;\n end process;\n\n out_dv <= tmp_dv;\n out_fv <= delay_fv;\nend architecture;\n", "groundtruth": " enable : in std_logic;\n in_data : in std_logic_vector((BITWIDTH-1) downto 0);\n in_dv : in std_logic;\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/PoolLayer.vhd", "left_context": "---------------------------------------------------------------------------------\n-- Design Name : poolLayer\n-- Coder : Kamel ABDELOUAHAB\n-- Institution : Institut Pascal - 2016\n---------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\nlibrary work;\nuse work.cnn_types.all;\n\nentity PoolLayer is\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer;\n NB_OUT_FLOWS : integer\n );\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array(0 to NB_OUT_FLOWS - 1);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out pixel_array(0 to NB_OUT_FLOWS - 1);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend entity;\n\narchitecture STRUCTURAL of PoolLayer is\n --------------------------------------------------------------------------------\n -- COMPONENTS\n --------------------------------------------------------------------------------\n component maxPool\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector (BITWIDTH - 1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (BITWIDTH - 1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\n\n end component;\n--------------------------------------------------------------------------------\nbegin\n\n generate_maxPool : for i in 0 to NB_OUT_FLOWS-1 generate\n first_maxpool : if i = 0 generate\n maxPool_0 : maxPool\n generic map(\n BITWIDTH => BITWIDTH,\n IMAGE_WIDTH => IMAGE_WIDTH,\n KERNEL_SIZE => KERNEL_SIZE\n )\n port map(\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => in_data(0),\n in_dv => in_dv,\n in_fv => in_fv,\n out_data => out_data(0),\n out_dv => out_dv,\n out_fv => out_fv\n );\n end generate first_maxpool;\n\n other_maxPool : if i > 0 generate\n maxPool_i : maxPool\n generic map(\n BITWIDTH => BITWIDTH,\n IMAGE_WIDTH => IMAGE_WIDTH,\n KERNEL_SIZE => KERNEL_SIZE\n )\n port map(\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n", "right_context": " in_dv => in_dv,\n in_fv => in_fv,\n out_data => out_data(i),\n out_dv => open,\n out_fv => open\n );\n end generate other_maxPool;\n end generate generate_maxPool;\nend STRUCTURAL;\n", "groundtruth": " in_data => in_data(i),\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/TanhLayer.vhd", "left_context": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\nlibrary work;\nuse work.cnn_types.all;\n\nentity TanhLayer is\n generic(\n BITWIDTH : integer;\n", "right_context": "\narchitecture Bhv of TanhLayer is\n-- Piecewise implementation of TanH\n\nbegin\n --sum_s <= signed(in_data);\n out_data <= std_logic_vector(to_signed(-V2, BITWIDTH)) when (signed(in_data) < to_signed(-T2, SUM_WIDTH)) else\n std_logic_vector(to_signed( V2, BITWIDTH)) when (signed(in_data) > to_signed( T2, SUM_WIDTH)) else\n std_logic_vector(SHIFT_RIGHT(signed(in_data),BITWIDTH)(BITWIDTH-1 downto 0));\nend architecture;\n", "groundtruth": " SUM_WIDTH : integer\n );\n port(\n in_data : in std_logic_vector (SUM_WIDTH-1 downto 0);\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/Taps.vhd", "left_context": "------------------------------------------------------------------------------\n-- Title : taps\n-- Project : Haddoc2\n------------------------------------------------------------------------------\n-- File : taps.vhd\n-- Author : K. Abdelouahab\n-- Company : Institut Pascal\n-- Last update: 2018-08-23\n------------------------------------------------------------------------------\n-- Description: Shift registers used in neighExtractor design.\n\n-- taps_data(0) taps_data(KERNEL_SIZE-1)\n-- ^ ^\n-- | |\n-- ------- | ------- ------- | ---------------------------\n-- | | | | | | | | | |\n-- in_data --->| |---|--> | |-- ... -> | |---|-->| BUFFER |---> out_data\n-- | | | | | | | SIZE =(TAPS_WIDTH-KERNEL)|\n-- | | | | | | | |\n-- ------- ------- ------- ---------------------------\n------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\n\nlibrary work;\nuse work.cnn_types.all;\n\n\nentity Taps is\n generic (\n BITWIDTH : integer;\n TAPS_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n", "right_context": " in_data : in std_logic_vector (BITWIDTH-1 downto 0);\n taps_data : out pixel_array (0 to KERNEL_SIZE -1);\n out_data : out std_logic_vector (BITWIDTH-1 downto 0)\n );\nend Taps;\n\n\narchitecture bhv of Taps is\n\n signal cell : pixel_array (0 to TAPS_WIDTH-1);\n\nbegin\n\n process(clk)\n variable i : integer := 0;\n begin\n\n if (reset_n = '0') then\n cell <= (others => (others => '0'));\n out_data <= (others => '0');\n taps_data <= (others => (others => '0'));\n\n elsif (rising_edge(clk)) then\n if (enable = '1') then\n cell(0) <= in_data;\n for i in 1 to (TAPS_WIDTH-1) loop\n cell(i) <= cell(i-1);\n end loop;\n taps_data <= cell(0 to KERNEL_SIZE-1);\n out_data <= cell(TAPS_WIDTH-1);\n end if;\n end if;\n end process;\nend bhv;\n", "groundtruth": "\n port (\n clk : in std_logic;\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/TensorExtractor.vhd", "left_context": "------------------------------------------------------------------------------\n-- Title : TensorExtractor\n-- Project : Haddoc2\n------------------------------------------------------------------------------------------------------------\n-- File : TensorExtractor.vhd\n-- Author : K. Abdelouahab\n-- Company : Institut Pascal\n-- Last update: 2018-08-23\n-------------------------------------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nlibrary work;\nuse work.cnn_types.all;\n\nentity TensorExtractor is\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer;\n NB_IN_FLOWS : integer\n );\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in pixel_array (0 to NB_IN_FLOWS - 1);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out pixel_array (0 to NB_IN_FLOWS * KERNEL_SIZE * KERNEL_SIZE- 1);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend TensorExtractor;\n\narchitecture rtl of TensorExtractor is\n -- components\n component neighExtractor\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector(BITWIDTH-1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE- 1);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\n end component;\n\n-- begin\nbegin\n neighExtractor_gen : for c in 0 to NB_IN_FLOWS-1 generate\n\n SINGLE_CHANNEL : if c = 0 generate\n neighExtractor_0 : neighExtractor\n generic map (\n BITWIDTH => BITWIDTH,\n IMAGE_WIDTH => IMAGE_WIDTH,\n KERNEL_SIZE => KERNEL_SIZE\n )\n", "right_context": " clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => in_data(0),\n in_dv => in_dv,\n in_fv => in_fv,\n out_data => out_data(0 to KERNEL_SIZE * KERNEL_SIZE - 1),\n out_dv => out_dv,\n out_fv => out_fv\n );\n end generate SINGLE_CHANNEL;\n\n MULTI_CHANNEL : if c > 0 generate\n neighExtractor_i : neighExtractor\n generic map (\n BITWIDTH => BITWIDTH,\n IMAGE_WIDTH => IMAGE_WIDTH,\n KERNEL_SIZE => KERNEL_SIZE\n )\n port map (\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => in_data(c),\n in_dv => in_dv,\n in_fv => in_fv,\n out_data => out_data(c * KERNEL_SIZE * KERNEL_SIZE to (c+1) * KERNEL_SIZE * KERNEL_SIZE - 1),\n out_dv => open,\n out_fv => open\n );\n end generate MULTI_CHANNEL;\n end generate neighExtractor_gen;\nend architecture;\n", "groundtruth": " port map (\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/cnn_types.vhd", "left_context": "------------------------------------------------------------------------------\n-- Title : cnn_types\n-- Project : Haddoc2\n------------------------------------------------------------------------------\n-- File : cnn_types.vhd\n-- Author : K. Abdelouahab\n-- Company : Institut Pascal\n-- Last update: 2018-08-23\n------------------------------------------------------------------------------\n-- Description: A package defining the types, functions and constants used in\n-- the Haddoc2 IP VHDL library\n------------------------------------------------------------------------------\n\nlibrary ieee;\nuse ieee.numeric_std.all;\nuse ieee.std_logic_1164.all;\nuse ieee.math_real.all;\nuse work.bitwidths.all;\n\npackage cnn_types is\n ------------------------------------------------------------------------------\n -- Types\n type pixel_array is array (integer range <>) of std_logic_vector (GENERAL_BITWIDTH-1 downto 0);\n type sum_array is array (integer range <>) of std_logic_vector (SUM_WIDTH-1 downto 0);\n type prod_array is array (integer range <>) of std_logic_vector (2*GENERAL_BITWIDTH-1 downto 0);\n type pixel_matrix is array (integer range <>, integer range <>) of std_logic_vector (GENERAL_BITWIDTH-1 downto 0);\n ------------------------------------------------------------------------------\n -- Constants to implement piecewize TanH : cf DotProduct.vhd\n constant SCALE_FACTOR : integer := 2 **(GENERAL_BITWIDTH-1) - 1;\n constant A1 : integer := GENERAL_BITWIDTH - 1;\n constant A2 : integer := GENERAL_BITWIDTH;\n constant T1 : integer := SCALE_FACTOR * SCALE_FACTOR / 2;\n constant T2 : integer := SCALE_FACTOR * SCALE_FACTOR * 5/4;\n constant V1 : integer := SCALE_FACTOR / 4;\n", "right_context": " ------------------------------------------------------------------------------\n -- Functions:\n -- extractRow : Extracts a row of pixel_array data from a pixel_matrix.\n function extractRow(target_row : integer;\n nb_row : integer;\n nb_col : integer;\n in_matrix : pixel_matrix)\n return pixel_array;\n------------------------------------------------------------------------------\nend cnn_types;\n\n\npackage body cnn_types is\n function extractRow(target_row : integer;\n nb_row : integer;\n nb_col : integer;\n in_matrix : pixel_matrix)\n return pixel_array is\n variable out_vec : pixel_array (0 to nb_col - 1);\n begin\n for index_col in 0 to (nb_col - 1) loop\n out_vec(index_col) := in_matrix(target_row, index_col);\n end loop;\n return out_vec;\n end extractRow;\nend cnn_types;\n", "groundtruth": " constant V2 : integer := SCALE_FACTOR - 10;\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/maxPool.vhd", "left_context": "------------------------------------------------------------------------------\n-- Title : maxPool\n-- Project : Haddoc2\n------------------------------------------------------------------------------\n-- File : maxPool.vhd\n-- Author : K. Abdelouahab\n-- Company : Institut Pascal\n-- Last update: 2018-08-23\n------------------------------------------------------------------------------\n-- Description: 2x2 subsampling with max operator\n--\n-- ------- -------\n-- | | | |\n-- --->| PoolH |------>| PoolV | --->\n-- | | | |\n-- ------- -------\n--\n-----------------------------------------------------------------------------\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\n\n", "right_context": " port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector (BITWIDTH - 1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (BITWIDTH - 1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend entity;\n\narchitecture rtl of maxPool is\n --------------------------------------------------------------------------\n -- Signals\n --------------------------------------------------------------------------\n signal connect_data : std_logic_vector (BITWIDTH - 1 downto 0);\n signal connect_dv : std_logic;\n signal connect_fv : std_logic;\n\n --------------------------------------------------------------------------\n -- components\n --------------------------------------------------------------------------\n component poolH\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector (BITWIDTH - 1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (BITWIDTH - 1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\n\n end component;\n --------------------------------------------------------------------------\n component poolV\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector (BITWIDTH - 1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (BITWIDTH - 1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\n\n end component;\n --------------------------------------------------------------------------\n\nbegin\n poolv_inst : poolV\n generic map (\n BITWIDTH => BITWIDTH,\n KERNEL_SIZE => KERNEL_SIZE,\n IMAGE_WIDTH => IMAGE_WIDTH\n )\n\n port map (\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => in_data,\n in_dv => in_dv,\n in_fv => in_fv,\n out_data => connect_data,\n out_dv => connect_dv,\n out_fv => connect_fv\n );\n\n --------------------------------------------------------------------------\n\n poolh_inst : poolH\n generic map (\n BITWIDTH => BITWIDTH,\n KERNEL_SIZE => KERNEL_SIZE,\n IMAGE_WIDTH => IMAGE_WIDTH\n )\n\n port map (\n clk => clk,\n reset_n => reset_n,\n enable => enable,\n in_data => connect_data,\n in_dv => connect_dv,\n in_fv => connect_fv,\n out_data => out_data,\n out_dv => out_dv,\n out_fv => out_fv\n );\n\nend rtl;\n", "groundtruth": "entity maxPool is\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/poolH.vhd", "left_context": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\n\nentity poolH is\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n", "right_context": " in_data : in std_logic_vector (BITWIDTH - 1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (BITWIDTH - 1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend entity;\n\narchitecture rtl of poolH is\n --------------------------------------------------------------------------\n -- Signals\n --------------------------------------------------------------------------\n type buffer_data_type is array (integer range <>) of signed (BITWIDTH-1 downto 0);\n\n signal buffer_data : buffer_data_type (KERNEL_SIZE - 1 downto 0);\n signal max_value_signal : signed(BITWIDTH-1 downto 0);\n signal buffer_fv : std_logic_vector(KERNEL_SIZE downto 0);\n signal delay_fv : std_logic := '0';\n signal tmp_dv : std_logic := '0';\n\n\n\nbegin\n\n process (clk)\n variable x_cmp : unsigned (15 downto 0) := (others => '0');\n begin\n if (reset_n = '0') then\n tmp_dv <= '0';\n buffer_data <= (others => (others => '0'));\n max_value_signal <= (others => '0');\n x_cmp := (others => '0');\n elsif (rising_edge(clk)) then\n if (enable = '1') then\n if (in_fv = '1') then\n if (in_dv = '1') then\n -- Bufferize data --------------------------------------------------------\n buffer_data(KERNEL_SIZE - 1) <= signed(in_data);\n BUFFER_LOOP : for i in (KERNEL_SIZE - 1) downto 1 loop\n buffer_data(i-1) <= buffer_data(i);\n end loop;\n\n -- Compute max -----------------------------------------------------------\n if (buffer_data(0) > buffer_data(1)) then\n max_value_signal <= buffer_data(0);\n else\n max_value_signal <= buffer_data(1);\n end if;\n\n -- H Subsample -------------------------------------------------------------\n if (x_cmp = to_unsigned(KERNEL_SIZE, 16)) then\n tmp_dv <= '1';\n x_cmp := to_unsigned(1, 16);\n else\n tmp_dv <= '0';\n x_cmp := x_cmp + to_unsigned(1, 16);\n end if;\n --------------------------------------------------------------------------\n else\n -- Data is not valid\n tmp_dv <= '0';\n end if;\n\n else\n -- Frame is not valid\n tmp_dv <= '0';\n buffer_data <= (others => (others => '0'));\n max_value_signal <= (others => '0');\n x_cmp := (others => '0');\n end if;\n end if;\n end if;\n end process;\n --------------------------------------------------------------------------\n delay : process(clk)\n begin\n if (reset_n = '0') then\n delay_fv <= '0';\n buffer_fv <= (others => '0');\n elsif (rising_edge(clk)) then\n if (enable = '1') then\n buffer_fv <= buffer_fv(buffer_fv'high -1 downto 0) & in_fv;\n delay_fv <= buffer_fv(buffer_fv'high);\n end if;\n end if;\n end process;\n\n out_data <= std_logic_vector(max_value_signal);\n out_fv <= delay_fv;\n out_dv <= tmp_dv;\nend architecture;\n", "groundtruth": " enable : in std_logic;\n", "crossfile_context": ""} {"task_id": "haddoc2", "path": "haddoc2/lib/hdl/poolV.vhd", "left_context": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;\nuse ieee.math_real.all;\n\nentity poolV is\n\n generic(\n BITWIDTH : integer;\n IMAGE_WIDTH : integer;\n KERNEL_SIZE : integer\n );\n\n port(\n clk : in std_logic;\n reset_n : in std_logic;\n enable : in std_logic;\n in_data : in std_logic_vector (BITWIDTH - 1 downto 0);\n in_dv : in std_logic;\n in_fv : in std_logic;\n out_data : out std_logic_vector (BITWIDTH - 1 downto 0);\n out_dv : out std_logic;\n out_fv : out std_logic\n );\nend entity;\n\narchitecture rtl of poolV is\n --------------------------------------------------------------------------\n -- Signals\n --------------------------------------------------------------------------\n type buffer_data_type is array (integer range <>) of signed (BITWIDTH-1 downto 0);\n\n signal buffer_line : buffer_data_type (IMAGE_WIDTH - 1 downto 0);\n signal buffer_data : buffer_data_type (KERNEL_SIZE - 1 downto 0);\n signal max_value_signal : signed (BITWIDTH - 1 downto 0);\n signal buffer_fv : std_logic_vector(KERNEL_SIZE downto 0);\n signal delay_fv : std_logic := '0';\n signal tmp_dv : std_logic := '0';\n\n\nbegin\n\n process (clk)\n variable x_cmp : unsigned (15 downto 0);\n\n begin\n if (reset_n = '0') then\n tmp_dv <= '0';\n buffer_data <= (others => (others => '0'));\n buffer_line <= (others => (others => '0'));\n max_value_signal <= (others => '0');\n x_cmp := (others => '0');\n\n elsif (rising_edge(clk)) then\n if (enable = '1') then\n if (in_fv = '1') then\n if (in_dv = '1') then\n\n -- Bufferize line --------------------------------------------------------\n buffer_line(IMAGE_WIDTH - 1) <= signed(in_data);\n BUFFER_LOOP : for i in (IMAGE_WIDTH - 1) downto 1 loop\n buffer_line(i-1) <= buffer_line(i);\n end loop;\n\n buffer_data(0) <= signed(in_data);\n buffer_data(1) <= buffer_line(0);\n\n -- Compute max : Case2 , just a comparator --------------------------------\n if (buffer_data(0) > buffer_data(1)) then\n max_value_signal <= buffer_data(0);\n else\n max_value_signal <= buffer_data(1);\n end if;\n\n -- V Subsample -------------------------------------------------------------\n if (x_cmp < to_unsigned(IMAGE_WIDTH+1, 16)) then\n tmp_dv <= '0';\n x_cmp := x_cmp + to_unsigned(1, 16);\n elsif (x_cmp > to_unsigned(IMAGE_WIDTH + IMAGE_WIDTH, 16)) then\n tmp_dv <= '0';\n x_cmp := to_unsigned(2, 16);\n else\n tmp_dv <= '1';\n x_cmp := x_cmp + to_unsigned(1, 16);\n end if;\n --------------------------------------------------------------------------\n else\n -- Data is not valid\n tmp_dv <= '0';\n end if;\n else\n buffer_data <= (others => (others => '0'));\n buffer_line <= (others => (others => '0'));\n max_value_signal <= (others => '0');\n x_cmp := (others => '0');\n", "right_context": " end if;\n end if;\n end process;\n --------------------------------------------------------------------------\n delay : process(clk)\n begin\n if (reset_n = '0') then\n delay_fv <= '0';\n buffer_fv <= (others => '0');\n elsif (rising_edge(clk)) then\n if (enable = '1') then\n buffer_fv <= buffer_fv(buffer_fv'high -1 downto 0) & in_fv;\n delay_fv <= buffer_fv(buffer_fv'high);\n end if;\n end if;\n end process;\n\n\n out_data <= std_logic_vector(max_value_signal);\n out_fv <= delay_fv;\n out_dv <= tmp_dv;\n\nend architecture;\n", "groundtruth": " end if;\n", "crossfile_context": ""}