{"task_id": "chipfail-glitcher", "path": "chipfail-glitcher/chipfail-glitcher.srcs/sources_1/new/uart_tx.v", "left_context": "`timescale 1ns / 1ps\n`include \"uart_definitions.v\"\n\nmodule uart_tx(\n // System clock\n input wire clk,\n // Data input\n input wire [7:0] data,\n // Enable, pull high for one cycle to start sending\n input wire enable,\n // Resets the entire module\n input wire reset,\n \n // The data line\n output reg tx,\n // Indicates the module is ready to receive\n output reg ready = 1'b1\n );\n\n\n\n// States\nparameter STATE_IDLE = 4'd0;\nparameter STATE_START_BIT = 4'd1;\nparameter STATE_DATA_BITS = 4'd2;\nparameter STATE_STOP_BIT = 4'd3;\nparameter STATE_DONE = 4'd5;\n\n// Hold state in this\nreg [3:0] state = STATE_IDLE;\n\n// The bit we are sending currently\nreg [3:0] current_bit = 4'd0;\n\n// Counter for baudrate\nreg [31:0] etu_counter = 32'd0;\n\nwire etu_full;\nwire etu_half;\n\nassign etu_full = (etu_counter == `UART_FULL_ETU);\nassign etu_half = (etu_counter == `UART_HALF_ETU);\n\nreg [7:0] data_local;\n\nalways @(posedge clk)\nbegin\n if(reset == 1'b1)\n begin\n state <= STATE_IDLE;\n current_bit <= 8'd0;\n tx <= 1'b1;\n end\n else\n begin\n // Default assignments\n tx <= tx;\n ready <= ready;\n state <= state;\n current_bit <= current_bit;\n data_local <= data_local;\n\n // Always count up the ETU counter\n etu_counter <= etu_counter + 1'd1;\n\n case(state)\n STATE_IDLE:\n begin\n // Our state is idle, but we just got an enable signal. Start sending!\n if(enable)\n begin\n data_local <= data;\n state <= STATE_DATA_BITS;\n tx <= 1'b0;\n ready <= 1'b0;\n current_bit <= 4'd0;\n // Start etu_counter\n etu_counter <= 32'd0;\n end\n else\n begin\n tx <= 1'b1;\n ready <= 1'b1;\n end\n end\n STATE_START_BIT:\n begin\n state <= STATE_DATA_BITS;\n etu_counter <= 32'd0;\n end\n STATE_DATA_BITS:\n begin\n if(etu_full)\n begin\n etu_counter <= 32'd0;\n tx <= data_local[0];\n data_local <= {data_local[0], data_local[7:1]};\n current_bit <= current_bit + 1'd1;\n if(current_bit == 3'd7)\n begin\n state <= STATE_STOP_BIT;\n end\n end\n end\n STATE_STOP_BIT:\n\n tx <= 1'd1;\n etu_counter <= 32'd0;\n state <= STATE_DONE;\n end\n end\n STATE_DONE:\n", "right_context": " ready <= 1'b1;\n state <= STATE_IDLE;\n end\n end\n endcase\n end\n \nend\n\n\n\n\nendmodule\n", "groundtruth": " begin\n if(etu_full)\n begin\n", "crossfile_context": ""} {"task_id": "CHIPKIT", "path": "CHIPKIT/ip/ahb/AHB_MEM.sv", "left_context": "// AHB_MEM.sv - A 64KB AHB memory\n// PNW\n\n`include \"RTL.svh\"\n\n// TODO generate wait state only on RaW hazard\n\n\nmodule AHB_MEM \n#(\n parameter AW = 16, // Address width (16bits = 64KB)\n parameter filename = \"\" // Initialization hex file\n) (\n input logic HCLK, HRESETn,\n ahb_slave_intf.source S,\n \n input logic SC_SRAM_STOV,\n input logic [2:0] SC_SRAM_EMA,\n input logic [1:0] SC_SRAM_EMAW,\n input logic SC_SRAM_EMAS\n);\n\nlogic clk, rstn;\n\nalways_comb clk = HCLK;\nalways_comb rstn = HRESETn;\n\n\n// Detect valid transaction\n\n// Transaction is split into two phases: APHASE and DPHASE\n// Useful part of APHASE is 1 cycle.\n// DPHASE is controlled by by slave.\n// In this case, it is either 1 cycle for a READ,\n// or 2 cycles for a WRITE.\n\nlogic aphase;\nlogic dphase;\nalways_comb aphase = S.HSEL & S.HREADY & S.HTRANS[1];\n//`FF(aphase,dphase,clk,'1,rstn,'0);\n\n// determine if it's a read or write transaction\nlogic write_en;\nlogic read_en;\nlogic write_en_reg;\nalways_comb write_en = aphase & S.HWRITE & (~write_en_reg);\nalways_comb read_en = aphase & (~S.HWRITE);\n`FF(write_en,write_en_reg,clk,'1,rstn,'0);\n\n// Read enable for each byte (address phase)\nlogic [3:0] byte_lane_nxt;\n\nalways_comb begin\nif (aphase)\n begin\n case (S.HSIZE)\n 0 : // Byte\n begin\n case (S.HADDR[1:0])\n", "right_context": " 1 : // Halfword\n begin\n if (S.HADDR[1])\n byte_lane_nxt = 4'b1100; // Upper halfword\n else\n byte_lane_nxt = 4'b0011; // Lower halfword\n end\n default : // Word\n byte_lane_nxt = 4'b1111; // Whole word\n endcase\n end\nelse\n byte_lane_nxt = 4'b0000; // Not reading\nend\n\n// Register address phase control signals\nlogic [3:0] byte_lane_reg; \nlogic [AW-1:0] word_addr_reg; \nlogic [AW-1:0] word_addr_nxt;\nalways_comb word_addr_nxt = {S.HADDR[AW-1:2], 2'b00};\n`FF(byte_lane_nxt[3:0],byte_lane_reg[3:0],clk,'1,rstn,'0);\n`FF(word_addr_nxt[AW-1:0],word_addr_reg[AW-1:0],clk,'1,rstn,'0);\n\n\n// SRAM\n\nlogic sram_cen;\nlogic sram_gwen;\nlogic [AW-1:0] sram_a;\nlogic [31:0] sram_wen;\nlogic [31:0] sram_d;\nlogic [31:0] sram_q;\nlogic [7:0] sram_q0, sram_q1, sram_q2, sram_q3;\nalways_comb sram_cen = ~(read_en | write_en_reg);\nalways_comb sram_gwen = read_en;\nalways_comb sram_a = read_en ? word_addr_nxt : word_addr_reg;\nalways_comb sram_d[31:0] = S.HWDATA[31:0];\nalways_comb sram_wen = {{8{~byte_lane_reg[3]}},{8{~byte_lane_reg[2]}},{8{~byte_lane_reg[1]}},{8{~byte_lane_reg[0]}}};\nalways_comb sram_q0[7:0] = byte_lane_reg[0] ? sram_q[7:0] : 8'h00;\nalways_comb sram_q1[7:0] = byte_lane_reg[1] ? sram_q[15:8] : 8'h00;\nalways_comb sram_q2[7:0] = byte_lane_reg[2] ? sram_q[23:16] : 8'h00;\nalways_comb sram_q3[7:0] = byte_lane_reg[3] ? sram_q[31:24] : 8'h00;\n\n\nLIB_SRAM_16384x32 \nu_64kb_sram (\n .Q(sram_q[31:0]),\n .CLK(clk),\n .CEN(sram_cen),\n .GWEN(sram_gwen),\n .WEN(sram_wen),\n .A(sram_a[AW-1:2]),\n .D(sram_d[31:0]),\n .STOV(SC_SRAM_STOV),\n .EMA(SC_SRAM_EMA[2:0]),\n .EMAW(SC_SRAM_EMAW[1:0]),\n .EMAS(SC_SRAM_EMAS)\n);\n\n\n// Connect to top level\nalways_comb S.HREADYOUT = ~write_en_reg; // READ does not require wait state, WRITE requires 1 wait state\nalways_comb S.HRESP = 1'b0; // Always response with OKAY\nalways_comb S.HRDATA[31:0] = {sram_q3[7:0],sram_q2[7:0],sram_q1[7:0],sram_q0[7:0]};\n\n\n//----------------------------------\n//logging\n//--------------------------------\n\n`LOGF_INIT\n\n\n//add delay before logging read or write, but don't let address change for read\nlogic [AW-3:0] this_addr;\nlogic did_read;\n`FF(read_en, did_read, clk, '1, rstn, '0);\n\nalways_ff @(posedge clk, negedge rstn)\nbegin\n if (!rstn) this_addr <= sram_a[AW-1:2];\n else if (read_en) this_addr <= sram_a[AW-1:2];\nend\n\n`LOGF(clk, rstn, read_en, (\"READ: %8h : %8h\", this_addr, sram_q));\n\nlogic did_write;\n`FF(write_en, did_write, clk, '1, rstn, '0);\n\n`LOGF(clk, rstn, did_write, (\"WRITE: %8h : %8h\", sram_a[AW-1:2], sram_d));\n\nendmodule\n", "groundtruth": " 0: byte_lane_nxt = 4'b0001; // Byte 0\r\n 1: byte_lane_nxt = 4'b0010; // Byte 1\r\n 2: byte_lane_nxt = 4'b0100; // Byte 2\r\n 3: byte_lane_nxt = 4'b1000; // Byte 3\r\n", "crossfile_context": ""} {"task_id": "ISP_UVM", "path": "ISP_UVM/frame_monitor.sv", "left_context": "", "right_context": "\nclass frame_monitor extends uvm_monitor;\n rgb_vif vif;\n\n frame_rgb_tr tr;\n uvm_analysis_port #(frame_rgb_tr) item_collected_port;\n `uvm_component_utils(frame_monitor)\n \n function new(string name, uvm_component parent);\n super.new(name, parent);\n item_collected_port = new (\"item_collected_port\", this);\n\t`uvm_info(\"MONITOR CREATED\",\"new\",UVM_MEDIUM)\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n assert(uvm_config_db#(rgb_vif)::get(this, \"\", \"vif\", vif));\n tr = frame_rgb_tr::type_id::create(\"tr\", this);\n endfunction\n\n virtual task run_phase(uvm_phase phase);\n `uvm_info(\"Monitor rgb\",\"started run_phase\",UVM_MEDIUM)\n\n wait (vif.rst === 1);\n @(negedge vif.rst);\n\n //forever begin\n tr.a = allocateFrame();\n @(posedge vif.clk);\n begin_tr(tr, \"frame_monitor\");\n\t for(int i = 0; i < `HEIGHT; i++)begin\n for(int j = 0; j < `WIDTH; j++)begin\n setPixel(tr.a, i, j, vif.R, vif.G, vif.B);\n `uvm_info(\"Monitor rgb\",$sformatf(\"Received pixel i=%d j=%d R=%d G=%d, B=%d\", i, j, vif.R, vif.G, vif.B), UVM_LOW)\n\t \t @(posedge vif.clk); \n end\n end\n `uvm_info(\"Monitor rgb \", \"Received frame\", UVM_LOW)\t \n item_collected_port.write(tr);\n `uvm_info(\"Monitor rgb \", \"Wrote frame to port\", UVM_LOW)\t \n end_tr(tr);\n `uvm_info(\"Monitor rgb \", \"ended tr\", UVM_LOW)\t \n //end\n endtask\n\t\nendclass\n", "groundtruth": "`include \"cvFunction.svh\"\n", "crossfile_context": ""} {"task_id": "JSilicon", "path": "JSilicon/sim/jsilicon_tb_top.sv", "left_context": "// SPDX-FileCopyrightText: © 2024 JSilicon\n// SPDX-License-Identifier: Apache-2.0\n\n`timescale 1ns/1ps\n\nmodule jsilicon_tb_top;\n \n import uvm_pkg::*;\n import jsilicon_pkg::*;\n \n // Clock generation\n logic clk;\n initial begin\n", "right_context": " forever #5 clk = ~clk; // 100MHz clock (10ns period)\n end\n \n // Interface instantiation\n jsilicon_if vif(clk);\n \n // DUT instantiation\n tt_um_Jsilicon dut (\n .clk (vif.clk),\n .rst_n (vif.rst_n),\n .ena (vif.ena),\n .ui_in (vif.ui_in),\n .uio_in (vif.uio_in),\n .uo_out (vif.uo_out),\n .uio_out (vif.uio_out),\n .uio_oe (vif.uio_oe)\n );\n \n // Waveform dumping\n initial begin\n `ifdef VCS\n // FSDB dumping for Verdi\n $fsdbDumpfile(\"jsilicon.fsdb\");\n $fsdbDumpvars(0, jsilicon_tb_top);\n $fsdbDumpMDA();\n `else\n // VCD dumping as fallback\n $dumpfile(\"jsilicon_uvm.vcd\");\n $dumpvars(0, jsilicon_tb_top);\n `endif\n end\n \n // UVM configuration and test execution\n initial begin\n // Set virtual interface in config DB\n uvm_config_db#(virtual jsilicon_if)::set(null, \"*\", \"vif\", vif);\n \n // Run the test\n run_test();\n end\n \n // Timeout watchdog\n initial begin\n #1000000; // 1ms timeout\n `uvm_error(\"TIMEOUT\", \"Simulation timeout reached\")\n $finish;\n end\n\nendmodule : jsilicon_tb_top\n\n", "groundtruth": " clk = 0;\n", "crossfile_context": ""} {"task_id": "vdf-fpga", "path": "vdf-fpga/modular_square/rtl/modular_square_simple.sv", "left_context": "/*******************************************************************************\n Copyright 2019 Supranational LLC\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n*******************************************************************************/\n\n`include \"msuconfig.vh\"\n\n// Set a default modulus and bitwidth but allow them to be defined \n// externally as well. \n`ifndef MOD_LEN_DEF\n`define MOD_LEN_DEF 1024\n`endif\n`ifndef MODULUS_DEF\n `define MODULUS_DEF 1024'd124066695684124741398798927404814432744698427125735684128131855064976895337309138910015071214657674309443149407457493434579063840841220334555160125016331040933690674569571217337630239191517205721310197608387239846364360850220896772964978569683229449266819903414117058030106528073928633017118689826625594484331\n`endif\n\nmodule modular_square_simple\n #(\n parameter int MOD_LEN = `MOD_LEN_DEF\n )\n (\n input logic clk,\n input logic reset,\n input logic start,\n input logic [MOD_LEN-1:0] sq_in,\n output logic [MOD_LEN-1:0] sq_out,\n output logic valid\n );\n\n localparam [MOD_LEN-1:0] MODULUS = `MODULUS_DEF;\n\n logic [MOD_LEN-1:0] cur_sq_in;\n logic [MOD_LEN*2-1:0] squared;\n logic [MOD_LEN-1:0] sq_out_comb;\n\n // Mimic a pipeline\n localparam [3:0] PIPELINE_DEPTH = 10;\n logic [3:0] valid_count;\n logic running;\n logic valid_next;\n\n // Store the square input, circulate the result back to the input\n always_ff @(posedge clk) begin\n if(start) begin\n cur_sq_in <= sq_in;\n end else if(valid_next) begin\n cur_sq_in <= sq_out_comb;\n end\n end\n assign sq_out = valid ? cur_sq_in : {MOD_LEN{1'bx}};\n\n // Control\n always_ff @(posedge clk) begin\n if(reset) begin\n running <= 0;\n valid_count <= 0;\n end else begin\n if(start || valid_next) begin\n running <= 1;\n valid_count <= 0;\n end else begin\n valid_count <= valid_count + 1;\n", "right_context": " //----------------------------------------------------------------------\n // EDIT HERE\n // Insert/instantiate your multiplier below\n // Modify control above as needed while satisfying the interface\n //\n\n // Compute the modular square function\n always_comb begin\n squared = {{MOD_LEN{1'b0}}, cur_sq_in};\n squared = squared * squared;\n squared = squared % {{MOD_LEN{1'b0}}, MODULUS};\n sq_out_comb = squared[MOD_LEN-1:0];\n end\n\n // EDIT HERE\n //----------------------------------------------------------------------\n\nendmodule\n", "groundtruth": " end\n end\n end\n \n assign valid_next = running && (valid_count == PIPELINE_DEPTH-1);\n", "crossfile_context": ""} {"task_id": "10g-low-latency-ethernet", "path": "10g-low-latency-ethernet/example/hdl/example_10g_eth.sv", "left_context": "// MIT License\n\n// Copyright (c) 2023 Tom Chisholm\n\n// Permission is hereby granted, free of charge, to any person obtaining a copy\n// of this software and associated documentation files (the \"Software\"), to deal\n// in the Software without restriction, including without limitation the rights\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n// copies of the Software, and to permit persons to whom the Software is\n// furnished to do so, subject to the following conditions:\n\n// The above copyright notice and this permission notice shall be included in all\n// copies or substantial portions of the Software.\n\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n// SOFTWARE.\n\n/*\n* Module: example_10g_eth\n*\n* Description: Example design for low-latency 10G Ethernet core.\n* This design generates test packets and measures latency when transceiver\n* is in loopback.\n*\n*/\n\n`timescale 1ns/1ps\n`default_nettype none\n\n", "right_context": " parameter bit TX_XVER_BUFFER = 0,\n parameter real INIT_CLK_FREQ = 100.0\n) (\n\n input wire i_init_clk,\n\n // Differential reference clock inputs\n input wire i_mgtrefclk0_x0y3_p,\n input wire i_mgtrefclk0_x0y3_n,\n\n // Serial data ports for transceiver channel 0\n input wire i_ch0_gtyrxn_in,\n input wire i_ch0_gtyrxp_in,\n output wire o_ch0_gtytxn_out,\n output wire o_ch0_gtytxp_out\n);\n\n /********* Internal Declarations ********/\n wire packet_gen_reset;\n logic [1:0] reset_cdc;\n wire core_reset;\n\n // Packet gen\n wire [15:0] packet_length;\n logic [15:0] packet_length_cnt;\n logic [31:0] packet_vio_data;\n\n // Tx AXIS\n wire s00_axis_aclk;\n wire [31:0] s00_axis_tdata;\n wire [3:0] s00_axis_tkeep;\n wire s00_axis_tvalid;\n wire s00_axis_tready;\n wire s00_axis_tlast;\n\n // Rx AXIS\n wire m00_axis_aclk;\n wire [31:0] m00_axis_tdata;\n wire [3:0] m00_axis_tkeep;\n wire m00_axis_tvalid;\n wire m00_axis_tlast;\n wire m00_axis_tuser;\n\n // Resets\n wire mac_pcs_rx_reset, mac_pcs_tx_reset;\n\n // Performance meas\n wire [15:0] perf_latency;\n wire perf_complete;\n wire perf_tx_start, perf_rx_stop;\n\n /********* Transmit Packet Gen ********/\n\n always_ff @(posedge s00_axis_aclk)\n if (packet_gen_reset) begin\n packet_length_cnt <= '0;\n end else if (s00_axis_tready) begin\n packet_length_cnt <= (packet_length_cnt == packet_length) ? '0 : packet_length_cnt + 1;\n end\n\n assign s00_axis_tdata = {packet_vio_data[31:16], packet_length_cnt}; // Set lower 16 bits to packet index counter\n assign s00_axis_tkeep = '1;\n assign s00_axis_tlast = packet_length_cnt == packet_length;\n assign s00_axis_tvalid = !packet_gen_reset;\n\n /********* Latency Measurement ********/\n\n assign perf_tx_start = s00_axis_tvalid && s00_axis_tready && s00_axis_tdata[15:0] == 16'b0;\n assign perf_rx_stop = m00_axis_tvalid && m00_axis_tdata[15:0] == 16'b0;\n\n eth_perf u_eth_perf (\n .i_tx_reset(mac_pcs_tx_reset),\n .i_tx_clk(s00_axis_aclk),\n .i_tx_start(perf_tx_start),\n .o_latency(perf_latency),\n .o_test_complete(perf_complete),\n\n .i_rx_stop(perf_rx_stop)\n );\n\n /********* Debug Cores ********/\n\n // Packet Gen VIO\n eth_core_control_vio u_packet_control_vio (\n .clk(s00_axis_aclk), // input wire clk\n .probe_out0(packet_gen_reset), // output wire [0 : 0] probe_out0\n .probe_out1(packet_length), // output wire [15 : 0] probe_out1\n .probe_out2(packet_vio_data) // output wire [63 : 0] probe_out2\n );\n\n eth_core_control_vio u_core_reset_vio (\n .clk(i_init_clk), // input wire clk\n .probe_out0(core_reset), // output wire [0 : 0] probe_out0\n .probe_out1(), // output wire [15 : 0] probe_out1\n .probe_out2() // output wire [63 : 0] probe_out2\n );\n\n // Data monitor ILAs\n example_packet_ila tx_packet_ila (\n .clk(s00_axis_aclk), // input wire clk\n .probe0(s00_axis_tdata), // input wire [63:0] probe0\n .probe1(s00_axis_tkeep), // input wire [7:0] probe1\n .probe2(s00_axis_tready), // input wire [0:0] probe2\n .probe3(s00_axis_tvalid), // input wire [0:0] probe3\n .probe4(s00_axis_tlast), // input wire [0:0] probe4\n .probe5(perf_latency),\n .probe6(perf_complete)\n );\n\n example_packet_ila rx_packet_ila (\n .clk(m00_axis_aclk), // input wire clk\n .probe0(m00_axis_tdata), // input wire [63:0] probe0\n .probe1(m00_axis_tkeep), // input wire [7:0] probe1\n .probe2(m00_axis_tuser), // input wire [0:0] probe2\n .probe3(m00_axis_tvalid), // input wire [0:0] probe3\n .probe4(m00_axis_tlast), // input wire [0:0] probe4\n .probe5(16'h0),\n .probe6(perf_rx_stop)\n );\n\n /********* Ethernet Core ********/\n\n eth_10g #(\n .SCRAMBLER_BYPASS(SCRAMBLER_BYPASS),\n .EXTERNAL_GEARBOX(EXTERNAL_GEARBOX),\n .TX_XVER_BUFFER(TX_XVER_BUFFER),\n .INIT_CLK_FREQ(INIT_CLK_FREQ)\n ) u_eth_10g (\n .i_reset(core_reset),\n .i_init_clk(i_init_clk),\n .i_mgtrefclk0_x0y3_p(i_mgtrefclk0_x0y3_p),\n .i_mgtrefclk0_x0y3_n(i_mgtrefclk0_x0y3_n),\n .s00_axis_aclk(s00_axis_aclk),\n .s00_axis_tdata(s00_axis_tdata),\n .s00_axis_tkeep(s00_axis_tkeep),\n .s00_axis_tvalid(s00_axis_tvalid),\n .s00_axis_tready(s00_axis_tready),\n .s00_axis_tlast(s00_axis_tlast),\n .m00_axis_aclk(m00_axis_aclk),\n .m00_axis_tdata(m00_axis_tdata),\n .m00_axis_tkeep(m00_axis_tkeep),\n .m00_axis_tvalid(m00_axis_tvalid),\n .m00_axis_tlast(m00_axis_tlast),\n .m00_axis_tuser(m00_axis_tuser),\n .i_ch0_gtyrxn(i_ch0_gtyrxn_in),\n .i_ch0_gtyrxp(i_ch0_gtyrxp_in),\n .o_ch0_gtytxn(o_ch0_gtytxn_out),\n .o_ch0_gtytxp(o_ch0_gtytxp_out),\n .o_mac_pcs_tx_reset(mac_pcs_tx_reset),\n .o_mac_pcs_rx_reset(mac_pcs_rx_reset)\n );\n\n\nendmodule\n", "groundtruth": "module example_10g_eth #(\n parameter bit SCRAMBLER_BYPASS = 0,\n", "crossfile_context": ""} {"task_id": "DDR4Sim", "path": "DDR4Sim/src/burst_rw.sv", "left_context": "///////////////////////////////////////////////////////////////////////////////\n//\n// FILE NAME: BURST_RW.SV\n//\n// AUTHOR: Jeff Nguyen\n//\n// DATE CREATED: 07/29/2014\n//\n// DESCRIPTION: The module implements FSM to control write and read timing. \n// The FSM controls the CL and CWL, which are latency between CAS and read,and\n// write data, respectively.\n// The queues are provided to keep track when CAS occurs while the FSM executing\n// the past CAS command. Each time, a CAS pops out of the queue, each CAS in \n// the queue is updated for # cycles has been waited.\n//\n// Note: use clock_t as main clock\n/////////////////////////////////////////////////////////////////////////////// \n \n`include \"ddr_package.pkg\"\n\nmodule BURST_RW (DDR_INTERFACE intf,\n CTRL_INTERFACE ctrl_intf);\n\nint DELAY; \n \nrw_fsm_type rw_state, rw_next_state;\n\nlogic next_rw; \n", "right_context": "int rw_counter,rw_delay;\n\n//tracking the CAS command occurs\nint rw_cmd_trk[$]; \nlogic [1:0] rw_trk[$];\n \nint temp; \n \n//fsm control timing between CAS and data \nalways_ff @(posedge intf.clock_t, negedge intf.reset_n)\nbegin\n if (!intf.reset_n) \n rw_state <= RW_IDLE;\n else \n rw_state <= rw_next_state;\nend\n \n \n//next state generate logic\n\nalways_comb\nbegin\n if (!intf.reset_n) begin \n rw_next_state <= RW_IDLE;\n clear_rw_counter <= 1'b1;\n ctrl_intf.rw_done <= 1'b0;\n ctrl_intf.rw_rdy <= 1'b0;\n end\n else begin\n case (rw_state)\n RW_IDLE: begin\n ctrl_intf.rw_done <= 1'b1;\n ctrl_intf.data_idle <= 1'b1;\n if (ctrl_intf.cas_rdy) begin\n rw_next_state <= RW_WAIT_STATE;\n clear_rw_counter <= 1'b1; \n end else \n begin\n rw_next_state <= RW_IDLE;\n clear_rw_counter <= 1'b0; \n end\n end\n \n RW_WAIT_STATE: begin\n ctrl_intf.rw_done <= 1'b0;\n ctrl_intf.data_idle <= 1'b0;\n clear_rw_counter <= 1'b0;\n if (rw_counter == rw_delay) begin\n rw_next_state <= RW_DATA;\n clear_rw_counter <= 1'b1;\n ctrl_intf.rw_rdy <= 1'b1;\n end else\n rw_next_state <= RW_WAIT_STATE; \n end\n \n RW_DATA: begin\n ctrl_intf.rw_done <= 1'b1; //set data done\n ctrl_intf.rw_rdy <= 1'b0;\n clear_rw_counter <= 1'b0;\n if (next_rw) //next rw avail in queue\n rw_next_state <= RW_WAIT_STATE;\n else \n rw_next_state <= RW_IDLE;\n end\n \n default : rw_next_state <= RW_IDLE;\n\n endcase\n end \nend \n\n// keep track when CAS occurs \nalways @(intf.reset_n, ctrl_intf.cas_rdy, next_rw)\nbegin\n int temp;\n if (!intf.reset_n) begin\n rw_cmd_trk.delete(); //delete the queues\n rw_delay = 0;\n end\n \n //calculate # cycles each CAS command waited in queue\n if((rw_state == RW_IDLE) && \n (ctrl_intf.cas_rdy))begin \n if (ctrl_intf.act_rw == READ)\n DELAY = ctrl_intf.RD_DELAY;\n else \n DELAY = ctrl_intf.WR_DELAY; \n rw_delay = DELAY - 1;\n end \n else if ((rw_state == RW_DATA) && (next_rw)) begin \n if (rw_trk.pop_front === READ)\n DELAY = ctrl_intf.RD_DELAY;\n else\n DELAY = ctrl_intf.WR_DELAY; \n \n temp = DELAY - rw_cmd_trk.pop_front -1;\n if (temp > DELAY)\n rw_delay = temp;\n else\n rw_delay = DELAY + ctrl_intf.BL/2; // enough for the preamble \n \n //update # cycles each RW cmd waited\n foreach (rw_cmd_trk[i]) \n rw_cmd_trk [i] = {(rw_cmd_trk[i] + rw_delay +1 )};\n end\n \n if ((ctrl_intf.cas_rdy) &&\n (rw_state != RW_IDLE))\n begin\n rw_cmd_trk = {rw_cmd_trk, (rw_delay - rw_counter)};\n rw_trk = {rw_trk, ctrl_intf.cas_rw}; \n end \nend\n \n// simple rw_counter \nalways_ff @(posedge intf.clock_t)\nbegin\n if(clear_rw_counter == 1'b1)\n rw_counter <= 0;\n else \n rw_counter <= rw_counter + 1;\nend\n \n//determine the next CAS command avail in queue.\nalways_ff @ (posedge intf.clock_t)\nbegin\n if ((rw_next_state == RW_DATA) && \n (rw_cmd_trk.size != 0)) \n next_rw <= 1'b1;\n else\n next_rw <= 1'b0;\nend \n \nendmodule \n", "groundtruth": "logic clear_rw_counter = 1'b0; \n", "crossfile_context": ""} {"task_id": "PDPU", "path": "PDPU/sources/counter_5to3.sv", "left_context": "// 5:3 counter, the basic module that constitutes the 4:2 compressor\nmodule counter_5to3(\n input logic x1,x2,x3,x4,cin,\n output logic sum,carry,cout\n", "right_context": "", "groundtruth": ");\n assign sum = x1 ^ x2 ^ x3 ^ x4 ^ cin;\n assign cout = (x1 ^ x2) & x3 | ~(x1 ^ x2) & x1;\n assign carry = (x1 ^ x2 ^ x3 ^ x4) & cin | ~(x1 ^ x2 ^ x3 ^ x4) & x4;\nendmodule", "crossfile_context": ""} {"task_id": "UVM-APB_RAL", "path": "UVM-APB_RAL/tb/reg_rw_test.sv", "left_context": "class reg_rw_test extends base_test;\n `uvm_component_utils (reg_rw_test)\n \n my_sequence m_seq;\n \n function new (string name=\"reg_rw_test\", uvm_component parent);\n super.new (name, parent);\n endfunction\n\n virtual task main_phase(uvm_phase phase);\n\n phase.raise_objection(this);\n m_seq = my_sequence::type_id::create(\"m_seq\");\n\n m_seq.model = m_ral_model;\n\n\n", "right_context": "\n phase.drop_objection(this);\n endtask\nendclass", "groundtruth": " m_seq.start(m_env.m_agent.m_seqr);\n", "crossfile_context": ""} {"task_id": "ravenoc", "path": "ravenoc/src/ravenoc_wrapper.sv", "left_context": "/**\n * File: RaveNoC wrapper module\n * Description: It only exists because it facilitates intg. with cocotb\n * Author: Anderson Ignacio da Silva \n *\n * MIT License\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\nmodule ravenoc_wrapper\n import amba_axi_pkg::*;\n import ravenoc_pkg::*;\n#(\n parameter bit DEBUG = 0\n)(\n /*verilator coverage_off*/\n input clk_axi,\n input clk_noc,\n input arst_axi,\n input arst_noc,\n // AXI mux I/F\n input act_in,\n input [$clog2(NoCSize)-1:0] axi_sel_in,\n input act_out,\n input [$clog2(NoCSize)-1:0] axi_sel_out,\n // Used to test when clk_axi == clk_noc to bypass CDC\n input bypass_cdc,\n // AXI in I/F\n // AXI Interface - MOSI\n // Write Address channel\n input logic noc_in_awid,\n input axi_addr_t noc_in_awaddr,\n input logic [`AXI_ALEN_WIDTH-1:0] noc_in_awlen,\n input axi_size_t noc_in_awsize,\n input axi_burst_t noc_in_awburst,\n input logic noc_in_awlock,\n input logic [3:0] noc_in_awcache,\n input logic [2:0] noc_in_awprot,\n input logic [3:0] noc_in_awqos,\n input logic [3:0] noc_in_awregion,\n input logic [`AXI_USER_REQ_WIDTH-1:0] noc_in_awuser,\n input logic noc_in_awvalid,\n // Write Data channel\n //input logic noc_in_wid,\n input logic [`AXI_DATA_WIDTH-1:0] noc_in_wdata,\n input logic [(`AXI_DATA_WIDTH/8)-1:0] noc_in_wstrb,\n input logic noc_in_wlast,\n input logic [`AXI_USER_DATA_WIDTH-1:0] noc_in_wuser,\n input logic noc_in_wvalid,\n // Write Response channel\n input logic noc_in_bready,\n // Read Address channel\n input logic noc_in_arid,\n input axi_addr_t noc_in_araddr,\n input logic [`AXI_ALEN_WIDTH-1:0] noc_in_arlen,\n input axi_size_t noc_in_arsize,\n input axi_burst_t noc_in_arburst,\n input logic noc_in_arlock,\n input logic [3:0] noc_in_arcache,\n input logic [2:0] noc_in_arprot,\n input logic [3:0] noc_in_arqos,\n input logic [3:0] noc_in_arregion,\n input logic [`AXI_USER_REQ_WIDTH-1:0] noc_in_aruser,\n input logic noc_in_arvalid,\n // Read Data channel\n input logic noc_in_rready,\n\n // AXI Interface - MISO\n // Write Addr channel\n output logic noc_in_awready,\n // Write Data channel\n output logic noc_in_wready,\n // Write Response channel\n output logic noc_in_bid,\n output axi_resp_t noc_in_bresp,\n output logic [`AXI_USER_RESP_WIDTH-1:0] noc_in_buser,\n output logic noc_in_bvalid,\n // Read addr channel\n output logic noc_in_arready,\n // Read data channel\n output logic noc_in_rid,\n output logic [`AXI_DATA_WIDTH-1:0] noc_in_rdata,\n output axi_resp_t noc_in_rresp,\n output logic noc_in_rlast,\n output logic [`AXI_USER_REQ_WIDTH-1:0] noc_in_ruser,\n output logic noc_in_rvalid,\n\n // AXI out I/F\n // AXI Interface - MOSI\n // Write Address channel\n input logic noc_out_awid,\n input axi_addr_t noc_out_awaddr,\n input logic [`AXI_ALEN_WIDTH-1:0] noc_out_awlen,\n input axi_size_t noc_out_awsize,\n input axi_burst_t noc_out_awburst,\n input logic noc_out_awlock,\n input logic [3:0] noc_out_awcache,\n input logic [2:0] noc_out_awprot,\n input logic [3:0] noc_out_awqos,\n input logic [3:0] noc_out_awregion,\n input logic [`AXI_USER_REQ_WIDTH-1:0] noc_out_awuser,\n input logic noc_out_awvalid,\n // Write Data channel\n //input logic noc_out_wid,\n input logic [`AXI_DATA_WIDTH-1:0] noc_out_wdata,\n input logic [(`AXI_DATA_WIDTH/8)-1:0] noc_out_wstrb,\n input logic noc_out_wlast,\n input logic [`AXI_USER_DATA_WIDTH-1:0] noc_out_wuser,\n input logic noc_out_wvalid,\n // Write Response channel\n input logic noc_out_bready,\n // Read Address channel\n input logic noc_out_arid,\n input axi_addr_t noc_out_araddr,\n input logic [`AXI_ALEN_WIDTH-1:0] noc_out_arlen,\n input axi_size_t noc_out_arsize,\n input axi_burst_t noc_out_arburst,\n input logic noc_out_arlock,\n input logic [3:0] noc_out_arcache,\n input logic [2:0] noc_out_arprot,\n input logic [3:0] noc_out_arqos,\n input logic [3:0] noc_out_arregion,\n input logic [`AXI_USER_REQ_WIDTH-1:0] noc_out_aruser,\n input logic noc_out_arvalid,\n // Read Data channel\n input logic noc_out_rready,\n // AXI Interface - MISO\n // Write Addr channel\n output logic noc_out_awready,\n // Write Data channel\n output logic noc_out_wready,\n // Write Response channel\n output logic noc_out_bid,\n output axi_resp_t noc_out_bresp,\n output logic [`AXI_USER_RESP_WIDTH-1:0] noc_out_buser,\n output logic noc_out_bvalid,\n // Read addr channel\n output logic noc_out_arready,\n // Read data channel\n output logic noc_out_rid,\n output logic [`AXI_DATA_WIDTH-1:0] noc_out_rdata,\n output axi_resp_t noc_out_rresp,\n output logic noc_out_rlast,\n output logic [`AXI_USER_REQ_WIDTH-1:0] noc_out_ruser,\n output logic noc_out_rvalid,\n // IRQs\n output logic [NumVirtChn*NoCSize-1:0] irqs_out\n);\n s_axi_mosi_t [NoCSize-1:0] axi_mosi;\n s_axi_miso_t [NoCSize-1:0] axi_miso;\n s_irq_ni_t [NoCSize-1:0] irqs;\n logic [NoCSize-1:0] bypass_cdc_vec;\n logic [NoCSize-1:0] clk_axi_array;\n logic [NoCSize-1:0] arst_axi_array;\n\n always begin\n for (int i=0;i (axi_sel_in != axi_sel_out)\n ) else $error(\"Illegal mux on the AXI!\");\n\nendmodule\n", "groundtruth": " axi_mosi[i].arlock = noc_out_arlock;\n", "crossfile_context": ""} {"task_id": "risc-v-single-cycle", "path": "risc-v-single-cycle/sources_1/new/Alu.sv", "left_context": "\nmodule Alu(\n input logic [3:0] aluControl,\n input logic [31:0] op1, op2,\n output logic [31:0] aluOut,\n output logic isZero\n);\n\n always_comb \n", "right_context": " 4'h2: aluOut <= op1 << op2;\n 4'h3: aluOut <= $signed(op1) < $signed(op2);\n 4'h4: aluOut <= op1 < op2;\n 4'h5: aluOut <= op1 ^ op2;\n 4'h6: aluOut <= $signed(op1) >>> op2;\n 4'h7: aluOut <= op1 >> op2;\n 4'h8: aluOut <= op1 | op2;\n 4'h9: aluOut <= op1 & op2;\n 4'ha: aluOut <= op1 == op2;\n 4'hb: aluOut <= op1 != op2;\n 4'hc: aluOut <= $signed(op1) >= $signed(op2);\n 4'hd: aluOut <= op1 >= op2;\n default: aluOut <= 31'b0;\n endcase\n\n assign isZero = ~|aluOut; \n\nendmodule\n", "groundtruth": " case (aluControl)\n 4'h0: aluOut <= op1 + op2;\n", "crossfile_context": ""} {"task_id": "uvm_example", "path": "uvm_example/src/uvm/ue_pkg.svh", "left_context": "import uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`include \"./interface/ue_interface.sv\"\n\n\n`include \"./obj/ue_transaction.sv\"\n`include \"./obj/ue_config.sv\"\n\n`include \"./obj/sequence/ue_base_sequense.sv\"\n`include \"./obj/sequence/ue_base_sequense_lib.sv\"\n\n\n`include \"./compoment/ue_driver.sv\"\n`include \"./compoment/ue_monitor.sv\"\n`include \"./compoment/ue_sequencer.sv\"\n\n`include \"./compoment/ue_agent.sv\"\n\n`include \"./compoment/ue_ref_model.sv\"\n`include \"./compoment/ue_scoreboard.sv\"\n\n\n`include \"./compoment/ue_env.sv\"\n`include \"./compoment/ue_base_test.sv\"\n\n`include \"./test_case/ue_case0_test.sv\"\n", "right_context": "`include \"./test_case/ue_case2_test.sv\"\n", "groundtruth": "`include \"./test_case/ue_case1_test.sv\"\n", "crossfile_context": ""} {"task_id": "RISC-V-Pipelined-Processor", "path": "RISC-V-Pipelined-Processor/RISC-V Pipelined Processor/RISC-V/ThreebyOneMux.sv", "left_context": "\nmodule ThreebyOneMux\n (\n input[63:0] a,\n input[63:0] b,\n input[63:0] c,\n input [1:0] sel,\n", "right_context": " 2'b00: out = a;\n 2'b01: out = b;\n 2'b10: out = c;\n endcase\n end\nendmodule", "groundtruth": " output reg [63:0] out\r\n );\r\n always @(*)\r\n", "crossfile_context": ""} {"task_id": "UART", "path": "UART/uart_tx.sv", "left_context": "/*\n * Copyright (C) 2018 Siddharth J \n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule uart_tx(clk,rst,start,tx_data_in,tx,tx_active,done_tx);\n\nparameter clk_freq = 50000000; //MHz\nparameter baud_rate = 19200; //bits per second\ninput clk,rst;\ninput start;\ninput [7:0] tx_data_in;\noutput tx;\noutput tx_active;\noutput logic done_tx;\n\nlocalparam clock_divide = (clk_freq/baud_rate);\n\nenum bit [2:0]{ tx_IDLE = 3'b000,\n tx_START = 3'b001,\n\t\ttx_DATA = 3'b010,\n\t tx_STOP = 3'b011,\n\t\ttx_DONE = 3'b100 } tx_STATE, tx_NEXT;\n\t\t\t\t\t \nlogic [11:0] clk_div_reg,clk_div_next;\nlogic [7:0] tx_data_reg, tx_data_next;\nlogic tx_out_reg,tx_out_next;\nlogic [2:0] index_bit_reg,index_bit_next;\n\nassign tx_active = (tx_STATE == tx_DATA);\nassign tx = tx_out_reg;\n\nalways_ff @(posedge clk) begin\nif(rst) begin\ntx_STATE <= tx_IDLE;\nclk_div_reg <= 0;\ntx_out_reg <= 0;\ntx_data_reg <= 0;\nindex_bit_reg <= 0;\nend\nelse begin\ntx_STATE <= tx_NEXT;\nclk_div_reg <= clk_div_next;\ntx_out_reg <= tx_out_next;\ntx_data_reg <= tx_data_next;\nindex_bit_reg <= index_bit_next;\nend\nend\n\nalways @(*) begin\ntx_NEXT = tx_STATE;\nclk_div_next = clk_div_reg;\ntx_out_next = tx_out_reg;\ntx_data_next = tx_data_reg;\nindex_bit_next = index_bit_reg;\ndone_tx = 0;\n\ncase(tx_STATE)\n\ntx_IDLE: begin\ntx_out_next = 1;\nclk_div_next = 0;\nindex_bit_next = 0;\nif(start == 1) begin\ntx_data_next = tx_data_in;\ntx_NEXT = tx_START;\nend\n", "right_context": "tx_NEXT = tx_IDLE;\nend\nend\n\ntx_START: begin\ntx_out_next = 0;\nif(clk_div_reg < clock_divide-1) begin\nclk_div_next = clk_div_reg + 1'b1;\ntx_NEXT = tx_START;\nend\nelse begin\nclk_div_next = 0;\ntx_NEXT = tx_DATA;\nend\nend\n\ntx_DATA: begin\ntx_out_next = tx_data_reg[index_bit_reg];\nif(clk_div_reg < clock_divide-1) begin\nclk_div_next = clk_div_reg + 1'b1;\ntx_NEXT = tx_DATA;\nend\nelse begin\nclk_div_next = 0;\nif(index_bit_reg < 7) begin\nindex_bit_next = index_bit_reg + 1'b1;\ntx_NEXT = tx_DATA;\nend\nelse begin\nindex_bit_next = 0;\ntx_NEXT = tx_STOP; \nend\nend\nend\n\ntx_STOP: begin\ntx_out_next = 1;\nif(clk_div_reg < clock_divide-1) begin\nclk_div_next = clk_div_reg + 1'b1;\ntx_NEXT = tx_STOP;\nend\nelse begin\nclk_div_next = 0;\ntx_NEXT = tx_DONE;\nend\nend\n\ntx_DONE: begin\ndone_tx = 1;\ntx_NEXT = tx_IDLE;\nend\n\ndefault: tx_NEXT = tx_IDLE;\nendcase\nend\n\nendmodule \n\n", "groundtruth": "else begin\n", "crossfile_context": ""} {"task_id": "proto245", "path": "proto245/examples/ft2232h_de10lite/hw/sync245.svh", "left_context": "localparam TX_FIFO_SIZE = 4096;\nlocalparam TX_START_THRESHOLD = 1024;\nlocalparam TX_BURST_SIZE = 0;\nlocalparam TX_BACKOFF_TIMEOUT = 64;\nlocalparam RX_FIFO_SIZE = 4096;\nlocalparam RX_START_THRESHOLD = 3072;\nlocalparam RX_BURST_SIZE = 0;\nlocalparam SINGLE_CLK_DOMAIN = 0;\nlocalparam TX_FIFO_LOAD_W = $clog2(TX_FIFO_SIZE) + 1;\nlocalparam RX_FIFO_LOAD_W = $clog2(RX_FIFO_SIZE) + 1;\n\nlogic [DATA_W-1:0] ft_din, ft_dout;\n\nlogic rxfifo_rd;\nlogic [DATA_W-1:0] rxfifo_data;\nlogic rxfifo_valid;\nlogic [RX_FIFO_LOAD_W-1:0] rxfifo_load;\nlogic rxfifo_empty;\nlogic [DATA_W-1:0] txfifo_data;\nlogic txfifo_wr;\nlogic [TX_FIFO_LOAD_W-1:0] txfifo_load;\nlogic txfifo_full;\n\nproto245s #(\n .DATA_W (DATA_W),\n .TX_FIFO_SIZE (TX_FIFO_SIZE),\n .TX_START_THRESHOLD (TX_START_THRESHOLD),\n .TX_BURST_SIZE (TX_BURST_SIZE),\n .TX_BACKOFF_TIMEOUT (TX_BACKOFF_TIMEOUT),\n .RX_FIFO_SIZE (RX_FIFO_SIZE),\n .RX_START_THRESHOLD (RX_START_THRESHOLD),\n .RX_BURST_SIZE (RX_BURST_SIZE),\n .SINGLE_CLK_DOMAIN (SINGLE_CLK_DOMAIN)\n) proto245 (\n // FT interface - should be routed directly to IO\n .ft_rst (ft_rst),\n .ft_clk (ft_clk),\n .ft_rxfn (ft_rxfn),\n .ft_txen (ft_txen),\n .ft_din (ft_din),\n .ft_dout (ft_dout),\n .ft_bein (0),\n .ft_beout (),\n .ft_rdn (ft_rdn),\n .ft_wrn (ft_wrn),\n .ft_oen (ft_oen),\n .ft_siwu (ft_siwu),\n // RX FIFO (Host -> FTDI chip -> FPGA -> FIFO)\n .rxfifo_clk (sys_clk),\n .rxfifo_rst (sys_rst),\n .rxfifo_rd (rxfifo_rd),\n .rxfifo_data (rxfifo_data),\n .rxfifo_valid (rxfifo_valid),\n .rxfifo_load (rxfifo_load),\n .rxfifo_empty (rxfifo_empty),\n // TX FIFO (FIFO -> FPGA -> FTDI chip -> Host)\n .txfifo_clk (sys_clk),\n .txfifo_rst (sys_rst),\n .txfifo_data (txfifo_data),\n .txfifo_wr (txfifo_wr),\n .txfifo_load (txfifo_load),\n .txfifo_full (txfifo_full)\n);\n\nassign ft_data = ft_oen ? ft_dout : 'z;\n", "right_context": "", "groundtruth": "assign ft_din = ft_data;\n", "crossfile_context": ""} {"task_id": "Async_FIFO_Verification", "path": "Async_FIFO_Verification/tb/SV_OO/tb_classes/tb.svh", "left_context": "/***********************************************************************\n $FILENAME : tb.svh\n\n $TITLE : Testbench module\n\n $DATE : 11 Nov 2017\n\n $VERSION : 1.0.0\n\n $DESCRIPTION : This module defines the high level tester module\n which schedules the entire test scenario.\n\n************************************************************************/\n\n\nclass tb;\n\n // Bus Functional Model interface\n virtual async_fifo_bfm bfm;\n\n tester tester_h;\n coverage coverage_h;\n scoreboard scoreboard_h;\n \n\n //\n // Class constructor method\n //\n function new (virtual async_fifo_bfm b);\n bfm = b;\n endfunction : new\n\n\n //\n // This method launches all the subcomponents of the testbench concurrently\n //\n", "right_context": " tester_h = new(bfm);\n coverage_h = new(bfm);\n scoreboard_h = new(bfm);\n\n fork\n coverage_h.execute();\n scoreboard_h.execute();\n tester_h.execute();\n join_none\n endtask : execute\n\nendclass : tb\n\n", "groundtruth": " task execute();\n", "crossfile_context": ""} {"task_id": "USTC-RVSoC", "path": "USTC-RVSoC/RTL/cpu/core_bus_wrapper.sv", "left_context": "\nmodule core_bus_wrapper(\n input logic clk, rstn,\n input logic i_re, i_we,\n output logic o_conflict,\n input logic [ 2:0] i_funct3,\n input logic [31:0] i_addr,\n input logic [31:0] i_wdata,\n output logic [31:0] o_rdata,\n \n naive_bus.master bus_master\n);\n\nlogic i_re_latch=1'b0, o_conflict_latch=1'b0;\nlogic [1:0] addr_lsb, rd_addr_lsb=2'b0;\nlogic [31:0] addr_bus, wdata, rdata, rdata_latch=0;\nlogic [2:0] rd_funct3=3'b0;\nlogic [3:0] byte_enable;\n\nassign addr_bus = {i_addr[31:2], 2'b0};\nassign addr_lsb = i_addr[1:0];\n\nassign o_conflict = (bus_master.rd_req & ~bus_master.rd_gnt) | (bus_master.wr_req & ~bus_master.wr_gnt);\n\nassign bus_master.rd_req = i_re;\nassign bus_master.rd_be = i_re ? byte_enable : 4'h0;\nassign bus_master.rd_addr = i_re ? addr_bus : 0;\nassign rdata = bus_master.rd_data;\n\nassign bus_master.wr_req = i_we;\nassign bus_master.wr_be = i_we ? byte_enable : 4'h0;\nassign bus_master.wr_addr = i_we ? addr_bus : 0;\nassign bus_master.wr_data = i_we ? wdata : 0;\n\n\nalways_comb\n casex(i_funct3)\n 3'bx00 : if (addr_lsb==2'b00) byte_enable <= 4'b0001;\n else if(addr_lsb==2'b01) byte_enable <= 4'b0010;\n else if(addr_lsb==2'b10) byte_enable <= 4'b0100;\n else byte_enable <= 4'b1000;\n 3'bx01 : if (addr_lsb==2'b00) byte_enable <= 4'b0011;\n else if(addr_lsb==2'b10) byte_enable <= 4'b1100;\n else byte_enable <= 4'b0000;\n 3'b010 : if (addr_lsb==2'b00) byte_enable <= 4'b1111;\n else byte_enable <= 4'b0000;\n default : byte_enable <= 4'b0000;\n endcase\n\n\nalways_comb\n case(i_funct3)\n 3'b000 : if (addr_lsb==2'b00) wdata <= {24'b0, i_wdata[7:0] };\n else if(addr_lsb==2'b01) wdata <= {16'b0, i_wdata[7:0], 8'b0};\n else if(addr_lsb==2'b10) wdata <= { 8'b0, i_wdata[7:0], 16'b0};\n else wdata <= { i_wdata[7:0], 24'b0};\n 3'b001 : if (addr_lsb==2'b00) wdata <= {16'b0, i_wdata[15:0]};\n else if(addr_lsb==2'b10) wdata <= {i_wdata[15:0], 16'b0};\n else wdata <= 0;\n 3'b010 : if (addr_lsb==2'b00) wdata <= i_wdata;\n else wdata <= 0;\n default : wdata <= 0;\n endcase\n \n\nalways @ (posedge clk or negedge rstn)\n if(~rstn) begin\n i_re_latch <= 1'b0;\n rd_addr_lsb <= 2'b0;\n rd_funct3 <= 3'b0;\n o_conflict_latch <= 1'b0;\n rdata_latch <= 0;\n end else begin\n i_re_latch <= i_re;\n rd_addr_lsb <= addr_lsb;\n rd_funct3 <= i_funct3;\n o_conflict_latch <= o_conflict;\n rdata_latch <= o_rdata;\n end\n\n// assign o_rdata\nalways_comb\n if(i_re_latch) begin\n if(~o_conflict_latch)\n case(rd_funct3)\n 3'b000 : if (rd_addr_lsb==2'b00) o_rdata <= {{24{rdata[ 7]}}, rdata[ 7: 0]};\n else if(rd_addr_lsb==2'b01) o_rdata <= {{24{rdata[15]}}, rdata[15: 8]};\n else if(rd_addr_lsb==2'b10) o_rdata <= {{24{rdata[23]}}, rdata[23:16]};\n else o_rdata <= {{24{rdata[31]}}, rdata[31:24]};\n", "right_context": " else if(rd_addr_lsb==2'b10) o_rdata <= {{16{rdata[31]}}, rdata[31:16]};\n else o_rdata <= 0;\n 3'b101 : if (rd_addr_lsb==2'b00) o_rdata <= { 16'b0, rdata[15: 0]};\n else if(rd_addr_lsb==2'b10) o_rdata <= { 16'b0, rdata[31:16]};\n else o_rdata <= 0;\n 3'b010 : if (rd_addr_lsb==2'b00) o_rdata <= rdata;\n else o_rdata <= 0;\n default : o_rdata <= 0;\n endcase\n else\n o_rdata <= 0;\n end else begin\n o_rdata <= rdata_latch;\n end\n\nendmodule\n", "groundtruth": " 3'b100 : if (rd_addr_lsb==2'b00) o_rdata <= { 24'b0, rdata[ 7: 0]};\r\n else if(rd_addr_lsb==2'b01) o_rdata <= { 24'b0, rdata[15: 8]};\r\n else if(rd_addr_lsb==2'b10) o_rdata <= { 24'b0, rdata[23:16]};\r\n", "crossfile_context": ""} {"task_id": "ahb3lite_interconnect", "path": "ahb3lite_interconnect/rtl/verilog/ahb3lite_interconnect_slave_priority.sv", "left_context": "/////////////////////////////////////////////////////////////////////\n// ,------. ,--. ,--. //\n// | .--. ' ,---. ,--,--. | | ,---. ,---. `--' ,---. //\n// | '--'.'| .-. |' ,-. | | | | .-. | .-. |,--.| .--' //\n// | |\\ \\ ' '-' '\\ '-' | | '--.' '-' ' '-' || |\\ `--. //\n// `--' '--' `---' `--`--' `-----' `---' `- /`--' `---' //\n// `---' //\n// AHB3-Lite Interconnect Switch (Multi-Layer Switch) //\n// Slave Priority decoder //\n// //\n/////////////////////////////////////////////////////////////////////\n// //\n// Copyright (C) 2016-2023 ROA Logic BV //\n// www.roalogic.com //\n// //\n// Unless specifically agreed in writing, this software is //\n// licensed under the RoaLogic Non-Commercial License //\n// version-1.0 (the \"License\"), a copy of which is included //\n// with this file or may be found on the RoaLogic website //\n// http://www.roalogic.com. You may not use the file except //\n// in compliance with the License. //\n// //\n// THIS SOFTWARE IS PROVIDED \"AS IS\" AND WITHOUT ANY //\n// EXPRESS OF IMPLIED WARRANTIES OF ANY KIND. //\n// See the License for permissions and limitations under the //\n// License. //\n// //\n/////////////////////////////////////////////////////////////////////\n\n\n// +FHDR - Semiconductor Reuse Standard File Header Section -------\n// FILE NAME : ahb3lite_interconnect_slave_priority.sv\n// DEPARTMENT :\n// AUTHOR : rherveille\n// AUTHOR'S EMAIL :\n// ------------------------------------------------------------------\n// RELEASE HISTORY\n// VERSION DATE AUTHOR DESCRIPTION\n// 1.0 2019-09-01 rherveille initial release\n// ------------------------------------------------------------------\n// KEYWORDS : AMBA AHB AHB3-Lite Interconnect Matrix\n// ------------------------------------------------------------------\n// PURPOSE : Builds a binary tree to search for the highest priority\n// ------------------------------------------------------------------\n// PARAMETERS\n// PARAM NAME RANGE DESCRIPTION DEFAULT UNITS\n// SOURCES 1+ No. of interupt sources 8\n// PRIORITIES 1+ No. of priority levels 8\n// HI\n// LO\n// ------------------------------------------------------------------\n// REUSE ISSUES \n// Reset Strategy : none\n// Clock Domains : none\n// Critical Timing :\n// Test Features : na\n// Asynchronous I/F : yes\n// Scan Methodology : na\n// Instantiations : Itself (recursive)\n// Synthesizable (y/n) : Yes\n// Other : \n// -FHDR-------------------------------------------------------------\n\nmodule ahb3lite_interconnect_slave_priority #(\n parameter MASTERS = 3,\n parameter HI = MASTERS-1,\n parameter LO = 0,\n\n //really a localparam\n parameter PRIORITY_BITS = MASTERS==1 ? 1 : $clog2(MASTERS)\n)\n(\n input [MASTERS -1:0] HSEL,\n input [MASTERS -1:0][PRIORITY_BITS-1:0] priority_i,\n output [PRIORITY_BITS-1:0] priority_o\n);\n\n //////////////////////////////////////////////////////////////////\n //\n // Variables\n //\n\n logic [PRIORITY_BITS-1:0] priority_hi, priority_lo;\n\n //initial if (HI-LO>1) $display (\"HI=%0d, LO=%0d -> hi(%0d,%0d) lo(%0d,%0d)\", HI, LO, HI, HI-(HI-LO)/2, LO+(HI-LO)/2, LO);\n\n //////////////////////////////////////////////////////////////////\n //\n // Module Body\n //\n\n generate\n if (HI - LO > 1)\n begin\n //built tree ...\n ahb3lite_interconnect_slave_priority #(\n .MASTERS ( MASTERS ),\n .HI ( LO + (HI-LO)/2 ),\n .LO ( LO )\n )\n lo (\n .HSEL ( HSEL ),\n .priority_i ( priority_i ),\n .priority_o ( priority_lo )\n );\n\n ahb3lite_interconnect_slave_priority #(\n .MASTERS ( MASTERS ),\n", "right_context": " .LO ( HI - (HI-LO)/2 )\n ) hi\n (\n .HSEL ( HSEL ),\n .priority_i ( priority_i ),\n .priority_o ( priority_hi )\n );\n end\n else\n begin\n //get priority for master[LO] and master[HI]\n //set priority to 0 when HSEL negated\n assign priority_lo = HSEL[LO] ? priority_i[LO] : {PRIORITY_BITS{1'b0}};\n assign priority_hi = HSEL[HI] ? priority_i[HI] : {PRIORITY_BITS{1'b0}};\n end\n endgenerate\n\n\n //finally do comparison\n assign priority_o = priority_hi > priority_lo ? priority_hi : priority_lo;\n\nendmodule : ahb3lite_interconnect_slave_priority\n\n", "groundtruth": " .HI ( HI ),\n", "crossfile_context": ""} {"task_id": "my_verilog_projects", "path": "my_verilog_projects/parallel_serial_switch/serial_to_parallel.v", "left_context": "module serial_to_parallel #(parameter WEIDTH=8)\n(\n\tinput rst_n,\n\tinput clk,\n\tinput data_in,\n\toutput reg [WEIDTH-1:0] data_out,\n", "right_context": ");\n\n\nreg [2:0] cnt;\n\nalways@(posedge clk or negedge rst_n) begin\n\tif(!rst_n) begin\n\t\tdata_out<=8'b0;\n\t\tend\n\telse begin\n\t\tdata_out<={data_out[WEIDTH-2:0],data_in};\n\tend\nend\n\n\nendmodule", "groundtruth": "\toutput done\n", "crossfile_context": ""} {"task_id": "systemverilog.io", "path": "systemverilog.io/macros/macros1.sv", "left_context": "/*\n * Article:\n * SystemVerilog Macros\n *\n * Description:\n * This file has examples 1.1, 1.2 and 1.3. The run command will run\n * all 3 examples\n * \n * Run instructions\n * (use run_questa.sh instead of run_vcs.sh to run with Mentor simulator):\n * ./run_vcs.sh macros1.sv\n */\n/* Example 1.1 */\n`define simplemacro $display(\"\\n This is a simple macro\\n\");\n", "right_context": "`define append_front_1_good(MOD) `\"MOD.master`\"\n\n/* Example 1.2 */\n`define append_front_2a(MOD) `\"MOD.master`\"\n`define append_front_2b(MOD) `\"MOD master`\"\n`define append_front_2c_bad(MOD) `\"MOD_master`\"\n`define append_front_2c_good(MOD) `\"MOD``_master`\"\n`define append_middle(MOD) `\"top_``MOD``_master`\"\n`define append_end(MOD) `\"top_``MOD`\"\n`define append_front_3(MOD) `\"MOD``.master`\"\n\n/* Example 1.3 */\n`define complex_string(ARG1, ARG2) \\\n `\"This `\\`\"Blue``ARG1`\\`\" is Really `\\`\"ARG2`\\`\"`\"\n\nprogram automatic test;\n initial begin\n /* Example 1.1 */\n `simplemacro\n $display(`append_front_1_bad(clock1));\n $display(`append_front_1_good(clock1));\n \n /* Example 1.2 */\n $display(`append_front_2a(clock2a));\n $display(`append_front_2b(clock2b));\n $display(`append_front_2c_bad(clock2c));\n $display(`append_front_2c_good(clock2c));\n $display(`append_front_3(clock3));\n $display(`append_middle(clock4));\n $display(`append_end(clock5));\n\n /* Example 1.3 */\n $display(`complex_string(Beast, Black));\n end\nendprogram: test\n", "groundtruth": "`define append_front_1_bad(MOD) \"MOD.master\"\n", "crossfile_context": ""} {"task_id": "i2c_vip", "path": "i2c_vip/I2C_tb_files/src/slave_agt_top/slave_agt_top.sv", "left_context": "// ############################################################################\n//\n// Project : Verification of I2C VIP\n//\n// File_name : slave_agt_top.sv\n//\n// https://github.com/muneebullashariff/i2c_vip\n//\n// ############################################################################\n\n//-----------------------------------------------------------------------------\n// Class: slave_agt_top\n// Description of the class :\n// This class acts like a container to slave agents \n//-----------------------------------------------------------------------------\n\n\nclass slave_agt_top extends uvm_agent;\n`uvm_component_utils(slave_agt_top)\n\nslave_agent sagt[];\nenvironment_config ecfg;\n\n\n//---------------------------------------------\n// Externally defined tasks and functions\n//---------------------------------------------\n\n\nextern function new(string name=\"slave_agt_top\",uvm_component parent);\nextern function void build_phase(uvm_phase phase);\n\nendclass\n\n//-----------------------------------------------------------------------------\n// Constructor: new\n// Initializes the slave_agt_top class object\n//\n// Parameters:\n// name - instance name of the slave_agt_top\n// parent - parent under which this component is created\n//-----------------------------------------------------------------------------\n\n\nfunction slave_agt_top::new(string name=\"slave_agt_top\",uvm_component parent);\n", "right_context": "endfunction:new\n\n\n//-----------------------------------------------------------------------------\n// Function: build_phase\n// Creates the slave_agent components \n//\n// Parameters:\n// phase - stores the current phase \n//-----------------------------------------------------------------------------\n\n\nfunction void slave_agt_top::build_phase(uvm_phase phase);\n if(!uvm_config_db#(environment_config)::get(this,\"\",\"ENVIRONMENT_CONFIG\",ecfg))\n `uvm_fatal(\"SLAVE_AGT_TOP\",\"couldnt get\")\n\n sagt=new[ecfg.no_of_sagent];\nforeach(sagt[i])\n begin\n sagt[i]=slave_agent::type_id::create($sformatf(\"magt[%0d]\",i),this);\n uvm_config_db#(slave_agent_config)::set(this,\"*\",\"SLAVE_AGT_CONFIG\",ecfg.scfg[i]);\n end\nendfunction:build_phase\n", "groundtruth": "\tsuper.new(name,parent);\n", "crossfile_context": ""} {"task_id": "reDIP-SID", "path": "reDIP-SID/gateware/cells_sim/SB_RGBA_DRV.v", "left_context": "/* verilator lint_off UNUSED */\n/* verilator lint_off UNDRIVEN */\n(* blackbox *)\nmodule SB_RGBA_DRV(\n\tinput CURREN,\n", "right_context": "parameter RGB0_CURRENT = \"0b000000\";\nparameter RGB1_CURRENT = \"0b000000\";\nparameter RGB2_CURRENT = \"0b000000\";\nendmodule\n/* verilator lint_on UNDRIVEN */\n/* verilator lint_on UNUSED */\n", "groundtruth": "\tinput RGBLEDEN,\n\tinput RGB0PWM,\n\tinput RGB1PWM,\n\tinput RGB2PWM,\n\toutput RGB0,\n", "crossfile_context": ""} {"task_id": "CX", "path": "CX/2019/bnn.v", "left_context": "// Copyright (C) 2019, Gray Research LLC\n//\n\n//////////////////////////////////////////////////////////////////////////////\n// BNNDotProd CFU\n\n/* verilator lint_off DECLFILENAME */\n\n`include \"cfu.vh\"\n\n// Test bench\nmodule BNNDotProd32TB #(\n parameter CFU_FUNC_ID_W = 1,\n parameter CFU_REQ_DATA_W = 32,\n parameter CFU_RESP_DATA_W = CFU_REQ_DATA_W\n) (\n input clk,\n input [15:0] cycle,\n input [15:0] lfsr);\n\n wire `CFU_FUNC_ID req_func_id = 0;\n reg `CFU_REQ_DATA req_data0 `vp = 0;\n reg `CFU_REQ_DATA req_data1 `vp = 0;\n reg `CFU_RESP_DATA resp_data `vp = 0;\n\n reg `CFU_RESP_DATA xnor_ `vp = 0;\n reg `CFU_RESP_DATA answer `vp = 0;\n int i;\n always @* begin\n req_data0 = {cycle-1'b1,cycle};\n req_data1 = {16'b0,lfsr};\n\n xnor_ = req_data0 ~^ req_data1;\n answer = 0;\n for (i = 0; i < CFU_REQ_DATA_W; i = i + 1) begin\n if (xnor_[i])\n answer = answer + 1;\n end\n end\n\n BNNDotProd32_CFU_LI0 #(\n .CFU_FUNC_ID_W(CFU_FUNC_ID_W),\n .CFU_REQ_DATA_W(CFU_REQ_DATA_W),\n .CFU_RESP_DATA_W(CFU_RESP_DATA_W))\n", "right_context": " end\nendmodule\n\n\n// Level-0 (Combinational) 1b binary neural net dot product combinational CFU\n//\n// A binary neural net has 1b weights and activations, each encoded { 0=>+1, 1=>-1 }.\n// The (biased) dot product of W: w*1b weights and A: w*1b activations is popcount(W~^A).\n//\n// (Obselete) Metadata -- REVIEW\n// Supports: REQ_WIDTH==32 or REQ_WIDTH==64\n// IID: IID_BNNDotProd\n// Functions: {BNNDotProd}\n// Inputs: w*1b activations, w*1b weights\n// Outputs: w-bit BNN dot product\n// \n/* Metadata\nCFU_LI:\n - feature_level: 0\n - cfu_req_data_w: [32]\n - cfu_resp_data_w: [32]\n - cfu_func_id_w: [1]\n*/\nmodule BNNDotProd32_CFU_LI0 #(\n parameter CFU_FUNC_ID_W = 1,\n parameter CFU_REQ_DATA_W = 32,\n parameter CFU_RESP_DATA_W = 32\n) (\n input req_valid, // unused\n input `CFU_FUNC_ID req_func_id, // unused\n input `CFU_REQ_DATA req_data0,\n input `CFU_REQ_DATA req_data1,\n output `CFU_RESP_DATA resp_data\n);\n wire `CFU_REQ_DATA xnor_ = req_data0 ~^ req_data1;\n wire [5:0] count;\n Popcount32 count_(.i(xnor_), .popcount(count));\n assign resp_data = {26'b0,count};\n\n // assert(req_function_id == IID_BNNDotProd32.BNNDotProd32)\n wire _unused_ok = &{1'b0,req_valid,req_func_id,1'b0};\nendmodule\n\n", "groundtruth": " bnn(.req_valid(1'b1), .req_func_id(req_func_id), .req_data0(req_data0), .req_data1(req_data1), .resp_data(resp_data));\n\n always @(posedge clk) begin\n", "crossfile_context": ""} {"task_id": "RecoNIC", "path": "RecoNIC/sim/src/axi_5to2_interconnect_to_sys_mem.sv", "left_context": "//==============================================================================\n// Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.\n// SPDX-License-Identifier: MIT\n//\n//==============================================================================\n`timescale 1ns/1ps\n\nmodule axi_5to2_interconnect_to_sys_mem #(\n parameter C_AXI_DATA_WIDTH = 512,\n parameter C_AXI_ADDR_WIDTH = 64\n) (\n input s_axi_rdma_get_wqe_awid,\n input [63 : 0] s_axi_rdma_get_wqe_awaddr,\n input [3 : 0] s_axi_rdma_get_wqe_awqos,\n input [7 : 0] s_axi_rdma_get_wqe_awlen,\n input [2 : 0] s_axi_rdma_get_wqe_awsize,\n input [1 : 0] s_axi_rdma_get_wqe_awburst,\n input [3 : 0] s_axi_rdma_get_wqe_awcache,\n input [2 : 0] s_axi_rdma_get_wqe_awprot,\n input s_axi_rdma_get_wqe_awvalid,\n output s_axi_rdma_get_wqe_awready,\n input [511 : 0] s_axi_rdma_get_wqe_wdata,\n input [63 : 0] s_axi_rdma_get_wqe_wstrb,\n input s_axi_rdma_get_wqe_wlast,\n input s_axi_rdma_get_wqe_wvalid,\n output s_axi_rdma_get_wqe_wready,\n input s_axi_rdma_get_wqe_awlock,\n output s_axi_rdma_get_wqe_bid,\n output [1 : 0] s_axi_rdma_get_wqe_bresp,\n output s_axi_rdma_get_wqe_bvalid,\n input s_axi_rdma_get_wqe_bready,\n input s_axi_rdma_get_wqe_arid,\n input [63 : 0] s_axi_rdma_get_wqe_araddr,\n input [7 : 0] s_axi_rdma_get_wqe_arlen,\n input [2 : 0] s_axi_rdma_get_wqe_arsize,\n input [1 : 0] s_axi_rdma_get_wqe_arburst,\n input [3 : 0] s_axi_rdma_get_wqe_arcache,\n input [2 : 0] s_axi_rdma_get_wqe_arprot,\n input s_axi_rdma_get_wqe_arvalid,\n output s_axi_rdma_get_wqe_arready,\n output s_axi_rdma_get_wqe_rid,\n output [511 : 0] s_axi_rdma_get_wqe_rdata,\n output [1 : 0] s_axi_rdma_get_wqe_rresp,\n output s_axi_rdma_get_wqe_rlast,\n output s_axi_rdma_get_wqe_rvalid,\n input s_axi_rdma_get_wqe_rready,\n input s_axi_rdma_get_wqe_arlock,\n input [3 : 0] s_axi_rdma_get_wqe_arqos,\n\n input [1 : 0] s_axi_rdma_get_payload_awid,\n input [63 : 0] s_axi_rdma_get_payload_awaddr,\n input [3 : 0] s_axi_rdma_get_payload_awqos,\n input [7 : 0] s_axi_rdma_get_payload_awlen,\n input [2 : 0] s_axi_rdma_get_payload_awsize,\n input [1 : 0] s_axi_rdma_get_payload_awburst,\n input [3 : 0] s_axi_rdma_get_payload_awcache,\n input [2 : 0] s_axi_rdma_get_payload_awprot,\n input s_axi_rdma_get_payload_awvalid,\n output s_axi_rdma_get_payload_awready,\n input [511 : 0] s_axi_rdma_get_payload_wdata,\n input [63 : 0] s_axi_rdma_get_payload_wstrb,\n input s_axi_rdma_get_payload_wlast,\n input s_axi_rdma_get_payload_wvalid,\n output s_axi_rdma_get_payload_wready,\n input s_axi_rdma_get_payload_awlock,\n output [1 : 0] s_axi_rdma_get_payload_bid,\n output [1 : 0] s_axi_rdma_get_payload_bresp,\n output s_axi_rdma_get_payload_bvalid,\n input s_axi_rdma_get_payload_bready,\n input [1 : 0] s_axi_rdma_get_payload_arid,\n input [63 : 0] s_axi_rdma_get_payload_araddr,\n input [7 : 0] s_axi_rdma_get_payload_arlen,\n input [2 : 0] s_axi_rdma_get_payload_arsize,\n input [1 : 0] s_axi_rdma_get_payload_arburst,\n input [3 : 0] s_axi_rdma_get_payload_arcache,\n input [2 : 0] s_axi_rdma_get_payload_arprot,\n input s_axi_rdma_get_payload_arvalid,\n output s_axi_rdma_get_payload_arready,\n output [1 : 0] s_axi_rdma_get_payload_rid,\n output [511 : 0] s_axi_rdma_get_payload_rdata,\n output [1 : 0] s_axi_rdma_get_payload_rresp,\n output s_axi_rdma_get_payload_rlast,\n output s_axi_rdma_get_payload_rvalid,\n input s_axi_rdma_get_payload_rready,\n input s_axi_rdma_get_payload_arlock,\n input [3 : 0] s_axi_rdma_get_payload_arqos,\n\n input s_axi_rdma_completion_awid,\n input [63 : 0] s_axi_rdma_completion_awaddr,\n input [3 : 0] s_axi_rdma_completion_awqos,\n input [7 : 0] s_axi_rdma_completion_awlen,\n input [2 : 0] s_axi_rdma_completion_awsize,\n input [1 : 0] s_axi_rdma_completion_awburst,\n input [3 : 0] s_axi_rdma_completion_awcache,\n input [2 : 0] s_axi_rdma_completion_awprot,\n input s_axi_rdma_completion_awvalid,\n output s_axi_rdma_completion_awready,\n input [511 : 0] s_axi_rdma_completion_wdata,\n input [63 : 0] s_axi_rdma_completion_wstrb,\n input s_axi_rdma_completion_wlast,\n input s_axi_rdma_completion_wvalid,\n output s_axi_rdma_completion_wready,\n input s_axi_rdma_completion_awlock,\n output s_axi_rdma_completion_bid,\n output [1 : 0] s_axi_rdma_completion_bresp,\n output s_axi_rdma_completion_bvalid,\n input s_axi_rdma_completion_bready,\n input s_axi_rdma_completion_arid,\n input [63 : 0] s_axi_rdma_completion_araddr,\n input [7 : 0] s_axi_rdma_completion_arlen,\n input [2 : 0] s_axi_rdma_completion_arsize,\n input [1 : 0] s_axi_rdma_completion_arburst,\n input [3 : 0] s_axi_rdma_completion_arcache,\n input [2 : 0] s_axi_rdma_completion_arprot,\n input s_axi_rdma_completion_arvalid,\n output s_axi_rdma_completion_arready,\n output s_axi_rdma_completion_rid,\n output [511 : 0] s_axi_rdma_completion_rdata,\n output [1 : 0] s_axi_rdma_completion_rresp,\n output s_axi_rdma_completion_rlast,\n output s_axi_rdma_completion_rvalid,\n input s_axi_rdma_completion_rready,\n input s_axi_rdma_completion_arlock,\n input [3 : 0] s_axi_rdma_completion_arqos,\n\n input s_axi_rdma_send_write_payload_awid,\n input [63 : 0] s_axi_rdma_send_write_payload_awaddr,\n input [3 : 0] s_axi_rdma_send_write_payload_awqos,\n input [7 : 0] s_axi_rdma_send_write_payload_awlen,\n input [2 : 0] s_axi_rdma_send_write_payload_awsize,\n input [1 : 0] s_axi_rdma_send_write_payload_awburst,\n input [3 : 0] s_axi_rdma_send_write_payload_awcache,\n input [2 : 0] s_axi_rdma_send_write_payload_awprot,\n input s_axi_rdma_send_write_payload_awvalid,\n output s_axi_rdma_send_write_payload_awready,\n input [511 : 0] s_axi_rdma_send_write_payload_wdata,\n input [63 : 0] s_axi_rdma_send_write_payload_wstrb,\n input s_axi_rdma_send_write_payload_wlast,\n input s_axi_rdma_send_write_payload_wvalid,\n output s_axi_rdma_send_write_payload_wready,\n input s_axi_rdma_send_write_payload_awlock,\n output s_axi_rdma_send_write_payload_bid,\n output [1 : 0] s_axi_rdma_send_write_payload_bresp,\n output s_axi_rdma_send_write_payload_bvalid,\n input s_axi_rdma_send_write_payload_bready,\n input s_axi_rdma_send_write_payload_arid,\n input [63 : 0] s_axi_rdma_send_write_payload_araddr,\n input [7 : 0] s_axi_rdma_send_write_payload_arlen,\n input [2 : 0] s_axi_rdma_send_write_payload_arsize,\n input [1 : 0] s_axi_rdma_send_write_payload_arburst,\n input [3 : 0] s_axi_rdma_send_write_payload_arcache,\n input [2 : 0] s_axi_rdma_send_write_payload_arprot,\n input s_axi_rdma_send_write_payload_arvalid,\n output s_axi_rdma_send_write_payload_arready,\n output s_axi_rdma_send_write_payload_rid,\n output [511 : 0] s_axi_rdma_send_write_payload_rdata,\n output [1 : 0] s_axi_rdma_send_write_payload_rresp,\n output s_axi_rdma_send_write_payload_rlast,\n output s_axi_rdma_send_write_payload_rvalid,\n input s_axi_rdma_send_write_payload_rready,\n input s_axi_rdma_send_write_payload_arlock,\n input [3 : 0] s_axi_rdma_send_write_payload_arqos,\n\n input s_axi_rdma_rsp_payload_awid,\n input [63 : 0] s_axi_rdma_rsp_payload_awaddr,\n input [3 : 0] s_axi_rdma_rsp_payload_awqos,\n input [7 : 0] s_axi_rdma_rsp_payload_awlen,\n input [2 : 0] s_axi_rdma_rsp_payload_awsize,\n input [1 : 0] s_axi_rdma_rsp_payload_awburst,\n input [3 : 0] s_axi_rdma_rsp_payload_awcache,\n input [2 : 0] s_axi_rdma_rsp_payload_awprot,\n input s_axi_rdma_rsp_payload_awvalid,\n output s_axi_rdma_rsp_payload_awready,\n input [511 : 0] s_axi_rdma_rsp_payload_wdata,\n input [63 : 0] s_axi_rdma_rsp_payload_wstrb,\n input s_axi_rdma_rsp_payload_wlast,\n input s_axi_rdma_rsp_payload_wvalid,\n output s_axi_rdma_rsp_payload_wready,\n input s_axi_rdma_rsp_payload_awlock,\n output s_axi_rdma_rsp_payload_bid,\n output [1 : 0] s_axi_rdma_rsp_payload_bresp,\n output s_axi_rdma_rsp_payload_bvalid,\n input s_axi_rdma_rsp_payload_bready,\n input s_axi_rdma_rsp_payload_arid,\n input [63 : 0] s_axi_rdma_rsp_payload_araddr,\n input [7 : 0] s_axi_rdma_rsp_payload_arlen,\n input [2 : 0] s_axi_rdma_rsp_payload_arsize,\n input [1 : 0] s_axi_rdma_rsp_payload_arburst,\n input [3 : 0] s_axi_rdma_rsp_payload_arcache,\n input [2 : 0] s_axi_rdma_rsp_payload_arprot,\n input s_axi_rdma_rsp_payload_arvalid,\n output s_axi_rdma_rsp_payload_arready,\n output s_axi_rdma_rsp_payload_rid,\n output [511 : 0] s_axi_rdma_rsp_payload_rdata,\n output [1 : 0] s_axi_rdma_rsp_payload_rresp,\n output s_axi_rdma_rsp_payload_rlast,\n output s_axi_rdma_rsp_payload_rvalid,\n input s_axi_rdma_rsp_payload_rready,\n input s_axi_rdma_rsp_payload_arlock,\n input [3 : 0] s_axi_rdma_rsp_payload_arqos,\n\n output [2:0] m_axi_sys_mem_awid,\n output [63:0] m_axi_sys_mem_awaddr,\n output [7:0] m_axi_sys_mem_awlen,\n output [2:0] m_axi_sys_mem_awsize,\n output [1:0] m_axi_sys_mem_awburst,\n output m_axi_sys_mem_awlock,\n output [3:0] m_axi_sys_mem_awqos,\n output [3:0] m_axi_sys_mem_awregion,\n output [3:0] m_axi_sys_mem_awcache,\n output [2:0] m_axi_sys_mem_awprot,\n output m_axi_sys_mem_awvalid,\n input m_axi_sys_mem_awready,\n output [511:0] m_axi_sys_mem_wdata,\n output [63:0] m_axi_sys_mem_wstrb,\n output m_axi_sys_mem_wlast,\n output m_axi_sys_mem_wvalid,\n input m_axi_sys_mem_wready,\n input [2:0] m_axi_sys_mem_bid,\n input [1:0] m_axi_sys_mem_bresp,\n input m_axi_sys_mem_bvalid,\n output m_axi_sys_mem_bready,\n output [2:0] m_axi_sys_mem_arid,\n output [63:0] m_axi_sys_mem_araddr,\n output [7:0] m_axi_sys_mem_arlen,\n output [2:0] m_axi_sys_mem_arsize,\n output [1:0] m_axi_sys_mem_arburst,\n output m_axi_sys_mem_arlock,\n output [3:0] m_axi_sys_mem_arqos,\n output [3:0] m_axi_sys_mem_arregion,\n output [3:0] m_axi_sys_mem_arcache,\n output [2:0] m_axi_sys_mem_arprot,\n output m_axi_sys_mem_arvalid,\n input m_axi_sys_mem_arready,\n input [2:0] m_axi_sys_mem_rid,\n input [511:0] m_axi_sys_mem_rdata,\n input [1:0] m_axi_sys_mem_rresp,\n input m_axi_sys_mem_rlast,\n input m_axi_sys_mem_rvalid,\n output m_axi_sys_mem_rready,\n\n output [2:0] m_axi_sys_to_dev_crossbar_awid,\n output [63:0] m_axi_sys_to_dev_crossbar_awaddr,\n output [7:0] m_axi_sys_to_dev_crossbar_awlen,\n output [2:0] m_axi_sys_to_dev_crossbar_awsize,\n output [1:0] m_axi_sys_to_dev_crossbar_awburst,\n output m_axi_sys_to_dev_crossbar_awlock,\n output [3:0] m_axi_sys_to_dev_crossbar_awqos,\n output [3:0] m_axi_sys_to_dev_crossbar_awregion,\n output [3:0] m_axi_sys_to_dev_crossbar_awcache,\n output [2:0] m_axi_sys_to_dev_crossbar_awprot,\n output m_axi_sys_to_dev_crossbar_awvalid,\n input m_axi_sys_to_dev_crossbar_awready,\n output [511:0] m_axi_sys_to_dev_crossbar_wdata,\n output [63:0] m_axi_sys_to_dev_crossbar_wstrb,\n output m_axi_sys_to_dev_crossbar_wlast,\n output m_axi_sys_to_dev_crossbar_wvalid,\n input m_axi_sys_to_dev_crossbar_wready,\n input [2:0] m_axi_sys_to_dev_crossbar_bid,\n input [1:0] m_axi_sys_to_dev_crossbar_bresp,\n input m_axi_sys_to_dev_crossbar_bvalid,\n output m_axi_sys_to_dev_crossbar_bready,\n output [2:0] m_axi_sys_to_dev_crossbar_arid,\n output [63:0] m_axi_sys_to_dev_crossbar_araddr,\n output [7:0] m_axi_sys_to_dev_crossbar_arlen,\n output [2:0] m_axi_sys_to_dev_crossbar_arsize,\n output [1:0] m_axi_sys_to_dev_crossbar_arburst,\n output m_axi_sys_to_dev_crossbar_arlock,\n output [3:0] m_axi_sys_to_dev_crossbar_arqos,\n output [3:0] m_axi_sys_to_dev_crossbar_arregion,\n output [3:0] m_axi_sys_to_dev_crossbar_arcache,\n output [2:0] m_axi_sys_to_dev_crossbar_arprot,\n output m_axi_sys_to_dev_crossbar_arvalid,\n input m_axi_sys_to_dev_crossbar_arready,\n input [2:0] m_axi_sys_to_dev_crossbar_rid,\n input [511:0] m_axi_sys_to_dev_crossbar_rdata,\n input [1:0] m_axi_sys_to_dev_crossbar_rresp,\n input m_axi_sys_to_dev_crossbar_rlast,\n input m_axi_sys_to_dev_crossbar_rvalid,\n output m_axi_sys_to_dev_crossbar_rready,\n\n input axis_aclk,\n input axis_arestn\n);\n\nlocalparam C_NUM_MASTERS = 5;\nlocalparam C_NUM_SLAVES = 2;\n\n\nlocalparam C_RDMA_GET_WQE_IDX = 0;\nlocalparam C_RDMA_GET_PAYLOAD_IDX = 1;\nlocalparam C_RDMA_COMPLETION_IDX = 2;\nlocalparam C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX = 3;\nlocalparam C_RDMA_RSP_PAYLOAD_IDX = 4;\n\nlocalparam C_SYS_MEM_IDX = 0;\nlocalparam C_SYS_TO_DEV_CROSSBAR_IDX = 1;\n\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_awid;\nlogic [C_NUM_MASTERS*64-1 : 0] s_axi_awaddr;\nlogic [C_NUM_MASTERS*8-1 : 0] s_axi_awlen;\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_awsize;\nlogic [C_NUM_MASTERS*2-1 : 0] s_axi_awburst;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_awlock;\nlogic [C_NUM_MASTERS*4-1 : 0] s_axi_awcache;\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_awprot;\nlogic [C_NUM_MASTERS*4-1 : 0] s_axi_awqos;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_awvalid;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_awready;\nlogic [C_NUM_MASTERS*512-1 : 0] s_axi_wdata;\nlogic [C_NUM_MASTERS*64-1 : 0] s_axi_wstrb;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_wlast;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_wvalid;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_wready;\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_bid;\nlogic [C_NUM_MASTERS*2-1 : 0] s_axi_bresp;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_bvalid;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_bready;\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_arid;\nlogic [C_NUM_MASTERS*64-1 : 0] s_axi_araddr;\nlogic [C_NUM_MASTERS*8-1 : 0] s_axi_arlen;\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_arsize;\nlogic [C_NUM_MASTERS*2-1 : 0] s_axi_arburst;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_arlock;\nlogic [C_NUM_MASTERS*4-1 : 0] s_axi_arcache;\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_arprot;\nlogic [C_NUM_MASTERS*4-1 : 0] s_axi_arqos;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_arvalid;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_arready;\nlogic [C_NUM_MASTERS*3-1 : 0] s_axi_rid;\nlogic [C_NUM_MASTERS*512-1 : 0] s_axi_rdata;\nlogic [C_NUM_MASTERS*2-1 : 0] s_axi_rresp;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_rlast;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_rvalid;\nlogic [C_NUM_MASTERS-1 : 0] s_axi_rready;\n\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_awid;\nlogic [C_NUM_SLAVES*64-1 : 0] m_axi_awaddr;\nlogic [C_NUM_SLAVES*8-1 : 0] m_axi_awlen;\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_awsize;\nlogic [C_NUM_SLAVES*2-1 : 0] m_axi_awburst;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_awlock;\nlogic [C_NUM_SLAVES*4-1 : 0] m_axi_awcache;\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_awprot;\nlogic [C_NUM_SLAVES*4-1 : 0] m_axi_awqos;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_awvalid;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_awready;\nlogic [C_NUM_SLAVES*512-1 : 0] m_axi_wdata;\nlogic [C_NUM_SLAVES*64-1 : 0] m_axi_wstrb;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_wlast;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_wvalid;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_wready;\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_bid;\nlogic [C_NUM_SLAVES*2-1 : 0] m_axi_bresp;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_bvalid;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_bready;\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_arid;\nlogic [C_NUM_SLAVES*64-1 : 0] m_axi_araddr;\nlogic [C_NUM_SLAVES*8-1 : 0] m_axi_arlen;\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_arsize;\nlogic [C_NUM_SLAVES*2-1 : 0] m_axi_arburst;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_arlock;\nlogic [C_NUM_SLAVES*4-1 : 0] m_axi_arcache;\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_arprot;\nlogic [C_NUM_SLAVES*4-1 : 0] m_axi_arqos;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_arvalid;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_arready;\nlogic [C_NUM_SLAVES*3-1 : 0] m_axi_rid;\nlogic [C_NUM_SLAVES*512-1 : 0] m_axi_rdata;\nlogic [C_NUM_SLAVES*2-1 : 0] m_axi_rresp;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_rlast;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_rvalid;\nlogic [C_NUM_SLAVES-1 : 0] m_axi_rready;\n\n// AXI slave signals for getting wqe from system memory\n//assign s_axi_awid [C_RDMA_GET_WQE_IDX *2 +: 2] = {1'b0, s_axi_rdma_get_wqe_awid};\nassign s_axi_awid [C_RDMA_GET_WQE_IDX *3 +: 3] = s_axi_rdma_get_wqe_awvalid ? 3'd0 : 3'd0;\nassign s_axi_awaddr [C_RDMA_GET_WQE_IDX *64 +: 64] = s_axi_rdma_get_wqe_awaddr;\nassign s_axi_awqos [C_RDMA_GET_WQE_IDX *4 +: 4] = s_axi_rdma_get_wqe_awqos;\nassign s_axi_awlen [C_RDMA_GET_WQE_IDX *8 +: 8] = s_axi_rdma_get_wqe_awlen;\nassign s_axi_awsize [C_RDMA_GET_WQE_IDX *3 +: 3] = s_axi_rdma_get_wqe_awsize;\nassign s_axi_awburst[C_RDMA_GET_WQE_IDX *2 +: 2] = s_axi_rdma_get_wqe_awburst;\nassign s_axi_awcache[C_RDMA_GET_WQE_IDX *4 +: 4] = s_axi_rdma_get_wqe_awcache;\nassign s_axi_awprot [C_RDMA_GET_WQE_IDX *3 +: 3] = s_axi_rdma_get_wqe_awprot;\nassign s_axi_awvalid[C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_awvalid;\nassign s_axi_rdma_get_wqe_awready = s_axi_awready[C_RDMA_GET_WQE_IDX *1 +: 1];\nassign s_axi_wdata [C_RDMA_GET_WQE_IDX *512 +: 512] = s_axi_rdma_get_wqe_wdata;\nassign s_axi_wstrb [C_RDMA_GET_WQE_IDX *64 +: 64] = s_axi_rdma_get_wqe_wstrb;\nassign s_axi_wlast [C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_wlast;\nassign s_axi_wvalid [C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_wvalid;\nassign s_axi_rdma_get_wqe_wready = s_axi_wready[C_RDMA_GET_WQE_IDX *1 +: 1];\nassign s_axi_awlock [C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_awlock;\nassign s_axi_rdma_get_wqe_bid = s_axi_bid[C_RDMA_GET_WQE_IDX *3 +: 1];\nassign s_axi_rdma_get_wqe_bresp = s_axi_bresp[C_RDMA_GET_WQE_IDX *2 +: 2];\nassign s_axi_rdma_get_wqe_bvalid = s_axi_bvalid[C_RDMA_GET_WQE_IDX *1 +: 1];\nassign s_axi_bready [C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_bready;\n//assign s_axi_arid [C_RDMA_GET_WQE_IDX *2 +: 2] = {1'b0, s_axi_rdma_get_wqe_arid};\nassign s_axi_arid [C_RDMA_GET_WQE_IDX *3 +: 3] = s_axi_rdma_get_wqe_arvalid ? 3'd0 : 3'd0;\nassign s_axi_araddr [C_RDMA_GET_WQE_IDX *64 +: 64] = s_axi_rdma_get_wqe_araddr;\nassign s_axi_arlen [C_RDMA_GET_WQE_IDX *8 +: 8] = s_axi_rdma_get_wqe_arlen;\nassign s_axi_arsize [C_RDMA_GET_WQE_IDX *3 +: 3] = s_axi_rdma_get_wqe_arsize;\nassign s_axi_arburst[C_RDMA_GET_WQE_IDX *2 +: 2] = s_axi_rdma_get_wqe_arburst;\nassign s_axi_arcache[C_RDMA_GET_WQE_IDX *4 +: 4] = s_axi_rdma_get_wqe_arcache;\nassign s_axi_arprot [C_RDMA_GET_WQE_IDX *3 +: 3] = s_axi_rdma_get_wqe_arprot;\nassign s_axi_arvalid[C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_arvalid;\nassign s_axi_rdma_get_wqe_arready = s_axi_arready[C_RDMA_GET_WQE_IDX *1 +: 1];\nassign s_axi_rdma_get_wqe_rid = s_axi_rid[C_RDMA_GET_WQE_IDX *3 +: 1];\nassign s_axi_rdma_get_wqe_rdata = s_axi_rdata[C_RDMA_GET_WQE_IDX *512 +: 512];\nassign s_axi_rdma_get_wqe_rresp = s_axi_rresp[C_RDMA_GET_WQE_IDX *2 +: 2];\nassign s_axi_rdma_get_wqe_rlast = s_axi_rlast[C_RDMA_GET_WQE_IDX *1 +: 1];\nassign s_axi_rdma_get_wqe_rvalid = s_axi_rvalid[C_RDMA_GET_WQE_IDX *1 +: 1];\nassign s_axi_rready [C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_rready;\nassign s_axi_arlock [C_RDMA_GET_WQE_IDX *1 +: 1] = s_axi_rdma_get_wqe_arlock;\nassign s_axi_arqos [C_RDMA_GET_WQE_IDX *4 +: 4] = s_axi_rdma_get_wqe_arqos;\n\n// AXI slave signals for getting payload from system memory\n//assign axi_awid [C_RDMA_GET_PAYLOAD_IDX*2 +: 2] = {1'b0, s_axi_rdma_get_payload_awid};\nassign s_axi_awid [C_RDMA_GET_PAYLOAD_IDX*3 +: 3] = s_axi_rdma_get_payload_awvalid ? 3'd1 : 3'd0;\nassign s_axi_awaddr [C_RDMA_GET_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_get_payload_awaddr;\nassign s_axi_awqos [C_RDMA_GET_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_get_payload_awqos;\nassign s_axi_awlen [C_RDMA_GET_PAYLOAD_IDX *8 +: 8] = s_axi_rdma_get_payload_awlen;\nassign s_axi_awsize [C_RDMA_GET_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_get_payload_awsize;\nassign s_axi_awburst[C_RDMA_GET_PAYLOAD_IDX *2 +: 2] = s_axi_rdma_get_payload_awburst;\nassign s_axi_awcache[C_RDMA_GET_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_get_payload_awcache;\nassign s_axi_awprot [C_RDMA_GET_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_get_payload_awprot;\nassign s_axi_awvalid[C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_awvalid;\nassign s_axi_rdma_get_payload_awready = s_axi_awready[C_RDMA_GET_PAYLOAD_IDX *1 +: 1];\nassign s_axi_wdata [C_RDMA_GET_PAYLOAD_IDX *512 +: 512] = s_axi_rdma_get_payload_wdata;\nassign s_axi_wstrb [C_RDMA_GET_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_get_payload_wstrb;\nassign s_axi_wlast [C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_wlast;\nassign s_axi_wvalid [C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_wvalid;\nassign s_axi_rdma_get_payload_wready = s_axi_wready[C_RDMA_GET_PAYLOAD_IDX *1 +: 1];\nassign s_axi_awlock [C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_awlock;\nassign s_axi_rdma_get_payload_bid = s_axi_bid[C_RDMA_GET_PAYLOAD_IDX *3 +: 2];\nassign s_axi_rdma_get_payload_bresp = s_axi_bresp[C_RDMA_GET_PAYLOAD_IDX *2 +: 2];\nassign s_axi_rdma_get_payload_bvalid = s_axi_bvalid[C_RDMA_GET_PAYLOAD_IDX *1 +: 1];\nassign s_axi_bready [C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_bready;\n//assign s_axi_arid [C_RDMA_GET_PAYLOAD_IDX *2 +: 2] = {1'b0, s_axi_rdma_get_payload_arid};\nassign s_axi_arid [C_RDMA_GET_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_get_payload_arvalid ? 3'd1: 3'd0;\nassign s_axi_araddr [C_RDMA_GET_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_get_payload_araddr;\nassign s_axi_arlen [C_RDMA_GET_PAYLOAD_IDX *8 +: 8] = s_axi_rdma_get_payload_arlen;\nassign s_axi_arsize [C_RDMA_GET_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_get_payload_arsize;\nassign s_axi_arburst[C_RDMA_GET_PAYLOAD_IDX *2 +: 2] = s_axi_rdma_get_payload_arburst;\nassign s_axi_arcache[C_RDMA_GET_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_get_payload_arcache;\nassign s_axi_arprot [C_RDMA_GET_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_get_payload_arprot;\nassign s_axi_arvalid[C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_arvalid;\nassign s_axi_rdma_get_payload_arready = s_axi_arready[C_RDMA_GET_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rdma_get_payload_rid = s_axi_rid[C_RDMA_GET_PAYLOAD_IDX *3 +: 2];\nassign s_axi_rdma_get_payload_rdata = s_axi_rdata[C_RDMA_GET_PAYLOAD_IDX *512 +: 512];\nassign s_axi_rdma_get_payload_rresp = s_axi_rresp[C_RDMA_GET_PAYLOAD_IDX *2 +: 2];\nassign s_axi_rdma_get_payload_rlast = s_axi_rlast[C_RDMA_GET_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rdma_get_payload_rvalid = s_axi_rvalid[C_RDMA_GET_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rready [C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_rready;\nassign s_axi_arlock [C_RDMA_GET_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_get_payload_arlock;\nassign s_axi_arqos [C_RDMA_GET_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_get_payload_arqos;\n\n// AXI slave signals for data access from qdma mm channel\n//assign axi_awid [C_RDMA_COMPLETION_IDX*2 +: 2] = {1'b0, s_axi_rdma_completion_awid};\nassign s_axi_awid [C_RDMA_COMPLETION_IDX*3 +: 3] = s_axi_rdma_completion_awvalid ? 3'd2 : 3'd0;\nassign s_axi_awaddr [C_RDMA_COMPLETION_IDX *64 +: 64] = s_axi_rdma_completion_awaddr;\nassign s_axi_awqos [C_RDMA_COMPLETION_IDX *4 +: 4] = s_axi_rdma_completion_awqos;\nassign s_axi_awlen [C_RDMA_COMPLETION_IDX *8 +: 8] = s_axi_rdma_completion_awlen;\nassign s_axi_awsize [C_RDMA_COMPLETION_IDX *3 +: 3] = s_axi_rdma_completion_awsize;\nassign s_axi_awburst[C_RDMA_COMPLETION_IDX *2 +: 2] = s_axi_rdma_completion_awburst;\nassign s_axi_awcache[C_RDMA_COMPLETION_IDX *4 +: 4] = s_axi_rdma_completion_awcache;\nassign s_axi_awprot [C_RDMA_COMPLETION_IDX *3 +: 3] = s_axi_rdma_completion_awprot;\nassign s_axi_awvalid[C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_awvalid;\nassign s_axi_rdma_completion_awready = s_axi_awready[C_RDMA_COMPLETION_IDX *1 +: 1];\nassign s_axi_wdata [C_RDMA_COMPLETION_IDX *512 +: 512] = s_axi_rdma_completion_wdata;\nassign s_axi_wstrb [C_RDMA_COMPLETION_IDX *64 +: 64] = s_axi_rdma_completion_wstrb;\nassign s_axi_wlast [C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_wlast;\nassign s_axi_wvalid [C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_wvalid;\nassign s_axi_rdma_completion_wready = s_axi_wready[C_RDMA_COMPLETION_IDX *1 +: 1];\nassign s_axi_awlock [C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_awlock;\nassign s_axi_rdma_completion_bid = s_axi_bid[C_RDMA_COMPLETION_IDX *3 +: 1];\nassign s_axi_rdma_completion_bresp = s_axi_bresp[C_RDMA_COMPLETION_IDX *2 +: 2];\nassign s_axi_rdma_completion_bvalid = s_axi_bvalid[C_RDMA_COMPLETION_IDX *1 +: 1];\nassign s_axi_bready [C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_bready;\n//assign s_axi_arid [C_RDMA_COMPLETION_IDX *2 +: 2] = {1'b0, s_axi_rdma_completion_arid};\nassign s_axi_arid [C_RDMA_COMPLETION_IDX *3 +: 3] = s_axi_rdma_completion_arvalid ? 3'd2 : 3'd0;\nassign s_axi_araddr [C_RDMA_COMPLETION_IDX *64 +: 64] = s_axi_rdma_completion_araddr;\nassign s_axi_arlen [C_RDMA_COMPLETION_IDX *8 +: 8] = s_axi_rdma_completion_arlen;\nassign s_axi_arsize [C_RDMA_COMPLETION_IDX *3 +: 3] = s_axi_rdma_completion_arsize;\nassign s_axi_arburst[C_RDMA_COMPLETION_IDX *2 +: 2] = s_axi_rdma_completion_arburst;\nassign s_axi_arcache[C_RDMA_COMPLETION_IDX *4 +: 4] = s_axi_rdma_completion_arcache;\nassign s_axi_arprot [C_RDMA_COMPLETION_IDX *3 +: 3] = s_axi_rdma_completion_arprot;\nassign s_axi_arvalid[C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_arvalid;\nassign s_axi_rdma_completion_arready = s_axi_arready[C_RDMA_COMPLETION_IDX *1 +: 1];\nassign s_axi_rdma_completion_rid = s_axi_rid[C_RDMA_COMPLETION_IDX *3 +: 1];\nassign s_axi_rdma_completion_rdata = s_axi_rdata[C_RDMA_COMPLETION_IDX *512 +: 512];\nassign s_axi_rdma_completion_rresp = s_axi_rresp[C_RDMA_COMPLETION_IDX *2 +: 2];\nassign s_axi_rdma_completion_rlast = s_axi_rlast[C_RDMA_COMPLETION_IDX *1 +: 1];\nassign s_axi_rdma_completion_rvalid = s_axi_rvalid[C_RDMA_COMPLETION_IDX *1 +: 1];\nassign s_axi_rready [C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_rready;\nassign s_axi_arlock [C_RDMA_COMPLETION_IDX *1 +: 1] = s_axi_rdma_completion_arlock;\nassign s_axi_arqos [C_RDMA_COMPLETION_IDX *4 +: 4] = s_axi_rdma_completion_arqos;\n\n// AXI slave signals for storing payload from RDMA send or write\n//assign axi_awid [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *2 +: 2] = {1'b0, s_axi_rdma_send_write_payload_awid};\nassign s_axi_awid [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_send_write_payload_awvalid ? 3'd3 : 3'd0;\nassign s_axi_awaddr [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_send_write_payload_awaddr;\nassign s_axi_awqos [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_send_write_payload_awqos;\nassign s_axi_awlen [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *8 +: 8] = s_axi_rdma_send_write_payload_awlen;\nassign s_axi_awsize [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_send_write_payload_awsize;\nassign s_axi_awburst[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *2 +: 2] = s_axi_rdma_send_write_payload_awburst;\nassign s_axi_awcache[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_send_write_payload_awcache;\nassign s_axi_awprot [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_send_write_payload_awprot;\nassign s_axi_awvalid[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_awvalid;\nassign s_axi_rdma_send_write_payload_awready = s_axi_awready[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1];\nassign s_axi_wdata [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *512 +: 512] = s_axi_rdma_send_write_payload_wdata;\nassign s_axi_wstrb [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_send_write_payload_wstrb;\nassign s_axi_wlast [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_wlast;\nassign s_axi_wvalid [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_wvalid;\n", "right_context": "assign s_axi_awlock [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_awlock;\nassign s_axi_rdma_send_write_payload_bid = s_axi_bid[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 1];\nassign s_axi_rdma_send_write_payload_bresp = s_axi_bresp[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *2 +: 2];\nassign s_axi_rdma_send_write_payload_bvalid = s_axi_bvalid[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1];\nassign s_axi_bready [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_bready;\n//assign s_axi_arid [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *2 +: 2] = {1'b0, s_axi_rdma_send_write_payload_arid};\nassign s_axi_arid [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_send_write_payload_arvalid ? 3'd3 : 3'd0;\nassign s_axi_araddr [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_send_write_payload_araddr;\nassign s_axi_arlen [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *8 +: 8] = s_axi_rdma_send_write_payload_arlen;\nassign s_axi_arsize [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_send_write_payload_arsize;\nassign s_axi_arburst[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *2 +: 2] = s_axi_rdma_send_write_payload_arburst;\nassign s_axi_arcache[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_send_write_payload_arcache;\nassign s_axi_arprot [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_send_write_payload_arprot;\nassign s_axi_arvalid[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_arvalid;\nassign s_axi_rdma_send_write_payload_arready = s_axi_arready[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rdma_send_write_payload_rid = s_axi_rid[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *3 +: 1];\nassign s_axi_rdma_send_write_payload_rdata = s_axi_rdata[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *512 +: 512];\nassign s_axi_rdma_send_write_payload_rresp = s_axi_rresp[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *2 +: 2];\nassign s_axi_rdma_send_write_payload_rlast = s_axi_rlast[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rdma_send_write_payload_rvalid = s_axi_rvalid[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rready [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_rready;\nassign s_axi_arlock [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_send_write_payload_arlock;\nassign s_axi_arqos [C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_send_write_payload_arqos;\n\n// AXI slave signals for storing payload from RDMA read response\n//assign axi_awid [C_RDMA_RSP_PAYLOAD_IDX*2 +: 2] = {1'b0, s_axi_rdma_rsp_payload_awid};\nassign s_axi_awid [C_RDMA_RSP_PAYLOAD_IDX*3 +: 3] = s_axi_rdma_rsp_payload_awvalid ? 3'd4 : 3'd0;\nassign s_axi_awaddr [C_RDMA_RSP_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_rsp_payload_awaddr;\nassign s_axi_awqos [C_RDMA_RSP_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_rsp_payload_awqos;\nassign s_axi_awlen [C_RDMA_RSP_PAYLOAD_IDX *8 +: 8] = s_axi_rdma_rsp_payload_awlen;\nassign s_axi_awsize [C_RDMA_RSP_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_rsp_payload_awsize;\nassign s_axi_awburst[C_RDMA_RSP_PAYLOAD_IDX *2 +: 2] = s_axi_rdma_rsp_payload_awburst;\nassign s_axi_awcache[C_RDMA_RSP_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_rsp_payload_awcache;\nassign s_axi_awprot [C_RDMA_RSP_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_rsp_payload_awprot;\nassign s_axi_awvalid[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_awvalid;\nassign s_axi_rdma_rsp_payload_awready = s_axi_awready[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1];\nassign s_axi_wdata [C_RDMA_RSP_PAYLOAD_IDX *512 +: 512] = s_axi_rdma_rsp_payload_wdata;\nassign s_axi_wstrb [C_RDMA_RSP_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_rsp_payload_wstrb;\nassign s_axi_wlast [C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_wlast;\nassign s_axi_wvalid [C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_wvalid;\nassign s_axi_rdma_rsp_payload_wready = s_axi_wready[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1];\nassign s_axi_awlock [C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_awlock;\nassign s_axi_rdma_rsp_payload_bid = s_axi_bid[C_RDMA_RSP_PAYLOAD_IDX *3 +: 1];\nassign s_axi_rdma_rsp_payload_bresp = s_axi_bresp[C_RDMA_RSP_PAYLOAD_IDX *2 +: 2];\nassign s_axi_rdma_rsp_payload_bvalid = s_axi_bvalid[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1];\nassign s_axi_bready [C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_bready;\n//assign axi_arid [C_RDMA_RSP_PAYLOAD_IDX *2 +: 2] = {1'b0, s_axi_rdma_rsp_payload_arid};\nassign s_axi_arid [C_RDMA_RSP_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_rsp_payload_arvalid ? 3'd4 : 3'd0;\nassign s_axi_araddr [C_RDMA_RSP_PAYLOAD_IDX *64 +: 64] = s_axi_rdma_rsp_payload_araddr;\nassign s_axi_arlen [C_RDMA_RSP_PAYLOAD_IDX *8 +: 8] = s_axi_rdma_rsp_payload_arlen;\nassign s_axi_arsize [C_RDMA_RSP_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_rsp_payload_arsize;\nassign s_axi_arburst[C_RDMA_RSP_PAYLOAD_IDX *2 +: 2] = s_axi_rdma_rsp_payload_arburst;\nassign s_axi_arcache[C_RDMA_RSP_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_rsp_payload_arcache;\nassign s_axi_arprot [C_RDMA_RSP_PAYLOAD_IDX *3 +: 3] = s_axi_rdma_rsp_payload_arprot;\nassign s_axi_arvalid[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_arvalid;\nassign s_axi_rdma_rsp_payload_arready = s_axi_arready[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rdma_rsp_payload_rid = s_axi_rid[C_RDMA_RSP_PAYLOAD_IDX *3 +: 1];\nassign s_axi_rdma_rsp_payload_rdata = s_axi_rdata[C_RDMA_RSP_PAYLOAD_IDX *512 +: 512];\nassign s_axi_rdma_rsp_payload_rresp = s_axi_rresp[C_RDMA_RSP_PAYLOAD_IDX *2 +: 2];\nassign s_axi_rdma_rsp_payload_rlast = s_axi_rlast[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rdma_rsp_payload_rvalid = s_axi_rvalid[C_RDMA_RSP_PAYLOAD_IDX *1 +: 1];\nassign s_axi_rready [C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_rready;\nassign s_axi_arlock [C_RDMA_RSP_PAYLOAD_IDX *1 +: 1] = s_axi_rdma_rsp_payload_arlock;\nassign s_axi_arqos [C_RDMA_RSP_PAYLOAD_IDX *4 +: 4] = s_axi_rdma_rsp_payload_arqos;\n\n//AXI signals to system memory\n//assign m_axi_awid [C_SYS_MEM_IDX *2 +: 2] = {1'b0, m_axi_sys_mem_awid};\nassign m_axi_sys_mem_awid = m_axi_awid [C_SYS_MEM_IDX *3 +: 3];\nassign m_axi_sys_mem_awaddr = m_axi_awaddr [C_SYS_MEM_IDX *64 +: 64];\nassign m_axi_sys_mem_awqos = m_axi_awqos [C_SYS_MEM_IDX *4 +: 4];\nassign m_axi_sys_mem_awlen = m_axi_awlen [C_SYS_MEM_IDX *8 +: 8];\nassign m_axi_sys_mem_awsize = m_axi_awsize [C_SYS_MEM_IDX *3 +: 3];\nassign m_axi_sys_mem_awburst = m_axi_awburst[C_SYS_MEM_IDX *2 +: 2];\nassign m_axi_sys_mem_awcache = m_axi_awcache[C_SYS_MEM_IDX *4 +: 4];\nassign m_axi_sys_mem_awprot = m_axi_awprot [C_SYS_MEM_IDX *3 +: 3];\nassign m_axi_sys_mem_awvalid = m_axi_awvalid[C_SYS_MEM_IDX *1 +: 1];\nassign m_axi_awready[C_SYS_MEM_IDX *1 +: 1] = m_axi_sys_mem_awready;\nassign m_axi_sys_mem_wdata = m_axi_wdata [C_SYS_MEM_IDX *512 +: 512];\nassign m_axi_sys_mem_wstrb = m_axi_wstrb [C_SYS_MEM_IDX *64 +: 64];\nassign m_axi_sys_mem_wlast = m_axi_wlast [C_SYS_MEM_IDX *1 +: 1];\nassign m_axi_sys_mem_wvalid = m_axi_wvalid [C_SYS_MEM_IDX *1 +: 1];\nassign m_axi_wready[C_SYS_MEM_IDX *1 +: 1] = m_axi_sys_mem_wready;\nassign m_axi_sys_mem_awlock = m_axi_awlock [C_SYS_MEM_IDX *1 +: 1];\nassign m_axi_bid[C_SYS_MEM_IDX *3 +: 3] = m_axi_sys_mem_bid;\nassign m_axi_bresp[C_SYS_MEM_IDX *2 +: 2] = m_axi_sys_mem_bresp;\nassign m_axi_bvalid[C_SYS_MEM_IDX *1 +: 1] = m_axi_sys_mem_bvalid;\nassign m_axi_sys_mem_bready = m_axi_bready [C_SYS_MEM_IDX *1 +: 1];\n//assign m_axi_sys_mem_arid = m_axi_arid [C_SYS_MEM_IDX *2 +: 2];\nassign m_axi_sys_mem_arid = m_axi_arid [C_SYS_MEM_IDX *3 +: 3];\nassign m_axi_sys_mem_araddr = m_axi_araddr [C_SYS_MEM_IDX *64 +: 64];\nassign m_axi_sys_mem_arlen = m_axi_arlen [C_SYS_MEM_IDX *8 +: 8];\nassign m_axi_sys_mem_arsize = m_axi_arsize [C_SYS_MEM_IDX *3 +: 3];\nassign m_axi_sys_mem_arburst = m_axi_arburst[C_SYS_MEM_IDX *2 +: 2];\nassign m_axi_sys_mem_arcache = m_axi_arcache[C_SYS_MEM_IDX *4 +: 4];\nassign m_axi_sys_mem_arprot = m_axi_arprot [C_SYS_MEM_IDX *3 +: 3];\nassign m_axi_sys_mem_arvalid = m_axi_arvalid[C_SYS_MEM_IDX *1 +: 1];\nassign m_axi_arready[C_SYS_MEM_IDX *1 +: 1] = m_axi_sys_mem_arready;\nassign m_axi_rid[C_SYS_MEM_IDX *3 +: 3] = m_axi_sys_mem_rid;\nassign m_axi_rdata[C_SYS_MEM_IDX *512 +: 512] = m_axi_sys_mem_rdata;\nassign m_axi_rresp[C_SYS_MEM_IDX *2 +: 2] = m_axi_sys_mem_rresp;\nassign m_axi_rlast[C_SYS_MEM_IDX *1 +: 1] = m_axi_sys_mem_rlast;\nassign m_axi_rvalid[C_SYS_MEM_IDX *1 +: 1] = m_axi_sys_mem_rvalid;\nassign m_axi_sys_mem_rready = m_axi_rready [C_SYS_MEM_IDX *1 +: 1];\nassign m_axi_sys_mem_arlock = m_axi_arlock [C_SYS_MEM_IDX *1 +: 1];\nassign m_axi_sys_mem_arqos = m_axi_arqos [C_SYS_MEM_IDX *4 +: 4];\n\n//AXI signals to device memory\n//assign m_axi_awid [C_SYS_TO_DEV_CROSSBAR_IDX *2 +: 2] = {1'b0, m_axi_sys_to_dev_crossbar_awid};\nassign m_axi_sys_to_dev_crossbar_awid = m_axi_awid [C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3];\nassign m_axi_sys_to_dev_crossbar_awaddr = m_axi_awaddr [C_SYS_TO_DEV_CROSSBAR_IDX *64 +: 64];\nassign m_axi_sys_to_dev_crossbar_awqos = m_axi_awqos [C_SYS_TO_DEV_CROSSBAR_IDX *4 +: 4];\nassign m_axi_sys_to_dev_crossbar_awlen = m_axi_awlen [C_SYS_TO_DEV_CROSSBAR_IDX *8 +: 8];\nassign m_axi_sys_to_dev_crossbar_awsize = m_axi_awsize [C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3];\nassign m_axi_sys_to_dev_crossbar_awburst = m_axi_awburst[C_SYS_TO_DEV_CROSSBAR_IDX *2 +: 2];\nassign m_axi_sys_to_dev_crossbar_awcache = m_axi_awcache[C_SYS_TO_DEV_CROSSBAR_IDX *4 +: 4];\nassign m_axi_sys_to_dev_crossbar_awprot = m_axi_awprot [C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3];\nassign m_axi_sys_to_dev_crossbar_awvalid = m_axi_awvalid[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\nassign m_axi_awready[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1] = m_axi_sys_to_dev_crossbar_awready;\nassign m_axi_sys_to_dev_crossbar_wdata = m_axi_wdata [C_SYS_TO_DEV_CROSSBAR_IDX *512 +: 512];\nassign m_axi_sys_to_dev_crossbar_wstrb = m_axi_wstrb [C_SYS_TO_DEV_CROSSBAR_IDX *64 +: 64];\nassign m_axi_sys_to_dev_crossbar_wlast = m_axi_wlast [C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\nassign m_axi_sys_to_dev_crossbar_wvalid = m_axi_wvalid [C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\nassign m_axi_wready[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1] = m_axi_sys_to_dev_crossbar_wready;\nassign m_axi_sys_to_dev_crossbar_awlock = m_axi_awlock [C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\nassign m_axi_bid[C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3] = m_axi_sys_to_dev_crossbar_bid;\nassign m_axi_bresp[C_SYS_TO_DEV_CROSSBAR_IDX *2 +: 2] = m_axi_sys_to_dev_crossbar_bresp;\nassign m_axi_bvalid[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1] = m_axi_sys_to_dev_crossbar_bvalid;\nassign m_axi_sys_to_dev_crossbar_bready = m_axi_bready [C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\n//assign m_axi_sys_to_dev_crossbar_arid = m_axi_arid [C_SYS_TO_DEV_CROSSBAR_IDX *2 +: 2];\nassign m_axi_sys_to_dev_crossbar_arid = m_axi_arid [C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3];\nassign m_axi_sys_to_dev_crossbar_araddr = m_axi_araddr [C_SYS_TO_DEV_CROSSBAR_IDX *64 +: 64];\nassign m_axi_sys_to_dev_crossbar_arlen = m_axi_arlen [C_SYS_TO_DEV_CROSSBAR_IDX *8 +: 8];\nassign m_axi_sys_to_dev_crossbar_arsize = m_axi_arsize [C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3];\nassign m_axi_sys_to_dev_crossbar_arburst = m_axi_arburst[C_SYS_TO_DEV_CROSSBAR_IDX *2 +: 2];\nassign m_axi_sys_to_dev_crossbar_arcache = m_axi_arcache[C_SYS_TO_DEV_CROSSBAR_IDX *4 +: 4];\nassign m_axi_sys_to_dev_crossbar_arprot = m_axi_arprot [C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3];\nassign m_axi_sys_to_dev_crossbar_arvalid = m_axi_arvalid[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\nassign m_axi_arready[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1] = m_axi_sys_to_dev_crossbar_arready;\nassign m_axi_rid[C_SYS_TO_DEV_CROSSBAR_IDX *3 +: 3] = m_axi_sys_to_dev_crossbar_rid;\nassign m_axi_rdata[C_SYS_TO_DEV_CROSSBAR_IDX *512 +: 512] = m_axi_sys_to_dev_crossbar_rdata;\nassign m_axi_rresp[C_SYS_TO_DEV_CROSSBAR_IDX *2 +: 2] = m_axi_sys_to_dev_crossbar_rresp;\nassign m_axi_rlast[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1] = m_axi_sys_to_dev_crossbar_rlast;\nassign m_axi_rvalid[C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1] = m_axi_sys_to_dev_crossbar_rvalid;\nassign m_axi_sys_to_dev_crossbar_rready = m_axi_rready [C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\nassign m_axi_sys_to_dev_crossbar_arlock = m_axi_arlock [C_SYS_TO_DEV_CROSSBAR_IDX *1 +: 1];\nassign m_axi_sys_to_dev_crossbar_arqos = m_axi_arqos [C_SYS_TO_DEV_CROSSBAR_IDX *4 +: 4];\n\nsys_mem_5to2_axi_crossbar sys_mem_5to2_axi_crossbar_inst (\n .m_axi_awaddr (m_axi_awaddr),\n .m_axi_awprot (m_axi_awprot),\n .m_axi_awvalid (m_axi_awvalid),\n .m_axi_awready (m_axi_awready),\n .m_axi_awsize (m_axi_awsize),\n .m_axi_awburst (m_axi_awburst),\n .m_axi_awcache (m_axi_awcache),\n .m_axi_awlen (m_axi_awlen),\n .m_axi_awlock (m_axi_awlock),\n .m_axi_awqos (m_axi_awqos),\n .m_axi_awregion (m_axi_awregion),\n .m_axi_awid (m_axi_awid),\n .m_axi_wdata (m_axi_wdata),\n .m_axi_wstrb (m_axi_wstrb),\n .m_axi_wvalid (m_axi_wvalid),\n .m_axi_wready (m_axi_wready),\n .m_axi_wlast (m_axi_wlast),\n .m_axi_bresp (m_axi_bresp),\n .m_axi_bvalid (m_axi_bvalid),\n .m_axi_bready (m_axi_bready),\n .m_axi_bid (m_axi_bid),\n .m_axi_araddr (m_axi_araddr),\n .m_axi_arprot (m_axi_arprot),\n .m_axi_arvalid (m_axi_arvalid),\n .m_axi_arready (m_axi_arready),\n .m_axi_arsize (m_axi_arsize),\n .m_axi_arburst (m_axi_arburst),\n .m_axi_arcache (m_axi_arcache),\n .m_axi_arlock (m_axi_arlock),\n .m_axi_arlen (m_axi_arlen),\n .m_axi_arqos (m_axi_arqos),\n .m_axi_arregion (m_axi_arregion),\n .m_axi_arid (m_axi_arid),\n .m_axi_rdata (m_axi_rdata),\n .m_axi_rresp (m_axi_rresp),\n .m_axi_rvalid (m_axi_rvalid),\n .m_axi_rready (m_axi_rready),\n .m_axi_rlast (m_axi_rlast),\n .m_axi_rid (m_axi_rid),\n\n .s_axi_awid (s_axi_awid),\n .s_axi_awaddr (s_axi_awaddr),\n .s_axi_awqos (s_axi_awqos),\n .s_axi_awlen (s_axi_awlen),\n .s_axi_awsize (s_axi_awsize),\n .s_axi_awburst (s_axi_awburst),\n .s_axi_awcache (s_axi_awcache),\n .s_axi_awprot (s_axi_awprot),\n .s_axi_awvalid (s_axi_awvalid),\n .s_axi_awready (s_axi_awready),\n .s_axi_wdata (s_axi_wdata),\n .s_axi_wstrb (s_axi_wstrb),\n .s_axi_wlast (s_axi_wlast),\n .s_axi_wvalid (s_axi_wvalid),\n .s_axi_wready (s_axi_wready),\n .s_axi_awlock (s_axi_awlock),\n .s_axi_bid (s_axi_bid),\n .s_axi_bresp (s_axi_bresp),\n .s_axi_bvalid (s_axi_bvalid),\n .s_axi_bready (s_axi_bready),\n .s_axi_arid (s_axi_arid),\n .s_axi_araddr (s_axi_araddr),\n .s_axi_arlen (s_axi_arlen),\n .s_axi_arsize (s_axi_arsize),\n .s_axi_arburst (s_axi_arburst),\n .s_axi_arcache (s_axi_arcache),\n .s_axi_arprot (s_axi_arprot),\n .s_axi_arvalid (s_axi_arvalid),\n .s_axi_arready (s_axi_arready),\n .s_axi_rid (s_axi_rid),\n .s_axi_rdata (s_axi_rdata),\n .s_axi_rresp (s_axi_rresp),\n .s_axi_rlast (s_axi_rlast),\n .s_axi_rvalid (s_axi_rvalid),\n .s_axi_rready (s_axi_rready),\n .s_axi_arlock (s_axi_arlock),\n .s_axi_arqos (s_axi_arqos),\n\n .aclk (axis_aclk),\n .aresetn(axis_arestn)\n);\n\nendmodule: axi_5to2_interconnect_to_sys_mem", "groundtruth": "assign s_axi_rdma_send_write_payload_wready = s_axi_wready[C_RDMA_GET_SEND_WRITE_PAYLOAD_IDX *1 +: 1];\n", "crossfile_context": ""} {"task_id": "kria-vitis-platforms", "path": "kria-vitis-platforms/kv260/overlays/dpu_ip/DPUCZDX8G_v4_0_0/inc/arch_def.vh", "left_context": "/* \n* Copyright 2019 Xilinx Inc. \n* \n* Licensed under the Apache License, Version 2.0 (the \"License\"); \n* you may not use this file except in compliance with the License. \n* You may obtain a copy of the License at \n* \n* http://www.apache.org/licenses/LICENSE-2.0 \n* \n* Unless required by applicable law or agreed to in writing, software \n* distributed under the License is distributed on an \"AS IS\" BASIS, \n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. \n* See the License for the specific language governing permissions and \n* limitations under the License. \n*/ \n\n`pragma protect begin_protected\n`pragma protect version = 2\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect encrypt_agent_info = \"Xilinx Encryption Tool 2022.1\"\n`pragma protect begin_commonblock\n`pragma protect control error_handling = \"delegated\"\n`pragma protect control runtime_visibility = \"delegated\"\n`pragma protect control child_visibility = \"delegated\"\n`pragma protect control decryption=(activity==simulation) ? \"false\" : \"true\"\n", "right_context": "`pragma protect begin_toolblock\n`pragma protect rights_digest_method=\"sha256\"\n`pragma protect key_keyowner = \"Xilinx\", key_keyname= \"xilinxt_2020_08\", key_method = \"rsa\", key_block\nCaihNQWwu+qKJWjcmdIgzgKIXQ8l3vMImmWHnChjYqoa51yMcErBScyiE64YZSDih9WCUqsVfjEZ\nHfdPZ9ljuyASaDAJWOBnJBbhrePBDPO5jKkFmPbv80QoBXSWaNMFc5sW0Ulg3lCiE5qq9SVr7IMd\nvkFVewJkI9IJKPXIqEiYLMio527A7EkzJrjUXC11BQnTYghbA5n7/6q2WIDOwjQ+BdLZXxGdIUKi\nihIieqBZEgdd6vwETSGv3sSorIwnUPSueC94L800xEEoFQmghwgPGvLA3IEIqt1YNZfrY4rcuvTH\nrxE5ve/ar6tMYP0QdSitAf/UOVre3EWtsP+Jcw==\n\n`pragma protect control xilinx_configuration_visible = \"false\"\n`pragma protect control xilinx_enable_modification = \"false\"\n`pragma protect control xilinx_enable_probing = \"false\"\n`pragma protect control xilinx_enable_netlist_export = \"false\"\n`pragma protect control xilinx_enable_bitstream = \"true\"\n`pragma protect control decryption=(xilinx_activity==simulation) ? \"false\" : \"true\"\n`pragma protect end_toolblock=\"IxINXwVvXQ/n7KwTaYrPoEaEACBK27oPy3cRIdl/LOI=\"\n`pragma protect data_method = \"AES128-CBC\"\n`pragma protect encoding = (enctype = \"BASE64\", line_length = 76, bytes = 880)\n`pragma protect data_block\nEiGu1ShDtOnFp1/lwt6VhcUR8yhnAB8O5e1xLbmtU8hFkeRUrpaBl1HAfyRFT7nbtX9ANec6bT/6\nM5F1wZGG5qSvkCUW8yVN2ibhwe39b3gqpxlAM0Rk2b5g0GPQS0EovauYN9XAQquN58ggK/O+KDM0\n63s7X7It+p/RSFzWWRGZS+v0XTm+D2a1XMT2uisqh8PefOCoBySO44oktKTY504wlCSc5omNSe+u\nzOKrUyvkLauqfVr0IymzexsmShoC8a5rxCwtiHWtuZd3ISZeseAH4yuuIE22EaResPkSs0AOtuxW\nLUa+5ziMFj1jUrwyX7edUaYFWubmHAbAkkw9Hm+C6bamM5RNvdj0nJ6+9kR3k9JEEwFcMnpU/+T7\nAyStZ42jqyndQBD+fvcXAhE7unT9l7MeF6FPz+f4fj9QLQ9uKKfDT4Z/nUyAujR54s7JMJPusI/1\n6kmMjc0VDkHnbDi2wkCweAVtI13pMf21kgykit61e5wC9yuUa3wMmmwN0K5j3CFUalZcs5zyaUEU\nRFQ6sxbZKoizpkyYAVpfJ5ooRM+2IwCcC/xaZGuC28xR1sA7FuTz8gJHfj+31ej4SmCB90pf8a1j\nv5GMWH/IC2k1qDCu3Nv9vlIh9ddPqzd8V2kbzHKQIixQUYVEYd6XzNzpOSAo7YP0yS1vkaxpM13/\ntmu8VZm2h2JkrlzFuDwth9ORNpQM+dxpUbIiNRz188RAIvel6yq9G8g7YjGY6Jq1qeGPfgm2uqIE\nOYHDHJww2kjAzMfBu4zQRXixjhSL5YOVbevDsp++Yot323jrunN6b3HYs5T3zX64N23723OKUorb\nBzfFPVvrOEw7oa31ZqgZSsWbWZMOkcIa955Zi5oSnEOq4KNx1IMlwiRrRVmeW2nzDZyOT/6kkiV5\nAy+TkZF19zF0PKmiNq0809vsxErEHL/7oYdQDYLNmot/tAe+f381qkRVEbZrjA0uWw8e7xnBZXdh\n276B2htPR1ezVeOX25aKI5B2G/pH+lUnzW5CqMGEcgS1yReFHycsSdJkPGQDl0uTLiAZLicoj2v3\nCAT2TDbLr2Obrdb1Xpom03ZaOT0ImqBumdzSoPD+eRvc0qT6AoCHxmNojpf4C2WADh3N57ctHcPk\nV7HEOkM7H6joRSQhUNMkeuqXc/t6IH5R7g==\n`pragma protect end_protected\n\n// \n", "groundtruth": "`pragma protect end_commonblock\n", "crossfile_context": ""} {"task_id": "redmule", "path": "redmule/rtl/redmule_castin.sv", "left_context": "// Copyright 2023 ETH Zurich and University of Bologna.\n// Solderpad Hardware License, Version 0.51, see LICENSE for details.\n// SPDX-License-Identifier: SHL-0.51\n//\n// Yvan Tortorella \n//\n\nimport fpnew_pkg::*;\nimport hci_package::*;\nimport redmule_pkg::*;\n\nmodule redmule_castin #(\n parameter int unsigned DATA_W = redmule_pkg::DATA_W,\n parameter fpnew_pkg::fmt_logic_t FpFmtConfig = FpFmtConfig,\n parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = IntFmtConfig,\n parameter fpnew_pkg::fp_format_e DstFormat = FPFORMAT,\n parameter fpnew_pkg::operation_e Operation = CAST_OP,\n parameter logic Pipe = 1'b0 ,\n localparam int unsigned BW = hci_package::DEFAULT_BW ,\n localparam int unsigned OW = ADDR_W ,\n localparam int unsigned UW = hci_package::DEFAULT_UW ,\n localparam int unsigned WIDTH = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpFmtConfig),\n fpnew_pkg::max_int_width(IntFmtConfig))\n)(\n input logic clk_i ,\n input logic rst_ni ,\n input logic clear_i ,\n input logic cast_i ,\n input logic [DATA_W-1:0] src_i ,\n input fpnew_pkg::fp_format_e src_fmt_i,\n output logic [DATA_W-1:0] dst_o\n);\n\nlocalparam int unsigned NUM_CAST = DATA_W/BITW;\n", "right_context": "logic [DATA_W-1:0] src_int;\n\nassign src_int[DATA_W-DW_CUT-1:0] = src_i[DATA_W-DW_CUT-1:0];\nassign src_int[DATA_W-1:DATA_W-DW_CUT] = '0;\n\nlogic [DATA_W-1:0] dst_int;\nlogic [NUM_CAST-1:0][WIDTH-1:0] result ,\n operand;\n\ngenerate\n for (genvar i = 0; i < NUM_CAST; i++) begin : gen_cast_units\n\n assign operand [i] = {{ZEROBITS{1'b0}}, src_int[i*MIN_FMT+:MIN_FMT]};\n\n fpnew_cast_multi #(\n .FpFmtConfig ( FpFmtConfig ),\n .IntFmtConfig ( IntFmtConfig )\n ) redmule_cast_i (\n .clk_i ( clk_i ),\n .rst_ni ( rst_ni ),\n .operands_i ( operand [i] ),\n .is_boxed_i ( '1 ),\n .rnd_mode_i ( fpnew_pkg::RNE ),\n .op_i ( Operation ),\n .op_mod_i ( '0 ),\n .src_fmt_i ( src_fmt_i ),\n .dst_fmt_i ( DstFormat ),\n .int_fmt_i ( INT_SRC ),\n .tag_i ( '0 ),\n .mask_i ( '0 ),\n .aux_i ( '0 ),\n .in_valid_i ( '1 ),\n .in_ready_o ( ),\n .flush_i ( '0 ),\n .result_o ( result [i] ),\n .status_o ( ),\n .extension_bit_o( ),\n .tag_o ( ),\n .mask_o ( ),\n .aux_o ( ),\n .out_valid_o ( ),\n .out_ready_i ( '1 ),\n .busy_o ( )\n );\n\n assign dst_int [i*WIDTH+:WIDTH] = result[i];\n\n end\n\nendgenerate\n\nassign dst_o = cast_i ? dst_int : src_i;\n\nendmodule : redmule_castin\n", "groundtruth": "localparam int unsigned NARRBITW = fpnew_pkg::fp_width(fpnew_pkg::FP8);\n// localparam int unsigned ZEROBITS = WIDTH - NARRBITW;\nlocalparam int unsigned ZEROBITS = MIN_FMT;\n", "crossfile_context": ""} {"task_id": "uvm_agents", "path": "uvm_agents/src/i2c/i2c_master_driver.sv", "left_context": "//////////////////////////////////////////////////////////////////////////////\n// Copyright 2014 Dov Stamler (dov.stamler@gmail.com)\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//////////////////////////////////////////////////////////////////////////////\n\n`ifndef I2C_MASTER_DRIVER__SV\n`define I2C_MASTER_DRIVER__SV\n\n// Class: i2c_master_driver\n// Master driver begins driving an I2C transaction when an is received from the \n// agents sequencer and the I2C bus is not busy. When the bus is busy, the driver will wait for the\n// bus to release and then begin the transaction. The pin wiggles are a function\n// of the current sequence item and the agents objects members values. \nclass i2c_master_driver extends uvm_driver #(i2c_sequence_item);\n `uvm_component_utils(i2c_master_driver)\n \n virtual i2c_if sigs;\n i2c_master_cfg cfg;\n i2c_common_methods common_mthds; // object holding common methods used by multiple I2C components\n \n bit bus_is_busy; // set on a start detection, dropped on a stop detection\n bit stop_scl; // used to notify SCL thread to terminate\n bit abritration_current_drive_value; // arbitration process uses this to compare current to bus value\n bit abritration_checking_enabled; // only when driving the bus should the arbitration be checking\n event start_detection_e; // triggered on a start detection\n event stop_detection_e; // triggered on a stop detection\n \n // bus timing values represented in clocking block cycles\n int num_of_clocks_for_scl_high_period; // calculated number of clock cycles for a SCL high period\n int num_of_clocks_for_scl_low_period; // calculated number of clock cycles for a SCL low period\n int num_of_clocks_for_t_hd_sta_min; // start hold time before SCL toggle\n int num_of_clocks_for_t_hd_dat_max; // data hold time from SCL negedge\n int num_of_clocks_for_t_su_dat_min; // data setup time to SCL posedge\n int num_of_clocks_for_t_su_sta_min; // repeated start SDA toggle from SCL negedge\n int num_of_clocks_for_t_su_sto_min; // setup time from SCL posedge to SDA assert\n int num_of_clocks_for_t_buf_min; // buffer time between stop and start conditions\n \n extern function new(string name = \"i2c_master_driver\", uvm_component parent);\n extern virtual function void build_phase(uvm_phase phase);\n extern virtual task run_phase(uvm_phase phase); \n extern virtual task monitor_for_start_condition();\n extern virtual task monitor_for_stop_condition();\n extern virtual task report_if_bus_is_busy();\n extern virtual task calculate_closest_scl_frequency_to_configuration();\n extern virtual task calculate_all_bus_timing_variables_in_num_of_clocks();\n extern virtual task drive_transaction();\n extern virtual task toggle_scl();\n extern virtual task create_start_condition(uvm_phase phase);\n extern virtual task create_stop_condition(uvm_phase phase);\n extern virtual task transmit_address();\n extern virtual task get_slave_ack(output logic ack);\n extern virtual task setup_for_a_continuous_start();\n extern virtual task transmit_write_data();\n extern virtual task receive_read_data();\n extern virtual task transmit_ack_for_read(bit ack = 0);\n extern virtual task drive_data_bit_to_sda(logic data_bit);\n extern virtual task check_if_arbitration_is_lost(output logic arbitration_lost);\n \nendclass: i2c_master_driver\n\n//------------------------------------------------------------------------//\nfunction i2c_master_driver::new(string name = \"i2c_master_driver\", uvm_component parent);\n super.new(name, parent);\n\nendfunction: new\n\n//------------------------------------------------------------------------//\nfunction void i2c_master_driver::build_phase(uvm_phase phase);\n super.build_phase(phase);\n \n //set initial values\n bus_is_busy = 0; \n abritration_current_drive_value = 0;\n abritration_checking_enabled = 0;\n \n common_mthds = i2c_common_methods::type_id::create(\"common_mthds\", this);\n common_mthds.sigs = sigs;\n \nendfunction: build_phase\n\n//------------------------------------------------------------------------//\n// task: run_phase\n// run phase is called by UVM flow. Driver is active during this phase.\ntask i2c_master_driver::run_phase(uvm_phase phase);\n process thread_process[$];\n int thread_number = 0;\n bit drive_thread_check_if_arbitration_was_lost = 0;\n super.run_phase(phase);\n \n common_mthds.calculate_input_clock_period();// set the clocking block period for the common_mthds object, must be done in the run_phase to guarantee clock is toggling\n calculate_all_bus_timing_variables_in_num_of_clocks();\n calculate_closest_scl_frequency_to_configuration();\n \n fork\n forever common_mthds.drive_x_to_outputs_during_reset();\n forever monitor_for_start_condition(); // used to verify if bus is free\n forever monitor_for_stop_condition(); // used to verify if bus is free\n forever report_if_bus_is_busy();\n \n forever begin\n fork\n begin // drive thread\n thread_process[thread_number] = process::self();\n \n if(drive_thread_check_if_arbitration_was_lost) drive_thread_check_if_arbitration_was_lost = 0; // use the previously item since it wasn't transmitted\n", "right_context": " wait(!bus_is_busy);\n do begin\n \n create_start_condition( .phase(phase) );\n drive_transaction();\n req.print();\n \n seq_item_port.item_done();\n seq_item_port.try_next_item(req); // if another item is ready process it now, create a continuous start\n end\n while(req);\n \n create_stop_condition( .phase(phase) );\n \n end\n \n // termination thread. terminate the drive thread if arbitration is lost. \n // terminate this thread once the drive thread has completed\n begin\n int wait_for_thread_number = thread_number;\n logic arbitration_lost = '0;\n \n \n while(!arbitration_lost && \n (thread_process[wait_for_thread_number].status != process::FINISHED) ) check_if_arbitration_is_lost( .arbitration_lost(arbitration_lost) );\n \n if (thread_process[wait_for_thread_number].status != process::FINISHED) thread_process[wait_for_thread_number].kill();\n if (arbitration_lost) begin\n `uvm_info(get_type_name(), $sformatf(\"arbitration has been lost\"), UVM_NONE )\n drive_thread_check_if_arbitration_was_lost = 1; //notify the drive thread so the next round won't pull a new item from the sequencer\n end\n end\n \n join_any\n \n thread_number++;\n \n end\n join\n \nendtask: run_phase\n\n//------------------------------------------------------------------------//\n// monitor if a different master created a start condition. This is used \n// to determine if the bus is busy.\ntask i2c_master_driver::monitor_for_start_condition();\n \n common_mthds.monitor_for_start_condition( .start_e(start_detection_e) );\n if(start_detection_e.triggered) `uvm_info(get_type_name(), $sformatf(\"Start detected\"), UVM_FULL )\n \nendtask: monitor_for_start_condition\n\n//------------------------------------------------------------------------//\n// monitor if a different master created a stop condition. used to determine when the bus is clear.\ntask i2c_master_driver::monitor_for_stop_condition();\n \n common_mthds.monitor_for_stop_condition( .stop_e(stop_detection_e) );\n if(stop_detection_e.triggered) `uvm_info(get_type_name(), $sformatf(\"Stop detected\"), UVM_FULL )\n \nendtask: monitor_for_stop_condition\n\n//------------------------------------------------------------------------//\n// raise bus_is_busy on a start condition, drop bus_is_busy on a stop condition. \n// bus is busy only after t_hd time. \ntask i2c_master_driver::report_if_bus_is_busy();\n \n wait(start_detection_e.triggered);\n repeat(num_of_clocks_for_t_hd_sta_min) @(sigs.drv_cb);\n bus_is_busy = 1;\n `uvm_info(get_type_name(), $sformatf(\"bus busy set\"), UVM_FULL )\n\n wait(stop_detection_e.triggered);\n repeat(num_of_clocks_for_t_buf_min) @(sigs.drv_cb); // don't release the bus for the buffer time between a start and stop\n bus_is_busy = 0;\n `uvm_info(get_type_name(), $sformatf(\"bus busy cleared\"), UVM_FULL )\n \nendtask: report_if_bus_is_busy\n\n//------------------------------------------------------------------------//\n// the requested SCL frequency is an exact number where the driver works with \n// a clocking block. calculate the closest frequency value to the requested SCL frequency in clock cycles.\ntask i2c_master_driver::calculate_closest_scl_frequency_to_configuration();\n int num_of_input_clock_for_scl = 0;\n realtime requested_period = 0;\n \n requested_period = 1s / (1000 * cfg.requested_scl_frequency_in_khz); // convert from KHz to seconds\n num_of_input_clock_for_scl = common_mthds.calculate_number_of_clocks_for_time( .time_value(requested_period) );\n \n //set values used by SCL creation task, for an odd number of cycles, split the high and low period to different values\n if (num_of_input_clock_for_scl % 2) begin\n num_of_clocks_for_scl_high_period = (num_of_input_clock_for_scl - 1) /2;\n num_of_clocks_for_scl_low_period = (num_of_input_clock_for_scl) /2;\n end\n else begin\n num_of_clocks_for_scl_high_period = (num_of_input_clock_for_scl) /2;\n num_of_clocks_for_scl_low_period = (num_of_input_clock_for_scl) /2;\n end\n \n `uvm_info(get_type_name(), $sformatf(\"SCL: number of clocks per period = %0d, closest period = %0t\", num_of_input_clock_for_scl, num_of_input_clock_for_scl * common_mthds.input_clock_period_in_ps), UVM_MEDIUM )\n `uvm_info(get_type_name(), $sformatf(\"SCL: closest frequency = %0d KHz\", 1s/( 1000* num_of_input_clock_for_scl * common_mthds.input_clock_period_in_ps * 1ps) ), UVM_MEDIUM )\n \nendtask: calculate_closest_scl_frequency_to_configuration\n\n//------------------------------------------------------------------------//\n// bus timing is represent in exact time value. driver drives bus with a clocking\n// block therefore, calculate the closest times for each variable based on the \n// clocking block period.\n// min values are not floored since then the requested value won't be met.\ntask i2c_master_driver::calculate_all_bus_timing_variables_in_num_of_clocks();\n\n num_of_clocks_for_t_hd_sta_min = common_mthds.calculate_number_of_clocks_for_time( .time_value(cfg.t_hd_sta_min), .floor_calculation(0) );\n num_of_clocks_for_t_hd_dat_max = common_mthds.calculate_number_of_clocks_for_time( .time_value(cfg.t_hd_dat_max), .floor_calculation(1) );\n num_of_clocks_for_t_su_dat_min = common_mthds.calculate_number_of_clocks_for_time( .time_value(cfg.t_su_dat_min), .floor_calculation(0) );\n num_of_clocks_for_t_su_sta_min = common_mthds.calculate_number_of_clocks_for_time( .time_value(cfg.t_su_sta_min), .floor_calculation(0) );\n num_of_clocks_for_t_su_sto_min = common_mthds.calculate_number_of_clocks_for_time( .time_value(cfg.t_su_sto_min), .floor_calculation(0) );\n num_of_clocks_for_t_buf_min = common_mthds.calculate_number_of_clocks_for_time( .time_value(cfg.t_buf_min), .floor_calculation(0) );\n \n `uvm_info(get_type_name(), $sformatf(\"num_of_clocks_for_t_hd_sta_min = %d\", num_of_clocks_for_t_hd_sta_min) , UVM_FULL )\n `uvm_info(get_type_name(), $sformatf(\"num_of_clocks_for_t_hd_dat_max = %d\", num_of_clocks_for_t_hd_dat_max) , UVM_FULL )\n `uvm_info(get_type_name(), $sformatf(\"num_of_clocks_for_t_su_dat_min = %d\", num_of_clocks_for_t_su_dat_min) , UVM_FULL )\n `uvm_info(get_type_name(), $sformatf(\"num_of_clocks_for_t_su_sta_min = %d\", num_of_clocks_for_t_su_sta_min) , UVM_FULL )\n `uvm_info(get_type_name(), $sformatf(\"num_of_clocks_for_t_su_sto_min = %d\", num_of_clocks_for_t_su_sto_min) , UVM_FULL )\n `uvm_info(get_type_name(), $sformatf(\"num_of_clocks_for_t_buf_min = %d\", num_of_clocks_for_t_buf_min) , UVM_FULL )\n\nendtask:calculate_all_bus_timing_variables_in_num_of_clocks\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::drive_transaction();\n logic ack = 1;\n stop_scl = 0;\n \n `uvm_info(get_type_name(), $sformatf(\"drive_transaction start\"), UVM_FULL )\n \n fork // creating start condition has completed previously, begin SCL toggle\n toggle_scl();\n join_none\n \n transmit_address();\n get_slave_ack( .ack(ack) );\n if (ack === 1'b0) begin //0 = ACK, 1 = NACK\n case(req.direction_e)\n I2C_DIR_WRITE: transmit_write_data();\n I2C_DIR_READ: receive_read_data();\n default: `uvm_error(get_type_name(), $sformatf(\"requested %s direction is not supported\", req.direction_e.name() ) )\n endcase\n end\n \nendtask: drive_transaction\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::toggle_scl();\n `uvm_info(get_type_name(), $sformatf(\"toggle_scl start\"), UVM_NONE )\n \n @(sigs.drv_cb); //synchronize to current clock\n while(!stop_scl) begin \n sigs.drv_cb.scl_out <= 1'b0;\n repeat(num_of_clocks_for_scl_low_period) @(sigs.drv_cb);\n \n sigs.drv_cb.scl_out <= 1'b1;\n wait(sigs.drv_cb.scl_in === 1'b1); // if the slave stretches the clock, wait for it to release\n repeat(num_of_clocks_for_scl_high_period) @(sigs.drv_cb);\n end\n \n stop_scl = 0;\n \n `uvm_info(get_type_name(), $sformatf(\"toggle_scl end\"), UVM_NONE )\nendtask: toggle_scl\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::create_start_condition(uvm_phase phase);\n `uvm_info(get_type_name(), $sformatf(\"create_start_condition start\"), UVM_FULL )\n \n if (bus_is_busy) setup_for_a_continuous_start(); \n else phase.raise_objection(this); // when grabbing the bus, raise objection\n \n if (sigs.drv_cb.scl_in !== 1'b1) `uvm_fatal(get_type_name(), $sformatf(\"creating start condition but SCL is not high\") )\n sigs.drv_cb.sda_out <= 1'b0;\n \n repeat(num_of_clocks_for_t_hd_sta_min) @(sigs.drv_cb);\n \n `uvm_info(get_type_name(), $sformatf(\"create_start_condition end\"), UVM_FULL )\nendtask: create_start_condition\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::create_stop_condition(uvm_phase phase);\n \n wait(sigs.drv_cb.scl_in === 1'b0);\n repeat(num_of_clocks_for_t_hd_dat_max) @(sigs.drv_cb);\n sigs.drv_cb.sda_out <= 1'b0; //prepare SDA to rise when clock is high\n \n wait(sigs.drv_cb.scl_in === 1'b1);\n repeat(num_of_clocks_for_t_su_sto_min) @(sigs.drv_cb);\n sigs.drv_cb.sda_out <= 1'b1;\n \n stop_scl = 1;\n \n repeat(num_of_clocks_for_t_buf_min) @(sigs.drv_cb);\n \n phase.drop_objection(this);\n \nendtask: create_stop_condition\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::transmit_address();\n \n for(int i = cfg.address_num_of_bits; i; i--) drive_data_bit_to_sda( .data_bit(req.address[i-1]) );\n drive_data_bit_to_sda( .data_bit( logic'(req.direction_e) ) );\n \nendtask: transmit_address\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::get_slave_ack(output logic ack);\n \n wait(sigs.drv_cb.scl_in === 1'b0); // wait for negedge where the slave drives the ack value\n wait(sigs.drv_cb.scl_in === 1'b1); // read the value when SCL is high\n ack = sigs.drv_cb.sda_in;\n \nendtask:get_slave_ack\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::setup_for_a_continuous_start();\n `uvm_info(get_type_name(), $sformatf(\"setup_for_a_continuous_start start\"), UVM_FULL )\n \n wait(sigs.drv_cb.scl_in === 1'b0);\n repeat(num_of_clocks_for_t_hd_dat_max) @(sigs.drv_cb);\n sigs.drv_cb.sda_out <= 1'b1; //prepare SDA to fall when clock is high\n \n stop_scl = 1; // SCL will be restarted after the continuous start is complete\n \n wait(sigs.drv_cb.scl_in === 1'b1);\n //repeat(num_of_clocks_for_scl_high_period) @(sigs.drv_cb); // TBD\n repeat(num_of_clocks_for_t_su_sta_min) @(sigs.drv_cb); //continuous start setup time\n \n `uvm_info(get_type_name(), $sformatf(\"setup_for_a_continuous_start end\"), UVM_FULL )\nendtask: setup_for_a_continuous_start\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::transmit_write_data();\n logic ack;\n \n for(int data_word = 0; data_word < req.data.size(); data_word++) begin\n // transmit current data word 1 bit at a time MSB to LSB, data is always 8 bit\n for(int i = 8; i ; i--) drive_data_bit_to_sda( .data_bit(req.data[data_word][i-1]) ); \n\n get_slave_ack( .ack(ack) ); // get the ack from the slave for each data word\n if (ack === 1'b1) break; // received a NACK, stop transmitting data words\n end\n\nendtask: transmit_write_data\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::receive_read_data();\n int number_of_read_words = req.data.size();\n logic [7:0] received_data = '0;\n \n if (number_of_read_words === 0) `uvm_error(get_type_name(), $sformatf(\"number_of_read_words = %0d\", number_of_read_words) )\n req.data.delete(); //remove any data that exists so that only data received will be in the data queue\n \n for(int current_read_word = 0; current_read_word < number_of_read_words; current_read_word++) begin\n \n // if the master previously responded with an ACK, release the SDA line here for the next read word\n // so the slave won't be blocked for transmission. \n if (sigs.drv_cb.sda_in === 1'b0) begin\n wait(sigs.drv_cb.scl_in === 1'b0);\n repeat(num_of_clocks_for_t_hd_dat_max) @(sigs.drv_cb);\n sigs.drv_cb.sda_out <= 1'b1;\n end\n \n // get data from slave\n for(int i = 8; i ; i--) begin\n wait(sigs.drv_cb.scl_in === 1'b0);\n wait(sigs.drv_cb.scl_in === 1'b1);\n req.data[current_read_word][i-1] = sigs.drv_cb.sda_in;\n `uvm_info(get_type_name(), $sformatf(\"i = %0d, sigs.drv_cb.sda_in = %0h, req.data[%0d] = %0h\", i, sigs.drv_cb.sda_in, current_read_word,req.data[current_read_word]), UVM_FULL )\n end\n \n if ( (current_read_word+1) !== number_of_read_words) transmit_ack_for_read( .ack(0) );\n else transmit_ack_for_read( .ack(1) ); // last read word, return NACK\n \n `uvm_info(get_type_name(), $sformatf(\"req.data[%0d] = %0h\", current_read_word, req.data[current_read_word]), UVM_NONE )\n end\n \nendtask: receive_read_data\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::transmit_ack_for_read(bit ack = 0);\n drive_data_bit_to_sda( .data_bit(ack) );\nendtask: transmit_ack_for_read\n\n//------------------------------------------------------------------------//\n// data is driven on the SDA only when the SCL is low and after the t_hd_dat.\n// t_hd_dat moves the data transition from the SCL falling edge. \ntask i2c_master_driver::drive_data_bit_to_sda(logic data_bit);\n abritration_checking_enabled = 1; // checking arbitration only when data is driven to the bus by the driver\n \n wait(sigs.drv_cb.scl_in === 1'b0);\n repeat(num_of_clocks_for_t_hd_dat_max) @(sigs.drv_cb);\n sigs.drv_cb.sda_out <= data_bit;\n abritration_current_drive_value = data_bit;\n wait(sigs.drv_cb.scl_in === 1'b1);\n \n abritration_checking_enabled = 0;\nendtask: drive_data_bit_to_sda\n\n//------------------------------------------------------------------------//\ntask i2c_master_driver::check_if_arbitration_is_lost(output logic arbitration_lost);\n arbitration_lost = '0;\n `uvm_info(get_type_name(), $sformatf(\"check_if_arbitration_is_lost start\"), UVM_FULL )\n \n wait(sigs.drv_cb.scl_in === 1'b0);\n wait(sigs.drv_cb.scl_in === 1'b1);\n if (abritration_checking_enabled) begin //arbitration is verified when SCL is high\n `uvm_info(get_type_name(), $sformatf(\"sigs.drv_cb.sda_in = %0h, arbitration_current_drive_value = %0h\", sigs.drv_cb.sda_in, abritration_current_drive_value), UVM_FULL )\n if(sigs.drv_cb.sda_in !== abritration_current_drive_value) arbitration_lost = 1'b1;\n end\n \nendtask: check_if_arbitration_is_lost\n\n`endif //I2C_MASTER_DRIVER__SV\n", "groundtruth": " else seq_item_port.get_next_item(req); //wait for a sequence item from the sequencer\n", "crossfile_context": ""} {"task_id": "UH-JLS", "path": "UH-JLS/RTL_develop_ver/merge.sv", "left_context": "`timescale 1 ns/1 ns\n\nmodule merge(\n input wire rst,\n input wire clk,\n input wire i_et,\n input wire i_vl [1:8],\n input wire [ 4:0] i_oc [1:8],\n input wire [14:0] i_pv [1:8],\n input wire [ 3:0] i_pc [1:8],\n input wire [ 4:0] i_zc [1:8],\n input wire [ 8:0] i_bv [1:8],\n input wire [ 3:0] i_bc [1:8],\n output reg o_vl [1:8],\n output reg [ 4:0] o_oc [1:8],\n output reg [14:0] o_pv [1:8],\n output reg [ 3:0] o_pc [1:8],\n output reg [ 4:0] o_zc [1:8],\n output reg [ 8:0] o_bv [1:8],\n output reg [ 3:0] o_bc [1:8]\n);\n\nreg a_vl [1:7];\nreg [ 4:0] a_oc [1:7];\nreg [14:0] a_pv [1:7];\nreg [ 3:0] a_pc [1:7];\nreg [ 4:0] a_zc [1:7];\nreg [ 8:0] a_bv [1:7];\nreg [ 3:0] a_bc [1:7];\n\nalways @ (posedge clk) begin\n for(int i=1; i<=7; i++) begin\n if(rst) begin\n a_vl[i] <= 1'b0;\n o_vl[i] <= 1'b0;\n end else if(i_et) begin\n a_vl[i] <= 1'b0;\n o_vl[i] <= a_vl[i] | i_vl[i];\n o_oc[i] <= i_vl[i] ? i_oc[i] : a_oc[i];\n o_pv[i] <= i_vl[i] ? i_pv[i] : a_pv[i];\n", "right_context": " a_zc[i] <= i_zc[i];\n a_bv[i] <= i_bv[i];\n a_bc[i] <= i_bc[i];\n o_vl[i] <= 1'b0;\n end else begin\n o_vl[i] <= 1'b0;\n end\n end\n o_vl[8] <= ~rst & i_et & i_vl[8];\n if(i_et) begin\n o_oc[8] <= i_oc[8];\n o_pv[8] <= i_pv[8];\n o_pc[8] <= i_pc[8];\n o_zc[8] <= i_zc[8];\n o_bv[8] <= i_bv[8];\n o_bc[8] <= i_bc[8];\n end\nend\n\nendmodule\n", "groundtruth": " o_pc[i] <= i_vl[i] ? i_pc[i] : a_pc[i];\r\n o_zc[i] <= i_vl[i] ? i_zc[i] : a_zc[i];\r\n o_bv[i] <= i_vl[i] ? i_bv[i] : a_bv[i];\r\n o_bc[i] <= i_vl[i] ? i_bc[i] : a_bc[i];\r\n end else if(i_vl[i]) begin\r\n", "crossfile_context": ""} {"task_id": "csi2_rx", "path": "csi2_rx/src/csi2_crc_calc.sv", "left_context": "module csi2_crc_calc\n(\n input clk_i,\n input rst_i,\n input [31 : 0] tdata_i,\n input [3 : 0] tstrb_i,\n input tvalid_i,\n input tlast_i,\n output logic crc_passed_o,\n output logic crc_failed_o\n);\n\nlocalparam int CSI2_CRC_POLY = 16'h1021;\n\nlogic [15 : 0] main_crc;\nlogic [15 : 0] crc_8bit;\nlogic [15 : 0] crc_8bit_prev;\nlogic [15 : 0] crc_16bit;\nlogic [15 : 0] crc_16bit_prev;\nlogic [15 : 0] crc_24bit;\nlogic [15 : 0] crc_24bit_prev;\nlogic payload_in_progress;\nlogic long_pkt_payload_valid;\nlogic [31 : 0] long_pkt_payload;\nlogic long_pkt_eop;\nlogic long_pkt_eop_d1;\nlogic crc_passed;\nlogic crc_failed;\n\nassign long_pkt_payload = tdata_i;\nassign long_pkt_payload_valid = tvalid_i && payload_in_progress;\nassign long_pkt_eop = tlast_i && payload_in_progress;\n\nalways_ff @( posedge clk_i, posedge rst_i )\n if( rst_i )\n payload_in_progress <= '0;\n else\n if( !payload_in_progress && tvalid_i &&\n tdata_i[7 : 0] > 8'hf )\n payload_in_progress <= 1'b1;\n else\n if( payload_in_progress && tvalid_i &&\n tlast_i )\n payload_in_progress <= 1'b0;\n\nalways_ff @( posedge clk_i, posedge rst_i )\n if( rst_i )\n long_pkt_eop_d1 <= 1'b0;\n else\n long_pkt_eop_d1 <= long_pkt_eop;\n\ncrc_calc #(\n .POLY ( CSI2_CRC_POLY ),\n .CRC_SIZE ( 16 ),\n .DATA_WIDTH ( 32 ),\n .INIT ( 16'hffff ),\n .REF_IN ( 1 ),\n .REF_OUT ( 1 ),\n .XOR_OUT ( 16'h0 )\n) main_calc (\n .clk_i ( clk_i ),\n .rst_i ( rst_i ),\n .soft_reset_i ( long_pkt_eop_d1 ),\n .valid_i ( long_pkt_payload_valid ),\n .data_i ( long_pkt_payload ),\n .crc_o ( main_crc )\n);\n\nalways_comb\n begin\n crc_8bit = main_crc;\n crc_8bit_prev = main_crc;\n for( int i = 0; i < 8; i++ )\n begin\n crc_8bit[15] = crc_8bit_prev[0] ^ long_pkt_payload[i];\n for( int j = 1; j < 16; j++ )\n if( CSI2_CRC_POLY[j] )\n crc_8bit[15 - j] = crc_8bit_prev[16 - j] ^ crc_8bit_prev[0] ^ \n long_pkt_payload[i];\n else\n crc_8bit[15 - j] = crc_8bit_prev[16 - j];\n crc_8bit_prev = crc_8bit;\n end\n end\n\nalways_comb\n begin\n crc_16bit = main_crc;\n crc_16bit_prev = main_crc;\n for( int i = 0; i < 16; i++ )\n begin\n crc_16bit[15] = crc_16bit_prev[0] ^ long_pkt_payload[i];\n for( int j = 1; j < 16; j++ )\n if( CSI2_CRC_POLY[j] )\n crc_16bit[15 - j] = crc_16bit_prev[16 - j] ^ crc_16bit_prev[0] ^ \n long_pkt_payload[i];\n else\n crc_16bit[15 - j] = crc_16bit_prev[16 - j];\n crc_16bit_prev = crc_16bit;\n end\n end\n\nalways_comb\n", "right_context": " long_pkt_payload[i];\n else\n crc_24bit[15 - j] = crc_24bit_prev[16 - j];\n crc_24bit_prev = crc_24bit;\n end\n end\n\nassign crc_passed = ( long_pkt_eop &&\n ( ( tstrb_i == 4'b0001 && crc_8bit == '0 ) ||\n ( tstrb_i == 4'b0011 && crc_16bit == '0 ) ||\n ( tstrb_i == 4'b0111 && crc_24bit == '0 ) ||\n ( tstrb_i == 4'b1111 && main_crc == '0 ) ) );\n\nassign crc_failed = ( long_pkt_eop &&\n ( ( tstrb_i == 4'b0001 && crc_8bit != '0 ) ||\n ( tstrb_i == 4'b0011 && crc_16bit != '0 ) ||\n ( tstrb_i == 4'b0111 && crc_24bit != '0 ) ||\n ( tstrb_i == 4'b1111 && main_crc != '0 ) ) );\n\n\nalways_ff @( posedge clk_i, posedge rst_i )\n if( rst_i )\n begin\n crc_passed_o <= '0;\n crc_failed_o <= '0;\n end\n else\n begin\n crc_passed_o <= crc_passed;\n crc_failed_o <= crc_failed;\n end\n\n\nendmodule\n", "groundtruth": " begin\n crc_24bit = main_crc;\n crc_24bit_prev = main_crc;\n for( int i = 0; i < 24; i++ )\n begin\n", "crossfile_context": ""} {"task_id": "riscv-proc", "path": "riscv-proc/source/mux4.sv", "left_context": "module mux4 (input logic [31:0] d0, d1, d2, d3, input logic [1:0] s, \n\t\t\toutput logic [31:0] y);\nalways_comb begin\n\tcase(s)\n", "right_context": "", "groundtruth": "\t\t\t2'b00: y = d0;\r\n\t\t\t2'b01: y = d1;\r\n\t\t\t2'b10: y = d2;\r\n\t\t\t2'b11: y = d3;\r\n\tendcase\r\n", "crossfile_context": ""} {"task_id": "tinyGPU", "path": "tinyGPU/Verilog/Testbenches/smcore_tb.sv", "left_context": "`include \"../constants_local.sv\"\n`include \"../constants.sv\"\n\n`include \"../Modules/SMCore/SPCore/ALU/ALU.sv\"\n`include \"../Modules/SMCore/SPCore/RegisterFile/RegisterFile.sv\"\n`include \"../Modules/SMCore/SPCore/Mux/Mux3x16.sv\"\n\n`include \"../Modules/SMCore/SPCore/SPCore.sv\"\n`include \"../Modules/SMCore/SPCore/N_SPCores.sv\"\n\n`include \"../Modules/SMCore/Scheduler/PC/PC.sv\"\n`include \"../Modules/SMCore/Scheduler/CU/CU.sv\"\n`include \"../Modules/SMCore/Scheduler/PStack/PStack.sv\"\n\n`include \"../Modules/SMCore/Scheduler/Scheduler.sv\"\n`include \"../Modules/MemoryController/MemoryController_NCores.sv\"\n\n`include \"../Modules/SMCore/SMCore.sv\"\n\n`include \"../Modules/DataMemory/DataMemory.sv\"\n`include \"../Modules/InstructionMemory/InstructionMemory.sv\"\n\n`timescale 1ns/10ps\n\nmodule smcore_tb;\n\n //Filet to save memory content\n integer mem_dumpfile;\n \n //Reset\n reg reset;\n initial begin \n reset=1; #5 reset=0; //reset PC register at the begining\n end \n\n //Clock\n parameter clk_period = 20;\t\n\treg clk = 1'b0;\n\talways begin\n\t\t#(clk_period/2) clk <= !clk;\n\tend\n wire memclk;\n // assign memclk=~clk;\n", "right_context": " wire [`DATAMEM_ADDR_WIDTH-1:0] DataAddress;\n wire [`DATA_WORD_LENGTH-1:0] DataToWrite;\n wire [`DATA_WORD_LENGTH-1:0] DataToRead;\n wire DataMemWrEn;\n\n // Modules\n DataMemory DMem(memclk,DataMemWrEn,DataAddress,DataToWrite,DataToRead);\n InstructionMemory IMem(clk,inst_addr,inst);\n SMCore SMCore(inst_addr,inst,DataAddress,DataToWrite,DataToRead,DataMemWrEn, clk, reset);\n\n // Dump Variables to file\n\tinitial begin\n\t\t$dumpfile(\"dump.vcd\");\n\t\t$dumpvars(0,smcore_tb);\n\tend\n\n // Logging\n initial begin\n $monitor(\"DMem[0]= %d DMem[1]= %d DMem[2]= %d DMem[3]= %d \\n \",DMem.RAM[0],DMem.RAM[1],DMem.RAM[2],DMem.RAM[3]);\n end\n\n //Finish simulation when there are no more instructions in the instruction memory\n always @(posedge clk) begin\n if (SMCore.Scheduler.CU.state == 19) begin //STATE_END\n\n // Save memory to file\n mem_dumpfile = $fopen(\"MemoryFiles/memory_out.hex\",\"w\"); // Change the \"w\" to \"a\" to append data to an existing file\n for (integer i = 0;i < 32;i = i + 1)\n $fdisplay(mem_dumpfile,\"%d \",DMem.RAM[i]); \n\n //Finish\n $display(\"------------------------\\nEnding Simulation \\n------------------------\\n\");\n $finish;\n end\n end\n\n\nendmodule\n", "groundtruth": " assign memclk=clk;\n\n //Connections to Instruction Memory\n wire [`INSTMEM_ADDR_WIDTH-1:0] inst_addr;\n", "crossfile_context": ""} {"task_id": "NiteFury-and-LiteFury", "path": "NiteFury-and-LiteFury/Sample-Projects/Project-0/FPGA/LiteFury/project/project.srcs/sources_1/imports/HDL/CodeBlinker.v", "left_context": "`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 10/31/2018 09:33:27 PM\n// Design Name: \n// Module Name: CodeBlinker\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: Blinks LED based on value, and also keeps LED on for a minimum time if the OK signal flickers\n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\n// !OK: On solid\n// When OK goes high:\n// (stays on dim for certain time)\n// (blinks based on code)\n// ('.' indicates some delay; '..' is twice the delay) \n// 0: dim .... off\n// 1: dim .... off .. on . off .. on . off .. [forever]\n// 2: dim .... off .. on . off. on. off .. on . off. on. off .. [forever] \n\t\t\t\t\t\t \n\nmodule CodeBlinker(\n input clk,\n\tinput ok,\n\tinput [2:0] code,\n\toutput reg led\n );\n\n\t// If we know the input clock, we can use reasonable rates for LED blinking\n\tparameter IN_CLK_MHZ = 32'd100;\n\n\n\t// Defines\n\tlocalparam LED_ON = 1'b0;\n\tlocalparam LED_OFF = 1'b1;\n\n\n // Default values for outputs\n\tinitial led = LED_ON;\n\n\t// Declare states\n\tlocalparam S_NOK = 0; \t// ok input is false- LED is ON\n\tlocalparam S_OFF = 1;\t \t// Displaying code- off time\n\tlocalparam S_ON = 2; \t// Displaying code- on time\n\tlocalparam S_CYCLEWAIT = 3; // Done displaying code- wait with LED off before repeating\n\n\t// Declare state register and other state variables\n\treg\t[2:0] state = S_NOK;\n\treg [2:0] curCodeDisp = 0;\n\n\t// Divides incoming clock\n\tlocalparam BASE_DELAY = 32'd672000 * IN_CLK_MHZ;\n\tlocalparam DELAY_STRETCH = BASE_DELAY << 2; // Lower 2 bits must be 0 for LED to be on solid in state S_NOK\n\tlocalparam DELAY_BLINK = BASE_DELAY;\n\tlocalparam DELAY_CYCLE = BASE_DELAY << 1;\n\treg signed [31:0] counter = DELAY_CYCLE;\n\n\t// Debouncing inputs\n\treg s_ok;\n\treg [2:0] s_code;\n\n\n\t// Output depends only on the state and the countdown counter\n\talways @(negedge clk)\n\tbegin\n\n\t\t// Sample inputs/update outputs on negative edge. Logic happens on positive edge\n\t\ts_ok <= ok;\n\t\ts_code <= code;\n\n\n\t\tcase (state)\n\t\t\tS_ON:\n\t\t\t\tled = LED_ON;\n\n\t\t S_NOK:\n\t\t\t\tled = | counter[1:0]; // Only on 1/4 duty\n\n\n\t\t\tdefault:\n\t\t\t\tled = LED_OFF; \n\t\tendcase\n\tend\n\n\n\talways @(posedge clk)\n\tbegin\n\t\tif (!s_ok)\n\t\t\tbegin\n\t\t\t\tstate <= S_NOK;\n\t\t\t\tcounter <= DELAY_STRETCH;\n\t\t\tend\n\t\telse\n\t\t\tbegin\n\t\t\t\tif (counter > 0)\n\t\t\t\t\tcounter <= counter - 1;\n\t\t\t\telse\n\t\t\t\t\tbegin\n", "right_context": "\t\t\t\t\t\t\tS_NOK: \n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tstate <= S_CYCLEWAIT;\n\t\t\t\t\t\t\t\tend\n\n\t\t\t\t\t\t\tS_OFF:\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tcounter <= DELAY_BLINK;\n\t\t\t\t\t\t\t\t\tcurCodeDisp <= curCodeDisp - 1;\n\n\t\t\t\t\t\t\t\t\tif (0 == curCodeDisp)\n\t\t\t\t\t\t\t\t\t\tstate <= S_CYCLEWAIT;\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\tstate <= S_ON;\n\n\t\t\t\t\t\t\t\tend\n\n\t\t\t\t\t\t\tS_ON:\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tcounter <= DELAY_BLINK;\n\t\t\t\t\t\t\t\t\tstate <= S_OFF;\n\t\t\t\t\t\t\t\tend\n\n\t\t\t\t\t\t\tS_CYCLEWAIT: // Done blinking the code- capture the next code to blink here\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tcounter <= DELAY_CYCLE;\n\t\t\t\t\t\t\t\t\tstate <= S_OFF;\n\t\t\t\t\t\t\t\t\tcurCodeDisp <= s_code;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\tendcase\n\n\t\t\t\t\tend\n\t\t\tend\n\tend\n\n\nendmodule\n", "groundtruth": "\t\t\t\t\t\tcase (state)\n", "crossfile_context": ""} {"task_id": "riscv-aia", "path": "riscv-aia/rtl/aplic_top.sv", "left_context": "/** \n* Copyright 2023 Francisco Marques & Zero-Day Labs, Lda\n* SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n* \n* Author: F.Marques \n*/\n\nmodule aplic_top \nimport aplic_pkg::*;\nimport imsic_pkg::*;\nimport imsic_protocol_pkg::*;\n#(\n parameter aplic_cfg_t AplicCfg = DefaultAplicCfg,\n parameter imsic_cfg_t ImsicCfg = DefaultImsicCfg,\n parameter protocol_cfg_t ProtocolCfg = DefaultImsicProtocolCfg,\n parameter type reg_req_t = logic ,\n parameter type reg_rsp_t = logic ,\n parameter type axi_req_t = logic ,\n parameter type axi_resp_t = logic\n) (\n input logic i_clk ,\n input logic ni_rst ,\n input logic [AplicCfg.NrSources-1:0] i_irq_sources ,\n /** APLIC domain interface */\n input reg_req_t i_req_cfg ,\n output reg_rsp_t o_resp_cfg ,\n `ifdef MSI_MODE\n `ifdef AIA_EMBEDDED\n /** IMSIC island CSR interface */\n input csr_channel_to_imsic_t [ImsicCfg.NrHarts-1:0] i_imsic_csr, \n output csr_channel_from_imsic_t [ImsicCfg.NrHarts-1:0] o_imsic_csr,\n /** IMSIC island AXI interface*/\n input axi_req_t i_imsic_req ,\n output axi_resp_t o_imsic_resp\n `elsif AIA_DISTRIBUTED\n output axi_req_t o_msi_req,\n input axi_resp_t i_msi_rsp\n `endif\n `elsif DIRECT_MODE\n output logic [AplicCfg.NrHarts-1:0] o_eintp_cpu [AplicCfg.NrDomains-1:0]\n `endif\n); /** End of APLIC top interface */\n\n /** \n * A 2-level synchronyzer to avoid metastability in the irq line\n */\n logic [AplicCfg.NrSources-1:0] sync_irq_src;\n synchronizer_multi_level #(\n .DataW ( AplicCfg.NrSources ),\n .NrLevels ( 2 )\n ) synchronizer_multi_level_i (\n .i_clk ( i_clk ),\n .ni_rst ( ni_rst ),\n .data_i ( i_irq_sources ),\n .data_o ( sync_irq_src )\n );\n\n /** APLIC Domain with IMSIC island */\n aplic_domain_top #(\n .AplicCfg ( AplicCfg ),\n .ImsicCfg ( ImsicCfg ),\n .ProtocolCfg ( ProtocolCfg ),\n .reg_req_t ( reg_req_t ),\n .reg_rsp_t ( reg_rsp_t ),\n .axi_req_t ( axi_req_t ),\n .axi_resp_t ( axi_resp_t )\n ) i_aplic_generic_domain_top (\n .i_clk ( i_clk ),\n .ni_rst ( ni_rst ),\n .i_req_cfg ( i_req_cfg ),\n .o_resp_cfg ( o_resp_cfg ),\n .i_irq_sources ( sync_irq_src ),\n `ifdef MSI_MODE\n `ifdef AIA_EMBEDDED\n .i_imsic_csr ( i_imsic_csr ),\n .o_imsic_csr ( o_imsic_csr ), \n .i_imsic_req ( i_imsic_req ),\n .o_imsic_resp ( o_imsic_resp ) \n `elsif AIA_DISTRIBUTED\n .o_msi_req ( o_msi_req ),\n", "right_context": " `endif\n `elsif DIRECT_MODE\n .o_eintp_cpu ( o_eintp_cpu )\n `endif\n );\n\nendmodule", "groundtruth": " .i_msi_rsp ( i_msi_rsp )\n", "crossfile_context": ""} {"task_id": "AHB-to-APB-Bridge-Verification", "path": "AHB-to-APB-Bridge-Verification/Bridge_rtl/ahb_apb_top.v", "left_context": "// Include definitions\n`include \"definitions.v\"\n module rtl_top (input Hclk,\n input Hresetn,\n input [1:0] Htrans,\n input [2:0]Hsize,\n input Hreadyin,\n input [`WIDTH-1:0]Hwdata,\n input [`WIDTH-1:0]Haddr,\n input Hwrite,\n input [`WIDTH-1:0]Prdata,\n output [`WIDTH-1:0]Hrdata,\n output [1:0]Hresp,\n output Hreadyout,\n output [`SLAVES-1:0]Pselx,\n output Pwrite,\n output Penable,\n output [`WIDTH-1:0] Paddr,\n output [`WIDTH-1:0] Pwdata\n ) ;\n\n wire valid,Pwrite_wire,Penable_wire,Hreadyout_wire;\n wire [`WIDTH-1 : 0] Pwdata_wire, Paddr_wire, Prdata_wire,inc_address,Haddr_reg_d1,Haddr_reg_d2,Haddr_reg_d3;\n wire [`SLAVES-1 : 0] Pselx_out, Pselx_wire;\n wire [`WIDTH-1:0] config_data;\n\n ahb AHB_SLAVE(Hclk,\n Hresetn,\n Htrans,\n Hsize,\n Hreadyin,\n Hwdata,\n Haddr,\n Hwrite,\n Hreadyout_wire,\n Penable_wire,\n Hresp,\n Hreadyout,\n Pselx_out,\n valid,\n config_data,\n inc_address,Haddr_reg_d1,Haddr_reg_d2,Haddr_reg_d3) ;\n\n", "right_context": " Pselx_out[1],\n Pselx_out[2],\n Pselx_out[3],\n Haddr_reg_d1,Haddr_reg_d2,Haddr_reg_d3,inc_address,\n Htrans,\n Hsize,\n Hwdata,\n Prdata_wire,\n config_data,\n Penable_wire,\n Pwrite_wire,\n Pselx_wire,\n Paddr_wire,\n Hreadyout_wire,\n Pwdata_wire,\n Hrdata);\n\n apb APB_MASTER( Paddr_wire,\n Penable_wire,\n Pwrite_wire,\n Pwdata_wire,\n Pselx_wire,\n Prdata,\n Paddr,\n Pwrite,\n Penable,\n Pwdata,\n Pselx,\n Prdata_wire );\n\n\n endmodule\n", "groundtruth": " apb_controller FSM(Hclk,\r\n Hresetn,\r\n valid,\r\n", "crossfile_context": ""} {"task_id": "FM_Radio", "path": "FM_Radio/rtl/iq_modulator.sv", "left_context": "/* 1-bit I/Q modulator\n *\n * ω1: broadcast carrier at input 'adc'\n * ω2: local oscillator from DDS\n *\n * Tuned, when ω1 = ω2.\n *\n * I = cos(ω1∙t + θ)∙cos(ω2)\n * Q = cos(ω1∙t + θ)∙(-sin(ω2))\n */\n\nmodule iq_modulator\n (input wire clk,\n input wire adc,\n input wire signed [1:0] phase,\n output logic signed [1:0] I, Q);\n\n /* I = cos(phase) * ADC\n * Q = -sin(phase) * ADC\n */\n always_ff @(posedge clk)\n case (phase)\n 2'b00:\n begin\n I <= to_signed(adc);\n Q <= -to_signed(adc);\n end\n\n 2'b01:\n begin\n I <= -to_signed(adc);\n Q <= -to_signed(adc);\n end\n\n 2'b10:\n", "right_context": " 2'b11:\n begin\n I <= to_signed(adc);\n Q <= to_signed(adc);\n end\n endcase\n\n function logic signed [1:0] to_signed(input x);\n return 2 * x - 1;\n endfunction\nendmodule\n", "groundtruth": " begin\n I <= -to_signed(adc);\n Q <= to_signed(adc);\n", "crossfile_context": ""} {"task_id": "aes128-hdl", "path": "aes128-hdl/src/sv/aes128Pkg.sv", "left_context": "/**\n * Package: aes128Pkg\n * \n * A package for the 128-bit version of the Advanced Encryption Standard (AES)\n * design. A couple of types, constants, and functions are defined herein,\n * which are used throughout the whole design.\n * \n * General Information:\n * File - aes128Pkg.sv\n * Title - AES-128 package\n * Project - VLSI Book AES-128 Example\n * Author - Michael Muehlberghuber (mbgh@iis.ee.ethz.ch)\n * Company - Integrated Systems Laboratory, ETH Zurich\n * Copyright - Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich\n * File Created - 2014-10-16\n * Last Updated - 2014-10-16\n * Platform - Simulation=QuestaSim; Synthesis=Synopsys\n * Standard - SystemVerilog 1800-2009\n * \n * Revision Control System Information:\n * File ID - $Id: aes128Pkg.sv 33 2014-10-22 07:26:02Z u59323933 $\n * Revision - $Revision: 33 $\n * Local Date - $Date: 2014-10-22 09:26:02 +0200 (Wed, 22 Oct 2014) $\n * Modified By - $Author: u59323933 $\n * \n * Major Revisions:\n * 2014-10-16 (v1.0) - Created (mbgh)\n */\n\npackage aes128Pkg;\n\t\n\t// --------------------------------------------------------------------------\n \t// Type definitions\n\t// --------------------------------------------------------------------------\n\t/**\n\t * Type: Byte\n\t * A synonym for a logic[7:0].\n\t */\n\ttypedef logic [7:0]\t\tByte;\n\t\n\t/**\n\t * Type: Word\n\t * A word made up of four .\n\t */\n\ttypedef Byte\t\t\t\t\tWord [0:3];\n\t\n\t/**\n\t * Type: Matrix\n\t * A matrix made up of four .\n\t */\n\ttypedef Word \tMatrix [0:3];\n\t\n\t/**\n\t * Type: roundkeyArrayType\n\t * An array for holding 11 round keys (each of them represented using a\n\t * logic[127:0]).\n\t */\n\ttypedef logic [127:0] roundkeyArrayType [0:10];\n\n\n\t// --------------------------------------------------------------------------\n\t// Functions\n\t// --------------------------------------------------------------------------\n\t\n\t/**\n\t * Function: to_word\n\t * \n\t * Converts a Word to a logic[31:0].\n\t */\n\tfunction automatic Word to_word;\n\t\tinput logic [31:0] inp;\n\t\tWord result;\n\t\tbegin\n\t\t\tresult[0] = inp[31:24];\n\t\t\tresult[1] = inp[23:16];\n\t\t\tresult[2] = inp[15:8];\n\t\t\tresult[3] = inp[7:0];\n\t\t\tto_word = result;\n\t\tend\n\tendfunction : to_word\n\t\n\t/**\n\t * Function: shift_rows\n\t * \n\t * Shifts the rows of a provided Matrix as defined for AES.\n\t */\n\tfunction automatic Matrix shift_rows;\n\t\tinput Matrix inp;\n\t\tMatrix result;\n\t\tbegin\n\t\t\t// First row\n\t\t\tresult[0][0] = inp[0][0];\n\t\t\tresult[1][0] = inp[1][0];\n\t\t\tresult[2][0] = inp[2][0];\n\t\t\tresult[3][0] = inp[3][0];\n\t\n\t\t\t// Second row\n\t\t\tresult[0][1] = inp[1][1];\n\t\t\tresult[1][1] = inp[2][1];\n\t\t\tresult[2][1] = inp[3][1];\n\t\t\tresult[3][1] = inp[0][1];\n\t\n\t\t\t// Third row\n\t\t\tresult[0][2] = inp[2][2];\n\t\t\tresult[1][2] = inp[3][2];\n\t\t\tresult[2][2] = inp[0][2];\n\t\t\tresult[3][2] = inp[1][2];\n\n\t\t\t// Fourth row\n\t\t\tresult[0][3] = inp[3][3];\n\t\t\tresult[1][3] = inp[0][3];\n", "right_context": "\t\t\tresult[3][3] = inp[2][3];\n\n\t\t\tshift_rows = result;\n\t\tend\n\tendfunction : shift_rows\n\t \n\t/**\n\t * Function: xor_matrix_logic\n\t * \n\t * Perform an XOR operation given a Matrix and a logic[127:0].\n\t */\n\tfunction automatic Matrix xor_matrix_logic;\n\t\tinput Matrix left;\n\t\tinput logic[127:0] right;\n \tMatrix result;\n\t\tbegin\n\t\t\t// First Column\n\t\t\tresult[0][0] = left[0][0] ^ right[127:120];\n\t\t\tresult[0][1] = left[0][1] ^ right[119:112];\n\t\t\tresult[0][2] = left[0][2] ^ right[111:104];\n\t\t\tresult[0][3] = left[0][3] ^ right[103:96];\n\t\t\t// Second Column\n\t\t\tresult[1][0] = left[1][0] ^ right[95:88];\n\t\t\tresult[1][1] = left[1][1] ^ right[87:80];\n\t\t\tresult[1][2] = left[1][2] ^ right[79:72];\n\t\t\tresult[1][3] = left[1][3] ^ right[71:64];\n\t\t\t// Third Column\n\t\t\tresult[2][0] = left[2][0] ^ right[63:56];\n\t\t\tresult[2][1] = left[2][1] ^ right[55:48];\n\t\t\tresult[2][2] = left[2][2] ^ right[47:40];\n\t\t\tresult[2][3] = left[2][3] ^ right[39:32];\n\t\t\t// Fourth Column\n\t\t\tresult[3][0] = left[3][0] ^ right[31:24];\n\t\t\tresult[3][1] = left[3][1] ^ right[23:16];\n\t\t\tresult[3][2] = left[3][2] ^ right[15:8];\n\t\t\tresult[3][3] = left[3][3] ^ right[7:0];\n\t\n\t\t\txor_matrix_logic = result;\n\t\tend\n\tendfunction : xor_matrix_logic\n\nendpackage : aes128Pkg\n\t ", "groundtruth": "\t\t\tresult[2][3] = inp[1][3];\n", "crossfile_context": ""} {"task_id": "register_interface", "path": "register_interface/src/axi_lite_to_reg.sv", "left_context": "// Copyright 2018-2020 ETH Zurich and University of Bologna.\n// Copyright and related rights are licensed under the Solderpad Hardware\n// License, Version 0.51 (the \"License\"); you may not use this file except in\n// compliance with the License. You may obtain a copy of the License at\n// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law\n// or agreed to in writing, software, hardware and materials distributed under\n// this License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n// CONDITIONS OF ANY KIND, either express or implied. See the License for the\n// specific language governing permissions and limitations under the License.\n//\n// Fabian Schuiki \n// Florian Zaruba \n\n/// A protocol converter from AXI4-Lite to a register interface.\nmodule axi_lite_to_reg #(\n /// The width of the address.\n parameter int ADDR_WIDTH = -1,\n /// The width of the data.\n parameter int DATA_WIDTH = -1,\n /// Buffer depth (how many outstanding transactions do we allow)\n parameter int BUFFER_DEPTH = 2,\n /// Whether the AXI-Lite W channel should be decoupled with a register. This\n /// can help break long paths at the expense of registers.\n parameter bit DECOUPLE_W = 1,\n /// AXI-Lite request struct type.\n parameter type axi_lite_req_t = logic,\n /// AXI-Lite response struct type.\n parameter type axi_lite_rsp_t = logic,\n /// Regbus request struct type.\n parameter type reg_req_t = logic,\n /// Regbus response struct type.\n parameter type reg_rsp_t = logic\n) (\n input logic clk_i ,\n input logic rst_ni ,\n input axi_lite_req_t axi_lite_req_i,\n output axi_lite_rsp_t axi_lite_rsp_o,\n output reg_req_t reg_req_o ,\n input reg_rsp_t reg_rsp_i\n);\n\n `ifndef SYNTHESIS\n initial begin\n assert(BUFFER_DEPTH > 0);\n assert(ADDR_WIDTH > 0);\n assert(DATA_WIDTH > 0);\n end\n `endif\n\n typedef struct packed {\n logic [ADDR_WIDTH-1:0] addr;\n logic [DATA_WIDTH-1:0] data;\n logic [DATA_WIDTH/8-1:0] strb; // byte-wise strobe\n } write_t;\n\n typedef struct packed {\n logic [ADDR_WIDTH-1:0] addr;\n logic write;\n } req_t;\n\n typedef struct packed {\n logic [DATA_WIDTH-1:0] data;\n logic error;\n } resp_t;\n\n logic write_fifo_full, write_fifo_empty;\n write_t write_fifo_in, write_fifo_out;\n logic write_fifo_push, write_fifo_pop;\n\n logic write_resp_fifo_full, write_resp_fifo_empty;\n logic write_resp_fifo_in, write_resp_fifo_out;\n logic write_resp_fifo_push, write_resp_fifo_pop;\n\n logic read_fifo_full, read_fifo_empty;\n logic [ADDR_WIDTH-1:0] read_fifo_in, read_fifo_out;\n logic read_fifo_push, read_fifo_pop;\n\n logic read_resp_fifo_full, read_resp_fifo_empty;\n resp_t read_resp_fifo_in, read_resp_fifo_out;\n logic read_resp_fifo_push, read_resp_fifo_pop;\n\n req_t read_req, write_req, arb_req;\n logic read_valid, write_valid;\n logic read_ready, write_ready;\n\n // Combine AW/W Channel\n fifo_v3 #(\n .FALL_THROUGH ( !DECOUPLE_W ),\n .DEPTH ( BUFFER_DEPTH ),\n .dtype ( write_t )\n ) i_fifo_write_req (\n .clk_i,\n .rst_ni,\n .flush_i ( 1'b0 ),\n .testmode_i ( 1'b0 ),\n .full_o ( write_fifo_full ),\n .empty_o ( write_fifo_empty ),\n .usage_o ( /* open */ ),\n .data_i ( write_fifo_in ),\n .push_i ( write_fifo_push ),\n .data_o ( write_fifo_out ),\n .pop_i ( write_fifo_pop )\n );\n\n assign axi_lite_rsp_o.aw_ready = write_fifo_push;\n assign axi_lite_rsp_o.w_ready = write_fifo_push;\n assign write_fifo_push = axi_lite_req_i.aw_valid & axi_lite_req_i.w_valid & ~write_fifo_full;\n assign write_fifo_in.addr = axi_lite_req_i.aw.addr;\n assign write_fifo_in.data = axi_lite_req_i.w.data;\n assign write_fifo_in.strb = axi_lite_req_i.w.strb;\n assign write_fifo_pop = write_valid & write_ready;\n\n // B Channel\n fifo_v3 #(\n .DEPTH ( BUFFER_DEPTH ),\n .dtype ( logic )\n ) i_fifo_write_resp (\n .clk_i,\n .rst_ni,\n .flush_i ( 1'b0 ),\n .testmode_i ( 1'b0 ),\n .full_o ( write_resp_fifo_full ),\n .empty_o ( write_resp_fifo_empty ),\n .usage_o ( /* open */ ),\n .data_i ( write_resp_fifo_in ),\n .push_i ( write_resp_fifo_push ),\n .data_o ( write_resp_fifo_out ),\n .pop_i ( write_resp_fifo_pop )\n );\n\n assign axi_lite_rsp_o.b_valid = ~write_resp_fifo_empty;\n assign axi_lite_rsp_o.b.resp = write_resp_fifo_out ? axi_pkg::RESP_SLVERR : axi_pkg::RESP_OKAY;\n assign write_resp_fifo_in = reg_rsp_i.error;\n assign write_resp_fifo_push = reg_req_o.valid & reg_rsp_i.ready & reg_req_o.write;\n assign write_resp_fifo_pop = axi_lite_rsp_o.b_valid & axi_lite_req_i.b_ready;\n\n // AR Channel\n fifo_v3 #(\n .DEPTH ( BUFFER_DEPTH ),\n .DATA_WIDTH ( ADDR_WIDTH )\n ) i_fifo_read (\n .clk_i,\n .rst_ni,\n .flush_i ( 1'b0 ),\n .testmode_i ( 1'b0 ),\n .full_o ( read_fifo_full ),\n .empty_o ( read_fifo_empty ),\n .usage_o ( /* open */ ),\n .data_i ( read_fifo_in ),\n .push_i ( read_fifo_push ),\n .data_o ( read_fifo_out ),\n .pop_i ( read_fifo_pop )\n );\n\n assign read_fifo_pop = read_valid && read_ready;\n assign axi_lite_rsp_o.ar_ready = ~read_fifo_full;\n assign read_fifo_push = axi_lite_rsp_o.ar_ready & axi_lite_req_i.ar_valid;\n assign read_fifo_in = axi_lite_req_i.ar.addr;\n\n // R Channel\n fifo_v3 #(\n .DEPTH ( BUFFER_DEPTH ),\n .dtype ( resp_t )\n ) i_fifo_read_resp (\n .clk_i,\n .rst_ni,\n .flush_i ( 1'b0 ),\n .testmode_i ( 1'b0 ),\n .full_o ( read_resp_fifo_full ),\n .empty_o ( read_resp_fifo_empty ),\n .usage_o ( /* open */ ),\n .data_i ( read_resp_fifo_in ),\n .push_i ( read_resp_fifo_push ),\n .data_o ( read_resp_fifo_out ),\n .pop_i ( read_resp_fifo_pop )\n );\n\n assign axi_lite_rsp_o.r.data = read_resp_fifo_out.data;\n assign axi_lite_rsp_o.r.resp =\n read_resp_fifo_out.error ? axi_pkg::RESP_SLVERR : axi_pkg::RESP_OKAY;\n assign axi_lite_rsp_o.r_valid = ~read_resp_fifo_empty;\n assign read_resp_fifo_pop = axi_lite_rsp_o.r_valid & axi_lite_req_i.r_ready;\n assign read_resp_fifo_push = reg_req_o.valid & reg_rsp_i.ready & ~reg_req_o.write;\n assign read_resp_fifo_in.data = reg_rsp_i.rdata;\n assign read_resp_fifo_in.error = reg_rsp_i.error;\n\n // Make sure we can capture the responses (e.g. have enough fifo space)\n assign read_valid = ~read_fifo_empty & ~read_resp_fifo_full;\n assign write_valid = ~write_fifo_empty & ~write_resp_fifo_full;\n\n // Arbitrate between read/write\n assign read_req.addr = read_fifo_out;\n assign read_req.write = 1'b0;\n assign write_req.addr = write_fifo_out.addr;\n assign write_req.write = 1'b1;\n\n stream_arbiter #(\n .DATA_T ( req_t ),\n .N_INP ( 2 ),\n .ARBITER ( \"rr\" )\n ) i_stream_arbiter (\n .clk_i,\n .rst_ni,\n .inp_data_i ( {read_req, write_req} ),\n .inp_valid_i ( {read_valid, write_valid} ),\n .inp_ready_o ( {read_ready, write_ready} ),\n .oup_data_o ( arb_req ),\n .oup_valid_o ( reg_req_o.valid ),\n .oup_ready_i ( reg_rsp_i.ready )\n );\n\n assign reg_req_o.addr = arb_req.addr;\n assign reg_req_o.write = arb_req.write;\n assign reg_req_o.wdata = write_fifo_out.data;\n assign reg_req_o.wstrb = write_fifo_out.strb;\n\nendmodule\n\n`include \"register_interface/typedef.svh\"\n`include \"register_interface/assign.svh\"\n`include \"axi/typedef.svh\"\n`include \"axi/assign.svh\"\n\n/// Interface wrapper.\nmodule axi_lite_to_reg_intf #(\n /// The width of the address.\n parameter int ADDR_WIDTH = -1,\n /// The width of the data.\n parameter int DATA_WIDTH = -1,\n /// Buffer depth (how many outstanding transactions do we allow)\n parameter int BUFFER_DEPTH = 2,\n /// Whether the AXI-Lite W channel should be decoupled with a register. This\n /// can help break long paths at the expense of registers.\n", "right_context": "\n typedef logic [ADDR_WIDTH-1:0] addr_t;\n typedef logic [DATA_WIDTH-1:0] data_t;\n typedef logic [DATA_WIDTH/8-1:0] strb_t;\n\n `REG_BUS_TYPEDEF_REQ(reg_req_t, addr_t, data_t, strb_t)\n `REG_BUS_TYPEDEF_RSP(reg_rsp_t, data_t)\n\n `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)\n `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)\n `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)\n `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)\n `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)\n `AXI_LITE_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)\n `AXI_LITE_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)\n\n axi_req_t axi_req;\n axi_resp_t axi_resp;\n reg_req_t reg_req;\n reg_rsp_t reg_rsp;\n\n `AXI_LITE_ASSIGN_TO_REQ(axi_req, axi_i)\n `AXI_LITE_ASSIGN_FROM_RESP(axi_i, axi_resp)\n\n `REG_BUS_ASSIGN_FROM_REQ(reg_o, reg_req)\n `REG_BUS_ASSIGN_TO_RSP(reg_rsp, reg_o)\n\n axi_lite_to_reg #(\n .ADDR_WIDTH (ADDR_WIDTH),\n .DATA_WIDTH (DATA_WIDTH),\n .BUFFER_DEPTH (BUFFER_DEPTH),\n .DECOUPLE_W (DECOUPLE_W),\n .axi_lite_req_t (axi_req_t),\n .axi_lite_rsp_t (axi_resp_t),\n .reg_req_t (reg_req_t),\n .reg_rsp_t (reg_rsp_t)\n ) i_axi_lite_to_reg (\n .clk_i (clk_i),\n .rst_ni (rst_ni),\n .axi_lite_req_i (axi_req),\n .axi_lite_rsp_o (axi_resp),\n .reg_req_o (reg_req),\n .reg_rsp_i (reg_rsp)\n );\n\nendmodule\n", "groundtruth": " parameter bit DECOUPLE_W = 1\n) (\n input logic clk_i ,\n input logic rst_ni ,\n", "crossfile_context": ""} {"task_id": "starshipraider", "path": "starshipraider/rtl/MAXWELL/main-fpga/main-fpga.srcs/sources_1/new/ClockSynthesis.sv", "left_context": "`default_nettype none\n`timescale 1ns/1ps\n/***********************************************************************************************************************\n* *\n* STARSHIPRAIDER v0.1 *\n* *\n* Copyright (c) 2012-2020 Andrew D. Zonenberg *\n* All rights reserved. *\n* *\n* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *\n* following conditions are met: *\n* *\n* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *\n* following disclaimer. *\n* *\n* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *\n* following disclaimer in the documentation and/or other materials provided with the distribution. *\n* *\n* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *\n* derived from this software without specific prior written permission. *\n* *\n* THIS SOFTWARE IS PROVIDED BY THE AUTHORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *\n* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *\n* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *\n* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *\n* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *\n* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *\n* POSSIBILITY OF SUCH DAMAGE. *\n* *\n***********************************************************************************************************************/\n\n/**\n\t@file\n\t@author Andrew D. Zonenberg\n\t@brief Clock generation for MAXWELL\n */\nmodule ClockSynthesis(\n\n\t//156.25 MHz LVDS clock from LMK04806\n\tinput wire\t\tk7_clk_p,\n\tinput wire\t\tk7_clk_n,\n\n\t//50 MHz RMII reference clock\n\toutput wire\t\tclk_50mhz,\n\n\t//125 MHz clock for RGMII\n\toutput wire\t\tclk_125mhz,\n\n\t//156.25 MHz system clock\n\toutput wire\t\tclk_156mhz,\n\n\t//200 MHz clock for IDELAYCTRL\n\toutput wire\t\tclk_200mhz,\n\n\t//250 MHz clock for RGMII\n\toutput wire\t\tclk_250mhz,\n\n\t//312.5 MHz system clock\n\toutput wire\t\tclk_312mhz,\n\n\t//400 MHz clock for IDELAYCTRL\n\toutput wire\t\tclk_400mhz,\n\n\t//625 MHz clock for LVDS probe inputs\n\toutput wire\t\tclk_625mhz,\n\n\toutput wire\t\tlocked\n);\n\n\t////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n\t// Input clock buffer\n\n\twire\tk7_clk;\n\n\tDifferentialInputBuffer #(\n\t\t.WIDTH(1),\n\t\t.IOSTANDARD(\"LVDS_25\"),\n\t\t.ODT(1),\n\t\t.OPTIMIZE(\"SPEED\")\n\t) ibuf_clk (\n\t\t.pad_in_p(k7_clk_p),\n\t\t.pad_in_n(k7_clk_n),\n\t\t.fabric_out(k7_clk)\n\t);\n\n\t////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n\t// Primary clock PLL used for all system clocks\n\n\twire\tmain_locked;\n\n\tReconfigurablePLL #(\n\t\t.OUTPUT_GATE(6'b111111),\n\t\t.OUTPUT_BUF_GLOBAL(6'b111111),\n\t\t.IN0_PERIOD(6.4),\n\t\t.IN1_PERIOD(6.4),\n\t\t.OUT0_MIN_PERIOD(20),\t//clk_50mhz\n\t\t.OUT1_MIN_PERIOD(8),\t//clk_125mhz,\n\t\t.OUT2_MIN_PERIOD(6.4),\t//clk_156mhz,\n\t\t.OUT3_MIN_PERIOD(4),\t//clk_250mhz,\n\t\t.OUT4_MIN_PERIOD(3.2),\t//clk_312mhz\n\t\t.OUT5_MIN_PERIOD(1.6),\t//clk_625mhz\n\t\t.ACTIVE_ON_START(1)\t\t//start PLL automatically out of reset\n\t) main_pll (\n\t\t.clkin({k7_clk, k7_clk}),\n\t\t.clksel(1'b0),\n\n\t\t.clkout({clk_625mhz, clk_312mhz, clk_250mhz, clk_156mhz, clk_125mhz, clk_50mhz}),\n\t\t.reset(1'b0),\n\t\t.locked(main_locked),\n\n\t\t.busy(),\n\t\t.reconfig_clk(k7_clk),\n\t\t.reconfig_start(1'b0),\n\t\t.reconfig_finish(1'b0),\n\t\t.reconfig_cmd_done(),\n\t\t.reconfig_vco_en(1'b0),\n\t\t.reconfig_vco_mult(7'b0),\n\t\t.reconfig_vco_indiv(7'b0),\n\t\t.reconfig_vco_bandwidth(1'b0),\n\t\t.reconfig_output_en(1'b0),\n\t\t.reconfig_output_idx(3'b0),\n\t\t.reconfig_output_div(8'b0),\n\t\t.reconfig_output_phase(9'b0)\n\t);\n\n\t////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n\t// Cascaded PLL used to produce the 400 MHz IDELAYCTRL clock and other even frequencies\n\n\twire[3:0] unused;\n\n\twire\teven_locked;\n\n\tReconfigurablePLL #(\n\t\t.OUTPUT_GATE(6'b000011),\n\t\t.OUTPUT_BUF_GLOBAL(6'b000011),\n\t\t.IN0_PERIOD(20),\n\t\t.IN1_PERIOD(20),\n\t\t.OUT0_MIN_PERIOD(2.5),\t//clk_400mhz\n\t\t.OUT1_MIN_PERIOD(5),\t//clk_200mhz\n\t\t.OUT2_MIN_PERIOD(2.5),\t//unused\n\t\t.OUT3_MIN_PERIOD(2.5),\t//unused\n\t\t.OUT4_MIN_PERIOD(2.5),\t//unused\n\t\t.OUT5_MIN_PERIOD(2.5),\t//unused\n\t\t.ACTIVE_ON_START(1)\t\t//start PLL automatically out of reset\n", "right_context": "\t\t.clkin({clk_50mhz, clk_50mhz}),\n\t\t.clksel(1'b0),\n\n\t\t.clkout({unused, clk_200mhz, clk_400mhz}),\n\t\t.reset(1'b0),\n\t\t.locked(even_locked),\n\n\t\t.busy(),\n\t\t.reconfig_clk(k7_clk),\n\t\t.reconfig_start(1'b0),\n\t\t.reconfig_finish(1'b0),\n\t\t.reconfig_cmd_done(),\n\t\t.reconfig_vco_en(1'b0),\n\t\t.reconfig_vco_mult(7'b0),\n\t\t.reconfig_vco_indiv(7'b0),\n\t\t.reconfig_vco_bandwidth(1'b0),\n\t\t.reconfig_output_en(1'b0),\n\t\t.reconfig_output_idx(3'b0),\n\t\t.reconfig_output_div(8'b0),\n\t\t.reconfig_output_phase(9'b0)\n\t);\n\n\t////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n\t// Status output\n\n\tassign locked = main_locked && even_locked;\n\nendmodule\n", "groundtruth": "\t) even_pll (\n", "crossfile_context": ""} {"task_id": "async_FIFO", "path": "async_FIFO/sim_uvm/asyncf_down_transaction.sv", "left_context": "`ifndef ASYNCF_DOWN_TRANSACTION__SV\n`define ASYNCF_DOWN_TRANSACTION__SV\n\nclass asyncf_down_transaction extends uvm_sequence_item;\n\n rand bit rinc;\n\n `uvm_object_utils_begin(asyncf_down_transaction)\n `uvm_field_int(rinc, UVM_ALL_ON)\n `uvm_object_utils_end\n\n", "right_context": " super.new();\n endfunction\n\nendclass\n`endif\n", "groundtruth": " function new(string name = \"asyncf_down_transaction\");\n", "crossfile_context": ""} {"task_id": "axi-crossbar", "path": "axi-crossbar/rtl/orig.axicb_round_robin_core.sv", "left_context": "// distributed under the mit license\n// https://opensource.org/licenses/mit-license.php\n\n`timescale 1 ns / 1 ps\n`default_nettype none\n\n///////////////////////////////////////////////////////////////////////////////\n//\n// Non-blocking round robin arbiter:\n//\n// - if all requesters are enabled, will grant the access from LSB to MSB,\n// thus from req 0 to req 3 and then restart from 0\n//\n// req mask grant next-mask\n//\n// 1111 1111 0001 1110\n// 1111 1110 0010 1100\n// 1111 1100 0100 1000\n// 1111 1000 1000 1111\n// 1111 1111 0001 1110\n// ...\n//\n// - if the next allowed is not active, pass to the next+2\n//\n// req mask grant next-mask\n//\n// 1101 1111 0001 1110\n// 1101 1110 0100 1000\n// 1101 1000 1000 1111\n// 1101 1111 0001 1110\n// 1111 1110 0010 1100\n// 1111 1100 0100 1000\n// ...\n//\n// - if a lonely request doesn't match a mask, pass anyway and reboot the\n// mask if no next req index is active\n//\n// req mask grant next-mask\n//\n// 0011 1111 0001 1110\n// 0011 1110 0010 1100\n// 0011 1100 0001 1110\n// 0111 1110 0010 1100\n// 0111 1100 0100 1000\n// ...\n//\n// - to balance granting, masters can be prioritzed (from 0 to 3); an\n// activated highest priority layer prevent computation of lowest\n// priority layers.\n//\n// (here, priority 2 for req 2, 0 for others)\n//\n// req mask grant next-mask (p2) next-mask (p0)\n//\n// 1111 1111 0100 1000 1111\n// 1011 1111 0001 1100 1110\n// 1011 1110 0010 1100 1100\n// 1111 1000 0100 1111 1100\n// 1011 1100 1000 1111 1111\n// ...\n//\n///////////////////////////////////////////////////////////////////////////////\n\nmodule axicb_round_robin_core\n\n #(\n // Number of requesters\n parameter REQ_NB = 4\n )(\n input wire aclk,\n input wire aresetn,\n input wire srst,\n input wire en,\n input wire [REQ_NB -1:0] req,\n output logic [REQ_NB -1:0] grant\n );\n\n logic [REQ_NB -1:0] mask;\n logic [REQ_NB -1:0] masked;\n logic [REQ_NB -1:0] grant_r;\n logic [REQ_NB -1:0] grant_c;\n\n\n ///////////////////////////////////////////////////////////////////////////\n // Compute the requester granted based on mask state\n ///////////////////////////////////////////////////////////////////////////\n\n generate\n if (REQ_NB==4) begin : GRANT_4\n\n always @ (*) begin\n\n // 1. Applies the mask and init the granted output\n masked = mask & req;\n\n // 2. Zeroes the grants once found a first activated one\n\n // 2.1 handles first the reqs which fall into the mask\n if (|masked) begin\n if (masked[0]) grant_c = 4'b0001;\n else if (masked[1]) grant_c = 4'b0010;\n else if (masked[2]) grant_c = 4'b0100;\n else if (masked[3]) grant_c = 4'b1000;\n else grant_c = 4'b0000;\n\n // 2.2 if the mask doesn't match the reqs, uses the unmasked ones\n end else begin\n if (req[0]) grant_c = 4'b0001;\n else if (req[1]) grant_c = 4'b0010;\n else if (req[2]) grant_c = 4'b0100;\n else if (req[3]) grant_c = 4'b1000;\n else grant_c = 4'b0000;\n end\n end\n\n end else if (REQ_NB==8) begin : GRANT_8\n\n always @ (*) begin\n\n // 1. Applies the mask and init the granted output\n masked = mask & req;\n\n // 2. Zeroes the grants once found a first activated one\n\n // 2.1 handles first the reqs which fall into the mask\n if (|masked) begin\n if (masked[0]) grant_c = 8'b00000001;\n else if (masked[1]) grant_c = 8'b00000010;\n else if (masked[2]) grant_c = 8'b00000100;\n else if (masked[3]) grant_c = 8'b00001000;\n else if (masked[4]) grant_c = 8'b00010000;\n else if (masked[5]) grant_c = 8'b00100000;\n else if (masked[6]) grant_c = 8'b01000000;\n else if (masked[7]) grant_c = 8'b10000000;\n else grant_c = 8'b00000000;\n\n // 2.2 if the mask doesn't match the reqs, uses the unmasked ones\n end else begin\n if (req[0]) grant_c = 8'b00000001;\n else if (req[1]) grant_c = 8'b00000010;\n else if (req[2]) grant_c = 8'b00000100;\n else if (req[3]) grant_c = 8'b00001000;\n else if (req[4]) grant_c = 8'b00010000;\n else if (req[5]) grant_c = 8'b00100000;\n else if (req[6]) grant_c = 8'b01000000;\n else if (req[7]) grant_c = 8'b10000000;\n else grant_c = 8'b00000000;\n end\n end\n\n end\n\n endgenerate\n\n\n always @ (posedge aclk or negedge aresetn) begin\n if (!aresetn) begin\n grant_r <= '0;\n end else if (srst) begin\n grant_r <= '0;\n end else begin\n if (en) begin\n grant_r <= grant_c;\n end\n end\n end\n\n always @ (*) begin\n if (en)\n grant = grant_c;\n else\n grant = grant_r;\n end\n\n ///////////////////////////////////////////////////////////////////////////\n // Generate the next mask\n ///////////////////////////////////////////////////////////////////////////\n\n generate\n if (REQ_NB==4) begin : REQ_4\n\n always @ (posedge aclk or negedge aresetn) begin\n\n if (!aresetn) begin\n mask <= '0;\n end else if (srst) begin\n mask <= '0;\n end else begin\n if (en && |grant) begin\n if (grant[0]) mask <= 4'b1110;\n else if (grant[1]) mask <= 4'b1100;\n else if (grant[2]) mask <= 4'b1000;\n else if (grant[3]) mask <= 4'b1111;\n end\n end\n", "right_context": " mask <= '0;\n end else if (srst) begin\n mask <= '0;\n end else begin\n if (en && |grant) begin\n if (grant[0]) mask <= 8'b11111110;\n else if (grant[1]) mask <= 8'b11111100;\n else if (grant[2]) mask <= 8'b11111000;\n else if (grant[3]) mask <= 8'b11110000;\n else if (grant[4]) mask <= 8'b11100000;\n else if (grant[5]) mask <= 8'b11000000;\n else if (grant[6]) mask <= 8'b10000000;\n else mask <= 8'b11111111;\n\n end\n end\n end\n\n end\n endgenerate\n\nendmodule\n\n`resetall\n", "groundtruth": " end\n\n end else if (REQ_NB==8) begin : REQ_8\n\n", "crossfile_context": ""} {"task_id": "fpga-hash-table", "path": "fpga-hash-table/rtl/hash_table_pkg.sv", "left_context": "//-----------------------------------------------------------------------------\n// Project : fpga-hash-table\n//-----------------------------------------------------------------------------\n// Author : Ivan Shevchuk (github/johan92)\n//-----------------------------------------------------------------------------\n\npackage hash_table;\n \n parameter KEY_WIDTH = 32;\n parameter VALUE_WIDTH = 16;\n parameter BUCKET_WIDTH = 8;\n parameter HASH_TYPE = \"dummy\";\n parameter TABLE_ADDR_WIDTH = 10;\n parameter HEAD_PTR_WIDTH = TABLE_ADDR_WIDTH;\n\n typedef enum logic [1:0] {\n OP_SEARCH,\n OP_INSERT,\n OP_DELETE\n } ht_opcode_t;\n\n typedef enum int unsigned {\n SEARCH_FOUND,\n SEARCH_NOT_SUCCESS_NO_ENTRY,\n\n INSERT_SUCCESS,\n INSERT_SUCCESS_SAME_KEY, \n INSERT_NOT_SUCCESS_TABLE_IS_FULL,\n\n DELETE_SUCCESS,\n DELETE_NOT_SUCCESS_NO_ENTRY\n } ht_rescode_t;\n \n typedef enum int unsigned {\n READ_NO_HEAD,\n KEY_MATCH,\n KEY_NO_MATCH_HAVE_NEXT_PTR,\n GOT_TAIL\n } ht_data_table_state_t;\n \n typedef enum int unsigned {\n NO_CHAIN,\n\n IN_HEAD,\n IN_MIDDLE,\n IN_TAIL,\n\n IN_TAIL_NO_MATCH\n } ht_chain_state_t;\n\n typedef struct packed {\n logic [HEAD_PTR_WIDTH-1:0] ptr;\n logic ptr_val;\n } head_ram_data_t;\n\n typedef struct packed {\n logic [KEY_WIDTH-1:0] key;\n logic [VALUE_WIDTH-1:0] value;\n logic [HEAD_PTR_WIDTH-1:0] next_ptr;\n logic next_ptr_val;\n } ram_data_t; \n \n typedef struct packed {\n logic [KEY_WIDTH-1:0] key;\n logic [VALUE_WIDTH-1:0] value;\n ht_opcode_t opcode;\n } ht_command_t;\n \n // pdata - data to pipeline/proccessing\n typedef struct packed {\n ht_command_t cmd;\n\n logic [BUCKET_WIDTH-1:0] bucket;\n\n logic [HEAD_PTR_WIDTH-1:0] head_ptr;\n logic head_ptr_val;\n } ht_pdata_t;\n\n typedef struct packed {\n ht_command_t cmd;\n ht_rescode_t rescode;\n \n logic [BUCKET_WIDTH-1:0] bucket;\n\n // valid only for opcode = OP_SEARCH\n logic [VALUE_WIDTH-1:0] found_value; \n \n // only for verification\n ht_chain_state_t chain_state;\n } ht_result_t;\n\n function string pdata2str( input ht_pdata_t pdata );\n string s;\n\n $sformat( s, \"opcode = %s key = 0x%x value = 0x%x head_ptr = 0x%x head_ptr_val = 0x%x\", \n pdata.cmd.opcode, pdata.cmd.key, pdata.cmd.value, pdata.head_ptr, pdata.head_ptr_val );\n \n return s;\n endfunction\n\n function string ram_data2str( input ram_data_t data );\n string s;\n\n $sformat( s, \"key = 0x%x value = 0x%x next_ptr = 0x%x next_ptr_val = 0x%x\",\n data.key, data.value, data.next_ptr, data.next_ptr_val );\n\n return s;\n endfunction\n\n function string result2str( input ht_result_t result );\n string s;\n case( result.cmd.opcode )\n OP_SEARCH:\n $sformat( s, \"key = 0x%x value = 0x%x rescode = %s chain_state = %s\", \n", "right_context": " OP_INSERT, OP_DELETE:\n $sformat( s, \"key = 0x%x value = 0x%x rescode = %s chain_state = %s\", \n result.cmd.key, result.cmd.value, result.rescode, result.chain_state );\n endcase\n \n return s;\n endfunction\n\nendpackage\n", "groundtruth": " result.cmd.key, result.found_value, result.rescode, result.chain_state );\n", "crossfile_context": ""} {"task_id": "riscv-dbg", "path": "riscv-dbg/src/dmi_test.sv", "left_context": "// Copyright 2021 ETH Zurich and University of Bologna.\n// Solderpad Hardware License, Version 0.51, see LICENSE for details.\n// SPDX-License-Identifier: SHL-0.51\n\n// Florian Zaruba \n\n/// A set of testbench utilities for the DMI interfaces.\npackage dmi_test;\n\n import dm::*;\n\n class req_t #(\n parameter int AW = 7\n );\n rand logic [AW-1:0] addr;\n rand dtm_op_e op;\n rand logic [31:0] data;\n\n /// Compare objects of same type.\n function do_compare(req_t rhs);\n return addr == rhs.addr &\n op == rhs.op &\n data == rhs.data;\n endfunction\n\n endclass\n\n class rsp_t;\n rand logic [31:0] data;\n rand logic [1:0] resp;\n\n /// Compare objects of same type.\n function do_compare(rsp_t rhs);\n return data == rhs.data &\n resp == rhs.resp;\n endfunction\n\n endclass\n\n /// A driver for the DMI interface.\n class dmi_driver #(\n parameter int AW = -1,\n parameter time TA = 0 , // stimuli application time\n parameter time TT = 0 // stimuli test time\n );\n virtual DMI_BUS_DV #(\n .ADDR_WIDTH(AW)\n ) bus;\n\n function new(\n virtual DMI_BUS_DV #(\n .ADDR_WIDTH(AW)\n ) bus\n );\n this.bus = bus;\n endfunction\n\n task reset_master;\n bus.q_addr <= '0;\n bus.q_op <= DTM_NOP;\n bus.q_data <= '0;\n bus.q_valid <= '0;\n bus.p_ready <= '0;\n endtask\n\n task reset_slave;\n bus.q_ready <= '0;\n bus.p_data <= '0;\n bus.p_resp <= '0;\n bus.p_valid <= '0;\n endtask\n\n task cycle_start;\n #TT;\n endtask\n\n task cycle_end;\n @(posedge bus.clk_i);\n endtask\n\n /// Send a request.\n task send_req (input req_t req);\n bus.q_addr <= #TA req.addr;\n bus.q_op <= #TA req.op;\n bus.q_data <= #TA req.data;\n bus.q_valid <= #TA 1;\n cycle_start();\n", "right_context": " cycle_end();\n bus.q_addr <= #TA '0;\n bus.q_op <= #TA DTM_NOP;\n bus.q_data <= #TA '0;\n bus.q_valid <= #TA 0;\n endtask\n\n /// Send a response.\n task send_rsp (input rsp_t rsp);\n bus.p_data <= #TA rsp.data;\n bus.p_resp <= #TA rsp.resp;\n bus.p_valid <= #TA 1;\n cycle_start();\n while (bus.p_ready != 1) begin cycle_end(); cycle_start(); end\n cycle_end();\n bus.p_data <= #TA '0;\n bus.p_resp <= #TA '0;\n bus.p_valid <= #TA 0;\n endtask\n\n /// Receive a request.\n task recv_req (output req_t req);\n bus.q_ready <= #TA 1;\n cycle_start();\n while (bus.q_valid != 1) begin cycle_end(); cycle_start(); end\n req = new;\n req.addr = bus.q_addr;\n req.op = bus.q_op;\n req.data = bus.q_data;\n cycle_end();\n bus.q_ready <= #TA 0;\n endtask\n\n /// Receive a response.\n task recv_rsp (output rsp_t rsp);\n bus.p_ready <= #TA 1;\n cycle_start();\n while (bus.p_valid != 1) begin cycle_end(); cycle_start(); end\n rsp = new;\n rsp.data = bus.p_data;\n rsp.resp = bus.p_resp;\n cycle_end();\n bus.p_ready <= #TA 0;\n endtask\n\n /// Monitor request.\n task mon_req (output req_t req);\n cycle_start();\n while (!(bus.q_valid && bus.q_ready)) begin cycle_end(); cycle_start(); end\n req = new;\n req.addr = bus.q_addr;\n req.op = bus.q_op;\n req.data = bus.q_data;\n cycle_end();\n endtask\n\n /// Monitor response.\n task mon_rsp (output rsp_t rsp);\n cycle_start();\n while (!(bus.p_valid && bus.p_ready)) begin cycle_end(); cycle_start(); end\n rsp = new;\n rsp.data = bus.p_data;\n rsp.resp = bus.p_resp;\n cycle_end();\n endtask\n\n endclass\n\n // Super class for random dmi drivers.\n virtual class rand_dmi #(\n // dmi interface parameters\n parameter int AW = 32,\n // Stimuli application and test time\n parameter time TA = 0ps,\n parameter time TT = 0ps\n );\n\n typedef dmi_test::dmi_driver #(\n // dmi bus interface parameters;\n .AW ( AW ),\n // Stimuli application and test time\n .TA ( TA ),\n .TT ( TT )\n ) dmi_driver_t;\n\n dmi_driver_t drv;\n\n function new(virtual DMI_BUS_DV #( .ADDR_WIDTH (AW)) bus);\n this.drv = new (bus);\n endfunction\n\n task automatic rand_wait(input int unsigned min, input int unsigned max);\n int unsigned rand_success, cycles;\n rand_success = std::randomize(cycles) with {\n cycles >= min;\n cycles <= max;\n // Weigh the distribution so that the minimum cycle time is the common\n // case.\n cycles dist {min := 10, [min+1:max] := 1};\n };\n assert (rand_success) else $error(\"Failed to randomize wait cycles!\");\n repeat (cycles) @(posedge this.drv.bus.clk_i);\n endtask\n\n endclass\n\n /// Generate random requests as a master device.\n class rand_dmi_master #(\n // dmi interface parameters\n parameter int AW = 32,\n // Stimuli application and test time\n parameter time TA = 0ps,\n parameter time TT = 0ps,\n parameter int unsigned REQ_MIN_WAIT_CYCLES = 1,\n parameter int unsigned REQ_MAX_WAIT_CYCLES = 20,\n parameter int unsigned RSP_MIN_WAIT_CYCLES = 1,\n parameter int unsigned RSP_MAX_WAIT_CYCLES = 20\n ) extends rand_dmi #(.AW(AW), .TA(TA), .TT(TT));\n\n int unsigned cnt = 0;\n bit req_done = 0;\n\n /// Reset the driver.\n task reset();\n drv.reset_master();\n endtask\n\n /// Constructor.\n function new(virtual DMI_BUS_DV #( .ADDR_WIDTH (AW)) bus);\n super.new(bus);\n endfunction\n\n task run(input int n);\n fork\n send_requests(n);\n recv_response();\n join\n endtask\n\n /// Send random requests.\n task send_requests (input int n);\n automatic req_t r = new;\n\n repeat (n) begin\n this.cnt++;\n assert(r.randomize());\n rand_wait(REQ_MIN_WAIT_CYCLES, REQ_MAX_WAIT_CYCLES);\n this.drv.send_req(r);\n end\n this.req_done = 1;\n endtask\n\n /// Receive random responses.\n task recv_response;\n while (!this.req_done || this.cnt > 0) begin\n automatic rsp_t rsp;\n this.cnt--;\n rand_wait(RSP_MIN_WAIT_CYCLES, RSP_MAX_WAIT_CYCLES);\n this.drv.recv_rsp(rsp);\n end\n endtask\n endclass\n\n class rand_dmi_slave #(\n // dmi interface parameters\n parameter int AW = 32,\n // Stimuli application and test time\n parameter time TA = 0ps,\n parameter time TT = 0ps,\n parameter int unsigned REQ_MIN_WAIT_CYCLES = 0,\n parameter int unsigned REQ_MAX_WAIT_CYCLES = 10,\n parameter int unsigned RSP_MIN_WAIT_CYCLES = 0,\n parameter int unsigned RSP_MAX_WAIT_CYCLES = 10\n ) extends rand_dmi #(.AW(AW), .TA(TA), .TT(TT));\n\n mailbox req_mbx = new();\n\n /// Reset the driver.\n task reset();\n drv.reset_slave();\n endtask\n\n task run();\n fork\n recv_requests();\n send_responses();\n join\n endtask\n\n /// Constructor.\n function new(virtual DMI_BUS_DV #( .ADDR_WIDTH (AW)) bus);\n super.new(bus);\n endfunction\n\n task recv_requests();\n forever begin\n automatic req_t req;\n rand_wait(REQ_MIN_WAIT_CYCLES, REQ_MAX_WAIT_CYCLES);\n this.drv.recv_req(req);\n req_mbx.put(req);\n end\n endtask\n\n task send_responses();\n automatic rsp_t rsp = new;\n automatic req_t req;\n forever begin\n req_mbx.get(req);\n assert(rsp.randomize());\n @(posedge this.drv.bus.clk_i);\n rand_wait(RSP_MIN_WAIT_CYCLES, RSP_MAX_WAIT_CYCLES);\n this.drv.send_rsp(rsp);\n end\n endtask\n endclass\n\n class dmi_monitor #(\n // dmi interface parameters\n parameter int AW = 32,\n // Stimuli application and test time\n parameter time TA = 0ps,\n parameter time TT = 0ps\n ) extends rand_dmi #(.AW(AW), .TA(TA), .TT(TT));\n\n mailbox req_mbx = new, rsp_mbx = new;\n\n /// Constructor.\n function new(virtual DMI_BUS_DV #( .ADDR_WIDTH (AW)) bus);\n super.new(bus);\n endfunction\n\n // dmi Monitor.\n task monitor;\n fork\n forever begin\n automatic dmi_test::req_t req;\n this.drv.mon_req(req);\n req_mbx.put(req);\n end\n forever begin\n automatic dmi_test::rsp_t rsp;\n this.drv.mon_rsp(rsp);\n rsp_mbx.put(rsp);\n end\n join\n endtask\n endclass\n\nendpackage", "groundtruth": " while (bus.q_ready != 1) begin cycle_end(); cycle_start(); end\n", "crossfile_context": ""} {"task_id": "AMBA_APB_SRAM", "path": "AMBA_APB_SRAM/tb/test_lib/apb_mstr_test_lib/apb_reg_por_read_test.sv", "left_context": "///////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n// File Name: apb_reg_por_read_test.sv\n// Author: Farshad\n// Email: farshad112@gmail.com\n// Revision: 0.1\n// Description: power on reset test. Read the default value of the RAM after power on reset.\n////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n\nclass apb_reg_por_read_test extends apb_base_test;\n `uvm_component_utils(apb_reg_por_read_test)\n\n // constructor function\n function new(string name=\"apb_reg_por_read_test\", uvm_component parent=null);\n super.new(name, parent);\n endfunction: new\n \n // build_phase\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n endfunction: build_phase\n \n // connect_phase\n virtual function void connect_phase(uvm_phase phase);\n super.connect_phase(phase);\n endfunction: connect_phase\n \n // run_phase\n virtual task run_phase(uvm_phase phase);\n", "right_context": " phase.raise_objection(this);\n // read all memories after reset\n for(int i=0; i< `APB_SRAM_SIZE; i++) begin\n rd_nd_compare_mem(i, 0);\n end\n phase.drop_objection(this);\n endtask: run_phase\n \nendclass: apb_reg_por_read_test", "groundtruth": " super.run_phase(phase); \r\n", "crossfile_context": ""} {"task_id": "DDR5_PHY_WriteOperation", "path": "DDR5_PHY_WriteOperation/RTL/ddr5_phy_write_fsm.sv", "left_context": "/*****************************************************************************\n** Company: Si-Vision & FOE ASU\n** Author: AHMED MOSTAFA KAMAL , ADHAM HAZEM ALGENDI AND AHMED MOHAMED AMIN\n**\n** Create Date: 24/3/2022\n** Edited on : 21/4/2022\n** Module Name: asu_ddr5_write_fsm\n** Description: this file contains the FSM RTL, the design implementation\n** is based on IEEE standard (Std 802.15.4-2011)\n**\n**\n*****************************************************************************/\n\n`timescale 1ns / 1ps\n\n\n// Defining the module external interface (NAME ,input ports and output ports).\nmodule ddr5_phy_write_fsm\n # (parameter pDRAM_SIZE = 4 ) //DRAM size \n(\n //////input signals //////////// \n\t\t\t\t \n\t\t\t\t \n input\twire \t\t\t\tclk_i , // system phy clock\n\t\n \t\t\tinput \twire \t\t\t\trst_i , // system reset\n\t\t \n \t\t\tinput \twire \t\t\t\tenable_i , // system block enable\n\t\t\t\n \t\t\tinput \twire \t\t\twr_en_i , // write enable signal from freq ratio block \n \t\n\t\t\tinput \twire preamble_valid_i , // valid signal that indcates correct preamble pattern is sent on dqs signal \n\t\t\n\t\t\tinput \twire\t\t\t\tpreamble_done_i , // signal that indicates that whole preamble pattern is sent\n\t\t\n\t\t\tinput \twire\t\t\t\tpostamble_done_i , // signal that indicates that whole postamble pattern is sent on dqs bus\n\t\t\n\t\t\tinput \twire\t\t\t\tinteramble_done_i , // signal that indicates that whole interamble pattern is sent ondqs bus\n\t \n\t\t\tinput \twire\t\t\t\twrdata_crc_done_i , // signal that indicates that whole data is sent on DQ bus (MC crc support) \n\t\t\n\t\t\tinput \twire wrdata_done_i , // signal that indicates that whole data is sent on DQ bus (phy crc support)\n\n\t\t\tinput \twire data_burst_done_i , // signal that indicates data is sent on DQ bus (burst length = 8)\n\t\n\t\t\tinput \twire wrmask_done_i , // signal that indicates whole data is sent on DQ bus (data mask)\n\t\t \n\t\t\tinput \twire crc_generate_i , // indicates that phy will generate crc or not\n\t\t\n\t\t\tinput \twire interamble_i , // indicates that if there is interamble exist\n\t\n\t\t\tinput \twire\t[1: 0]\t\tpreamble_bits_i , // preamble bits result from shifting preamble pattern \n\t\t \n\t\t\tinput \twire [1:0] interamble_bits_i , // interamble bits result from shifting interamble pattern\n\t\t\t \n\t\t\tinput \twire [3:0] gap_i , // signal detect number of cycles at which write enable is low \n \n\t\t\tinput \twire [2*pDRAM_SIZE -1: 0]\twr_data_i , // input wrdata from freq ratio block\n\t\t\t \n\t\t\tinput \twire [(pDRAM_SIZE /4-1):0]\twr_datamask_i , // input data mask from freq ratio block\n\t\t \n\t\t\tinput \twire [2*pDRAM_SIZE -1: 0]\tcrc_code_i , // input crc data from crc block\n\n\t\t\tinput \twire [1:0] burstlength_i , // input burstlength from command block\n\t\t\t \n\t\t\t /////////output signals ////////////////\n\n\t\t\toutput reg data_state_o , // output signal indicates to write data states\n \t\t\n\t\t\toutput reg \t\t\t\tpreamble_state_o , // output signal indicates to preamble , postamble ,interamble states \n\t\t\n\t\t\toutput reg [2*pDRAM_SIZE -1: 0]\tcrc_data_o , // output data to crc block\n\t\t\n \t\t\toutput reg \t\t\t\tcrc_enable_o , // output enable to crc block\n\t\t\n\t\t\toutput reg [1:0]\t\t dqs_o , // output data strobe to DRAM\n\t\t\n \t\t\toutput reg [2*pDRAM_SIZE -1: 0] dq_o , // output data to DRAM\n\t\t\n\t\t\toutput reg \t\t\tdqs_valid_o , // output signal indicates that data strobe is sent or not\n\t\t\n\t\t\toutput reg \t\t\t\tdq_valid_o , // output signal indicates that data is sent or not\n\t\t\n\t\t\toutput reg [(pDRAM_SIZE /4-1):0] \tdm_o , // output data mask to DRAM\n\t\n\t\t\toutput reg interamble_valid_o // output signal indicates that interamble bits is sent ondqs bus\n\t\t\n\t\t\t\n\t\t\t \n \n);\n\n////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// internal signals and registers\n\n\n //state defintions\n typedef enum reg [2:0] { idle , preamble , wr_data_crc , wr_data , data_burst8 ,crc , postamble , interamble } state_t ;\n state_t current_state , next_state ;\n\nreg [1:0]\t\t\tdqs ;\nreg [2*pDRAM_SIZE -1 : 0] \tdq ;\nreg \t\t\t\tdqs_valid ;\nreg \t\t\t\tdq_valid ;\nreg [(pDRAM_SIZE /4-1):0] \tdm ; \n\n// state transition \t\t\nalways_ff @(posedge clk_i or negedge rst_i)\n begin\n\tif(!rst_i) // Asynchronous active low reset \n\t begin\n\t\tcurrent_state <= idle ;\n\t end\n \n\telse if (enable_i) // enable fsm \n\t begin\t\n\t current_state <= next_state ;\n\t end\n\t \n end\n \n////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// \n \n// next_state and output logic\nalways_comb \n begin\n case(current_state)\n idle : \t\tbegin \n dq = {(2*pDRAM_SIZE){1'b0}} ;\n\t\t dq_valid = 1'b0 ;\n\t\t\t dm = {(pDRAM_SIZE /4){1'b0}} ;\t\t\t\n\t\t\t\t\tdqs = 2'b00 ;\n\t\t\t\t\tinteramble_valid_o= 1'b0 ;\n\t\t\t\t\tdqs_valid = 1'b0 ;\t\n\t\t\t\t\tdata_state_o = 1'b0 ;\n\t\t\t\t\tpreamble_state_o = 1'b0 ;\n\t\t\t crc_data_o = {(2*pDRAM_SIZE){1'b0}} ;\n crc_enable_o = 1'b0 ; \n\t\t\t\t\t\n\t\t\t\t\tif(wr_en_i) \n\t\t\t\t\t next_state = preamble;\n\t\t\t\t\telse\n\t\t\t\t\t next_state = idle ;\t\t\t \n\t\t\t\tend\n\t\t\t\t\t\n\t\t\t\t\t// no operation in this state, when wr_en is high move to preamble state \n\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t \n preamble :\tbegin \n // preamble pattern is sent ondqs bus ,anddqs valid will be high when the correct pattern is sent \n dq = {(2*pDRAM_SIZE){1'b0}};\n\t\t dq_valid = 1'b0 ;\n\t\t\t dm = {(pDRAM_SIZE /4){1'b0}} ;\t\t\t\t \n \t dqs = preamble_bits_i ;\n\t\t\t\t interamble_valid_o= 1'b0 ;\n\t\t\t dqs_valid = preamble_valid_i ;\n\t\t\t\t data_state_o = 1'b0 ;\n\t\t\t\t preamble_state_o = 1'b1 ;\n\t\t\t \tcrc_data_o = {(2*pDRAM_SIZE){1'b0}} ;\n crc_enable_o = 1'b0 ;\n \t\t\t\n\t\t\t\t\t // when preamble is sent ondqs bus and check crc_generate_i if low then move to wr_data_crc or if crc_generate_i is high then move to wr_data \n\t\t\t\t\n if ( preamble_done_i && !crc_generate_i ) \n\t\t\t\t\t next_state = wr_data_crc ;\t\t\t\t\t \n\t\t\t\t\telse if ( preamble_done_i && crc_generate_i )\n\t\t\t\t\t next_state = wr_data ;\t\t \n\t\t\t\t\telse \t\t\t\t\t \n\t\t\t\t\t next_state = preamble ;\t\t\t\t \n\t\t\t\tend\n\t\t\t \n\t\t\t\t\n\t\t\t\t\n\t\t\t\n wr_data_crc : begin // (MC crc support or data mask) \n // wr_data from MC will be sent on dq bus with dq_valid ,dqS will be phy _clock,wrdata mask is sent on dm bus\n dq = wr_data_i ;\n\t\t dq_valid = 1'b1 ;\n\t\t\t dm = wr_datamask_i ;\t\t\t \n\t\t\t\t\tdqs = 2'b10 ;\n\t\t\t\t interamble_valid_o= 1'b0 ;\n\t\t\t dqs_valid = 1'b1 ;\t\n\t\t\t\t\tdata_state_o = 1'b1 ;\n\t\t\t\t\tpreamble_state_o = 1'b0 ;\n\t\t\t crc_data_o = {(2*pDRAM_SIZE){1'b0}} ;\n crc_enable_o = 1'b0 ;\n\t\t\t \n\t\t\t\t // when data is sent on dq bus and check i_interamble if high move to interamble state ,if low move to postamble\n\t\t\t\t\tif( !interamble_i && (wrdata_crc_done_i|| wrmask_done_i) ) \n\t\t\t\t\t next_state = postamble ; \n\t\t\t\t\telse if ( interamble_i &&(wrdata_crc_done_i|| wrmask_done_i) )\n\t\t\t\t\t next_state = interamble ; \t\t\t\t\t\n\t\t\t\t\telse \n\t\t\t\t\t next_state = wr_data_crc;\t \n\t\t\t\t end\n\t\t\t\t\t\n\t\t\t\t\t// when data is sent on dq bus and check interamble_i if high move to interamble state ,if low move to postamble\n\t\t\t\t\t\n \t\t\t\t\t\n\t\t\t\t\t\n\twr_data :\tbegin // (phy crc support)\n\t // data will be sent on dq bus and to crc block to generate crc anddqs will be phy _clock\n\t dq = wr_data_i ; \n\t\t dq_valid = 1'b1 ;\n\t\t\t dm = {(pDRAM_SIZE /4){1'b0}} ;\t\t\t \n\t\t\t dqs = 2'b10 ;\n\t\t\t\t interamble_valid_o= 1'b0 ;\n\t\t\t dqs_valid = 1'b1 ;\t\n crc_data_o = wr_data_i ;\n crc_enable_o = 1'b1 ;\t\n\t\t\t\t data_state_o = 1'b1 ;\n\t\t\t\t preamble_state_o = 1'b0 ;\n\t\t\t\t\n // when data is sent on dq bus and checkburstlength_i if burstlength_i = 8 ,move to data_burst8 state\n\t\t\t\t\tif(burstlength_i == 2'b01 && data_burst_done_i )\n\t\t\t\t\t next_state = data_burst8 ;\n\t\t\t\t\telse if (wrdata_done_i)\n\t\t\t\t\t next_state = crc ; \n\t\t\t\t\telse \n\t\t\t\t\t next_state = wr_data;\t \n\t\t\t\tend\n\t\t\t \n\n\t\t\t\t \n\t\t\t\t\t\n\tdata_burst8 : begin \t// (i_burstlength = 8)\n\t\n\t // rest of wr_data will be completed with ones and sent it on dq bus and crc block \n\t\t dq_valid = 1'b1 ; //(burstlength =8)\n\t\t\t\t dq = {(2*pDRAM_SIZE){1'b1}} ; // rest of wr_data will be completed with ones and sent it on dq bus and crc block\n\t\t\t dm = {(pDRAM_SIZE /4){1'b0}} ;\t\t\t \n\t\t\t\t\tdqs = 2'b10 ;\n\t\t\t\t\tinteramble_valid_o= 1'b0 ;\n\t\t\t\t\tdqs_valid = 1'b1 ;\t\n\t\t\t\t crc_data_o = {(2*pDRAM_SIZE){1'b1}} ;\n crc_enable_o = 1'b1 ;\n\t\t\t\t\tdata_state_o = 1'b1 ;\n\t\t\t\t\tpreamble_state_o= 1'b0 ;\n\t\t\t\t\t\n\t\t\t\t\t// when rest of wr_data is sent on dq bus move to crc state\n\t\t\t\t\tif(wrdata_done_i )\n\t\t\t\t\t next_state = crc ;\n\t\t\t\t\telse \n\t\t\t\t\t next_state = data_burst8;\t \n\t\t\t\t end\n\t\t\t\t \n\t\t\t\t \n\t\t\t\t \n\tcrc : begin \t// (phy crc support)\n\t // crc code is taken from crc block and sent it after data on dq bus\n // sends interamble_valid to shift register to shift interamble pattern\n\t dq = crc_code_i ; \t\t\t\t \n\t\t dq_valid = 1'b1 ;\n\t\t\t dm = {(pDRAM_SIZE /4){1'b0}} ;\t\t\t \n\t\t\t dqs = 2'b10 ;\n\t\t\t\t interamble_valid_o = 1'b1 ; \n\t\t\t dqs_valid = 1'b1 ;\t\n\t\t\t\t crc_data_o = {(2*pDRAM_SIZE){1'b0}} ;\n\t\t\t\t crc_enable_o = 1'b1 ;\n\t\t\t\t data_state_o = 1'b0 ;\n\t\t\t \tpreamble_state_o = 1'b0 ;\n\t\n // check interamble_i if high move to interamble state ,if not move to postamble state\t\n\t\t\t\t\tif (gap_i ==3'b001 )\n", "right_context": "\t\t\t\tend\t\t\n\t\t\t\t \t\n\t\t\t\t\t\n\t\t\t\t\t\n postamble : begin \n // postaamble pattern is sent ondqs bus \n dq = {(2*pDRAM_SIZE){1'b0}} ; \n\t\t dq_valid = 1'b0 ;\n\t\t\t dm = {(pDRAM_SIZE /4){1'b0}} ;\t\t\t \n\t\t\t dqs = 2'b00 ;\n\t\t\t\t interamble_valid_o= 1'b1 ;\n\t\t\t dqs_valid = 1'b1 ;\t\n\t\t\t\t crc_data_o = {(2*pDRAM_SIZE){1'b0}} ;\n crc_enable_o = 1'b0 ;\t\n\t\t\t\t data_state_o = 1'b0 ;\n\t\t\t\t preamble_state_o = 1'b0 ;\n\t\t\t\t\t \n\t\t\t\t\t // when postamble pattern is sent ondqs bus , check wr_en_i if high move to preamble state ,if low move to idle\n\t\t\t\t\tif (postamble_done_i && !wr_en_i)\n\t\t\t\t\t next_state =idle ;\n\t\t\t\t\telse if ( postamble_done_i && wr_en_i )\n\t\t\t\t\t next_state = preamble ;\t\t\t\t\t\n\t\t\t\t\telse \n\t\t\t\t\t next_state = postamble;\t\n\t\t\t\tend\n \n\t\t\t\t\t\n\t\t\t\t\t\n interamble :begin \n // interamble pattern is sent ondqs bus\n dq = {(2*pDRAM_SIZE){1'b0}} ;\n\t\t dq_valid = 1'b0 ;\n\t\t\t dm = {(pDRAM_SIZE /4){1'b0}} ;\n\t\t\t dqs = interamble_bits_i ;\n\t\t\t\t interamble_valid_o= 1'b1 ;\n\t\t\t dqs_valid = 1'b1 ;\n\t\t\t\t\tcrc_data_o = {(2*pDRAM_SIZE){1'b0}} ; \n\t\t\t\t\tdata_state_o = 1'b0 ;\n\t\t\t\t\tpreamble_state_o = 1'b0 ;\n\t\t\t\t\tcrc_enable_o = 1'b0 ;\n\t\t\t\t\t // when interamble pattern is ent ondqs ,check crc_generate_i if low then move to wr_data_crc , if crc_generate_i is high then move to wr_data \n\t\t\t\n\t\t\t\t\tif (interamble_done_i&&crc_generate_i)\n\t\t\t\t\t next_state = wr_data ;\t\t\t\t\t\n\t\t\t\t\telse if (interamble_done_i&&!crc_generate_i)\t\t\t\t\t\n\t\t\t\t\t next_state = wr_data_crc ;\t\t\t\t \n\t\t\t\t\telse \t\t\t\t\t\n\t\t\t\t\t next_state = interamble;\t\t\t\t\n\n\t\t\t\tend\n \n\t\t \n default : begin\t\t\t \n\t\t\t\t\tdq_valid = 1'b0 ;\n\t\t\t\t\tdm = {(pDRAM_SIZE /4){1'b0}} ;\n\t\t\t\t\tdqs = 2'b00; \n\t\t\t\t\tinteramble_valid_o= 1'b0 ;\n\t\t\t\t\tdqs_valid = 1'b0 ;\t\n\t\t\t\t\tcrc_enable_o = 1'b0 ;\t\t\t\t\n\t\t\t\t\tnext_state = idle ; \t\t \n end\n endcase\n \n end\t\n\n////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// \n\n// registered output \t\t\nalways_ff @(posedge clk_i or negedge rst_i)\n begin\n\tif(!rst_i) // Asynchronous active low reset \n\t begin\n\t\tdq_o <= {(2*pDRAM_SIZE){1'b0}} ;\n\t\tdqs_o <= 2'b00 ;\n\t\tdq_valid_o <= 1'b0;\n dqs_valid_o <=1'b0 ;\n \tdm_o <= \t{(pDRAM_SIZE /4){1'b0}} ;\n\t end\n \n\telse if (enable_i) // enable fsm \n\t begin\t\n\t dq_o <= dq ;\n\t\tdqs_o <=dqs ;\n\t\tdq_valid_o <= dq_valid ;\n dqs_valid_o <=dqs_valid ;\n \tdm_o <= dm;\n\t end\n end\n\t \n\nendmodule \n\n\n\n\n\n\n\n\n\n", "groundtruth": "\t\t\t\t\t next_state = wr_data ; \r\n\t\t\t\t\telse if (interamble_i)\r\n\t\t\t\t\t next_state = interamble ;\r\n", "crossfile_context": ""} {"task_id": "axi4_vip", "path": "axi4_vip/axi_virtual_seqr.sv", "left_context": "// ###########################################################################\n//\n// Licensed to the Apache Software Foundation (ASF) under one\n// or more contributor license agreements. See the NOTICE file\n// distributed with this work for additional information\n// regarding copyright ownership. The ASF licenses this file\n// to you under the Apache License, Version 2.0 (the\n// \"License\"); you may not use this file except in compliance\n// with the License. You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing,\n// software distributed under the License is distributed on an\n// \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n// KIND, either express or implied. See the License for the\n// specific language governing permissions and limitations\n// under the License.\n// \n// ###########################################################################\n\nclass axi_virtual_seqr extends uvm_sequencer #(axi_seq_item);\n\n\taxi_master_sequencer mstr_vseqr_h;\n\taxi_slave_sequencer slv_vseqr_h;\n\t\n//Fatory Registration\n\t`uvm_component_utils(axi_virtual_seqr)\n\t\n//Constructor\t\n", "right_context": " \tsuper.new(name, parent);\n\tendfunction\n\t\n\tfunction void build_phase (uvm_phase phase);\t\n\t\tsuper.build_phase(phase);\n\tendfunction\n\t\nendclass", "groundtruth": "\tfunction new(string name = \"axi_env\", uvm_component parent);\r\n", "crossfile_context": ""} {"task_id": "davos", "path": "davos/hdl/ultraplus/rx_interface.v", "left_context": "/*******************************************************************************\n** ? Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.\n** This file contains confidential and proprietary information of Xilinx, Inc. and\n** is protected under U.S. and international copyright and other intellectual property laww\nw\ns.\n*******************************************************************************\n** ____ ____\n** / /\\/ /\n** /___/ \\ / Vendor: Xilinx\n** \\ \\ \\/\n** \\ \\\n** / /\n** /___/ /\\\n** \\ \\ / \\ Virtex-7 XT Connectivity Domain Targeted Reference Design\n** \\___\\/\\___\\\n**\n** Device: xc7k325t-ffg900-2\n** Version: 1.0\n**\n*******************************************************************************\n**\n*******************************************************************************/\n\n/******************************************************************************\nThe module performs address filtering on the receive. The receive logic FSM detects\na good frame and makes it available to the packet FIFO interface. Two state machines\nare implemented: one FSM covers the write data from XGEMAC interface and another FSM controls \nthe read logic to packet FIFO\n*******************************************************************************/\n\n`timescale 1ps / 1ps\n\nmodule rx_interface #(\n parameter FIFO_CNT_WIDTH = 11\n)\n(\n input [63:0] axi_str_tdata_from_xgmac,\n input [7:0] axi_str_tkeep_from_xgmac,\n input axi_str_tvalid_from_xgmac,\n input axi_str_tlast_from_xgmac,\n input axi_str_tuser_from_xgmac,\n\n input axi_str_tready_from_fifo,\n\n output [63:0] axi_str_tdata_to_fifo, \n output [7:0] axi_str_tkeep_to_fifo, \n output axi_str_tvalid_to_fifo,\n output axi_str_tlast_to_fifo,\n output [15:0] rd_pkt_len,\n output reg rx_fifo_overflow = 1'b0,\n \n input [13:0] rx_statistics_vector,\n input rx_statistics_valid,\n\n output [FIFO_CNT_WIDTH-1:0] rd_data_count ,\n\n input user_clk,\n input reset\n\n);\n\n //Wire declaration\n //wire broadcast_detect;\n //wire [47:0] rx_mac_id_i;\n wire axis_rd_tlast;\n wire axis_rd_tvalid;\n wire [63:0] axis_rd_tdata;\n wire [7:0] axis_rd_tkeep;\n wire axis_wr_tlast;\n wire axis_wr_tvalid;\n wire [63:0] axis_wr_tdata;\n wire [7:0] axis_wr_tkeep;\n //wire da_match ;\n wire full;\n wire empty;\n wire valid_cmd;\n wire crc_pass;\n wire [15:0] cmd_out;\n wire axis_wr_tready;\n wire [FIFO_CNT_WIDTH-1:0] wr_data_count ;\n wire [FIFO_CNT_WIDTH-1:0] left_over_space_in_fifo; \n wire wr_reached_threshold;\n wire wr_reached_threshold_extend;\n //wire [47:0] mac_id_sync;\n //wire mac_id_valid_sync;\n //wire promiscuous_mode_en_sync;\n wire frame_len_ctr_valid;\n\n //Reg declaration\n reg [63:0] axi_str_tdata_from_xgmac_r ;\n reg [7:0] axi_str_tkeep_from_xgmac_r ;\n reg axi_str_tvalid_from_xgmac_r;\n reg axi_str_tlast_from_xgmac_r ;\n reg axi_str_tuser_from_xgmac_r ;\n reg force_tlast_to_fifo='d0 ;\n reg address_chk_en = 'd0;\n reg assert_rd='d0;\n reg [15:0] cmd_in = 'd0;\n reg wr_en=1'b0;\n reg rd_en=1'b0;\n reg axis_rd_tready='d0 ;\n reg axis_rd_tvalid_from_fsm=1'b0;\n reg [3:0] tkeep_decoded_value;\n// reg axi_str_tvalid_from_fsm=1'b0;\n reg [12:0] rd_pkt_len_count='d0;\n reg [13:0] rx_stats_vec_reg='d0;\n\n reg [3:0] frame_len_ctr;\n \nlocalparam\n //states for Write FSM\n IDLE_WR = 4'b0001,\n DA_DECODE = 4'b0010,\n BEGIN_WRITE = 4'b0100,\n DROP_FRAME = 4'b1000,\n \n //states for Read FSM\n IDLE_RD = 4'b0001,\n PREP_READ_1 = 4'b0010, \n PREP_READ_2 = 4'b0100, \n BEGIN_READ = 4'b1000;\n\nlocalparam THRESHOLD = 200;\nlocalparam THRESHOLD_EXT = 400;\n\n reg [3:0] state_wr = IDLE_WR;\n reg [3:0] state_rd = IDLE_RD;\n\n\n //Synchronize mac_id, promiscuous_mode_en and mac_id_valid with the destination clock\n /*synchronizer_simple #(.DATA_WIDTH (1)) sync_to_mac_clk_0\n (\n .data_in (promiscuous_mode_en),\n .new_clk (user_clk),\n .data_out (promiscuous_mode_en_sync)\n );\n\n synchronizer_simple #(.DATA_WIDTH (1)) sync_to_mac_clk_1\n (\n .data_in (mac_id_valid),\n .new_clk (user_clk),\n .data_out (mac_id_valid_sync)\n );\n\n synchronizer_simple #(.DATA_WIDTH (48)) sync_to_mac_clk_2\n (\n .data_in (mac_id),\n .new_clk (user_clk),\n .data_out (mac_id_sync)\n );*/\n \n //assign broadcast_detect = ((axi_str_tdata_from_xgmac_r[47:0]== {48{1'b1}}) && (address_chk_en == 1'b1))?1'b1:1'b0;\n \n //assign rx_mac_id_i = (address_chk_en == 1'b1)?axi_str_tdata_from_xgmac_r[47:0]:48'b0;\n\n //assign da_match = ((rx_mac_id_i == mac_id_sync) & mac_id_valid_sync)?1'b1:1'b0;\n \n //Add a pipelining stage for received data from xgemac interface.\n //This is necessary for FSM control logic\n always @(posedge user_clk)\n begin\n axi_str_tdata_from_xgmac_r <= axi_str_tdata_from_xgmac;\n axi_str_tkeep_from_xgmac_r <= axi_str_tkeep_from_xgmac;\n axi_str_tvalid_from_xgmac_r <= axi_str_tvalid_from_xgmac;\n axi_str_tlast_from_xgmac_r <= axi_str_tlast_from_xgmac;\n axi_str_tuser_from_xgmac_r <= axi_str_tuser_from_xgmac;\n end\n \n \n begin\n assign axis_wr_tvalid = (state_wr==DROP_FRAME) ? 1'b0 : \n (axi_str_tvalid_from_xgmac_r | (force_tlast_to_fifo & (state_wr == BEGIN_WRITE))); \n end\n\n assign axis_wr_tlast = (axi_str_tlast_from_xgmac_r | force_tlast_to_fifo); \n assign axis_wr_tkeep = axi_str_tkeep_from_xgmac_r; \n assign axis_wr_tdata = axi_str_tdata_from_xgmac_r;\n\n //Register Rx statistics vector to be used in the read FSM later\n //Rx statistics is valid only if rx_statistics_valid is asserted\n //from XGEMAC \n //- bits 18:5 in stats vector provide frame length including FCS, hence\n //subtract 4 bytes to get the frame length only.\n always @(posedge user_clk)\n begin\n if(rx_statistics_valid)\n rx_stats_vec_reg <= rx_statistics_vector[13:0] - 14'd4;\n end\n\n assign left_over_space_in_fifo = {1'b1,{(FIFO_CNT_WIDTH-1){1'b0}}} - wr_data_count[FIFO_CNT_WIDTH-1:0];\n\n assign wr_reached_threshold = (left_over_space_in_fifo < THRESHOLD)?1'b1:1'b0;\n assign wr_reached_threshold_extend = (left_over_space_in_fifo < THRESHOLD_EXT)?1'b1:1'b0;\n\n always @(posedge user_clk)\n begin\n if(force_tlast_to_fifo)\n force_tlast_to_fifo <= 1'b0;\n else if(wr_reached_threshold & !(axi_str_tlast_from_xgmac & axi_str_tvalid_from_xgmac))\n force_tlast_to_fifo <= 1'b1;\n end\n\n // Counter to count frame length when length is less than 64B\n // For frame length less than 64B, XGEMAC core reports length including the\n // padded characters. To overcome this situation, a separate counter is implemented\n always @(posedge user_clk)\n begin\n if (reset)\n frame_len_ctr <= 'd0;\n else if (axi_str_tlast_from_xgmac & axi_str_tvalid_from_xgmac)\n frame_len_ctr <= 'd0;\n else if (frame_len_ctr > 4'h8)\n frame_len_ctr <= frame_len_ctr;\n else if(axi_str_tvalid_from_xgmac)\n frame_len_ctr <= frame_len_ctr+1;\n end\n\n assign frame_len_ctr_valid = (frame_len_ctr != 0) & (frame_len_ctr < 8) & axi_str_tvalid_from_xgmac & axi_str_tlast_from_xgmac;\n\n // Decoder for TKEEP signal\n always @(axi_str_tkeep_from_xgmac)\n case(axi_str_tkeep_from_xgmac) \n 'h00 : tkeep_decoded_value <= 'd0;\n 'h01 : tkeep_decoded_value <= 'd1;\n 'h03 : tkeep_decoded_value <= 'd2;\n 'h07 : tkeep_decoded_value <= 'd3;\n 'h0F : tkeep_decoded_value <= 'd4;\n 'h1F : tkeep_decoded_value <= 'd5;\n 'h3F : tkeep_decoded_value <= 'd6;\n 'h7F : tkeep_decoded_value <= 'd7;\n 'hFF : tkeep_decoded_value <= 'd8;\n default : tkeep_decoded_value <= 'h00;\n endcase\n\n //Two FIFOs are implemented: one for XGEMAC data(data FIFO) and the other for controlling \n //read side command(command FIFO). \n //Write FSM: 6 states control the entire write operation\n //cmd_in is an input to the command FIFO and controls the read side command\n //Ethernet packet frame size is available from Rx statistics vector and is\n //made available to the read side through command FIFO\n //FSM states:\n //IDLE_WR : Wait in this state until valid is received from XGEMAC. If the \n // data FIFO is full or tready is de-asserted from FIFO interface\n // it drops the current frame from XGEMAC\n //DA_DECODE: Destination Address from XGEMAC is decoded in this state. If destination\n // address matches with MAC address or promiscuous mode is enabled\n // or broadcast is detected, next state is BEGIN_WRITE. Else the FSM transitions\n // to IDLE_WR state \n //BEGIN_WRITE: The FSM continues to write data into data FIFO until tlast from XGEMAC is hit.\n // FSM transitions to CHECK_ERROR state if tlast has arrived \n //DROP_FRAME: The FSM enters into this state if the data FIFO is full or tready from data FIFO is de-asserted\n // In this state, tvalid to FIFO is de-asserted\nalways @(posedge user_clk)\n begin\n if(reset)\n state_wr <= IDLE_WR;\n else\n begin\n case(state_wr)\n IDLE_WR : begin\n cmd_in <= 'b0;\n wr_en <= 1'b0;\n\n if(axi_str_tvalid_from_xgmac & (full | wr_reached_threshold))\n begin\n state_wr <= DROP_FRAME;\n end\n else if(axi_str_tvalid_from_xgmac)\n begin\n state_wr <= DA_DECODE;\n end\n else\n begin\n state_wr <= IDLE_WR;\n end\n end\n DA_DECODE : begin\n", "right_context": " ((frame_len_ctr << 3) + tkeep_decoded_value) : rx_stats_vec_reg;\n if(force_tlast_to_fifo) \n begin\n wr_en <= 1'b1; \n cmd_in[0] <= 1'b0;\n state_wr <= DROP_FRAME; \n end \n else if(axi_str_tlast_from_xgmac & axi_str_tvalid_from_xgmac)\n begin\n wr_en <= 1'b1; \n cmd_in[0] <= axi_str_tuser_from_xgmac;\n state_wr <= IDLE_WR; \n end\n else\n begin\n wr_en <= 1'b0; \n cmd_in[0] <= 1'b0;\n state_wr <= BEGIN_WRITE;\n end\n end\n DROP_FRAME : begin\n wr_en <= 1'b0; \n if(axi_str_tlast_from_xgmac_r & axi_str_tvalid_from_xgmac_r & !wr_reached_threshold_extend)\n\n begin\n //- signals a back 2 back packet\n if(axi_str_tvalid_from_xgmac)\n begin\n state_wr <= DA_DECODE;\n end\n else\n state_wr <= IDLE_WR;\n end\n else\n state_wr <= DROP_FRAME;\n end\n default : state_wr <= IDLE_WR;\n endcase\n end\n end\n \n assign valid_cmd = cmd_out[1]; \n assign crc_pass = ~cmd_out[0];\n assign rd_pkt_len = {2'b0,cmd_out[15:2]};\n \n //Read FSM reads out the data from data FIFO and present it to the packet FIFO interface\n //The read FSM starts reading data from the data FIFO as soon as it decodes a valid command\n //from the command FIFO. Various state transitions are basically controlled by the command FIFO\n //empty flag and tready assertion from packet FIFO interface \n //FSM states\n //IDLE_RD: The FSM stays in this state until command FIFO empty is de-asserted and tready from packet \n // FIFO interface is active low. \n //PREP_READ_1: This is an idle cycle, used basically to de-assert rd_en so that command FIFO is read only \n // once\n //PREP_READ_2: If the decoded command from command FIFO is valid and CRC detects no error for the frame\n // the FSM transitions to BEGIN_READ state. tready to FIFO is controlled by tready\n // from the packet FIFO interface. If CRC fails for a frame, the entire frame is dropped\n // by de-asserting tvalid to packet FIFO interface\n //BEGIN_READ: In this state, the FSM reads data until tlast from XGEMAC is encountered\n always @(posedge user_clk)\n begin\n if(reset)\n begin\n state_rd <= IDLE_RD;\n end\n else\n begin\n case(state_rd)\n IDLE_RD : begin\n if(axi_str_tready_from_fifo & !empty)\n begin\n state_rd <= PREP_READ_1;\n rd_en <= 1'b1; \n end\n else\n begin\n state_rd <= IDLE_RD;\n end\n end \n PREP_READ_1 : begin \n rd_en <= 1'b0;\n state_rd <= PREP_READ_2;\n end\n PREP_READ_2 : begin\n //Continue reading data if CRC passes for a forthcoming frame\n //CRC check is passed through command FIFO from write side logic \n if(valid_cmd & crc_pass)\n begin\n state_rd <= BEGIN_READ; \n end\n else\n begin\n state_rd <= BEGIN_READ;\n end\n end\n BEGIN_READ : begin\n //Continue reading data until tlast from XGEMAC is received \n if(axis_rd_tlast & axis_rd_tvalid & axis_rd_tready)\n begin\n state_rd <= IDLE_RD;\n end \n else\n begin\n state_rd <= BEGIN_READ;\n end \n end\n default : state_rd <= IDLE_RD;\n endcase\n end\n end \n \n always @(state_rd, valid_cmd, crc_pass,axis_rd_tlast,axis_rd_tvalid,axi_str_tready_from_fifo)\n begin\n if(state_rd==PREP_READ_2)\n begin \n if(valid_cmd & crc_pass)\n begin\n axis_rd_tready <= axi_str_tready_from_fifo;\n axis_rd_tvalid_from_fsm <= axis_rd_tvalid;\n // rd_pkt_len_count <= rd_pkt_len;\n end\n else\n begin \n axis_rd_tready <= 1'b1;\n axis_rd_tvalid_from_fsm <= 1'b0;\n end\n end \n else if(state_rd==BEGIN_READ)\n begin\n if (valid_cmd & crc_pass)\n begin\n //if (rd_pkt_len_count >\n axis_rd_tready <= axi_str_tready_from_fifo;\n axis_rd_tvalid_from_fsm <= axis_rd_tvalid;\n //rd_pkt_len_count <= rd_pkt_len_count -= 8;\n end\n else\n begin\n axis_rd_tready <= 1'b1;\n axis_rd_tvalid_from_fsm <= 1'b0;\n end\n end \n else\n begin\n axis_rd_tready <= 1'b0; \n axis_rd_tvalid_from_fsm <= 1'b0;\n end\n end\n\n //-Data FIFO instance: AXI Stream Asynchronous FIFO\n //XGEMAC interface outputs an entire frame in a single shot\n //TREADY signal from slave interface of FIFO is left unconnected\n axis_sync_fifo axis_fifo_inst1 (\n .m_axis_tready (axis_rd_tready ),\n .s_aresetn (~reset ),\n .s_axis_tready (axis_wr_tready ),\n //.s_aclk (user_clk ),\n .s_axis_tvalid (axis_wr_tvalid ),\n .m_axis_tvalid (axis_rd_tvalid ),\n .s_aclk (user_clk ),\n .m_axis_tlast (axis_rd_tlast ),\n .s_axis_tlast (axis_wr_tlast ),\n .s_axis_tdata (axis_wr_tdata ),\n .m_axis_tdata (axis_rd_tdata ),\n .s_axis_tkeep (axis_wr_tkeep ),\n .m_axis_tkeep (axis_rd_tkeep ),\n //.axis_rd_data_count (rd_data_count ),\n //.axis_wr_data_count (wr_data_count )\n .axis_data_count (wr_data_count ) //1024 items = [10:0]\n );\n\n //command FIFO interface for controlling the read side interface\n cmd_fifo_xgemac_rxif cmd_fifo_inst (\n .clk (user_clk ),\n .rst (reset ),\n .din (cmd_in ), // Bus [15 : 0] \n .wr_en (wr_en ),\n .rd_en (rd_en ),\n .dout (cmd_out ), // Bus [15 : 0] \n .full (full ),\n .empty (empty )\n );\n\n assign axi_str_tdata_to_fifo = axis_rd_tdata; \n assign axi_str_tkeep_to_fifo = axis_rd_tkeep; \n assign axi_str_tlast_to_fifo = axis_rd_tlast; \n assign axi_str_tvalid_to_fifo = axis_rd_tvalid_from_fsm; \n\n always @(posedge user_clk)\n if (reset)\n rx_fifo_overflow <= 1'b0;\n else if (state_wr==DROP_FRAME)\n rx_fifo_overflow <= 1'b1;\n\n\n\n/*wire [35:0] control0;\nwire [35:0] control1;\nwire [63:0] vio_signals;\nwire [127:0] debug_signal;\n\nicon icon_isnt\n(\n .CONTROL0 (control0),\n .CONTROL1 (control1)\n);\n\nila ila_inst\n(\n .CLK (user_clk),\n .CONTROL (control0),\n .TRIG0 (debug_signal)\n);\n\nvio vio_inst\n(\n .CLK (user_clk),\n .CONTROL (control1),\n .SYNC_OUT (vio_signals)\n);\n\n\nreg[2:0] pkg_count;\n\nalways @(posedge user_clk)\nbegin\n if (reset == 1) begin\n pkg_count <= 3'b000;\n end\n else begin\n if ((axi_str_tvalid_from_xgmac == 1'b1) && (axi_str_tlast_from_xgmac == 1'b1)) begin\n pkg_count <= pkg_count + 1;\n end\n end\nend\n\n\nassign debug_signal[3:0] = frame_len_ctr;\nassign debug_signal[4] = frame_len_ctr_valid;\nassign debug_signal[8:5] = state_wr;\nassign debug_signal[12:9] = state_rd;\nassign debug_signal[28:13] = cmd_in;\nassign debug_signal[31:29] = cmd_out[3:0];\nassign debug_signal[63:32] = axi_str_tdata_from_xgmac[31:0];\nassign debug_signal[71:64] = axi_str_tkeep_from_xgmac;\nassign debug_signal[72] = axi_str_tvalid_from_xgmac;\nassign debug_signal[73] = rx_statistics_valid;\nassign debug_signal[87:74] = rx_stats_vec_reg;\nassign debug_signal[105:90] = axi_str_tdata_to_fifo[15:0];\nassign debug_signal[113:106] = axi_str_tkeep_to_fifo;\nassign debug_signal[114] = axi_str_tvalid_to_fifo;\nassign debug_signal[115] = axi_str_tready_from_fifo;\n//assign debug_signal[118:116] = rx_stats_vec_reg[2:0];\n//assign debug_signal[116] = ap_ready;\n//assign debug_signal[117] = ap_done;\n//assign debug_signal[118] = ap_idle;\nassign debug_signal[119] = axi_str_tlast_from_xgmac;\nassign debug_signal[120] = axi_str_tlast_to_fifo;\nassign debug_signal[123:121] = pkg_count;\nassign debug_signal[124] = force_tlast_to_fifo;\n\nassign debug_signal[125] = axis_rd_tvalid;\nassign debug_signal[126] = axis_rd_tready;\nassign debug_signal[127] = axis_rd_tlast;*/\n\nendmodule \n", "groundtruth": " wr_en <= 1'b0; \n cmd_in[1] <= 1'b1;\n\n state_wr <= BEGIN_WRITE;\n", "crossfile_context": ""} {"task_id": "eurorack-pmod", "path": "eurorack-pmod/gateware/cores/util/filter/karlsen_lpf_pipelined.sv", "left_context": "/*\n Karlsen Fast Ladder low-pass filter.\n\n Pipelined version that only requires 1 18x18 multiplier block.\n\n Inspired by:\n https://www.musicdsp.org/en/latest/Filters/240-karlsen-fast-ladder.html\n\n Translated to Verilog by Seb (me@sebholzapfel.com)\n\n Note on parameters and fixed point scaling:\n - g = cutoff = tan(pi * cutoff_freq / fs) => (0 is 0, 1 is about 0.2fs)\n -> Fixed point we expect g is in [0, 32768], where 32678 represents 1 (0.2fs)\n - resonance scales from 0 to 4 (where 4 is far in self-oscillation)\n -> Fixed point we expect resonance in [0, 32768] wher 32768 scales to 2.\n*/\n\n`default_nettype none\n\n// Helper module to perform one `a + (b - a) * scale` operation. The\n// ladder filter does this operation 5 times in a row so this is shared.\nmodule smul_shift_18x18 (\n input signed [17:0] a,\n input signed [17:0] b,\n", "right_context": " input rst,\n input clk,\n input strobe,\n // See header comment for what these parameters mean.\n input signed [W-1:0] g,\n input signed [W-1:0] resonance,\n input signed [W-1:0] sample_in,\n output logic signed [W-1:0] sample_out\n);\n\n\n`define CLAMP(x) ((x>MAX)?MAX:((x>> W));\n smul_a <= WMULT'(in_ex);\n smul_b <= a4;\n smul_scale <= resonance_ex;\n end\n 1: begin\n // Fix sign of smul_shift operation\n clip <= (in_ex<<<1) - WMULT'(smul_out);\n end\n 2: begin\n // Saturation (simplified)\n clip <= `CLAMP(clip);\n end\n 3: begin\n // a1 <= a1 + (((-a1 + sat) * g_ex) >>> W);\n smul_a <= a1;\n smul_b <= clip;\n smul_scale <= g_ex;\n end\n 4: begin\n // a2 <= a2 + (((-a2 + a1) * g_ex) >>> W);\n a1 <= WMULT'(smul_out);\n smul_a <= a2;\n smul_b <= WMULT'(smul_out);\n end\n 5: begin\n // a3 <= a3 + (((-a3 + a2) * g_ex) >>> W);\n a2 <= WMULT'(smul_out);\n smul_a <= a3;\n smul_b <= WMULT'(smul_out);\n end\n 6: begin\n // a4 <= a4 + (((-a4 + a3) * g_ex) >>> W);\n a3 <= WMULT'(smul_out);\n smul_a <= a4;\n smul_b <= WMULT'(smul_out);\n end\n 7: begin\n a4 <= WMULT'(smul_out);\n sample_out <= smul_out[W-1:0];\n end\n default: begin\n // Sit here until next sample.\n end\n endcase\n end\n end\nend\n\n`ifdef COCOTB_SIM\ninitial begin\n $dumpfile (\"karlsen_lpf_pipelined.vcd\");\n $dumpvars;\n #1;\nend\n`endif\n\nendmodule\n", "groundtruth": " input signed [17:0] scale,\n output signed [35:0] o\n);\nassign o = 36'(a) + (36'(18'(-a + b) * 18'(scale)) >>> 16);\nendmodule\n", "crossfile_context": ""} {"task_id": "riscv-tests-intro", "path": "riscv-tests-intro/practice/02_aapg/golden/tb/miriscv_mem_intf.sv", "left_context": "interface miriscv_mem_intf (\n", "right_context": " input logic arst_n\n);\n\n // Instruction memory signals\n logic instr_rvalid;\n logic [31:0] instr_rdata;\n logic instr_req;\n logic [31:0] instr_addr;\n\n // Data memory signals\n logic data_rvalid;\n logic [31:0] data_rdata;\n logic data_req;\n logic [31:0] data_wdata;\n logic [31:0] data_addr;\n logic data_we;\n logic [ 3:0] data_be;\n\n function void get_bus_status (\n miriscv_test_pkg::miriscv_mem_item t\n );\n t.instr_rvalid = instr_rvalid;\n t.instr_rdata = instr_rdata;\n t.instr_req = instr_req;\n t.instr_addr = instr_addr;\n t.data_rvalid = data_rvalid;\n t.data_rdata = data_rdata;\n t.data_req = data_req;\n t.data_wdata = data_wdata;\n t.data_addr = data_addr;\n t.data_we = data_we;\n t.data_be = data_be;\n endfunction\n\n task wait_clks(input int num);\n repeat (num) @(posedge clk);\n endtask\n\n task wait_neg_clks(input int num);\n repeat (num) @(negedge clk);\n endtask\n \nendinterface", "groundtruth": " input logic clk,\n", "crossfile_context": ""} {"task_id": "tiny-tpu", "path": "tiny-tpu/src/gradient_descent.sv", "left_context": "`timescale 1ns/1ps\n`default_nettype none\n\nmodule gradient_descent (\n input logic clk,\n input logic rst,\n\n // learning rate\n input logic [15:0] lr_in,\n\n // old weight\n input logic [15:0] value_old_in,\n\n // gradient\n input logic [15:0] grad_in,\n\n // start signal\n input logic grad_descent_valid_in,\n\n // bias or weight\n input logic grad_bias_or_weight,\n\n // updated weight and done signal\n output logic [15:0] value_updated_out,\n output logic grad_descent_done_out\n);\n\n logic [15:0] sub_value_out;\n logic grad_descent_in_reg;\n logic [15:0] sub_in_a;\n logic [15:0] mul_out;\n\n fxp_mul mul_inst (\n .ina(grad_in),\n .inb(lr_in),\n .out(mul_out),\n .overflow()\n );\n\n fxp_addsub sub_inst (\n .ina(sub_in_a),\n .inb(mul_out),\n .sub(1'b1),\n .out(sub_value_out),\n .overflow()\n );\n\n always_comb begin\n case(grad_bias_or_weight)\n 1'b0: begin\n if(grad_descent_done_out) begin\n sub_in_a = value_updated_out;\n end else begin\n sub_in_a = value_old_in;\n end\n end\n\n", "right_context": " sub_in_a = value_old_in;\n end\n endcase\n end\n\n always_ff @(posedge clk or posedge rst) begin\n if(rst) begin\n sub_in_a <= '0;\n value_updated_out <= '0;\n grad_descent_done_out <= '0;\n end else begin\n grad_descent_done_out <= grad_descent_valid_in;\n if(grad_descent_valid_in) begin\n value_updated_out <= sub_value_out;\n end else begin\n value_updated_out <= '0;\n end\n end\n end\n\n\nendmodule", "groundtruth": " 1'b1: begin\n", "crossfile_context": ""} {"task_id": "ahb2apb-bridge", "path": "ahb2apb-bridge/AHB2APB_Bridge/dv/env/ahb2apb_scb.svh", "left_context": "\n//////////////////////////////////////////////////////////////////////////////////\n// Engineer: \t\tTravis\n// \n// Create Date: \t12/17/2020 Thu 10:30\n// Filename: \t\tahb2apb_scb.svh\n// class Name: \t\tahb2apb_scb\n// Project Name: \tahb2apb_bridge\n// Revision 0.01 - File Created \n// Additional Comments:\n// -------------------------------------------------------------------------------\n// \t-> Compare AHBL pkt with apb pkt \n//////////////////////////////////////////////////////////////////////////////////\n\nclass ahb2apb_scb extends uvm_scoreboard;\n\n\n\t\n\t//------------------------------------------\n\t// Data, Interface, port Members\n\t//------------------------------------------\n\tuvm_blocking_get_port #(apb_trans) \tapb_port;\n\tuvm_blocking_get_port #(ahbl_trans)\tahbl_port;\n\t\n\tfunc_cov\tfcov;\n\n\t//Factory Registration\n\t//\n\t`uvm_component_utils(ahb2apb_scb)\n\n\t//----------------------------------------------\n\t// Methods\n\t// ---------------------------------------------\n\t// Standard UVM Methods:\t\n\textern function new(string name = \"ahb2apb_scb\", uvm_component parent);\n\textern virtual function void build_phase(uvm_phase phase);\n\textern virtual task main_phase(uvm_phase phase);\n\t// User Defined Methods:\n\textern virtual task check_pkt();\nendclass\n\n//Constructor\nfunction ahb2apb_scb::new(string name = \"ahb2apb_scb\", uvm_component parent);\n\tsuper.new(name, parent);\nendfunction\n\n//Build_Phase\nfunction void ahb2apb_scb::build_phase(uvm_phase phase);\n\tsuper.build_phase(phase);\n\tapb_port = new(\"apb_port\", this);\n\tahbl_port = new(\"ahbl_port\", this);\n\tfcov = new(\"fcov\");\nendfunction\n\n//Main_Phase\ntask ahb2apb_scb::main_phase(uvm_phase phase);\n\tcheck_pkt();\nendtask\n\ntask ahb2apb_scb::check_pkt();\n\tapb_trans\tapb_pkt;\n\tahbl_trans\tahbl_pkt;\n\tbit \t\terr_flag;\n\t\n\twhile(1) begin\n\t\terr_flag = 0;\n\t\tahbl_port.get(ahbl_pkt);\n\t\tapb_port.get(apb_pkt);\n\t\t\n\t\tfcov.cg.sample(ahbl_pkt, apb_pkt);\n\t\t//------------------------------------------\n\t\t//Check address:\n\t\t//------------------------------------------\n\t\t\n\t\tif(ahbl_pkt.haddr[15:2] != apb_pkt.paddr[15:2]) begin\n\t\t\t`uvm_error(get_type_name(), $sformatf(\"address mismatch! ahb-addr[15:2][%0h], apb-addr[15:2][%0h]\",ahbl_pkt.haddr[15:2], apb_pkt.paddr[15:2]))\n\t\t\terr_flag = 1;\n\t\tend\n\t\t//------------------------------------------\n\t\t//Check data:\n\t\t//------------------------------------------\n\t\tif(ahbl_pkt.hwrite)\n\t\t\tif(ahbl_pkt.hrwdata != apb_pkt.data) begin\n\t\t\t\t`uvm_error(get_type_name(), $sformatf(\"write data mismatch! ahb-data = %0h, apb-data = %0h\",ahbl_pkt.hrwdata, apb_pkt.data))\n\t\t\t\terr_flag = 1;\n\t\t\tend\n\t\telse if(!ahbl_pkt.hwrite)\n\t\t\tif(ahbl_pkt.hrwdata != apb_pkt.prdata) begin\n\t\t\t\t`uvm_error(get_type_name(), $sformatf(\"read data mismatch! ahb-data = %0h, apb-prdata = %0h\",ahbl_pkt.hrwdata, apb_pkt.prdata))\n\t\t\t\terr_flag = 1;\n\t\t\tend\t\n\t\t//------------------------------------------\n\t\t//Check read of write:\n\t\t//------------------------------------------\n\t\tif(ahbl_pkt.hwrite == (apb_pkt.kind == apb_slv_pkg::READ)) begin\n\t\t\t`uvm_error(get_type_name(), \"AHB-packet and APB-packet read/write mismatch! ahb-write, apb-read\")\n\t\t\terr_flag = 1;\t\n\t\tend\n\t\t\n\t\t//------------------------------------------\n\t\tif(!ahbl_pkt.hwrite == (apb_pkt.kind == apb_slv_pkg::WRITE)) begin\n", "right_context": "\t\t\terr_flag = 1;\t\n\t\tend\n\t\t\n\t\t\n\t\t//------------------------------------------\n\t\t//Check hprot and pprot signal:\n\t\t//------------------------------------------\n\t\t/* \n\t\t\tHPROT[3]:Modifiable\n\t\t\tHPROT[2]:Bufferable\n\t\t\tHPROT[1]:Privileged\n\t\t\tHPROT[0]:Data/Opcode */\n\t\t\t\t\t\n\t\t//user or priviledged\n\t\tif(ahbl_pkt.hprot[1] != apb_pkt.pprot[0]) begin\n\t\t\t`uvm_error(get_type_name(), $sformatf(\"hprot/pprot mismatch ahbl[1] =%0h ,apb[0] = %0h \", ahbl_pkt.hprot[1], apb_pkt.pprot[0] ))\n\t\t\terr_flag = 1;\n\t\tend\n\n\t\t//secure or non-secure\n\t\tif(ahbl_pkt.hprot[0] == apb_pkt.pprot[2]) begin \n\t\t\t`uvm_error(get_type_name(), $sformatf(\"hprot/pprot mismatch ahbl[0] = %0h , apb[2] = %0h \", ahbl_pkt.hprot[0], apb_pkt.pprot[2]))\n\t\t\terr_flag = 1;\n\t\tend\n\t\t\n\t\t//------------------------------------------\n\t\t//check hsize and pstrb when it is a write access\n\t\t//------------------------------------------\n\t\tif((ahbl_pkt.hsize == WORD) & (apb_pkt.pstrb != 4'b1111))begin\n\t\t\t`uvm_error(get_type_name(), $sformatf(\"hsize/haddr/pstrb mismatch! ahbl-size:WORD, apb-pstrb:%4b\", apb_pkt.pstrb))\n\t\t\terr_flag = 1;\n\t\tend\n\t\t\n\t\tif(\t((ahbl_pkt.hsize == HWORD) & !ahbl_pkt.haddr[1] & (apb_pkt.pstrb != 4'b0011)) \n\t\t\t| ((ahbl_pkt.hsize == HWORD) & ahbl_pkt.haddr[1] & (apb_pkt.pstrb != 4'b1100)))begin\n\t\t\t`uvm_error(get_type_name(), $sformatf(\"hsize/haddr/pstrb mismatch! ahbl-size:HWORD, ahbl-addr[1]:%d, apb-pstrb:%4b\", ahbl_pkt.haddr[1], apb_pkt.pstrb))\n\t\t\terr_flag = 1;\n\t\tend\n\t\t\n\t\tif(\t ((ahbl_pkt.hsize == BYTE) & (ahbl_pkt.haddr[1:0] == 2'b00) & (apb_pkt.pstrb != 4'b0001)) \n\t\t\t| ((ahbl_pkt.hsize == BYTE) & (ahbl_pkt.haddr[1:0] == 2'b01) & (apb_pkt.pstrb != 4'b0010))\n\t\t\t| ((ahbl_pkt.hsize == BYTE) & (ahbl_pkt.haddr[1:0] == 2'b10) & (apb_pkt.pstrb != 4'b0100))\n\t\t\t| ((ahbl_pkt.hsize == BYTE) & (ahbl_pkt.haddr[1:0] == 2'b11) & (apb_pkt.pstrb != 4'b1000)))begin\n\t\t\t`uvm_error(get_type_name(), $sformatf(\"hsize/haddr/pstrb mismatch! ahbl-size:BYTE, ahbl-addr[1:0]:%d, apb-pstrb:%4b\", ahbl_pkt.haddr[1], apb_pkt.pstrb))\n\t\t\terr_flag = 1;\n\t\tend\n\t\t//------------------------------------------\n\t\t//check hresp and pslverr\n\t\t//------------------------------------------\n\t\tif(ahbl_pkt.hresp != apb_pkt.pslverr) begin\n\t\t\t`uvm_error(get_type_name(), $sformatf(\"hresp/pslverr mismatch hresp:[%0h], pslverr:[%0h]\", ahbl_pkt.hresp, apb_pkt.pslverr ))\n\t\t\terr_flag = 1;\n\t\tend\n\t\t\n\t\tif(ahbl_pkt.hresp != apb_pkt.pslverr) begin\n\t\t\t`uvm_error(get_type_name(), $sformatf(\"hresp/pslverr mismatch hresp:[%0h], pslverr:[%0h]\", ahbl_pkt.hresp, apb_pkt.pslverr ))\n\t\t\terr_flag = 1;\n\t\tend\n\t\t//final-display if correct\n\t\tif(err_flag)\n\t\t\t`uvm_error(get_type_name(), \"Pkt comparing failed\")\n\t\telse \n\t\t\t`uvm_info(get_type_name(), \"Pkt comparing passed\", UVM_LOW)\n\t\t#20ns;\n\tend\n\nendtask:check_pkt\n", "groundtruth": "\t\t\t`uvm_error(get_type_name(), \"AHB-packet and APB-packet read/write mismatch! ahb-read, apb-write\")\n", "crossfile_context": ""} {"task_id": "riscv-vip", "path": "riscv-vip/src/riscv_vip_csr_if.sv", "left_context": "\n\n//###############################################################\n//\n// Licensed to the Apache Software Foundation (ASF) under one\n// or more contributor license agreements. See the NOTICE file\n// distributed with this work for additional information\n// regarding copyright ownership. The ASF licenses this file\n// to you under the Apache License, Version 2.0 (the\n// \"License\"); you may not use this file except in compliance\n// with the License. You may obtain a copy of the License at\n// \n// http://www.apache.org/licenses/LICENSE-2.0\n// \n// Unless required by applicable law or agreed to in writing,\n// software distributed under the License is distributed on an\n// \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY\n// KIND, either express or implied. See the License for the\n// specific language governing permissions and limitations\n// under the License.\n//\n//###############################################################\n\n\n`ifndef _RISCV_VIP_CSR_IF_INCLUDED_\n`define _RISCV_VIP_CSR_IF_INCLUDED_\n\n`include \"riscv_vip_pkg.sv\"\n\n", "right_context": "\n riscv_vip_pkg::csrs_t csrs;\n \nendinterface\n\n`endif\n", "groundtruth": "interface riscv_vip_csr_if (input clk, input rstn);\n", "crossfile_context": ""} {"task_id": "DUA", "path": "DUA/Hardware/Common/SiliconNet/SiliconNet.sv", "left_context": "///////////////////////////////////////////////////////////////\n//\n// Copyright (c) Microsoft Corporation. All rights reserved.\n// Licensed under the MIT License.\n//\n////////////////////////////////////////////////////////////////\n\nimport SiliconNetTypes::*;\nimport NetworkTypes::IP4Address;\n\nmodule SiliconNet\n#(\n ////////// Connector\n // Interface parameter\n parameter DATA_WIDTH = SN_DATA_WIDTH,\n parameter UID_WIDTH = SN_UID_WIDTH,\n parameter LENGTH_WIDTH = SN_LENGTH_WIDTH,\n parameter FLAG_WIDTH = SN_FLAG_WIDTH,\n parameter SEQNUM_WIDTH = SN_SEQNUM_WIDTH,\n parameter TYPE_WIDTH = SN_TYPE_WIDTH,\n parameter PARAM_WIDTH = SN_PARAM_WIDTH,\n parameter NUM_PORTS = SN_NUM_PORTS,\n parameter MAX_MSG_LENGTH = SN_MAX_MSG_LENGTH,\n // ForwardingTable related\n parameter NUM_TABLES = 2,\n parameter NUM_KEYS_HIGH = 16,\n parameter NUM_KEYS_LOW = 64,\n parameter WIDTH_HIGH = $bits(IP4Address),\n parameter WIDTH_LOW = SN_DEVID_WIDTH,\n // ForwardingTable config parameters\n parameter CTL_REG_WRITE_KEY_ADDR = SN_CTL_REG_WRITE_KEY_ADDR,\n parameter CTL_REG_WRITE_MSK_ADDR = SN_CTL_REG_WRITE_MSK_ADDR,\n parameter CTL_REG_READ_KEY_ADDR = SN_CTL_REG_READ_KEY_ADDR,\n parameter CTL_REG_READ_MSK_ADDR = SN_CTL_REG_READ_MSK_ADDR,\n parameter CTL_REG_READ_EP_ADDR = SN_CTL_REG_READ_EP_ADDR,\n parameter CTL_REG_ADDR = SN_CTL_REG_ADDR,\n // Connector counter\n parameter CTL_REG_COUNTER_VALUE_ADDR = SN_CTL_REG_COUNTER_VALUE_ADDR,\n\n ////////// SiliconSwitch\n // Core parameter\n parameter NUM_VCS = SN_NUM_VCS,\n parameter PHIT_WIDTH = SN_PHIT_WIDTH,\n parameter FLIT_WIDTH = SN_FLIT_WIDTH,\n // Per-Input Port Parameters\n parameter NUM_FLITS = SN_NUM_FLITS,\n parameter FLITS_PER_MESSAGE = SN_FLITS_PER_MESSAGE,\n // Per-Output Downstream Parameters\n parameter MAX_FLITS_PER_PORT_DOWNSTREAM = SN_FLITS_PER_PORT_DOWNSTREAM,\n parameter MAX_CREDIT_WIDTH = SN_MAX_CREDIT_WIDTH,\n // Optimization\n parameter DISABLE_UTURN = SN_DISABLE_UTURN,\n parameter USE_LUTRAM = SN_USE_LUTRAM\n)\n( \n input clk,\n input rst,\n\n // Stack/App side\n input sa_clk [NUM_PORTS-1:0],\n input sa_rst [NUM_PORTS-1:0],\n\n // Stack/App Side - (RX: SiliconNet -> Stack/App)\n output reg [DATA_WIDTH-1:0] sa_data_out [NUM_PORTS-1:0],\n output reg sa_valid_out [NUM_PORTS-1:0],\n output reg sa_first_out [NUM_PORTS-1:0],\n output reg sa_last_out [NUM_PORTS-1:0],\n input sa_ready_in [NUM_PORTS-1:0],\n\n // Stack/App Side - (TX: Stack/App -> SiliconNet)\n input [DATA_WIDTH-1:0] sa_data_in [NUM_PORTS-1:0],\n input sa_valid_in [NUM_PORTS-1:0],\n input sa_first_in [NUM_PORTS-1:0],\n input sa_last_in [NUM_PORTS-1:0],\n output reg sa_ready_out [NUM_PORTS-1:0],\n\n // ForwardingTable in Connector Configuration\n input ctl_read_in,\n input ctl_write_in,\n input [15:0] ctl_addr_in,\n input [63:0] ctl_wrdata_in,\n output reg [63:0] ctl_rddata_out,\n output reg ctl_rdvalid_out\n);\n\n // Address high field configure\n reg high_cfg_in [NUM_PORTS-1:0]; \n reg [$clog2(NUM_KEYS_HIGH):0] high_cfg_index_in [NUM_PORTS-1:0];\n reg high_cfg_valid_in [NUM_PORTS-1:0];\n reg [WIDTH_HIGH-1:0] high_cfg_key_in [NUM_PORTS-1:0];\n reg [WIDTH_HIGH-1:0] high_cfg_msk_in [NUM_PORTS-1:0];\n reg [$clog2(NUM_PORTS)-1:0] high_cfg_endpoint_in [NUM_PORTS-1:0];\n //\n reg high_cfg_read_in [NUM_PORTS-1:0];\n wire high_cfg_read_valid_out [NUM_PORTS-1:0];\n wire high_cfg_valid_out [NUM_PORTS-1:0];\n wire [WIDTH_HIGH-1:0] high_cfg_key_out [NUM_PORTS-1:0];\n wire [WIDTH_HIGH-1:0] high_cfg_msk_out [NUM_PORTS-1:0];\n wire [$clog2(NUM_PORTS)-1:0] high_cfg_endpoint_out [NUM_PORTS-1:0];\n\n // Address low field onfigure\n reg low_cfg_in [NUM_PORTS-1:0]; \n reg [$clog2(NUM_KEYS_LOW):0] low_cfg_index_in [NUM_PORTS-1:0];\n reg low_cfg_valid_in [NUM_PORTS-1:0];\n reg [WIDTH_LOW-1:0] low_cfg_key_in [NUM_PORTS-1:0];\n reg [WIDTH_LOW-1:0] low_cfg_msk_in [NUM_PORTS-1:0];\n reg [$clog2(NUM_PORTS)-1:0] low_cfg_endpoint_in [NUM_PORTS-1:0];\n //\n reg low_cfg_read_in [NUM_PORTS-1:0];\n wire low_cfg_read_valid_out [NUM_PORTS-1:0];\n wire low_cfg_valid_out [NUM_PORTS-1:0];\n wire [WIDTH_LOW-1:0] low_cfg_key_out [NUM_PORTS-1:0];\n wire [WIDTH_LOW-1:0] low_cfg_msk_out [NUM_PORTS-1:0];\n wire [$clog2(NUM_PORTS)-1:0] low_cfg_endpoint_out [NUM_PORTS-1:0];\n\n // counter related\n reg counter_read_in [NUM_PORTS-1:0];\n reg [2:0] counter_index_in [NUM_PORTS-1:0];\n wire counter_value_valid_out [NUM_PORTS-1:0];\n wire [63:0] counter_value_out [NUM_PORTS-1:0];\n \n // Input ports\n SwitchInterface rtr_input_ifc [NUM_PORTS-1:0];\n logic [NUM_PORTS-1:0] rtr_input_valid;\n\n // Input-side Credits\n SwitchCredit rtr_credit_out [NUM_PORTS-1:0];\n logic rtr_credack_in [NUM_PORTS-1:0];\n \n // Output port\n logic rtr_output_rst [NUM_PORTS-1:0];\n SwitchInterface rtr_output_ifc [NUM_PORTS-1:0];\n logic [NUM_PORTS-1:0] rtr_output_valid;\n logic rtr_output_stall [NUM_PORTS-1:0];\n\n // Credit returns\n SwitchCredit rtr_credit_in [NUM_PORTS-1:0];\n logic rtr_credack_out [NUM_PORTS-1:0];\n\n // ShimInterface\n SwitchInterface usr_in_ifc [NUM_PORTS-1:0];\n logic [NUM_PORTS-1:0] usr_in_wren;\n logic [NUM_PORTS-1:0] usr_out_full [NUM_PORTS-1:0];//20180308\n\n SwitchInterface usr_out_ifc [NUM_PORTS-1:0];\n logic [NUM_PORTS-1:0] usr_out_wren;\n logic [NUM_PORTS-1:0] usr_in_full;\n\n\n // debug only\n SiliconNetHead dbg_head_send [NUM_PORTS-1:0];\n SiliconData256 dbg_data_send [NUM_PORTS-1:0];\n SiliconNetHead dbg_head_receive [NUM_PORTS-1:0];\n SiliconData256 dbg_data_receive [NUM_PORTS-1:0];\n\n genvar i;\n\n ////////////////////////////////////////////////////////////////////////\n //SiliconSwitch/////////////////////////////////////////////////////////\n //////////////////////////////////////////////////////////////////////// \n SiliconSwitch\n #(\n .NUM_VCS (NUM_VCS),\n .PHIT_WIDTH (PHIT_WIDTH),\n .FLIT_WIDTH (FLIT_WIDTH),\n .NUM_PORTS (NUM_PORTS),\n\n .NUM_FLITS (NUM_FLITS),\n .FLITS_PER_MESSAGE (FLITS_PER_MESSAGE),\n\n .MAX_FLITS_PER_PORT_DOWNSTREAM (MAX_FLITS_PER_PORT_DOWNSTREAM),\n .MAX_CREDIT_WIDTH (MAX_CREDIT_WIDTH),\n\n .DISABLE_UTURN (DISABLE_UTURN),\n .USE_LUTRAM (USE_LUTRAM)\n )\n SiliconSwitch\n (\n .clk (clk),\n .rst (rst),\n\n .input_ifc_in (rtr_input_ifc),\n .input_valid_in (rtr_input_valid),\n .credit_out (rtr_credit_out),\n .credack_in (rtr_credack_in),\n\n .output_ifc_out (rtr_output_ifc),\n .output_valid_out (rtr_output_valid),\n .output_stall_in (rtr_output_stall),\n .credit_in (rtr_credit_in),\n .credack_out (rtr_credack_out)\n ); \n\n ////////////////////////////////////////////////////////////////////////\n //ShimInterface/////////////////////////////////////////////////////////\n //////////////////////////////////////////////////////////////////////// \n generate\n for(i=0; i < NUM_PORTS; i=i+1) begin : gen_ShimInterface\n ShimInterface\n #(\n .FLIT_WIDTH (FLIT_WIDTH),\n .PHIT_WIDTH (PHIT_WIDTH),\n .NUM_VCS (NUM_VCS),\n .NUM_PORTS (NUM_PORTS),\n .MAX_CREDIT_WIDTH (MAX_CREDIT_WIDTH),\n .DISABLE_FULL_PIPE (0)\n )\n ShimInterface\n (\n .clk (clk),\n .rst (rst),\n\n .usr_ifc_in (usr_in_ifc[i]),\n .usr_wren_in (usr_in_wren[i]),\n .usr_full_out (usr_out_full[i]),\n\n .usr_ifc_out (usr_out_ifc[i]),\n .usr_wren_out (usr_out_wren[i]),\n .usr_full_in (usr_in_full[i]),\n\n .rtr_ifc_out (rtr_input_ifc[i]),\n .rtr_valid_out (rtr_input_valid[i]),\n .rtr_credit_in (rtr_credit_out[i]),\n .rtr_credack_out (rtr_credack_in[i]),\n\n .rtr_ifc_in (rtr_output_ifc[i]),\n .rtr_valid_in (rtr_output_valid[i]),\n .rtr_output_stall_out (rtr_output_stall[i]),\n .rtr_credit_out (rtr_credit_in[i]),\n .rtr_credack_in (rtr_credack_out[i])\n ); \n end\n endgenerate\n\n ////////////////////////////////////////////////////////////////////////\n //Connector/////////////////////////////////////////////////////////////\n //////////////////////////////////////////////////////////////////////// \n generate\n for(i=0; i < NUM_PORTS; i=i+1) begin : gen_Connector\n Connector\n #(\n .DATA_WIDTH (DATA_WIDTH),\n .UID_WIDTH (UID_WIDTH),\n .LENGTH_WIDTH (LENGTH_WIDTH),\n .FLAG_WIDTH (FLAG_WIDTH),\n .SEQNUM_WIDTH (SEQNUM_WIDTH),\n .TYPE_WIDTH (TYPE_WIDTH),\n .PARAM_WIDTH (PARAM_WIDTH),\n .NUM_PORTS (NUM_PORTS),\n .MAX_MSG_LENGTH (MAX_MSG_LENGTH),\n .THIS_ID_PORT (i),\n .THIS_ID_VC (1),\n \n .NUM_TABLES (NUM_TABLES),\n .NUM_KEYS_HIGH (NUM_KEYS_HIGH),\n .NUM_KEYS_LOW (NUM_KEYS_LOW),\n .WIDTH_HIGH (WIDTH_HIGH),\n .WIDTH_LOW (WIDTH_LOW)\n )\n Connector\n (\n .clk (clk),\n .rst (rst),\n\n // Stack/App side\n .sa_clk (sa_clk[i]),\n .sa_rst (sa_rst[i]),\n\n // Full Switch Side - (RX: ShimInterface -> Connector) \n .fs_ifc_in (usr_out_ifc[i]),\n .fs_wren_in (usr_out_wren[i]),\n .fs_full_out (usr_in_full[i]),\n\n // Full Switch Side - (TX: Connctor -> ShimInterface) \n .fs_ifc_out (usr_in_ifc[i]),\n .fs_wren_out (usr_in_wren[i]),\n .fs_full_in (usr_out_full[i]),\n\n // Stack/App Side - (RX: Connector -> Stack/App)\n .sa_data_out (sa_data_out[i]),\n .sa_valid_out (sa_valid_out[i]),\n .sa_first_out (sa_first_out[i]),\n .sa_last_out (sa_last_out[i]),\n .sa_ready_in (sa_ready_in[i]),\n\n // Stack/App Side - (TX: Stack/App -> Connector)\n .sa_data_in (sa_data_in[i]),\n .sa_valid_in (sa_valid_in[i]),\n .sa_first_in (sa_first_in[i]),\n .sa_last_in (sa_last_in[i]),\n .sa_ready_out (sa_ready_out[i]),\n\n // Configure to FPGA CA\n\n // Address high field configure\n .high_cfg_in (high_cfg_in[i]), \n .high_cfg_index_in (high_cfg_index_in[i]),\n .high_cfg_valid_in (high_cfg_valid_in[i]),\n .high_cfg_key_in (high_cfg_key_in[i]),\n .high_cfg_msk_in (high_cfg_msk_in[i]),\n .high_cfg_endpoint_in (high_cfg_endpoint_in[i]),\n //\n .high_cfg_read_in (high_cfg_read_in[i]),\n .high_cfg_read_valid_out (high_cfg_read_valid_out[i]),\n .high_cfg_valid_out (high_cfg_valid_out[i]),\n .high_cfg_key_out (high_cfg_key_out[i]),\n .high_cfg_msk_out (high_cfg_msk_out[i]),\n .high_cfg_endpoint_out (high_cfg_endpoint_out[i]),\n\n // Address low field onfigure\n .low_cfg_in (low_cfg_in[i]), \n .low_cfg_index_in (low_cfg_index_in[i]),\n .low_cfg_valid_in (low_cfg_valid_in[i]),\n .low_cfg_key_in (low_cfg_key_in[i]),\n .low_cfg_msk_in (low_cfg_msk_in[i]),\n .low_cfg_endpoint_in (low_cfg_endpoint_in[i]),\n //\n .low_cfg_read_in (low_cfg_read_in[i]),\n .low_cfg_read_valid_out (low_cfg_read_valid_out[i]),\n .low_cfg_valid_out (low_cfg_valid_out[i]),\n .low_cfg_key_out (low_cfg_key_out[i]),\n .low_cfg_msk_out (low_cfg_msk_out[i]),\n .low_cfg_endpoint_out (low_cfg_endpoint_out[i]),\n\n .counter_read_in (counter_read_in[i]),\n .counter_index_in (counter_index_in[i]),\n .counter_value_valid_out (counter_value_valid_out[i]),\n .counter_value_out (counter_value_out[i])\n );\n end\n endgenerate\n\n ////////////////////////////////////////////////////////////////////////\n //Controller////////////////////////////////////////////////////////////\n //////////////////////////////////////////////////////////////////////// \n SiliconNetController\n #(\n \n .NUM_PORTS (NUM_PORTS),\n \n .NUM_TABLES (NUM_TABLES),\n .NUM_KEYS_HIGH (NUM_KEYS_HIGH),\n .NUM_KEYS_LOW (NUM_KEYS_LOW),\n .WIDTH_HIGH (WIDTH_HIGH),\n .WIDTH_LOW (WIDTH_LOW),\n \n .CTL_REG_WRITE_KEY_ADDR (CTL_REG_WRITE_KEY_ADDR),\n .CTL_REG_WRITE_MSK_ADDR (CTL_REG_WRITE_MSK_ADDR),\n .CTL_REG_READ_KEY_ADDR (CTL_REG_READ_KEY_ADDR),\n .CTL_REG_READ_MSK_ADDR (CTL_REG_READ_MSK_ADDR),\n .CTL_REG_ADDR (CTL_REG_ADDR),\n\n .CTL_REG_COUNTER_VALUE_ADDR (CTL_REG_COUNTER_VALUE_ADDR)\n )\n SiliconNetController\n (\n .clk (clk),\n .rst (rst),\n\n\n .ctl_read_in (ctl_read_in),\n .ctl_write_in (ctl_write_in),\n .ctl_addr_in (ctl_addr_in),\n .ctl_wrdata_in (ctl_wrdata_in),\n .ctl_rddata_out (ctl_rddata_out),\n .ctl_rdvalid_out (ctl_rdvalid_out),\n\n\n .high_cfg_out (high_cfg_in),\n .high_cfg_index_out (high_cfg_index_in),\n .high_cfg_valid_out (high_cfg_valid_in),\n .high_cfg_key_out (high_cfg_key_in),\n .high_cfg_msk_out (high_cfg_msk_in),\n .high_cfg_endpoint_out (high_cfg_endpoint_in),\n\n .high_cfg_read_out (high_cfg_read_in),\n", "right_context": " .high_cfg_valid_in (high_cfg_valid_out),\n .high_cfg_key_in (high_cfg_key_out),\n .high_cfg_msk_in (high_cfg_msk_out),\n .high_cfg_endpoint_in (high_cfg_endpoint_out),\n\n\n .low_cfg_out (low_cfg_in),\n .low_cfg_index_out (low_cfg_index_in),\n .low_cfg_valid_out (low_cfg_valid_in),\n .low_cfg_key_out (low_cfg_key_in),\n .low_cfg_msk_out (low_cfg_msk_in),\n .low_cfg_endpoint_out (low_cfg_endpoint_in),\n\n .low_cfg_read_out (low_cfg_read_in),\n .low_cfg_read_valid_in (low_cfg_read_valid_out),\n .low_cfg_valid_in (low_cfg_valid_out),\n .low_cfg_key_in (low_cfg_key_out),\n .low_cfg_msk_in (low_cfg_msk_out),\n .low_cfg_endpoint_in (low_cfg_endpoint_out),\n\n .counter_read_out (counter_read_in),\n .counter_index_out (counter_index_in),\n .counter_value_valid_in (counter_value_valid_out),\n .counter_value_in (counter_value_out)\n );\n\n // debug only\n genvar gen_i;\n // check send msg header \n generate\n for (gen_i = 0; gen_i < NUM_PORTS; gen_i++) begin : gen_dbg_head_send\n assign dbg_head_send[gen_i] = sa_first_in[gen_i] ? sa_data_in[gen_i] : {$bits(SiliconNetHead){1'bx}};\n end\n endgenerate\n // check send msg data\n generate\n for (gen_i = 0; gen_i < NUM_PORTS; gen_i++) begin : gen_dbg_data_send\n assign dbg_data_send[gen_i] = sa_valid_in[gen_i] ? (sa_first_in[gen_i] ? {{($bits(sa_data_in[gen_i])-1){1'bz}},1'b0} : sa_data_in[gen_i]) : {($bits(sa_data_in[gen_i])){1'bx}};\n end\n endgenerate\n\n // check received msg header \n generate\n for (gen_i = 0; gen_i < NUM_PORTS; gen_i++) begin : gen_dbg_head_receive\n assign dbg_head_receive[gen_i] = sa_first_out[gen_i] ? sa_data_out[gen_i] : {$bits(SiliconNetHead){1'bx}};\n end\n endgenerate\n // check received msg data\n generate\n for (gen_i = 0; gen_i < NUM_PORTS; gen_i++) begin : gen_dbg_data_receive\n assign dbg_data_receive[gen_i] = sa_valid_out[gen_i] ? (sa_first_out[gen_i] ? {{($bits(sa_data_out[gen_i])-1){1'bz}},1'b0} : sa_data_out[gen_i]) : {($bits(sa_data_out[gen_i])){1'bx}};\n end\n endgenerate\n\nendmodule", "groundtruth": " .high_cfg_read_valid_in (high_cfg_read_valid_out),\n", "crossfile_context": ""} {"task_id": "Design-Pattern-in-SV", "path": "Design-Pattern-in-SV/BehavioralDesignPatterns/ChainOfResponsibility/top.sv", "left_context": "`include \"transaction.sv\"\n`include \"ChainParentClass.sv\"\n`include \"ChainClasses.sv\"\n\n\nmodule top;\n\n ChainOne addChain;\n ChainTwo subChain;\n ChainThree mulChain;\n ChainFour divChain;\n\n // Simple method to define how to build chain. It is implemented in top module\n // for simplicity. It can be done in a wrapper class.\n function void build_chain ();\n addChain = new();\n subChain = new();\n mulChain = new();\n divChain = new();\n addChain.SetNextChainObject(subChain);\n subChain.SetNextChainObject(mulChain);\n mulChain.SetNextChainObject(divChain);\n //Div Chain Object will be the final one\n divChain.is_last_chain_part();\n endfunction\n\n initial begin\n transaction tr = new();\n int Result;\n build_chain();\n\n", "right_context": " tr.randomize();\n\n //Feed the transaction to the first chain part\n Result = addChain.process(tr);\n\n $display(\"op:%p\\t a1=%0d a2=%0d \\t\\t\\t Result=%0d\",tr.op_e,tr.a1,tr.a2,Result);\n end\n end\nendmodule\n", "groundtruth": " repeat(10) begin\n", "crossfile_context": ""} {"task_id": "FazyRV", "path": "FazyRV/soc/tb/fsoc_sim.sv", "left_context": "// Copyright (c) 2023 - 2024 Meinhard Kissich\n// -----------------------------------------------------------------------------\n// File : fsoc_sim.sv\n// Usage : Simulation wrapper for the fsoc SoC.\n// -----------------------------------------------------------------------------\n\n`default_nettype none\n\nmodule fsoc_sim #(\n parameter MEMFILE = \"\",\n parameter MEMSIZE = 8192,\n parameter CHUNKSIZE = 1,\n parameter RFTYPE = \"BRAM\",\n parameter CONF = \"MIN\",\n parameter MTVAL = 'h0,\n parameter BOOTADR = 'h1000\n) (\n input logic clk_i,\n input logic rst_in,\n output logic q\n);\n\nlocalparam MEMDLY1 = 0;\nlocalparam GPOCNT = 3;\n\nlogic [4095:0] firmware_file;\ninitial\n if ($value$plusargs(\"firmware=%s\", firmware_file)) begin\n\t $display(\"Loading RAM from %0s\", firmware_file);\n\t $readmemh(firmware_file, i_fsoc.i_mem.mem_r);\n end\n\nlogic [GPOCNT-1:0] gpo;\n\nassign q = gpo[0];\n\n// gpo is used by embench to determine timing\nlogic [1023:0] embench_file;\nlogic [GPOCNT-1:0] gpo_r = '0;\n\nreal start_time;\nreal release_time;\ninteger f = 0;\n\ninitial begin\n $timeformat(-6, 0, \"\", 1);\n\n /* verilator lint_off WIDTH */\n if ($value$plusargs(\"embench=%s\", embench_file)) begin\n $display(\"Writing embench_file timing to %0s\", embench_file);\n f = $fopen(embench_file, \"w\");\n end\n /* verilator lint_on WIDTH */\nend\n\nlogic rst_r = 'b0;\nalways @(posedge clk_i) begin\n rst_r <= rst_in;\n if (~rst_r & rst_in) begin\n release_time = $realtime;\n end\nend\n\nalways @(posedge clk_i) begin\n gpo_r <= gpo;\n if ((~gpo_r[0] & gpo[0]) & (f != 0)) begin\n start_time = $realtime - release_time; \n $display(\"Test started\");\n end else if((gpo_r[0] & ~gpo[0]) & (f != 0)) begin\n $fwrite(f, \"Bench time: %t\\n\", $realtime-start_time);\n $display(\"Test complete, waiting for validation\");\n end\n\n if ((gpo[2] | gpo[1]) & (f != 0)) begin\n if (gpo[2]) begin\n $fwrite(f, \"FAILED @ %t\\n\", $realtime-start_time);\n $display(\"FAILED\");\n $finish;\n end else begin\n $fwrite(f, \"SUCCESS @ %t\\n\", $realtime-start_time);\n $display(\"SUCCESS\");\n $finish;\n end\n end\nend\n\n\nfsoc #( \n .CHUNKSIZE ( CHUNKSIZE ),\n .CONF ( CONF ),\n .RFTYPE ( RFTYPE ),\n .MTVAL ( MTVAL ),\n .BOOTADR ( BOOTADR ),\n .MEMFILE ( MEMFILE ),\n .MEMSIZE ( MEMSIZE ),\n .MEMDLY1 ( MEMDLY1 ),\n .GPOCNT ( GPOCNT )\n) i_fsoc (\n .clk_i ( clk_i ),\n .rst_in ( rst_in ),\n //.tirq_i ( 1'b0 ),\n //.trap_o ( ),\n .gpi_i ( 1'b0 ),\n .gpo_o ( gpo )\n);\n\n\nlogic [63:0] mcycle_r;\n\n// --- Cylce counter ---\nalways @(posedge clk_i) begin\n if (~rst_in) begin\n mcycle_r = 'b0;\n end else begin\n mcycle_r = mcycle_r + 'b1;\n end \nend\n\n// --- Instr to ASCII ---\n/* verilator lint_off WIDTHEXPAND */\nlogic [128:0] dbg_ascii_instr;\n\n// 30 25 20 15 10 5 0\n// | | | | | | |\n`define INSTR_LUI (32'b??_?????_?????_?????_?????_???01_10111)\n`define INSTR_AUIPC (32'b??_?????_?????_?????_?????_???00_10111)\n`define INSTR_JAL (32'b??_?????_?????_?????_?????_???11_01111)\n`define INSTR_JALR (32'b??_?????_?????_?????_000??_???11_00111)\n`define INSTR_BEQ (32'b??_?????_?????_?????_000??_???11_00011)\n`define INSTR_BNE (32'b??_?????_?????_?????_001??_???11_00011)\n`define INSTR_BLT (32'b??_?????_?????_?????_100??_???11_00011)\n`define INSTR_BGE (32'b??_?????_?????_?????_101??_???11_00011)\n`define INSTR_BLTU (32'b??_?????_?????_?????_110??_???11_00011)\n`define INSTR_BGEU (32'b??_?????_?????_?????_111??_???11_00011)\n`define INSTR_LB (32'b??_?????_?????_?????_000??_???00_00011)\n`define INSTR_LH (32'b??_?????_?????_?????_001??_???00_00011)\n`define INSTR_LW (32'b??_?????_?????_?????_010??_???00_00011)\n`define INSTR_LBU (32'b??_?????_?????_?????_100??_???00_00011)\n`define INSTR_LHU (32'b??_?????_?????_?????_101??_???00_00011)\n`define INSTR_SB (32'b??_?????_?????_?????_000??_???01_00011)\n`define INSTR_SH (32'b??_?????_?????_?????_001??_???01_00011)\n`define INSTR_SW (32'b??_?????_?????_?????_010??_???01_00011)\n`define INSTR_ADDI (32'b??_?????_?????_?????_000??_???00_10011)\n`define INSTR_SLTI (32'b??_?????_?????_?????_010??_???00_10011)\n`define INSTR_SLTIU (32'b??_?????_?????_?????_011??_???00_10011)\n`define INSTR_XORI (32'b??_?????_?????_?????_100??_???00_10011)\n`define INSTR_ORI (32'b??_?????_?????_?????_110??_???00_10011)\n`define INSTR_ANDI (32'b??_?????_?????_?????_111??_???00_10011)\n`define INSTR_SLLI (32'b00_00000_?????_?????_001??_???00_10011)\n`define INSTR_SRLI (32'b00_00000_?????_?????_101??_???00_10011)\n`define INSTR_SRAI (32'b01_00000_?????_?????_101??_???00_10011)\n`define INSTR_ADD (32'b00_00000_?????_?????_000??_???01_10011)\n`define INSTR_SUB (32'b01_00000_?????_?????_000??_???01_10011)\n`define INSTR_SLL (32'b00_00000_?????_?????_001??_???01_10011)\n`define INSTR_SLT (32'b00_00000_?????_?????_010??_???01_10011)\n`define INSTR_SLTU (32'b00_00000_?????_?????_011??_???01_10011)\n`define INSTR_XOR (32'b00_00000_?????_?????_100??_???01_10011)\n`define INSTR_SRL (32'b00_00000_?????_?????_101??_???01_10011)\n`define INSTR_SRA (32'b01_00000_?????_?????_101??_???01_10011)\n`define INSTR_OR (32'b00_00000_?????_?????_110??_???01_10011)\n`define INSTR_AND (32'b00_00000_?????_?????_111??_???01_10011)\n`define INSTR_ECALL (32'b??_0????_????0_?????_000??_???11_10011)\n`define INSTR_EBREAK (32'b??_0????_????1_?????_000??_???11_10011)\n`define INSTR_CSRRW (32'b??_?????_?????_?????_001??_???11_10011)\n`define INSTR_CSRRS (32'b??_?????_?????_?????_010??_???11_10011)\n`define INSTR_CSRRC (32'b??_?????_?????_?????_011??_???11_10011)\n`define INSTR_CSRRWI (32'b??_?????_?????_?????_101??_???11_10011)\n`define INSTR_CSRRSI (32'b??_?????_?????_?????_110??_???11_10011)\n`define INSTR_CSRRCI (32'b??_?????_?????_?????_111??_???11_10011)\n`define INSTR_MRET (32'b??_1????_?????_?????_000??_???11_10011)\n\nalways_comb begin\n casez(i_fsoc.i_fazyrv_core.wb_imem_dat_i)\n `INSTR_LUI: dbg_ascii_instr = \"lui\";\n `INSTR_AUIPC: dbg_ascii_instr = \"auipc\";\n `INSTR_JAL: dbg_ascii_instr = \"jal\";\n `INSTR_JALR: dbg_ascii_instr = \"jalr\";\n `INSTR_BEQ: dbg_ascii_instr = \"beq\";\n `INSTR_BNE: dbg_ascii_instr = \"bne\";\n `INSTR_BLT: dbg_ascii_instr = \"blt\";\n", "right_context": " `INSTR_BLTU: dbg_ascii_instr = \"bltu\";\n `INSTR_BGEU: dbg_ascii_instr = \"bgeu\";\n `INSTR_LB: dbg_ascii_instr = \"lb\";\n `INSTR_LH: dbg_ascii_instr = \"lh\";\n `INSTR_LW: dbg_ascii_instr = \"lw\";\n `INSTR_LBU: dbg_ascii_instr = \"lbu\";\n `INSTR_LHU: dbg_ascii_instr = \"lhu\";\n `INSTR_SB: dbg_ascii_instr = \"sb\";\n `INSTR_SH: dbg_ascii_instr = \"sh\";\n `INSTR_SW: dbg_ascii_instr = \"sw\";\n `INSTR_ADDI: dbg_ascii_instr = \"addi\";\n `INSTR_SLTI: dbg_ascii_instr = \"slti\";\n `INSTR_SLTIU: dbg_ascii_instr = \"sltiu\";\n `INSTR_XORI: dbg_ascii_instr = \"xori\";\n `INSTR_ORI: dbg_ascii_instr = \"ori\";\n `INSTR_ANDI: dbg_ascii_instr = \"andi\";\n `INSTR_SLLI: dbg_ascii_instr = \"slli\";\n `INSTR_SRLI: dbg_ascii_instr = \"srli\";\n `INSTR_SRAI: dbg_ascii_instr = \"srai\";\n `INSTR_ADD: dbg_ascii_instr = \"add\";\n `INSTR_SUB: dbg_ascii_instr = \"sub\";\n `INSTR_SLL: dbg_ascii_instr = \"sll\";\n `INSTR_SLT: dbg_ascii_instr = \"slt\";\n `INSTR_SLTU: dbg_ascii_instr = \"sltu\";\n `INSTR_XOR: dbg_ascii_instr = \"xor\";\n `INSTR_SRL: dbg_ascii_instr = \"srl\";\n `INSTR_SRA: dbg_ascii_instr = \"sra\";\n `INSTR_OR: dbg_ascii_instr = \"or\";\n `INSTR_AND: dbg_ascii_instr = \"and\";\n `INSTR_CSRRW: dbg_ascii_instr = \"csrrw\";\n `INSTR_CSRRS: dbg_ascii_instr = \"csrrs\";\n `INSTR_CSRRC: dbg_ascii_instr = \"csrrc\";\n `INSTR_CSRRW: dbg_ascii_instr = \"csrrw\";\n `INSTR_CSRRS: dbg_ascii_instr = \"csrrs\";\n `INSTR_CSRRC: dbg_ascii_instr = \"csrrc\";\n `INSTR_CSRRWI: dbg_ascii_instr = \"csrrwi\";\n `INSTR_CSRRSI: dbg_ascii_instr = \"csrrsi\";\n `INSTR_CSRRCI: dbg_ascii_instr = \"csrrci\";\n `INSTR_ECALL: dbg_ascii_instr = \"ecall\";\n `INSTR_EBREAK: dbg_ascii_instr = \"ebreak\";\n `INSTR_MRET: dbg_ascii_instr = \"mret\";\n default: dbg_ascii_instr = \"illegal\";\n endcase\nend\n/* verilator lint_on WIDTHEXPAND */\n\nlogic [1023:0] timing_file;\ninteger f_timing = 0;\nlogic q_r;\n\ninitial begin\n if ($value$plusargs(\"timing=%s\", timing_file)) begin\n f_timing = $fopen(timing_file, \"w\");\n end\nend\n\nalways_ff @(posedge clk_i) begin\n q_r <= q;\nend\n\n(* keep *) logic dly_stb;\nalways_ff @(posedge clk_i) begin\n dly_stb <= i_fsoc.i_fazyrv_core.wb_imem_stb_o;\nend\n\n(* keep *) logic fwrite_stb;\n\ngenerate\nif (MEMDLY1 == 1) begin\n assign fwrite_stb = dly_stb;\nend else begin\n assign fwrite_stb = i_fsoc.i_fazyrv_core.wb_imem_stb_o & i_fsoc.i_fazyrv_core.wb_imem_ack_i;\nend\n\nendgenerate\n\nalways @(posedge clk_i) begin\n if ((f_timing != 0) && (q | q_r)) begin\n if (fwrite_stb) begin\n $fwrite(f_timing, \"## %-s %d\\n\", dbg_ascii_instr, mcycle_r);\n end\n end\n\n if (q_r & ~q) begin\n $fclose(f_timing);\n f_timing = 0;\n end\nend\n\nendmodule\n", "groundtruth": " `INSTR_BGE: dbg_ascii_instr = \"bge\";\n `INSTR_BLTU: dbg_ascii_instr = \"bltu\";\n `INSTR_BGEU: dbg_ascii_instr = \"bgeu\";\n `INSTR_BEQ: dbg_ascii_instr = \"beq\";\n", "crossfile_context": ""} {"task_id": "axi-uvm", "path": "axi-uvm/tb/axi_sequential_reads_test.svh", "left_context": "////////////////////////////////////////////////////////////////////////////////\n//\n// Copyright (C) 2017, Matt Dew @ Dew Technologies, LLC\n//\n// This program is free software (logic verification): you can redistribute it\n// and/or modify it under the terms of the GNU Lesser General Public License (LGPL)\n// as published by the Free Software Foundation, either version 3 of the License,\n// or (at your option) any later version.\n//\n// This program is distributed in the hope that it will be useful, but WITHOUT\n// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License\n// for more details.\n//\n// License:\tLGPL, v3, as defined and found on www.gnu.org,\n//\t\thttp://www.gnu.org/licenses/lgpl.html\n//\n//\n// Author's intent: If you use this AXI verification code and find or fix bugs\n// or make improvements, then share those fixes or improvements.\n// If you use this in a bigger project, I don't care about,\n// or want, any changes or code outside this block.\n// Example: If you use this in an SoC simulation/testbench\n// I don't want, or care about, your SoC or other blocks.\n// I just care about the enhancements to these AXI files.\n// That's why I have choosen the LGPL instead of the GPL.\n////////////////////////////////////////////////////////////////////////////////\n/*! \\class axi_sequential_reads_test\n * \\brief Sequential AXI reads. No pipelining.\n *\n * Backdoor write memory, then Send ReadAddress, wait for ReadData and verify.\n * Then repeat.\n */\nclass axi_sequential_reads_test extends axi_base_test;\n\n `uvm_component_utils(axi_sequential_reads_test)\n\n axi_agent_config driver_agent_config;\n axi_agent_config responder_agent_config;\n\n", "right_context": " super.new(name, parent);\n endfunction : new\n\n function void build_phase(uvm_phase phase);\n\n axi_seq::type_id::set_type_override(axi_sequential_reads_seq::get_type(), 1);\n\n driver_agent_config = axi_agent_config::type_id::create(\"driver_agent_config\", this);\n\n\n assert(driver_agent_config.randomize() with {\n //bready_toggle_pattern == 32'hFFFF_FFFF;\n // rready_toggle_pattern == 32'hFFFF_FFFF;\n\n // these don't matter for sequential since\n // they wont be back to back\n min_clks_between_ar_transfers == 0;\n max_clks_between_ar_transfers == 3;\n min_clks_between_aw_transfers == 0;\n max_clks_between_aw_transfers == 3;\n min_clks_between_w_transfers == 0;\n max_clks_between_w_transfers == 3;\n });\n\n driver_agent_config.m_active = UVM_ACTIVE;\n driver_agent_config.drv_type = e_DRIVER;\n\n // Put the agent_config handle into config_db\n uvm_config_db #(axi_agent_config)::set(null, \"*\", \"m_axidriver_agent.m_config\", driver_agent_config);\n\n\n responder_agent_config = axi_agent_config::type_id::create(\"responder_agent_config\", this);\n\n\n assert(responder_agent_config.randomize() with {\n // awready_toggle_pattern == 32'hFFFF_FFFF;\n // wready_toggle_pattern == 32'h111_1111;\n // arready_toggle_pattern == 32'hFFFF_FFFF;\n\n min_clks_between_r_transfers == 0;\n max_clks_between_r_transfers == 3;\n min_clks_between_b_transfers == 0;\n max_clks_between_b_transfers == 3;\n\n });\n\n responder_agent_config.m_active = UVM_ACTIVE;\n responder_agent_config.drv_type = e_RESPONDER;\n responder_agent_config.axi_incompatible_wvalid_toggling_mode=0;\n\n //responder_agent_config.rvalid = new[1];\n //responder_agent_config.rvalid[0] = 1'b1;\n\n // Put the agent_config handle into config_db\n uvm_config_db #(axi_agent_config)::set(null, \"*\", \"m_axiresponder_agent.m_config\", responder_agent_config);\n\n\n super.build_phase(phase);\n\n endfunction : build_phase\n\n task run_phase(uvm_phase phase);\n\n //bit valid[];\n\n phase.raise_objection(this);\n\n fork\n m_resp_seq.start(m_env.m_responder_seqr);\n join_none\n\n\n m_seq.start(m_env.m_driver_seqr);\n\n\n phase.drop_objection(this);\n endtask : run_phase\n\n\nendclass : axi_sequential_reads_test\n", "groundtruth": " function new (string name=\"axi_sequential_reads_test\", uvm_component parent=null);\n", "crossfile_context": ""} {"task_id": "openfpga-pokemonmini", "path": "openfpga-pokemonmini/src/fpga/core/rtl/key_input.sv", "left_context": "module key_input\n(\n input clk,\n input clk_ce,\n input reset,\n input [8:0] keys_active,\n input [23:0] bus_address_in,\n output logic [7:0] bus_data_out,\n output logic [8:0] key_irqs\n);\n\nwire [7:0] reg_keys = reset ? 8'hFF: ~keys_active[7:0];\n\nreg [8:0] key_latches;\nalways @ (posedge clk)\nbegin\n if(clk_ce)\n", "right_context": " end\nend\n\n\nalways_comb\nbegin\n bus_data_out = 0;\n if(bus_address_in == 24'h2052)\n bus_data_out = reg_keys;\nend\n\nendmodule\n", "groundtruth": " begin\n for(int i = 0; i < 9; ++i)\n begin\n key_irqs[i] <= 0;\n key_latches[i] <= keys_active[i];\n", "crossfile_context": ""} {"task_id": "tang-nano-9k--riscv--cache-psram", "path": "tang-nano-9k--riscv--cache-psram/notes/miscellaneous/study-fluke-with-version-of-uarttx/uarttx.sv", "left_context": "//\n// UART transmitter\n//\n// reviewed 2024-06-25\n//\n`timescale 1ns / 1ps\n//\n`default_nettype none\n// `define DBG\n// `define INFO\n\nmodule uarttx #(\n parameter int unsigned ClockFrequencyHz = 66_000_000,\n parameter int unsigned BaudRate = 9600\n) (\n input wire rst_n,\n input wire clk,\n\n input wire [7:0] data,\n // data to send\n\n input wire go,\n // enable to start transmission\n // disable after 'busy' has gone low to acknowledge that data has been sent\n // then enable to start sending new data\n\n output logic tx,\n // UART tx wire\n\n output logic busy\n // enabled while sending\n // after sending, 'busy' is set to low and needs to be acknowledged by setting 'go' low\n // before transmitting new 'data' by enabling 'go'\n);\n\n localparam int unsigned BIT_TIME = ClockFrequencyHz / BaudRate;\n\n typedef enum {\n Idle,\n StartBit,\n DataBits,\n StopBit,\n WaitForGoLow\n } state_e;\n\n state_e state;\n\n logic [2:0] bit_count; // 3 bits to fit number 7\n\n logic [(BIT_TIME == 1 ? 1 : $clog2(BIT_TIME))-1:0] bit_time_counter;\n\n always_comb begin\n unique case (state)\n\n Idle: begin\n if (go) begin\n // start sending start bit in this cycle\n tx = 0;\n busy = 1;\n end else begin\n tx = 1;\n busy = 0;\n end\n\n // this also flukes:\n // tx = go ? 0 : 1;\n // busy = go ? 1 : 0;\n\n end\n\n StartBit: begin\n tx = 0;\n busy = 1;\n end\n\n DataBits: begin\n tx = data[bit_count];\n busy = 1;\n end\n\n StopBit: begin\n tx = 1;\n busy = 1;\n end\n\n WaitForGoLow: begin\n tx = 1;\n busy = 0;\n end\n\n default: begin\n // note: not necessary but otherwise Gowin EDA 1.9.10.03 Educational\n // infers latches for 'busy' and 'tx'\n tx = 1;\n busy = 0;\n end\n\n endcase\n end\n\n always_ff @(posedge clk) begin\n if (!rst_n) begin\n state <= Idle;\n end else begin\n unique case (state)\n\n Idle: begin\n if (go) begin\n // start bit starts sending during this cycle\n if (BIT_TIME == 1) begin\n // special case: full start bit was sent during\n // this cycle. jump to send data bits\n bit_time_counter <= BIT_TIME - 1;\n bit_count <= 0;\n state <= DataBits;\n end else begin\n bit_time_counter <= BIT_TIME - 2;\n // note: -1 because first cycle in the start bit\n // is sent during this cycle and another -1 \n // because of the comparison when non-blocking \n // assignments\n state <= StartBit;\n end\n end\n end\n\n StartBit: begin\n bit_time_counter <= bit_time_counter - 1'b1;\n if (bit_time_counter == 0) begin\n bit_time_counter <= BIT_TIME - 1;\n bit_count <= 0;\n", "right_context": " bit_time_counter <= BIT_TIME - 1;\n bit_count <= bit_count + 1'b1;\n if (bit_count == 8 - 1) begin\n state <= StopBit;\n end\n end\n end\n\n StopBit: begin\n bit_time_counter <= bit_time_counter - 1'b1;\n if (bit_time_counter == 0) begin\n state <= WaitForGoLow;\n end\n end\n\n WaitForGoLow: begin\n // wait for acknowledge that 'data' has been sent\n if (!go) begin\n state <= Idle;\n end\n end\n\n default: ; // note: not necessary\n\n endcase\n end\n end\n\nendmodule\n\n`undef DBG\n`undef INFO\n`default_nettype wire\n", "groundtruth": " state <= DataBits;\n end\n end\n\n", "crossfile_context": ""} {"task_id": "pulp_cluster", "path": "pulp_cluster/tb/mock_uart.sv", "left_context": "// Copyright 2018 ETH Zurich and University of Bologna.\n// Copyright and related rights are licensed under the Solderpad Hardware\n// License, Version 0.51 (the \"License\"); you may not use this file except in\n// compliance with the License. You may obtain a copy of the License at\n// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law\n// or agreed to in writing, software, hardware and materials distributed under\n// this License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n// CONDITIONS OF ANY KIND, either express or implied. See the License for the\n// specific language governing permissions and limitations under the License.\n//\n// Author: Florian Zaruba, ETH Zurich\n// Date: 28/09/2018\n// Description: Mock replacement for UART in testbench (not synthesiesable!)\n \nmodule mock_uart #(\n parameter int UART_IDX = 0\n )(\n input logic clk_i,\n input logic rst_ni,\n input logic penable_i,\n input logic pwrite_i,\n input logic [31:0] paddr_i,\n input logic psel_i,\n input logic [31:0] pwdata_i,\n output logic [31:0] prdata_o,\n output logic pready_o,\n output logic pslverr_o\n);\n localparam RBR = 0;\n localparam THR = 0;\n localparam IER = 1;\n localparam IIR = 2;\n localparam FCR = 2;\n localparam LCR = 3;\n localparam MCR = 4;\n localparam LSR = 5;\n localparam MSR = 6;\n localparam SCR = 7;\n localparam DLL = 0;\n localparam DLM = 1;\n\n localparam THRE = 5; // transmit holding register empty\n localparam TEMT = 6; // transmit holding register empty\n\n byte lcr = 0;\n byte dlm = 0;\n byte dll = 0;\n byte mcr = 0;\n byte lsr = 0;\n byte ier = 0;\n byte msr = 0;\n byte scr = 0;\n logic fifo_enabled = 1'b0;\n\n integer charnum = 0;\n logic [256*8-1:0] stringa = '0;\n\n assign pready_o = 1'b1;\n assign pslverr_o = 1'b0;\n\n function void uart_tx(byte ch);\n if(ch==8'h0A) begin\n $display(\"[TB UART %2d] %s\", UART_IDX, stringa); \n charnum = 0;\n stringa = '0;\n end else begin\n stringa[(255-charnum)*8 +: 8] = ch;\n charnum = charnum + 1;\n end\n endfunction : uart_tx\n\n always_ff @(posedge clk_i or negedge rst_ni) begin\n if (rst_ni) begin\n if (psel_i & penable_i & pwrite_i) begin\n case ((paddr_i >> 'h2) & 'h7)\n THR: begin\n if (lcr & 'h80) dll <= byte'(pwdata_i[7:0]);\n else begin\n uart_tx(byte'(pwdata_i[7:0]));\n end\n end\n IER: begin\n if (lcr & 'h80) dlm <= byte'(pwdata_i[7:0]);\n else ier <= byte'(pwdata_i[7:0] & 'hF);\n end\n FCR: begin\n if (pwdata_i[0]) fifo_enabled <= 1'b1;\n else fifo_enabled <= 1'b0;\n end\n", "right_context": " end\n end\n end\n\n always_comb begin\n prdata_o = '0;\n if (psel_i & penable_i & ~pwrite_i) begin\n case ((paddr_i >> 'h2) & 'h7)\n THR: begin\n if (lcr & 'h80) prdata_o = {24'b0, dll};\n end\n IER: begin\n if (lcr & 'h80) prdata_o = {24'b0, dlm};\n else prdata_o = {24'b0, ier};\n end\n IIR: begin\n if (fifo_enabled) prdata_o = {24'b0, 8'hc0};\n else prdata_o = {24'b0, 8'b0};\n end\n LCR: prdata_o = {24'b0, lcr};\n MCR: prdata_o = {24'b0, mcr};\n LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))};\n MSR: prdata_o = {24'b0, msr};\n SCR: prdata_o = {24'b0, scr};\n default:;\n endcase\n end\n end\nendmodule\n", "groundtruth": " LCR: lcr <= byte'(pwdata_i[7:0]);\n MCR: mcr <= byte'(pwdata_i[7:0] & 'h1F);\n LSR: lsr <= byte'(pwdata_i[7:0]);\n MSR: msr <= byte'(pwdata_i[7:0]);\n", "crossfile_context": ""} {"task_id": "svaunit", "path": "svaunit/sv/svaunit_sequence_test.svh", "left_context": "/******************************************************************************\n * (C) Copyright 2015 AMIQ Consulting\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * MODULE: svaunit_sequence_test.svh\n * PROJECT: svaunit\n * Description: svaunit test class which starts a sequence\n *******************************************************************************/\n\n`ifndef SVAUNIT_SEQUENCE_TEST_SVH\n`define SVAUNIT_SEQUENCE_TEST_SVH\n\n/* SVAUnit test class which starts a sequence\n * SEQ_TYPE : sequence type used to check a scenario\n */\n", "right_context": " `uvm_component_param_utils(svaunit_sequence_test#(SEQ_TYPE))\n\n // Sequence which contains the SVA scenario\n SEQ_TYPE seq;\n\n /* Constructor for svaunit_sequence_test\n * @param name : instance name for svaunit_sequence_test object\n * @param parent : hierarchical parent for svaunit_sequence_test\n */\n function new(string name=\"svaunit_sequence_test\", uvm_component parent);\n super.new(name, parent);\n endfunction\n\n // Will set the name of the current test\n virtual function void set_name_for_test();\n update_test_name(seq.get_test_name());\n endfunction\n\n /* Form the test topology as a tree\n * @param a_level : the level where the test is created\n * @return a string representing the tree\n */\n virtual function string form_tree(int a_level);\n string extra = \"\";\n\n for(int level_idx = 0; level_idx < a_level; level_idx++) begin\n extra = {\"\\t\", extra};\n end\n\n return $sformatf(\"%s%s\", extra, seq.form_tree(a_level));\n endfunction\n\n // Task used to start testing - a sequence will be started here\n virtual task test();\n if(!seq.randomize()) begin\n `uvm_error(\"SVAUNIT_SEQUENCE_TEST_RANDOMIZE_ERR\",\n $sformatf(\"The sequence for %s could not be randomize\", get_test_name()))\n end\n seq.start(sequencer);\n endtask\nendclass\n\n`endif\n", "groundtruth": "class svaunit_sequence_test#(type SEQ_TYPE=svaunit_base_sequence) extends svaunit_test;\n", "crossfile_context": ""} {"task_id": "zerosoc", "path": "zerosoc/hw/prim/prim_pad_wrapper.sv", "left_context": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n\n// This file is auto-generated.\n\n`ifndef PRIM_DEFAULT_IMPL\n `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric\n`endif\n\n// This is to prevent AscentLint warnings in the generated\n// abstract prim wrapper. These warnings occur due to the .*\n// use. TODO: we may want to move these inline waivers\n// into a separate, generated waiver file for consistency.\n//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ\nmodule prim_pad_wrapper\nimport prim_pad_wrapper_pkg::*;\n#(\n\n // These parameters are ignored in this model.\n parameter pad_type_e PadType = BidirStd,\n parameter scan_role_e ScanRole = NoScan\n\n) (\n // This is only used for scanmode (not used in generic models)\n input clk_scan_i,\n input scanmode_i,\n // Power sequencing signals (not used in generic models)\n input pad_pok_t pok_i,\n // Main Pad signals\n", "right_context": "\nif (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx\n prim_xilinx_pad_wrapper #(\n .PadType(PadType),\n .ScanRole(ScanRole)\n ) u_impl_xilinx (\n .*\n );\nend else begin : gen_generic\n prim_generic_pad_wrapper #(\n .PadType(PadType),\n .ScanRole(ScanRole)\n ) u_impl_generic (\n .*\n );\nend\n\nendmodule\n//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ\n", "groundtruth": " inout wire inout_io, // bidirectional pad\n output logic in_o, // input data\n output logic in_raw_o, // uninverted output data\n input ie_i, // input enable\n input out_i, // output data\n", "crossfile_context": ""} {"task_id": "rtl-fuzz-lab", "path": "rtl-fuzz-lab/test/resources/fuzzing/aes_opentitan/aes_core.sv", "left_context": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n//\n// AES core implementation\n\n`include \"prim_assert.sv\"\n\nmodule aes_core\n import aes_pkg::*;\n import aes_reg_pkg::*;\n#(\n parameter bit AES192Enable = 1,\n parameter bit Masking = 0,\n parameter sbox_impl_e SBoxImpl = SBoxImplLut,\n parameter int unsigned SecStartTriggerDelay = 0,\n parameter bit SecAllowForcingMasks = 0,\n\n localparam int NumShares = Masking ? 2 : 1, // derived parameter\n\n parameter logic [WidthPRDClearing-1:0] SeedClearing = DefaultSeedClearing,\n parameter logic [WidthPRDMasking-1:0] SeedMasking = DefaultSeedMasking\n) (\n input logic clk_i,\n input logic rst_ni,\n\n // Entropy request interfaces for clearing and masking PRNGs\n output logic entropy_clearing_req_o,\n input logic entropy_clearing_ack_i,\n input logic [WidthPRDClearing-1:0] entropy_clearing_i,\n output logic entropy_masking_req_o,\n input logic entropy_masking_ack_i,\n input logic [WidthPRDMasking-1:0] entropy_masking_i,\n\n // Alerts\n output logic ctrl_err_update_o,\n output logic ctrl_err_storage_o,\n\n // Bus Interface\n input aes_reg2hw_t reg2hw,\n output aes_hw2reg_t hw2reg\n);\n\n // Signals\n logic ctrl_re;\n logic ctrl_qe;\n logic ctrl_we;\n aes_op_e aes_op_q;\n aes_mode_e mode;\n aes_mode_e aes_mode_q;\n ciph_op_e cipher_op;\n key_len_e key_len;\n key_len_e key_len_q;\n logic manual_operation_q;\n logic force_zero_masks_q;\n ctrl_reg_t ctrl_d, ctrl_q;\n\n logic [3:0][3:0][7:0] state_in;\n si_sel_e state_in_sel;\n logic [3:0][3:0][7:0] add_state_in;\n add_si_sel_e add_state_in_sel;\n\n logic [3:0][3:0][7:0] state_mask;\n logic [3:0][3:0][7:0] state_init [NumShares];\n logic [3:0][3:0][7:0] state_done [NumShares];\n logic [3:0][3:0][7:0] state_out;\n\n logic [7:0][31:0] key_init [2];\n logic [7:0] key_init_qe [2];\n logic [7:0][31:0] key_init_d [2];\n logic [7:0][31:0] key_init_q [2];\n logic [7:0][31:0] key_init_cipher [NumShares];\n logic [7:0] key_init_we [2];\n key_init_sel_e key_init_sel;\n\n logic [3:0][31:0] iv;\n logic [3:0] iv_qe;\n logic [7:0][15:0] iv_d;\n logic [7:0][15:0] iv_q;\n logic [7:0] iv_we;\n iv_sel_e iv_sel;\n\n logic [7:0][15:0] ctr;\n logic [7:0] ctr_we;\n logic ctr_incr;\n logic ctr_ready;\n\n logic [3:0][31:0] data_in_prev_d;\n logic [3:0][31:0] data_in_prev_q;\n logic data_in_prev_we;\n dip_sel_e data_in_prev_sel;\n\n logic [3:0][31:0] data_in;\n logic [3:0] data_in_qe;\n logic data_in_we;\n\n logic [3:0][3:0][7:0] add_state_out;\n add_so_sel_e add_state_out_sel;\n\n logic [3:0][31:0] data_out_d;\n logic [3:0][31:0] data_out_q;\n logic data_out_we;\n logic [3:0] data_out_re;\n\n logic cipher_in_valid;\n logic cipher_in_ready;\n logic cipher_out_valid;\n logic cipher_out_ready;\n logic cipher_crypt;\n logic cipher_crypt_busy;\n logic cipher_dec_key_gen;\n logic cipher_dec_key_gen_busy;\n logic cipher_key_clear;\n logic cipher_key_clear_busy;\n logic cipher_data_out_clear;\n logic cipher_data_out_clear_busy;\n\n // Pseudo-random data for clearing purposes\n logic [WidthPRDClearing-1:0] prd_clearing;\n logic prd_clearing_upd_req;\n logic prd_clearing_upd_ack;\n logic prd_clearing_rsd_req;\n logic prd_clearing_rsd_ack;\n logic [127:0] prd_clearing_128;\n logic [255:0] prd_clearing_256;\n\n // Unused signals\n logic [3:0][31:0] unused_data_out_q;\n logic unused_force_zero_masks;\n\n // The clearing PRNG provides pseudo-random data for register clearing purposes.\n aes_prng_clearing #(\n .Width ( WidthPRDClearing ),\n .DefaultSeed ( SeedClearing )\n ) u_aes_prng_clearing (\n .clk_i ( clk_i ),\n .rst_ni ( rst_ni ),\n\n .data_req_i ( prd_clearing_upd_req ),\n .data_ack_o ( prd_clearing_upd_ack ),\n .data_o ( prd_clearing ),\n .reseed_req_i ( prd_clearing_rsd_req ),\n .reseed_ack_o ( prd_clearing_rsd_ack ),\n\n .entropy_req_o ( entropy_clearing_req_o ),\n .entropy_ack_i ( entropy_clearing_ack_i ),\n .entropy_i ( entropy_clearing_i )\n );\n\n // Generate clearing signals of appropriate widths.\n localparam int unsigned NumChunks = 128/WidthPRDClearing;\n for (genvar c = 0; c < NumChunks; c++) begin : gen_prd_clearing\n assign prd_clearing_128[c * WidthPRDClearing +: WidthPRDClearing] = prd_clearing;\n assign prd_clearing_256[c * WidthPRDClearing +: WidthPRDClearing] = prd_clearing;\n assign prd_clearing_256[c * WidthPRDClearing + 128 +: WidthPRDClearing] = prd_clearing;\n end\n\n ////////////\n // Inputs //\n ////////////\n\n always_comb begin : key_init_get\n for (int i=0; i<8; i++) begin\n key_init[0][i] = reg2hw.key_share0[i].q;\n key_init_qe[0][i] = reg2hw.key_share0[i].qe;\n key_init[1][i] = reg2hw.key_share1[i].q;\n key_init_qe[1][i] = reg2hw.key_share1[i].qe;\n end\n end\n\n always_comb begin : iv_get\n for (int i=0; i<4; i++) begin\n iv[i] = reg2hw.iv[i].q;\n iv_qe[i] = reg2hw.iv[i].qe;\n end\n end\n\n always_comb begin : data_in_get\n for (int i=0; i<4; i++) begin\n data_in[i] = reg2hw.data_in[i].q;\n data_in_qe[i] = reg2hw.data_in[i].qe;\n end\n end\n\n always_comb begin : data_out_get\n for (int i=0; i<4; i++) begin\n // data_out is actually hwo, but we need hrw for hwre\n unused_data_out_q[i] = reg2hw.data_out[i].q;\n data_out_re[i] = reg2hw.data_out[i].re;\n end\n end\n\n //////////////////////\n // Key, IV and Data //\n //////////////////////\n\n // Initial Key registers\n always_comb begin : key_init_mux\n", "right_context": " for (int i=0; i<8; i++) begin\n if (key_init_we[s][i]) begin\n key_init_q[s][i] <= key_init_d[s][i];\n end\n end\n end\n end\n\n // IV registers\n always_comb begin : iv_mux\n unique case (iv_sel)\n IV_INPUT: iv_d = iv;\n IV_DATA_OUT: iv_d = data_out_d;\n IV_DATA_OUT_RAW: iv_d = aes_transpose(state_out);\n IV_DATA_IN_PREV: iv_d = data_in_prev_q;\n IV_CTR: iv_d = ctr;\n IV_CLEAR: iv_d = prd_clearing_128;\n default: iv_d = prd_clearing_128;\n endcase\n end\n\n always_ff @(posedge clk_i) begin : iv_reg\n for (int i=0; i<8; i++) begin\n if (iv_we[i]) begin\n iv_q[i] <= iv_d[i];\n end\n end\n end\n\n // Previous input data register\n always_comb begin : data_in_prev_mux\n unique case (data_in_prev_sel)\n DIP_DATA_IN: data_in_prev_d = data_in;\n DIP_CLEAR: data_in_prev_d = prd_clearing_128;\n default: data_in_prev_d = prd_clearing_128;\n endcase\n end\n\n always_ff @(posedge clk_i) begin : data_in_prev_reg\n if (data_in_prev_we) begin\n data_in_prev_q <= data_in_prev_d;\n end\n end\n\n /////////////\n // Counter //\n /////////////\n\n aes_ctr u_aes_ctr (\n .clk_i ( clk_i ),\n .rst_ni ( rst_ni ),\n\n .incr_i ( ctr_incr ),\n .ready_o ( ctr_ready ),\n\n .ctr_i ( iv_q ),\n .ctr_o ( ctr ),\n .ctr_we_o ( ctr_we )\n );\n\n /////////////////\n // Cipher Core //\n /////////////////\n\n // Cipher core operation\n assign cipher_op = (aes_mode_q == AES_ECB && aes_op_q == AES_ENC) ? CIPH_FWD :\n (aes_mode_q == AES_ECB && aes_op_q == AES_DEC) ? CIPH_INV :\n (aes_mode_q == AES_CBC && aes_op_q == AES_ENC) ? CIPH_FWD :\n (aes_mode_q == AES_CBC && aes_op_q == AES_DEC) ? CIPH_INV :\n (aes_mode_q == AES_CFB) ? CIPH_FWD :\n (aes_mode_q == AES_OFB) ? CIPH_FWD :\n (aes_mode_q == AES_CTR) ? CIPH_FWD : CIPH_FWD;\n\n // Convert input data/IV to state format (every word corresponds to one state column).\n // Mux for state input\n always_comb begin : state_in_mux\n unique case (state_in_sel)\n SI_ZERO: state_in = '0;\n SI_DATA: state_in = aes_transpose(data_in);\n default: state_in = '0;\n endcase\n end\n\n // Mux for addition to state input\n always_comb begin : add_state_in_mux\n unique case (add_state_in_sel)\n ADD_SI_ZERO: add_state_in = '0;\n ADD_SI_IV: add_state_in = aes_transpose(iv_q);\n default: add_state_in = '0;\n endcase\n end\n\n if (!Masking) begin : gen_state_init_unmasked\n assign state_init[0] = state_in ^ add_state_in;\n\n logic [3:0][3:0][7:0] unused_state_mask;\n assign unused_state_mask = state_mask;\n\n end else begin : gen_state_init_masked\n assign state_init[0] = (state_in ^ add_state_in) ^ state_mask; // Masked data share\n assign state_init[1] = state_mask; // Mask share\n end\n\n if (!Masking) begin : gen_key_init_unmasked\n // Combine the two key shares for the unmasked cipher core. This causes SCA leakage of the key\n // and thus should be avoided.\n assign key_init_cipher[0] = key_init_q[0] ^ key_init_q[1];\n\n end else begin : gen_key_init_masked\n // Forward the masked key share and the mask share to the masked cipher core.\n assign key_init_cipher = key_init_q;\n end\n\n // Cipher core\n aes_cipher_core #(\n .AES192Enable ( AES192Enable ),\n .Masking ( Masking ),\n .SBoxImpl ( SBoxImpl ),\n .SecAllowForcingMasks ( SecAllowForcingMasks ),\n .SeedMasking ( SeedMasking )\n ) u_aes_cipher_core (\n .clk_i ( clk_i ),\n .rst_ni ( rst_ni ),\n\n .in_valid_i ( cipher_in_valid ),\n .in_ready_o ( cipher_in_ready ),\n\n .out_valid_o ( cipher_out_valid ),\n .out_ready_i ( cipher_out_ready ),\n\n .cfg_valid_i ( ~ctrl_err_storage_o ),\n .op_i ( cipher_op ),\n .key_len_i ( key_len_q ),\n .crypt_i ( cipher_crypt ),\n .crypt_o ( cipher_crypt_busy ),\n .dec_key_gen_i ( cipher_dec_key_gen ),\n .dec_key_gen_o ( cipher_dec_key_gen_busy ),\n .key_clear_i ( cipher_key_clear ),\n .key_clear_o ( cipher_key_clear_busy ),\n .data_out_clear_i ( cipher_data_out_clear ),\n .data_out_clear_o ( cipher_data_out_clear_busy ),\n\n .prd_clearing_i ( prd_clearing ),\n\n .force_zero_masks_i ( force_zero_masks_q ),\n .data_in_mask_o ( state_mask ),\n .entropy_req_o ( entropy_masking_req_o ),\n .entropy_ack_i ( entropy_masking_ack_i ),\n .entropy_i ( entropy_masking_i ),\n\n .state_init_i ( state_init ),\n .key_init_i ( key_init_cipher ),\n .state_o ( state_done )\n );\n\n if (!Masking) begin : gen_state_out_unmasked\n assign state_out = state_done[0];\n end else begin : gen_state_out_masked\n // Unmask the cipher core output. This causes SCA leakage and should thus be avoided. This will\n // be reworked in the future when masking the counter and feedback path through the IV regs.\n assign state_out = state_done[0] ^ state_done[1];\n end\n\n // Mux for addition to state output\n always_comb begin : add_state_out_mux\n unique case (add_state_out_sel)\n ADD_SO_ZERO: add_state_out = '0;\n ADD_SO_IV: add_state_out = aes_transpose(iv_q);\n ADD_SO_DIP: add_state_out = aes_transpose(data_in_prev_q);\n default: add_state_out = '0;\n endcase\n end\n\n // Convert output state to output data format (every column corresponds to one output word).\n assign data_out_d = aes_transpose(state_out ^ add_state_out);\n\n //////////////////////\n // Control Register //\n //////////////////////\n\n // Get and resolve values from register interface.\n assign ctrl_d.operation = aes_op_e'(reg2hw.ctrl_shadowed.operation.q);\n\n assign mode = aes_mode_e'(reg2hw.ctrl_shadowed.mode.q);\n always_comb begin : mode_get\n unique case (mode)\n AES_ECB: ctrl_d.mode = AES_ECB;\n AES_CBC: ctrl_d.mode = AES_CBC;\n AES_CFB: ctrl_d.mode = AES_CFB;\n AES_OFB: ctrl_d.mode = AES_OFB;\n AES_CTR: ctrl_d.mode = AES_CTR;\n default: ctrl_d.mode = AES_NONE; // unsupported values are mapped to AES_NONE\n endcase\n end\n\n assign key_len = key_len_e'(reg2hw.ctrl_shadowed.key_len.q);\n always_comb begin : key_len_get\n unique case (key_len)\n AES_128: ctrl_d.key_len = AES_128;\n AES_256: ctrl_d.key_len = AES_256;\n AES_192: ctrl_d.key_len = AES192Enable ? AES_192 : AES_256;\n default: ctrl_d.key_len = AES_256; // unsupported values are mapped to AES_256\n endcase\n end\n\n assign ctrl_d.manual_operation = reg2hw.ctrl_shadowed.manual_operation.q;\n\n // SecAllowForcingMasks forbids forcing the masks. Forcing the masks to zero is only\n // useful for SCA.\n assign ctrl_d.force_zero_masks = SecAllowForcingMasks ?\n reg2hw.ctrl_shadowed.force_zero_masks.q : 1'b0;\n assign unused_force_zero_masks = SecAllowForcingMasks ?\n 1'b0 : reg2hw.ctrl_shadowed.force_zero_masks.q;\n\n // Get and forward write enable. Writes are only allowed if the module is idle.\n assign ctrl_re = reg2hw.ctrl_shadowed.operation.re & reg2hw.ctrl_shadowed.mode.re &\n reg2hw.ctrl_shadowed.key_len.re & reg2hw.ctrl_shadowed.manual_operation.re &\n reg2hw.ctrl_shadowed.force_zero_masks.re;\n assign ctrl_qe = reg2hw.ctrl_shadowed.operation.qe & reg2hw.ctrl_shadowed.mode.qe &\n reg2hw.ctrl_shadowed.key_len.qe & reg2hw.ctrl_shadowed.manual_operation.qe &\n reg2hw.ctrl_shadowed.force_zero_masks.qe;\n\n // Shadowed register primitve\n prim_subreg_shadow #(\n .DW ( $bits(ctrl_reg_t) ),\n .SWACCESS ( \"WO\" ),\n .RESVAL ( CTRL_RESET )\n ) u_ctrl_reg_shadowed (\n .clk_i ( clk_i ),\n .rst_ni ( rst_ni ),\n .re ( ctrl_re ),\n .we ( ctrl_we ),\n .wd ( ctrl_d ),\n .de ( 1'b0 ),\n .d ( '0 ),\n .qe ( ),\n .q ( ctrl_q ),\n .qs ( ),\n .err_update ( ctrl_err_update_o ),\n .err_storage ( ctrl_err_storage_o )\n );\n\n // Make sure the storage error is observable via status register.\n assign hw2reg.status.ctrl_err_storage.d = ctrl_err_storage_o;\n assign hw2reg.status.ctrl_err_storage.de = ctrl_err_storage_o;\n\n // Get shorter references.\n assign aes_op_q = ctrl_q.operation;\n assign aes_mode_q = ctrl_q.mode;\n assign key_len_q = ctrl_q.key_len;\n assign manual_operation_q = ctrl_q.manual_operation;\n assign force_zero_masks_q = ctrl_q.force_zero_masks;\n\n // Unused alert signals\n logic unused_alert_signals;\n assign unused_alert_signals = ^reg2hw.alert_test;\n\n /////////////\n // Control //\n /////////////\n\n // Control\n aes_control #(\n .SecStartTriggerDelay ( SecStartTriggerDelay )\n ) u_aes_control (\n .clk_i ( clk_i ),\n .rst_ni ( rst_ni ),\n\n .ctrl_qe_i ( ctrl_qe ),\n .ctrl_we_o ( ctrl_we ),\n .ctrl_err_storage_i ( ctrl_err_storage_o ),\n .op_i ( aes_op_q ),\n .mode_i ( aes_mode_q ),\n .cipher_op_i ( cipher_op ),\n .manual_operation_i ( manual_operation_q ),\n .start_i ( reg2hw.trigger.start.q ),\n .key_clear_i ( reg2hw.trigger.key_clear.q ),\n .iv_clear_i ( reg2hw.trigger.iv_clear.q ),\n .data_in_clear_i ( reg2hw.trigger.data_in_clear.q ),\n .data_out_clear_i ( reg2hw.trigger.data_out_clear.q ),\n .prng_reseed_i ( reg2hw.trigger.prng_reseed.q ),\n\n .key_init_qe_i ( key_init_qe ),\n .iv_qe_i ( iv_qe ),\n .data_in_qe_i ( data_in_qe ),\n .data_out_re_i ( data_out_re ),\n .data_in_we_o ( data_in_we ),\n .data_out_we_o ( data_out_we ),\n\n .data_in_prev_sel_o ( data_in_prev_sel ),\n .data_in_prev_we_o ( data_in_prev_we ),\n\n .state_in_sel_o ( state_in_sel ),\n .add_state_in_sel_o ( add_state_in_sel ),\n .add_state_out_sel_o ( add_state_out_sel ),\n\n .ctr_incr_o ( ctr_incr ),\n .ctr_ready_i ( ctr_ready ),\n .ctr_we_i ( ctr_we ),\n\n .cipher_in_valid_o ( cipher_in_valid ),\n .cipher_in_ready_i ( cipher_in_ready ),\n .cipher_out_valid_i ( cipher_out_valid ),\n .cipher_out_ready_o ( cipher_out_ready ),\n .cipher_crypt_o ( cipher_crypt ),\n .cipher_crypt_i ( cipher_crypt_busy ),\n .cipher_dec_key_gen_o ( cipher_dec_key_gen ),\n .cipher_dec_key_gen_i ( cipher_dec_key_gen_busy ),\n .cipher_key_clear_o ( cipher_key_clear ),\n .cipher_key_clear_i ( cipher_key_clear_busy ),\n .cipher_data_out_clear_o ( cipher_data_out_clear ),\n .cipher_data_out_clear_i ( cipher_data_out_clear_busy ),\n\n .key_init_sel_o ( key_init_sel ),\n .key_init_we_o ( key_init_we ),\n .iv_sel_o ( iv_sel ),\n .iv_we_o ( iv_we ),\n\n .prng_data_req_o ( prd_clearing_upd_req ),\n .prng_data_ack_i ( prd_clearing_upd_ack ),\n .prng_reseed_req_o ( prd_clearing_rsd_req ),\n .prng_reseed_ack_i ( prd_clearing_rsd_ack ),\n\n .start_o ( hw2reg.trigger.start.d ),\n .start_we_o ( hw2reg.trigger.start.de ),\n .key_clear_o ( hw2reg.trigger.key_clear.d ),\n .key_clear_we_o ( hw2reg.trigger.key_clear.de ),\n .iv_clear_o ( hw2reg.trigger.iv_clear.d ),\n .iv_clear_we_o ( hw2reg.trigger.iv_clear.de ),\n .data_in_clear_o ( hw2reg.trigger.data_in_clear.d ),\n .data_in_clear_we_o ( hw2reg.trigger.data_in_clear.de ),\n .data_out_clear_o ( hw2reg.trigger.data_out_clear.d ),\n .data_out_clear_we_o ( hw2reg.trigger.data_out_clear.de ),\n .prng_reseed_o ( hw2reg.trigger.prng_reseed.d ),\n .prng_reseed_we_o ( hw2reg.trigger.prng_reseed.de ),\n\n .output_valid_o ( hw2reg.status.output_valid.d ),\n .output_valid_we_o ( hw2reg.status.output_valid.de ),\n .input_ready_o ( hw2reg.status.input_ready.d ),\n .input_ready_we_o ( hw2reg.status.input_ready.de ),\n .idle_o ( hw2reg.status.idle.d ),\n .idle_we_o ( hw2reg.status.idle.de ),\n .stall_o ( hw2reg.status.stall.d ),\n .stall_we_o ( hw2reg.status.stall.de )\n );\n\n // Input data register clear\n always_comb begin : data_in_reg_clear\n for (int i=0; i<4; i++) begin\n hw2reg.data_in[i].d = '0;\n hw2reg.data_in[i].de = data_in_we;\n end\n end\n\n /////////////\n // Outputs //\n /////////////\n\n always_ff @(posedge clk_i) begin : data_out_reg\n if (data_out_we) begin\n data_out_q <= data_out_d;\n end\n end\n\n always_comb begin : key_reg_put\n for (int i=0; i<8; i++) begin\n hw2reg.key_share0[i].d = key_init_q[0][i];\n hw2reg.key_share1[i].d = key_init_q[1][i];\n end\n end\n\n always_comb begin : iv_reg_put\n for (int i=0; i<4; i++) begin\n hw2reg.iv[i].d = {iv_q[2*i+1], iv_q[2*i]};\n end\n end\n\n always_comb begin : data_out_put\n for (int i=0; i<4; i++) begin\n hw2reg.data_out[i].d = data_out_q[i];\n end\n end\n\n assign hw2reg.ctrl_shadowed.mode.d = {aes_mode_q};\n assign hw2reg.ctrl_shadowed.key_len.d = {key_len_q};\n\n // These fields are actually hro. But software must be able observe the current value (rw).\n assign hw2reg.ctrl_shadowed.operation.d = {aes_op_q};\n assign hw2reg.ctrl_shadowed.manual_operation.d = manual_operation_q;\n assign hw2reg.ctrl_shadowed.force_zero_masks.d = force_zero_masks_q;\n\n ////////////////\n // Assertions //\n ////////////////\n\n // Selectors must be known/valid\n `ASSERT_KNOWN(AesKeyInitSelKnown, key_init_sel)\n `ASSERT(AesIvSelValid, iv_sel inside {\n IV_INPUT,\n IV_DATA_OUT,\n IV_DATA_OUT_RAW,\n IV_DATA_IN_PREV,\n IV_CTR,\n IV_CLEAR\n })\n `ASSERT_KNOWN(AesDataInPrevSelKnown, data_in_prev_sel)\n `ASSERT(AesModeValid, !ctrl_err_storage_o |-> aes_mode_q inside {\n AES_ECB,\n AES_CBC,\n AES_CFB,\n AES_OFB,\n AES_CTR,\n AES_NONE\n })\n `ASSERT_KNOWN(AesOpKnown, aes_op_q)\n `ASSERT_KNOWN(AesStateInSelKnown, state_in_sel)\n `ASSERT_KNOWN(AesAddStateInSelKnown, add_state_in_sel)\n `ASSERT(AesAddStateOutSelValid, add_state_out_sel inside {\n ADD_SO_ZERO,\n ADD_SO_IV,\n ADD_SO_DIP\n })\n\nendmodule\n", "groundtruth": " unique case (key_init_sel)\n KEY_INIT_INPUT: key_init_d = key_init;\n KEY_INIT_CLEAR: key_init_d = '{default: prd_clearing_256};\n default: key_init_d = '{default: prd_clearing_256};\n endcase\n", "crossfile_context": ""} {"task_id": "CDIM", "path": "CDIM/mycpu/mycpu_top.sv", "left_context": "module mycpu_top (\n input wire aclk,\n input wire aresetn,\n\n input [5:0] ext_int, //interrupt\n\n output wire[3:0] arid,\n output wire[31:0] araddr,\n output wire[7:0] arlen,\n output wire[2:0] arsize,\n output wire[1:0] arburst,\n output wire[1:0] arlock,\n output wire[3:0] arcache,\n output wire[2:0] arprot,\n output wire arvalid,\n input wire arready,\n \n input wire[3:0] rid,\n input wire[31:0] rdata,\n input wire[1:0] rresp,\n input wire rlast,\n input wire rvalid,\n output wire rready,\n \n output wire[3:0] awid,\n output wire[31:0] awaddr,\n output wire[7:0] awlen,\n output wire[2:0] awsize,\n output wire[1:0] awburst,\n output wire[1:0] awlock,\n output wire[3:0] awcache,\n output wire[2:0] awprot,\n output wire awvalid,\n input wire awready,\n \n output wire[3:0] wid,\n output wire[31:0] wdata,\n output wire[3:0] wstrb,\n output wire wlast,\n output wire wvalid,\n input wire wready,\n \n input wire[3:0] bid,\n input wire[1:0] bresp,\n input bvalid,\n output bready,\n\n //debug interface\n output wire[31:0] debug_wb_pc,\n output wire[3:0] debug_wb_rf_wen,\n output wire[4:0] debug_wb_rf_wnum,\n output wire[31:0] debug_wb_rf_wdata,\n // soc-simulator + cemu debug interface\n output wire [31:0] debug_cp0_count,\n output wire [31:0] debug_cp0_random,\n output wire [31:0] debug_cp0_cause,\n output wire debug_int,\n output wire debug_commit\n);\n wire clk, rst;\n assign clk = aclk; // assign clk = aclk;\n assign rst = ~aresetn;\n\n //d_tlb - d_cache\n wire no_cache_d ; //数据\n wire no_cache_i ; //指令\n\n //datapath - cache\n wire inst_en ;\n wire [31:0] pcF ;\n wire [31:0] pcF_dp ;\n wire [31:0] pc_next ;\n wire [31:0] pc_next_dp ;\n wire i_cache_stall ;\n wire stallF ;\n wire stallM ;\n wire inst_data_ok1 ;\n wire inst_data_ok2 ;\n wire inst_tlb_refill ;\n wire inst_tlb_invalid ;\n wire [31:0] inst_rdata1 ;\n wire [31:0] inst_rdata2 ;\n wire fence_iE;\n wire [31:0] fence_addrE;\n wire fence_dM;\n wire [31:0] fence_addrM;\n wire fence_tlbE;\n wire [31:13]itlb_vpn2;\n wire itlb_found;\n tlb_entry itlb_entry;\n\n wire data_en ;\n wire [31:0] data_addr ;\n wire [31:0] data_addr_dp;\n wire [31:0] data_rdata ;\n wire [ 1:0] data_rlen ;\n wire [3:0] data_wen ;\n wire [31:0] data_wdata ;\n wire d_cache_stall ;\n wire [31:0] mem_addrE ;\n wire [31:0] mem_addrE_dp;\n wire mem_read_enE ;\n wire mem_write_enE ;\n\n //i_cache - arbitrater\n wire [31:0] i_araddr ;\n wire [7:0] i_arlen ;\n wire [2:0] i_arsize ;\n wire i_arvalid ;\n wire i_arready ;\n\n wire [31:0] i_rdata ;\n wire i_rlast ;\n wire i_rvalid ;\n wire i_rready ;\n\n //d_cache - arbitrater\n wire [31:0] d_araddr ;\n wire [7:0] d_arlen ;\n wire [2:0] d_arsize ;\n wire d_arvalid ;\n wire d_arready ;\n\n wire[31:0] d_rdata ;\n wire d_rlast ;\n wire d_rvalid ;\n wire d_rready ;\n\n wire [31:0] d_awaddr ;\n wire [7:0] d_awlen ;\n wire [2:0] d_awsize ;\n wire d_awvalid ;\n wire d_awready ;\n\n wire [31:0] d_wdata ;\n wire [3:0] d_wstrb ;\n wire d_wlast ;\n wire d_wvalid ;\n wire d_wready ;\n\n wire d_bvalid ;\n wire d_bready ;\n\n wire [31:13] dtlb_vpn2;\n wire dtlb_found;\n tlb_entry dtlb_entry;\n wire fence_tlbM;\n\n wire data_tlb_refill;\n wire data_tlb_invalid;\n wire data_tlb_mod;\n\n wire no_cache_E ;\n datapath u_datapath(\n //ports\n .clk \t\t( clk \t\t),\n .rst \t\t( rst \t\t),\n .ext_int \t\t( ext_int \t\t),\n // inst\n .i_stall \t\t( i_cache_stall \t\t),\n .stallF \t\t( stallF \t\t),\n .inst_sram_en \t\t( inst_en \t\t),\n .F_pc \t\t( pcF_dp \t\t),\n .F_pc_next \t\t( pc_next_dp \t\t),\n .inst_data_ok1 \t\t( inst_data_ok1 \t\t),\n .inst_data_ok2 \t\t( inst_data_ok2 \t\t),\n .inst_tlb_refill ( inst_tlb_refill ),\n .inst_tlb_invalid ( inst_tlb_invalid ),\n .inst_rdata1 \t\t( inst_rdata1 \t\t),\n .inst_rdata2 \t\t( inst_rdata2 \t\t),\n .fence_iE ( fence_iE ),\n .fence_addrE ( fence_addrE ),\n .fence_dM ( fence_dM ),\n .fence_addrM ( fence_addrM ),\n .fence_tlbE ( fence_tlbE ),\n .itlb_vpn2 ( itlb_vpn2 ),\n .itlb_found ( itlb_found ),\n .itlb_entry ( itlb_entry ),\n // data\n .d_stall \t\t( d_cache_stall \t),\n .stallM \t\t( stallM \t\t),\n .mem_read_enE \t\t( mem_read_enE \t\t),\n .mem_write_enE \t\t( mem_write_enE \t\t),\n .E_mem_va ( mem_addrE ),\n .mem_addrE \t\t( mem_addrE_dp \t\t), // TODO: delete\n .data_sram_enM \t\t( data_en \t\t),\n .data_sram_rdataM \t\t( data_rdata \t\t),\n .data_sram_rlenM \t\t( data_rlen \t\t),\n .data_sram_wenM \t\t( data_wen \t\t),\n .M_mem_va ( data_addr ),\n .data_sram_addrM \t\t( data_addr_dp \t\t), // TODO: delete\n .data_sram_wdataM \t\t( data_wdata \t\t),\n .dtlb_vpn2 ( dtlb_vpn2 ),\n .dtlb_found ( dtlb_found ),\n .dtlb_entry ( dtlb_entry ),\n .fence_tlbM ( fence_tlbM ),\n .data_tlb_refill ( data_tlb_refill ),\n .data_tlb_invalid ( data_tlb_invalid ),\n .data_tlb_mod ( data_tlb_mod ),\n // debug\n .debug_wb_pc \t\t( debug_wb_pc \t\t),\n .debug_wb_rf_wen \t\t( debug_wb_rf_wen \t\t),\n .debug_wb_rf_wnum \t\t( debug_wb_rf_wnum \t\t),\n .debug_wb_rf_wdata \t\t( debug_wb_rf_wdata \t\t),\n .debug_cp0_count ( debug_cp0_count ),\n .debug_cp0_random ( debug_cp0_random ),\n .debug_cp0_cause ( debug_cp0_cause ),\n .debug_int ( debug_int ),\n .debug_commit ( debug_commit )\n );\n\n i_cache i_cache_inst (\n .clk ( clk ),\n .rst ( rst ),\n .inst_en ( inst_en ),\n .inst_va ( pcF_dp ),\n .inst_va_next ( pc_next_dp ),\n .inst_rdata0 ( inst_rdata1 ),\n .inst_rdata1 ( inst_rdata2 ),\n .inst_ok0 ( inst_data_ok1 ),\n .inst_ok1 ( inst_data_ok2 ),\n .inst_tlb_refill (inst_tlb_refill ),\n .inst_tlb_invalid (inst_tlb_invalid ),\n .stallF ( stallF ),\n .istall ( i_cache_stall ),\n .fence_i ( fence_iE ),\n .fence_addr ( fence_addrE ),\n .fence_tlb ( fence_tlbE ),\n .itlb_vpn2 ( itlb_vpn2 ),\n .itlb_found ( itlb_found ),\n .itlb_entry ( itlb_entry ),\n .araddr ( i_araddr ),\n .arlen ( i_arlen ),\n .arsize ( i_arsize ),\n .arvalid ( i_arvalid ),\n .arready ( i_arready ),\n .rdata ( i_rdata ),\n .rlast ( i_rlast ),\n .rvalid ( i_rvalid ),\n .rready ( i_rready )\n );\n \n d_cache d_cache_inst (\n .clk ( clk ),\n .rst ( rst ),\n .stallM ( stallM ),\n .dstall ( d_cache_stall ),\n .E_mem_va ( mem_addrE ), // only used for match bram\n .M_mem_va ( data_addr ),\n .M_fence_addr ( fence_addrM ), // used for fence\n .M_fence_d ( fence_dM ), // fence address reuse the M_memva. Note: we shouldn't raise M_fence_en with M_mem_en.\n .M_mem_en ( data_en ),\n .M_mem_write ( |data_wen ),\n .M_wmask ( data_wen ),\n .M_mem_size ( data_rlen ),\n .M_wdata ( data_wdata ),\n .M_rdata ( data_rdata ),\n .dtlb_vpn2 ( dtlb_vpn2 ),\n .dtlb_found ( dtlb_found ),\n .dtlb_entry ( dtlb_entry ),\n .fence_tlb ( fence_tlbM ),\n .data_tlb_refill ( data_tlb_refill),\n .data_tlb_invalid ( data_tlb_invalid),\n .data_tlb_mod ( data_tlb_mod ),\n .araddr ( d_araddr ),\n .arlen ( d_arlen ),\n .arsize ( d_arsize ),\n .arvalid ( d_arvalid ),\n .arready ( d_arready ),\n .rdata ( d_rdata ),\n .rlast ( d_rlast ),\n .rvalid ( d_rvalid ),\n .rready ( d_rready ),\n .awaddr ( d_awaddr ),\n .awlen ( d_awlen ),\n .awsize ( d_awsize ),\n .awvalid ( d_awvalid ),\n .awready ( d_awready ),\n .wdata ( d_wdata ),\n .wstrb ( d_wstrb ),\n .wlast ( d_wlast ),\n .wvalid ( d_wvalid ),\n .wready ( d_wready ),\n .bvalid ( d_bvalid ),\n .bready ( d_bready )\n );\n\n arbitrater u_arbitrater(\n .clk(clk), \n .rst(rst),\n //I CACHE\n .i_araddr (i_araddr ),\n .i_arlen (i_arlen ),\n .i_arsize (i_arsize ),\n .i_arvalid (i_arvalid),\n .i_arready (i_arready),\n \n .i_rdata (i_rdata ),\n .i_rlast (i_rlast ),\n .i_rvalid (i_rvalid),\n .i_rready (i_rready),\n \n //D CACHE\n .d_araddr (d_araddr ),\n .d_arlen (d_arlen ),\n .d_arsize (d_arsize ),\n .d_arvalid (d_arvalid),\n .d_arready (d_arready),\n\n", "right_context": " .d_rlast (d_rlast ),\n .d_rvalid (d_rvalid),\n .d_rready (d_rready),\n\n .d_awaddr (d_awaddr ),\n .d_awlen (d_awlen ),\n .d_awsize (d_awsize ),\n .d_awvalid (d_awvalid),\n .d_awready (d_awready),\n\n .d_wdata (d_wdata ),\n .d_wstrb (d_wstrb ),\n .d_wlast (d_wlast ),\n .d_wvalid (d_wvalid),\n .d_wready (d_wready),\n\n .d_bvalid (d_bvalid),\n .d_bready (d_bready),\n //Outer\n .arid (arid ),\n .araddr (araddr ),\n .arlen (arlen ),\n .arsize (arsize ),\n .arburst (arburst),\n .arlock (arlock ),\n .arcache (arcache),\n .arprot (arprot ),\n .arvalid (arvalid),\n .arready (arready),\n \n .rid (rid ),\n .rdata (rdata ),\n .rresp (rresp ),\n .rlast (rlast ),\n .rvalid (rvalid),\n .rready (rready),\n \n .awid (awid ),\n .awaddr (awaddr ),\n .awlen (awlen ),\n .awsize (awsize ),\n .awburst (awburst),\n .awlock (awlock ),\n .awcache (awcache),\n .awprot (awprot ),\n .awvalid (awvalid),\n .awready (awready),\n \n .wid (wid ),\n .wdata (wdata ),\n .wstrb (wstrb ),\n .wlast (wlast ),\n .wvalid (wvalid),\n .wready (wready),\n .bid (bid ),\n .bresp (bresp ),\n .bvalid (bvalid),\n .bready (bready)\n );\nendmodule", "groundtruth": " .d_rdata (d_rdata ),\n", "crossfile_context": ""} {"task_id": "RTLStructLib", "path": "RTLStructLib/Systolic_Array/src/systolic_array_top.sv", "left_context": "`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n//\n// Create Date: 07/29/2025 08:48:20 PM\n// Design Name: \n// Module Name: systolic_array_top\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule systolic_array_top #(\n parameter LEFT_MATRIX_ROW = 50,\n", "right_context": " )(\n );\nendmodule\n", "groundtruth": " parameter INNER_DIMENSION = 50,\n parameter RIGHT_MATRIX_COL = 50,\n", "crossfile_context": ""} {"task_id": "fpu", "path": "fpu/hdl/fpu_fmac/booth_selector.sv", "left_context": "// Copyright 2017 ETH Zurich and University of Bologna.\n// Copyright and related rights are licensed under the Solderpad Hardware\n// License, Version 0.51 (the “License”); you may not use this file except in\n// compliance with the License. You may obtain a copy of the License at\n// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law\n// or agreed to in writing, software, hardware and materials distributed under\n// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR\n// CONDITIONS OF ANY KIND, either express or implied. See the License for the\n// specific language governing permissions and limitations under the License.\n////////////////////////////////////////////////////////////////////////////////\n// Company: IIS @ ETHZ - Federal Institute of Technology //\n// //\n// Engineers: Lei Li lile@iis.ee.ethz.ch //\n//\t\t //\n// Additional contributions by: //\n// //\n// //\n// //\n// Create Date: 01/12/2016 //\n// Design Name: fmac //\n// Module Name: booth_selector.sv //\n// Project Name: Private FPU //\n// Language: SystemVerilog //\n// //\n// Description: Booth Seletor //\n// //\n// //\n// //\n// Revision: 20/06/2017 //\n////////////////////////////////////////////////////////////////////////////////\n\nimport fpu_defs_fmac::*;\n\nmodule booth_selector\n (//Inputs\n input logic [1:0] Booth_a_DI,\n", "right_context": "endmodule\n", "groundtruth": " input logic Sel_1x_SI,\n input logic Sel_2x_SI,\n input logic Sel_sign_SI,\n //Outputs\n output logic Booth_pp_DO\n", "crossfile_context": ""} {"task_id": "pulpissimo", "path": "pulpissimo/hw/vendored_ips/gpio/src/gpio.sv", "left_context": "//-----------------------------------------------------------------------------\n// Title : GPIO Peripheral\n//-----------------------------------------------------------------------------\n// File : gpio.sv\n// Author : Manuel Eggimann \n// Created : 06.05.2021\n//-----------------------------------------------------------------------------\n// Description :\n// This Module contains a very simple but clean implementation of a GPIO\n// peripheral. The is controlled through a lightweight reg_bus interface. At the\n// bottom of this file there is a SV interface wrapper for the module.\n//-----------------------------------------------------------------------------\n// Copyright (C) 2013-2021 ETH Zurich, University of Bologna\n// Copyright and related rights are licensed under the Solderpad Hardware\n// License, Version 0.51 (the \"License\"); you may not use this file except in\n// compliance with the License. You may obtain a copy of the License at\n// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law\n// or agreed to in writing, software, hardware and materials distributed under\n// this License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR\n// CONDITIONS OF ANY KIND, either express or implied. See the License for the\n// specific language governing permissions and limitations under the License.\n//-----------------------------------------------------------------------------\n\n\n`include \"register_interface/typedef.svh\"\n`include \"register_interface/assign.svh\"\n\n`define assert_condition(cond, rst_ni) \\\nassert(^cond !== 1'bx | rst_ni !== 1'b1) \\\n else $error(\"Condition: %s = X in instance %m.\", `\"cond`\")\n\nmodule gpio #(\n /// Data width of the reg_bus\n parameter int unsigned DATA_WIDTH = 32,\n /// Regbus request struct type.\n parameter type reg_req_t = logic,\n /// Regbus response struct type.\n parameter type reg_rsp_t = logic,\n /// The number of GPIOs in this module. This parameter can only be changed if\n /// the corresponding register file is regenerated with the same number of\n /// GPIOs. The module will error out during elaboration if the given parameter\n /// does not match the number of defined GPIOs in the register file.\n localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount\n) (\n /// Primary input clock. The control interface is suposed to be synchronous to\n /// this clock.\n input logic clk_i,\n", "right_context": " output logic [NrGPIOs-1:0] gpio_out,\n /// GPIO tx enable signals. This signal is supposed to control the output\n /// buffer enable of the corresponding IO Pad. 0 -> RX (input), 1 -> TX (output).\n output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output\n /// Synchronized GPIO input signals. This port provides the `gpio_in` signal\n /// synchronized to `clk_i`.\n output logic [NrGPIOs-1:0] gpio_in_sync_o,\n /// Global interrupt line. The interrupt line is asserted for one `clk_i`\n /// whenever an unmasked interrupt on one of the GPIOs arrives.\n output logic global_interrupt_o,\n output logic [NrGPIOs-1:0] pin_level_interrupts_o,\n /// Control interface request side using register_interface protocol.\n input reg_req_t reg_req_i,\n /// Control interface request side using register_interface protocol.\n output reg_rsp_t reg_rsp_o\n);\n // The version number exposed via the INFO register\n localparam logic [9:0] HW_VERSION = 2;\n\n import gpio_reg_pkg::*;\n\n // Internal Signals\n gpio_reg2hw_t s_reg2hw;\n gpio_hw2reg_t s_hw2reg;\n\n // Synchronized inputs\n logic [NrGPIOs-1:0] s_gpio_in_sync;\n\n\n // Individual interrupt signals\n logic [NrGPIOs-1:0] s_gpio_rise_edge;\n logic [NrGPIOs-1:0] s_gpio_rise_intrpt_mask;\n logic [NrGPIOs-1:0] s_gpio_fall_edge;\n logic [NrGPIOs-1:0] s_gpio_fall_intrpt_mask;\n // for the level sensitive interrupts we can use the synchronized signal\n // directly, no need for an additional signal\n logic [NrGPIOs-1:0] s_gpio_high_intrpt_mask;\n logic [NrGPIOs-1:0] s_gpio_low_intrpt_mask;\n\n logic [NrGPIOs-1:0] s_gpio_rise_intrpt;\n logic [NrGPIOs-1:0] s_gpio_fall_intrpt;\n logic [NrGPIOs-1:0] s_gpio_high_intrpt;\n logic [NrGPIOs-1:0] s_gpio_low_intrpt;\n\n // Aggregated interrupts per GPIO\n logic [NrGPIOs-1:0] interrupts_edges; // Aggregates new interrupts\n logic [NrGPIOs-1:0] interrupts_pending; // Aggregates pending interrupts\n\n // Instantiate auto-generated register file\n gpio_reg_top #(\n .reg_req_t(reg_req_t),\n .reg_rsp_t(reg_rsp_t)\n ) i_reg_file (\n .clk_i,\n .rst_ni,\n .reg_req_i,\n .reg_rsp_o,\n .reg2hw(s_reg2hw),\n .hw2reg(s_hw2reg),\n .devmode_i(1'b1)\n );\n\n // Asign value to info register\n assign s_hw2reg.info.version.d = HW_VERSION;\n assign s_hw2reg.info.gpio_cnt.d = NrGPIOs[9:0];\n\n // Mask interrupts\n assign s_gpio_rise_intrpt = s_gpio_rise_edge & s_gpio_rise_intrpt_mask;\n assign s_gpio_fall_intrpt = s_gpio_fall_edge & s_gpio_fall_intrpt_mask;\n assign s_gpio_high_intrpt = s_gpio_in_sync & s_gpio_high_intrpt_mask;\n assign s_gpio_low_intrpt = ~s_gpio_in_sync & s_gpio_low_intrpt_mask;\n\n // Generate combined interrupt signal that combines all enabled interrupts for\n // each GPIO\n assign interrupts_edges = s_gpio_rise_intrpt | s_gpio_fall_intrpt | s_gpio_high_intrpt | s_gpio_low_intrpt;\n\n // Aggregate all pending interrupts. Aggregation of all sticky interrupts.\n assign interrupts_pending = s_reg2hw.intrpt_rise_status | s_reg2hw.intrpt_fall_status | s_reg2hw.intrpt_lvl_high_status | s_reg2hw.intrpt_lvl_low_status;\n\n // Assign interrupt output signal depending on inerrupt mode\n assign global_interrupt_o = (s_reg2hw.cfg.glbl_intrpt_mode.q)? |interrupts_pending : |interrupts_edges;\n assign pin_level_interrupts_o = (s_reg2hw.cfg.pin_lvl_intrpt_mode.q)? interrupts_pending : interrupts_edges;\n\n // Assign synchronized gpio inputs to external port\n assign gpio_in_sync_o = s_gpio_in_sync;\n\n // Instantiate logic for individual gpios in blocks of DATA_WIDTH\n for (genvar gpio_idx = 0; gpio_idx < NrGPIOs; gpio_idx++) begin : gen_gpios\n // Instantiate synchronizer to synchronize input to sampling clock\n gpio_input_stage #(\n .NrSyncStages(2)\n ) i_sync_gpio_input(\n .clk_i,\n .rst_ni,\n .en_i(s_reg2hw.gpio_en[gpio_idx].q && s_reg2hw.gpio_mode[gpio_idx].q == 0),\n .serial_i(gpio_in[gpio_idx]),\n .r_edge_o(s_gpio_rise_edge[gpio_idx]),\n .f_edge_o(s_gpio_fall_edge[gpio_idx]),\n .serial_o(s_gpio_in_sync[gpio_idx])\n );\n\n // Assign GPIO_IN register\n assign s_hw2reg.gpio_in[gpio_idx].d= s_gpio_in_sync[gpio_idx];\n\n // Control output with GPIO_OUT register\n assign gpio_out[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q;\n // Control gpio_tx_en_o depending on GPIO_MODE register value\n always_comb begin\n `assert_condition(s_reg2hw.gpio_mode[gpio_idx], rst_ni);\n case (s_reg2hw.gpio_mode[gpio_idx])\n 2'b00: begin //INPUT_ONLY\n gpio_tx_en_o[gpio_idx] = 1'b0;\n end\n 2'b01: begin //OUTPUT_ACTIVE\n gpio_tx_en_o[gpio_idx] = 1'b1;\n end\n 2'b10: begin // OPEN_DRAIN0\n gpio_tx_en_o[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q;\n end\n 2'b11: begin // OPEN_DRAIN1\n gpio_tx_en_o[gpio_idx] = ~s_reg2hw.gpio_out[gpio_idx].q;\n end\n default: begin\n gpio_tx_en_o[gpio_idx] = 1'b0;\n end\n endcase\n end\n\n // Wire individual masks\n assign s_gpio_rise_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_rise_en[gpio_idx].q;\n assign s_gpio_fall_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_fall_en[gpio_idx].q;\n assign s_gpio_high_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_lvl_high_en[gpio_idx].q;\n assign s_gpio_low_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_lvl_low_en[gpio_idx].q;\n\n // GPIO set, clear and toggle logic\n always_comb begin\n unique if (s_reg2hw.gpio_set[gpio_idx].qe && s_reg2hw.gpio_set[gpio_idx].q) begin\n `assert_condition(s_reg2hw.gpio_set[gpio_idx].qe && s_reg2hw.gpio_set[gpio_idx].q, rst_ni);\n s_hw2reg.gpio_out[gpio_idx].d = 1'b1;\n s_hw2reg.gpio_out[gpio_idx].de = 1'b1;\n end else if (s_reg2hw.gpio_clear[gpio_idx].qe && s_reg2hw.gpio_clear[gpio_idx].q) begin\n `assert_condition(s_reg2hw.gpio_clear[gpio_idx].qe && s_reg2hw.gpio_clear[gpio_idx].q, rst_ni);\n s_hw2reg.gpio_out[gpio_idx].d = 1'b0;\n s_hw2reg.gpio_out[gpio_idx].de = 1'b1;\n end else if (s_reg2hw.gpio_toggle[gpio_idx].qe && s_reg2hw.gpio_toggle[gpio_idx].q) begin\n `assert_condition(s_reg2hw.gpio_toggle[gpio_idx].qe && s_reg2hw.gpio_toggle[gpio_idx].q, rst_ni);\n s_hw2reg.gpio_out[gpio_idx].d = ~s_reg2hw.gpio_out[gpio_idx].q;\n s_hw2reg.gpio_out[gpio_idx].de = 1'b1;\n end else begin\n s_hw2reg.gpio_out[gpio_idx].d = s_reg2hw.gpio_out[gpio_idx].q;\n s_hw2reg.gpio_out[gpio_idx].de = 1'b0;\n end\n end\n\n //Wire interrupt status registers\n always_comb begin\n `assert_condition({s_reg2hw.intrpt_status[gpio_idx].qe && s_reg2hw.intrpt_status[gpio_idx].q}, rst_ni);\n //If we clear the aggregated, clear all individual interrupt status registers for the corresponding block of\n //GPIOs\n if (s_reg2hw.intrpt_status[gpio_idx].qe & (s_reg2hw.intrpt_status[gpio_idx].q == 1)) begin\n s_hw2reg.intrpt_rise_status[gpio_idx].d = '0;\n s_hw2reg.intrpt_rise_status[gpio_idx].de = 1'b1;\n s_hw2reg.intrpt_fall_status[gpio_idx].d = '0;\n s_hw2reg.intrpt_fall_status[gpio_idx].de = 1'b1;\n s_hw2reg.intrpt_lvl_high_status[gpio_idx].d = '0;\n s_hw2reg.intrpt_lvl_high_status[gpio_idx].de = 1'b1;\n s_hw2reg.intrpt_lvl_low_status[gpio_idx].d = '0;\n s_hw2reg.intrpt_lvl_low_status[gpio_idx].de = 1'b1;\n end else begin\n // Set new bits of the the individual status registers when an interrupt\n // arrives. Only update the registers (de) if there are any new\n // interrupts of the given type.\n s_hw2reg.intrpt_rise_status[gpio_idx].d = s_gpio_rise_intrpt[gpio_idx] | s_reg2hw.intrpt_rise_status[gpio_idx].q;\n s_hw2reg.intrpt_rise_status[gpio_idx].de = |s_gpio_rise_intrpt[gpio_idx];\n s_hw2reg.intrpt_fall_status[gpio_idx].d = s_gpio_fall_intrpt[gpio_idx] | s_reg2hw.intrpt_fall_status[gpio_idx].q;\n s_hw2reg.intrpt_fall_status[gpio_idx].de = |s_gpio_fall_intrpt[gpio_idx];\n s_hw2reg.intrpt_lvl_high_status[gpio_idx].d = s_gpio_high_intrpt[gpio_idx] | s_reg2hw.intrpt_lvl_high_status[gpio_idx].q;\n s_hw2reg.intrpt_lvl_high_status[gpio_idx].de = |s_gpio_high_intrpt[gpio_idx];\n s_hw2reg.intrpt_lvl_low_status[gpio_idx].d = s_gpio_low_intrpt[gpio_idx] | s_reg2hw.intrpt_lvl_low_status[gpio_idx].q;\n s_hw2reg.intrpt_lvl_low_status[gpio_idx].de = |s_gpio_low_intrpt[gpio_idx];\n end\n end // always_comb\n assign s_hw2reg.intrpt_status[gpio_idx].d = interrupts_pending[gpio_idx];\n end\nendmodule : gpio\n\nmodule gpio_intf #(\n /// ADDR_WIDTH of the reg_bus interface\n parameter int unsigned ADDR_WIDTH = 32,\n /// DATA_WIDTH of the reg_bus interface\n parameter int unsigned DATA_WIDTH = 32,\n localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount,\n localparam int unsigned STRB_WIDTH = DATA_WIDTH/8\n) (\n input logic clk_i,\n input logic rst_ni,\n input logic [NrGPIOs-1:0] gpio_in,\n output logic [NrGPIOs-1:0] gpio_out,\n output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output\n output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO\n // input.\n output logic global_interrupt_o,\n output logic [NrGPIOs-1:0] pin_level_interrupts_o,\n REG_BUS.in reg_bus\n);\n\n // Define structs for reg_bus\n typedef logic [ADDR_WIDTH-1:0] addr_t;\n typedef logic [DATA_WIDTH-1:0] data_t;\n typedef logic [STRB_WIDTH-1:0] strb_t;\n `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)\n\n reg_bus_req_t s_reg_req;\n reg_bus_rsp_t s_reg_rsp;\n\n // Assign SV interface to structs\n `REG_BUS_ASSIGN_TO_REQ(s_reg_req, reg_bus)\n `REG_BUS_ASSIGN_FROM_RSP(reg_bus, s_reg_rsp)\n\n gpio #(\n .reg_req_t(reg_bus_req_t),\n .reg_rsp_t(reg_bus_rsp_t)\n ) i_gpio (\n .clk_i,\n .rst_ni,\n .gpio_in,\n .gpio_out,\n .gpio_tx_en_o, // 0 -> input, 1 -> output\n .gpio_in_sync_o, // sampled and synchronized GPIO\n .global_interrupt_o,\n .pin_level_interrupts_o,\n .reg_req_i(s_reg_req),\n .reg_rsp_o(s_reg_rsp)\n );\n\nendmodule : gpio_intf\n", "groundtruth": " /// Asynchronous active-low reset\n input logic rst_ni,\n /// GPIO input signals from IO Pads (Pad -> SoC) signal.\n", "crossfile_context": ""} {"task_id": "riscv-simple-sv", "path": "riscv-simple-sv/core/common/control_transfer.sv", "left_context": "// RISC-V SiMPLE SV -- control transfer unit\n// BSD 3-Clause License\n// (c) 2017-2019, Arthur Matos, Marcus Vinicius Lamar, Universidade de Brasília,\n// Marek Materzok, University of Wrocław\n\n`include \"config.sv\"\n`include \"constants.sv\"\n\n", "right_context": " output logic take_branch\n);\n\n always_comb\n case (inst_funct3)\n `FUNCT3_BRANCH_EQ: take_branch = !result_equal_zero;\n `FUNCT3_BRANCH_NE: take_branch = result_equal_zero;\n `FUNCT3_BRANCH_LT: take_branch = !result_equal_zero;\n `FUNCT3_BRANCH_GE: take_branch = result_equal_zero;\n `FUNCT3_BRANCH_LTU: take_branch = !result_equal_zero;\n `FUNCT3_BRANCH_GEU: take_branch = result_equal_zero;\n default: take_branch = 1'bx;\n endcase\n\nendmodule\n\n", "groundtruth": "module control_transfer (\n input result_equal_zero,\n", "crossfile_context": ""} {"task_id": "DV-Interview-Prep-Guide", "path": "DV-Interview-Prep-Guide/01_Projects/Multi-Master_Multi-Slave/scoreboard.sv", "left_context": "class scoreboard extends uvm_scoreboard;\n `uvm_component_utils(scoreboard)\n\n packet_transaction m_tr, s_tr;\n uvm_tlm_analysis_fifo#(packet_transaction) master_fifo;\n uvm_tlm_analysis_fifo#(packet_transaction) slave_fifo;\n\n int pass_count = 0;\n int fail_count = 0;\n\n function new(string path = \"scoreboard\", uvm_component parent = null);\n super.new(path, parent);\n endfunction\n\n virtual function void build_phase(uvm_phase phase);\n super.build_phase(phase);\n m_tr = packet_transaction::type_id::create(\"m_tr\");\n s_tr = packet_transaction::type_id::create(\"s_tr\");\n master_fifo = new(\"master_fifo\", this);\n slave_fifo = new(\"slave_fifo\", this);\n endfunction\n\n virtual task run_phase(uvm_phase phase);\n forever begin\n master_fifo.get(m_tr);\n slave_fifo.get(s_tr);\n\n if(m_tr.compare(s_tr)) begin\n pass_count++;\n `uvm_info(\"SCO\", \"PASS: Transactions Matched\", UVM_NONE);\n end\n else begin\n fail_count++;\n", "right_context": " //UVM_ERROR @