---
license: other
task_categories:
- text-generation
language:
- code
tags:
- hardware
- verilog
- systemverilog
- vhdl
- chisel
- hls
- code-completion
size_categories:
- 1K<n<10K
---

# HDL-RepoBench Sample

This is a compact, deterministic sample of MHRC-Bench for lightweight
inspection and upload tests. It preserves the original language directories and
JSONL file names while keeping the output below 2 GB.

Sampling policy:

- Languages: chisel, hls, systemverilog, vhdl.
- Validation and test splits: copied in full by default.
- Training split: repository-stratified deterministic sample.
- Raw repository archive: omitted because `original_repo/collected_repos.tar.gz`
  is about 33 GB in the source dataset.

This generated sample contains 6,537 JSONL records and occupies
217.0 MiB on disk. See `sample_manifest.json` for exact
per-file counts, byte sizes, and generation arguments.