Upload chipbench_meta_data.json

chipbench_meta_data.json

@@ -0,0 +1,341 @@
+{
+  "@context": {
+    "@language": "en",
+    "@vocab": "https://schema.org/",
+    "citeAs": "cr:citeAs",
+    "column": "cr:column",
+    "conformsTo": "dct:conformsTo",
+    "cr": "http://mlcommons.org/croissant/",
+    "rai": "http://mlcommons.org/croissant/RAI/",
+    "data": {
+      "@id": "cr:data",
+      "@type": "@json"
+    },
+    "dataType": {
+      "@id": "cr:dataType",
+      "@type": "@vocab"
+    },
+    "dct": "http://purl.org/dc/terms/",
+    "examples": {
+      "@id": "cr:examples",
+      "@type": "@json"
+    },
+    "extract": "cr:extract",
+    "field": "cr:field",
+    "fileProperty": "cr:fileProperty",
+    "fileObject": "cr:fileObject",
+    "fileSet": "cr:fileSet",
+    "format": "cr:format",
+    "includes": "cr:includes",
+    "isLiveDataset": "cr:isLiveDataset",
+    "jsonPath": "cr:jsonPath",
+    "key": "cr:key",
+    "md5": "cr:md5",
+    "parentField": "cr:parentField",
+    "path": "cr:path",
+    "recordSet": "cr:recordSet",
+    "references": "cr:references",
+    "regex": "cr:regex",
+    "repeated": "cr:repeated",
+    "replace": "cr:replace",
+    "sc": "https://schema.org/",
+    "separator": "cr:separator",
+    "source": "cr:source",
+    "subField": "cr:subField",
+    "transform": "cr:transform"
+  },
+  "@type": "sc:Dataset",
+  "name": "ChiPBench-D",
+  "description": "A dataset of digital design with standard DEF/LEF/Liberty/Verilog/SDC files, intended for use in EDA placement benchmarks.",
+  "license": "https://opensource.org/licenses/MIT",
+  "version": "1.0",
+  "datePublished": "2025-05-08",
+  "url": "https://huggingface.co/datasets/MIRA-Lab/ChiPBench-D",
+  "creator": {
+    "@type": "sc:Person",
+    "name": "MIRA-Lab"
+  },
+  "citeAs": "ChiPBench-D",
+  "conformsTo": "http://mlcommons.org/croissant/1.0",
+  "distribution": [
+    {
+      "@type": "cr:FileObject",
+      "@id": "repo",
+      "name": "ChiPBench-D Repository",
+      "description": "Git repository containing all ChiPBench-D design files",
+      "contentUrl": "https://huggingface.co/datasets/MIRA-Lab/ChiPBench-D",
+      "encodingFormat": "git+https",
+      "sha256": "main"
+    },
+    {
+      "@type": "cr:FileSet",
+      "@id": "verilog-files",
+      "name": "Verilog Files",
+      "description": "Verilog Files",
+      "containedIn": {
+        "@id": "repo"
+      },
+      "includes": "data/*/*.v",
+      "encodingFormat": "text/plain"
+    },
+    {
+      "@type": "cr:FileSet",
+      "@id": "sdc-files",
+      "name": "SDC Files",
+      "description": "LEF Files",
+      "containedIn": {
+        "@id": "repo"
+      },
+      "includes": "data/*/*.sdc",
+      "encodingFormat": "text/plain"
+    },
+    {
+      "@type": "cr:FileSet",
+      "@id": "lef-files",
+      "name": "LEF Files",
+      "description": "LEF Files",
+      "containedIn": {
+        "@id": "repo"
+      },
+      "includes": "data/*/lef/*.lef",
+      "encodingFormat": "text/plain"
+    },
+    {
+      "@type": "cr:FileSet",
+      "@id": "lib-files",
+      "name": "Liberty Files",
+      "description": "Liberty Files",
+      "containedIn": {
+        "@id": "repo"
+      },
+      "includes": "data/*/lib/*.lib",
+      "encodingFormat": "text/plain"
+    },
+    {
+      "@type": "cr:FileSet",
+      "@id": "def-files",
+      "name": "DEF Files",
+      "description": "DEF Files",
+      "containedIn": {
+        "@id": "repo"
+      },
+      "includes": "data/*/def/*.def",
+      "encodingFormat": "text/plain"
+    }
+  ],
+"recordSet": [
+  {
+    "@type": "cr:RecordSet",
+    "@id": "verilog_file",
+    "name": "verilog_file",
+    "description": "Records of Verilog design files",
+    "field": [
+      {
+        "@type": "cr:Field",
+        "@id": "verilog_file/design_name",
+        "name": "design_name",
+        "dataType": "sc:Text",
+        "description": "Design name extracted from Verilog file path",
+        "source": {
+          "fileSet": { "@id": "verilog-files" },
+          "extract": { "fileProperty": "fullpath" },
+          "transform": { "regex": "data/([^/]+)/[^/]+\\.v$" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "verilog_file/verilog_path",
+        "name": "verilog_path",
+        "dataType": "sc:Text",
+        "description": "Full path of the Verilog file",
+        "source": {
+          "fileSet": { "@id": "verilog-files" },
+          "extract": { "fileProperty": "fullpath" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "verilog_file/verilog_content",
+        "name": "verilog_content",
+        "dataType": "sc:Text",
+        "description": "Content of the Verilog design file",
+        "source": {
+          "fileSet": { "@id": "verilog-files" },
+          "extract": { "fileProperty": "content" }
+        }
+      }
+    ]
+  },
+  {
+    "@type": "cr:RecordSet",
+    "@id": "sdc_file",
+    "name": "sdc_file",
+    "description": "Records of SDC timing constraint files",
+    "field": [
+      {
+        "@type": "cr:Field",
+        "@id": "sdc_file/design_name",
+        "name": "design_name",
+        "dataType": "sc:Text",
+        "description": "Design name extracted from SDC file path",
+        "source": {
+          "fileSet": { "@id": "sdc-files" },
+          "extract": { "fileProperty": "fullpath" },
+          "transform": { "regex": "data/([^/]+)/[^/]+\\.sdc$" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "sdc_file/sdc_path",
+        "name": "sdc_path",
+        "dataType": "sc:Text",
+        "description": "Full path of the SDC file",
+        "source": {
+          "fileSet": { "@id": "sdc-files" },
+          "extract": { "fileProperty": "fullpath" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "sdc_file/sdc_content",
+        "name": "sdc_content",
+        "dataType": "sc:Text",
+        "description": "Content of the SDC constraint file",
+        "source": {
+          "fileSet": { "@id": "sdc-files" },
+          "extract": { "fileProperty": "content" }
+        }
+      }
+    ]
+  },
+  {
+    "@type": "cr:RecordSet",
+    "@id": "lef_file",
+    "name": "lef_file",
+    "description": "Records of LEF technology/library files",
+    "field": [
+      {
+        "@type": "cr:Field",
+        "@id": "lef_file/design_name",
+        "name": "design_name",
+        "dataType": "sc:Text",
+        "description": "Design name extracted from LEF file path",
+        "source": {
+          "fileSet": { "@id": "lef-files" },
+          "extract": { "fileProperty": "fullpath" },
+          "transform": { "regex": "data\\/([^\\/]+)\\/lef\\/[^\\/]+\\.lef$" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "lef_file/lef_content",
+        "name": "lef_content",
+        "dataType": "sc:Text",
+        "description": "Content of the LEF file",
+        "source": {
+          "fileSet": { "@id": "lef-files" },
+          "extract": { "fileProperty": "content" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "lef_file/lef_paths",
+        "name": "lef_paths",
+        "dataType": "sc:Text",
+        "description": "Full path of the LEF file",
+        "source": {
+          "fileSet": { "@id": "lef-files" },
+          "extract": { "fileProperty": "fullpath" }
+        }
+      }
+    ]
+  },
+  {
+    "@type": "cr:RecordSet",
+    "@id": "lib_file",
+    "name": "lib_file",
+    "description": "Records of Liberty (.lib) timing files",
+    "field": [
+      {
+        "@type": "cr:Field",
+        "@id": "lib_file/design_name",
+        "name": "design_name",
+        "dataType": "sc:Text",
+        "description": "Design name extracted from Liberty file path",
+        "source": {
+          "fileSet": { "@id": "lib-files" },
+          "extract": { "fileProperty": "fullpath" },
+          "transform": { "regex": "data\\/([^\\/]+)\\/lib\\/[^\\/]+\\.lib$" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "lib_file/lib_paths",
+        "name": "lib_paths",
+        "dataType": "sc:Text",
+        "description": "Full path of the Liberty file",
+        "source": {
+          "fileSet": { "@id": "lib-files" },
+          "extract": { "fileProperty": "fullpath" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "lib_file/lib_content",
+        "name": "lib_content",
+        "dataType": "sc:Text",
+        "description": "Content of the Liberty timing file",
+        "source": {
+          "fileSet": { "@id": "lib-files" },
+          "extract": { "fileProperty": "content" }
+        }
+      }
+    ]
+  },
+  {
+    "@type": "cr:RecordSet",
+    "@id": "def_file",
+    "name": "def_file",
+    "description": "Records of DEF placement/routing files",
+    "field": [
+      {
+        "@type": "cr:Field",
+        "@id": "def_file/design_name",
+        "name": "design_name",
+        "dataType": "sc:Text",
+        "description": "Design name extracted from DEF file path",
+        "source": {
+          "fileSet": { "@id": "def-files" },
+          "extract": { "fileProperty": "fullpath" },
+          "transform": { "regex": "data\\/([^\\/]+)\\/def\\/[^\\/]+\\.def$" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "def_file/def_paths",
+        "name": "def_paths",
+        "dataType": "sc:Text",
+        "description": "Full path of the DEF file",
+        "source": {
+          "fileSet": { "@id": "def-files" },
+          "extract": { "fileProperty": "fullpath" }
+        }
+      },
+      {
+        "@type": "cr:Field",
+        "@id": "def_file/def_content",
+        "name": "def_content",
+        "dataType": "sc:Text",
+        "description": "Content of the DEF file",
+        "source": {
+          "fileSet": { "@id": "def-files" },
+          "extract": { "fileProperty": "content" }
+        }
+      }
+    ]
+  }
+]
+
+
+
+}