## Summary
RuC is a grammar-driven, rule-selectable benchmark generator that automatically produces RTL code-completion tasks from a set of input hardware description sources. It uses the target HDL grammar to mask syntactically defined code regions and prompts a model to regenerate them using the surrounding unmasked code as context.

**Paper**: https://arxiv.org/abs/2604.27780

RuC-datasets is a collection of design datasets processed with the RuC framework and used for the experimentations in the paper.
Although RuC-cve2_b72358c7-32k and RuC-tt07-32k share the same schema and preprocessing steps, they originate from different base datasets and should be treated as separate datasets.

## Datasets structure
Each project inside both datasets contains:

- <top_module>.sv for cve2 or <top_module>.v for tt07
Verilog or SystemVerilog hardware designs named after the top-level module.
- mask_idx.json
Indices of selected rule occurrences used for RuC.
- all_mask_idx.json
Full set of candidate rule occurrences eligible for masking.

## Dataset creation
Both datasets computed mask_idx.json and all_mask_idx.json using RuC as explained in the paper.

### RuC-tt07-32k
NotSoTiny shuttle tt07 (https://huggingface.co/datasets/HPAI-BSC/NotSoTiny-25-12) filtered to keep designs that contain less than 32000 tokens. 

### RuC-cve2_b72358c7-32k
CVE2 is an industry-grade RISC-V core maintained by OpenHWGroup. The CVE2 codebase preprocessed using vppreproc and filtered to keep designs that contain less than 32000 tokens.

## Datasets usage
These datasets are intended to be used together with the RuC framework (https://github.com/HPAI-BSC/RuC) to directly perform inference and evaluation with different LLMs.

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license: apache-2.0
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