chip__Archive__Hermes_V2.1___EEPROM___6175b33248/module_header.vh

module. Clock is max of 10MHz to give 5MHz SCK

/*
	The data at address 0xFA to 0xFF of the 25AA02E48 contains
	the MAC address to be used by this board. Once the initial address is set it 
	auto-increments.
	
	
	Waveforms:
	
			     +-------+
	read   ----+       +-----------------------------------------------------------------------------------------------------------
	
			--------+																									   		       +------
	CS			     +--------------------------------------------------------------------------------------------  ||		 -----+
	
						0   0   1   2   3   4   5   6   7   8   9  10  11  12  13  14   0   1   2   3   4   5   6   7      ----- 48   
					   +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+   
	SCK -----------+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
	
	SI    --------+----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
					  | 0	 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |A7 |A6 |A5 |A4 |A3 |A2 |A1 |A0 |   |   |   |   |   |   |   |   |   |
			--------+----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+  
					<--------read instruction-------><---------address--------------->
																			 		 +---+---+---+---+---+---+---+---+---+
	SO																				 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | Next byte follows
			-------------------------------------------------------------------------+---+---+---+---+---+---+---+---+---+
																					 <-----------data out------------------------> 
				                              																											     +-----------	
	ready   ---------------------------------------------------------------------------------------------------------------------+
 
 
	For write operations first use Write Enable Sequence (WREN)
 
 			     +-------+
	write  ----+       +----------------------------------------
	
		  --------+									           +------
	CS			    +------------------------------------+
	
					        0   1   2   3   4   5   6   7     
				          +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ 
	SCK     -----------+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+--------
	
	SI    --------+----+---+---+---+---+---+---+---+
					  | 0	 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
			--------+----+---+---+---+---+---+---+---+ 
					  <--------------WREN-------------->
 
 
	Then write the data 

	
			--------+																									   		                        +------
	CS		        +--------------------------------------------------------------------------------------------  ||		 -----+
	
					        0   0   1   2   3   4   5   6   7   8   9  10  11  12  13  14   0   1   2   3   4   5   6   7      ----- 32   
					       +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+   
	SCK     -----------+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
	
	SI    --------+----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
					  | 0	 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |A7 |A6 |A5 |A4 |A3 |A2 |A1 |A0 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | Next byte
			--------+----+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+  
				     <-------write instruction-------><---------address--------------><---------data------------------------------>

 
 	Followed by Write Disable Sequence (WRDI) *** automatically set following a Write so not required 
 
	
			--------+									         +------
	CS			     +------------------------------------+
	   
					        0   1   2   3   4   5   6   7     
					       +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ 
	SCK     -----------+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+--------
	
	SI    --------+----+---+---+---+---+---+---+---+
					  | 0	 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
			--------+----+---+---+---+---+---+---+---+ 
					<--------------WRDI-------------->
 
 														               +-----	
	ready   ----------------------------------------------+

 
*/

module EEPROM (clock, read_MAC, read_IP, write_IP, IP_to_write, CS, SCK, SI, SO, This_MAC, This_IP, MAC_ready, IP_ready, IP_write_done);