Fix clock spec and drop module/testbench counts

README.md

@@ -35,14 +35,14 @@ Open source 128-core neuromorphic processor with full mesh NoC, STDP learning, a
 | Host interface | UART (FPGA) / AXI-Lite (F2) / PCIe MMIO |
 | Management | RV32IM RISC-V cluster |
 | Multi-chip | Chip link with routing table |
-| Clock | 100 MHz (simulation default) |
+| Clock | 62.5 MHz |
 
 ## Directory Structure
 
 ```
 catalyst-n1/
-  rtl/           25 Verilog modules (core, NoC, memory, host, RISC-V)
-  tb/            46 testbenches (unit, integration, regression)
+  rtl/           Verilog sources (core, NoC, memory, host, RISC-V)
+  tb/            Testbenches (unit, integration, regression)
   sdk/           Python SDK with CPU, GPU, and FPGA backends
   fpga/          FPGA build files (Arty A7, AWS F2, Kria K26)
   sim/           Simulation scripts and visualization
@@ -57,7 +57,7 @@ Requires [Icarus Verilog](https://github.com/steveicarus/iverilog) (v12+).
 # Compile and run basic simulation
 make sim
 
-# Run full regression (25 testbenches)
+# Run full regression
 bash run_regression.sh
 
 # Run a single testbench